ATmega8515(L) - Summary

Features
• High-performance, Low-power AVR® 8-bit Microcontroller
• RISC Architecture
•
•
•
•
•
•
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
Nonvolatile Program and Data Memories
– 8K Bytes of In-System Self-programmable Flash
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– 512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 512 Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Three PWM Channels
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Three Sleep Modes: Idle, Power-down and Standby
I/O and Packages
– 35 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF
Operating Voltages
– 2.7 - 5.5V for ATmega8515L
– 4.5 - 5.5V for ATmega8515
Speed Grades
– 0 - 8 MHz for ATmega8515L
– 0 - 16 MHz for ATmega8515
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
ATmega8515
ATmega8515L
Summary
2512JS–AVR–10/06
Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.
Pin Configurations
Figure 1. Pinout ATmega8515
PDIP
(OC0/T0) PB0
(T1) PB1
(AIN0) PB2
(AIN1) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
(RXD) PD0
(TDX) PD1
(INT0) PD2
(INT1) PD3
(XCK) PD4
(OC1A) PD5
(WR) PD6
(RD) PD7
XTAL2
XTAL1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PE0 (ICP/INT2)
PE1 (ALE)
PE2 (OC1B)
PC7 (A15)
PC6 (A14)
PC5 (A13)
PC4 (A12)
PC3 (A11)
PC2 (A10)
PC1 (A9)
PC0 (A8)
TQFP/MLF
(WR) PD6
(RD) PD7
XTAL2
XTAL1
GND
NC*
(A8) PC0
(A9) PC1
(A10) PC2
(A11) PC3
(A12) PC4
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
(RXD) PD0
NC*
(TXD) PD1
(INT0) PD2
(INT1) PD3
(XCK) PD4
(OC1A) PD5
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PE0 (ICP/INT2)
NC*
PE1 (ALE)
PE2 (OC1B)
PC7 (A15)
PC6 (A14)
PC5 (A13)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PE0 (ICP/INT2)
NC*
PE1 (ALE)
PE2 (OC1B)
PC7 (A15)
PC6 (A14)
PC5 (A13)
(WR) PD6
(RD) PD7
XTAL2
XTAL1
GND
NC*
(A8) PC0
(A9) PC1
(A10) PC2
(A11) PC3
(A12) PC4
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
(RXD) PD0
NC*
(TXD) PD1
(INT0) PD2
(INT1) PD3
(XCK) PD4
(OC1A) PD5
6
5
4
3
2
1
44
43
42
41
40
44
43
42
41
40
39
38
37
36
35
34
PB4 (SS)
PB3 (AIN1)
PB2 (AIN0)
PB1 (T1)
PB0 (OC0/T0)
NC*
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
PA3 (AD3)
PB4 (SS)
PB3 (AIN1)
PB2 (AIN0)
PB1 (T1)
PB0 (OC0/T0)
NC*
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
PA3 (AD3)
PLCC
NOTES:
1. MLF bottom pad should be soldered to ground.
2. * NC = Do not connect (May be used in future devices)
2
ATmega8515(L)
2512JS–AVR–10/06
ATmega8515(L)
Overview
The ATmega8515 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle,
the ATmega8515 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
Block Diagram
Figure 2. Block Diagram
PA0 - PA7
PE0 - PE2
PC0 - PC7
PORTA DRIVERS/BUFFERS
PORTE
DRIVERS/
BUFFERS
PORTC DRIVERS/BUFFERS
PORTA DIGITAL INTERFACE
PORTE
DIGITAL
INTERFACE
PORTC DIGITAL INTERFACE
VCC
GND
PROGRAM
COUNTER
STACK
POINTER
PROGRAM
FLASH
SRAM
TIMERS/
COUNTERS
INTERNAL
OSCILLATOR
XTAL1
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
WATCHDOG
TIMER
OSCILLATOR
XTAL2
X
INSTRUCTION
DECODER
Y
MCU CTRL.
& TIMING
RESET
Z
CONTROL
LINES
ALU
INTERRUPT
UNIT
AVR CPU
STATUS
REGISTER
EEPROM
PROGRAMMING
LOGIC
SPI
USART
+
-
INTERNAL
CALIBRATED
OSCILLATOR
COMP.
INTERFACE
PORTB DIGITAL INTERFACE
PORTD DIGITAL INTERFACE
PORTB DRIVERS/BUFFERS
PORTD DRIVERS/BUFFERS
PB0 - PB7
PD0 - PD7
3
2512JS–AVR–10/06
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATmega8515 provides the following features: 8K bytes of In-System Programmable
Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, an
External memory interface, 35 general purpose I/O lines, 32 general purpose working
registers, two flexible Timer/Counters with compare modes, Internal and External interrupts, a Serial Programmable USART, a programmable Watchdog Timer with internal
Oscillator, a SPI serial port, and three software selectable power saving modes. The Idle
mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and Interrupt
system to continue functioning. The Power-down mode saves the Register contents but
freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Standby mode, the crystal/resonator Oscillator is running while the rest of
the device is sleeping. This allows very fast start-up combined with low-power
consumption.
The device is manufactured using Atmel’s high density nonvolatile memory technology.
The On-chip ISP Flash allows the Program memory to be reprogrammed In-System
through an SPI serial interface, by a conventional nonvolatile memory programmer, or
by an On-chip Boot program running on the AVR core. The boot program can use any
interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
with In-System Self-programmable Flash on a monolithic chip, the Atmel ATmega8515
is a powerful microcontroller that provides a highly flexible and cost effective solution to
many embedded control applications.
The ATmega8515 is supported with a full suite of program and system development
tools including: C Compilers, Macro assemblers, Program debugger/simulators, In-circuit Emulators, and Evaluation kits.
Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min
and Max values will be available after the device is characterized.
AT90S4414/8515 and
ATmega8515
Compatibility
The ATmega8515 provides all the features of the AT90S4414/8515. In addition, several
n e w f e a t u r e s a r e a d d e d . T h e A T m e g a 8 5 1 5 i s b a c k w a r d c o m p a t i b l e w i th
AT90S4414/8515 in most cases. However, some incompatibilities between the two
microcontrollers exist. To solve this problem, an AT90S4414/8515 compatibility mode
can be selected by programming the S8515C Fuse. ATmega8515 is 100% pin compatible with AT90S4414/8515, and can replace the AT90S4414/8515 on current printed
circuit boards. However, the location of Fuse bits and the electrical characteristics differs between the two devices.
AT90S4414/8515 Compatibility
Mode
Programming the S8515C Fuse will change the following functionality:
4
•
The timed sequence for changing the Watchdog Time-out period is disabled. See
“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page
53 for details.
•
The double buffering of the USART Receive Registers is disabled. See “AVR
USART vs. AVR UART – Compatibility” on page 137 for details.
•
PORTE(2:1) will be set as output, and PORTE0 will be set as input.
ATmega8515(L)
2512JS–AVR–10/06
ATmega8515(L)
Pin Descriptions
VCC
Digital supply voltage.
GND
Ground.
Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port A output buffers have symmetrical drive characteristics with both high sink
and source capability. When pins PA0 to PA7 are used as inputs and are externally
pulled low, they will source current if the internal pull-up resistors are activated. The Port
A pins are tri-stated when a reset condition becomes active, even if the clock is not
running.
Port A also serves the functions of various special features of the ATmega8515 as listed
on page 67.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega8515 as listed
on page 67.
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port C output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega8515 as listed
on page 72.
Port E(PE2..PE0)
Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port E output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port E pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the ATmega8515 as listed
on page 74.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table
18 on page 46. Shorter pulses are not guaranteed to generate a reset.
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting Oscillator amplifier.
5
2512JS–AVR–10/06
Resources
6
A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.
ATmega8515(L)
2512JS–AVR–10/06
ATmega8515(L)
About Code
Examples
This documentation contains simple code examples that briefly show how to use various
parts of the device. These code examples assume that the part specific header file is
included before compilation. Be aware that not all C Compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please
confirm with the C Compiler documentation for more details.
7
2512JS–AVR–10/06
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
$3F ($5F)
SREG
I
T
H
S
V
N
Z
C
10
$3E ($5E)
SPH
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
12
$3D ($5D)
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
12
$3C ($5C)
Reserved
$3B ($5B)
GICR
INT1
INT0
INT2
-
-
-
IVSEL
IVCE
57, 78
$3A ($5A)
GIFR
INTF1
INTF0
INTF2
-
-
-
-
-
79
$39 ($59)
TIMSK
TOIE1
OCIE1A
OCIE1B
-
TICIE1
-
TOIE0
OCIE0
93, 124
93, 125
-
$38 ($58)
TIFR
TOV1
OCF1A
OCF1B
-
ICF1
-
TOV0
OCF0
$37 ($57)
SPMCR
SPMIE
RWWSB
-
RWWSRE
BLBSET
PGWRT
PGERS
SPMEN
170
$36 ($56)
EMCUCR
SM0
SRL2
SRL1
SRL0
SRW01
SRW00
SRW11
ISC2
29,42,78
$35 ($55)
MCUCR
SRE
SRW10
SE
SM1
ISC11
ISC10
ISC01
ISC00
29,41,77
$34 ($54)
MCUCSR
-
-
SM2
-
WDRF
BORF
EXTRF
PORF
41,49
$33 ($53)
TCCR0
FOC0
WGM00
COM01
COM00
WGM01
CS02
CS01
CS00
$32 ($52)
$31 ($51)
TCNT0
$30 ($50)
SFIOR
-
XMBK
XMM2
XMM1
Timer/Counter0 (8 Bits)
OCR0
91
93
Timer/Counter0 Output Compare Register
93
XMM0
PUD
-
PSR10
31,66,96
$2F ($4F)
TCCR1A
COM1A1
COM1A0
COM1B1
COM1B0
FOC1A
FOC1B
WGM11
WGM10
119
$2E ($4E)
TCCR1B
ICNC1
ICES1
-
WGM13
WGM12
CS12
CS11
CS10
122
$2D ($4D)
TCNT1H
Timer/Counter1 - Counter Register High Byte
123
$2C ($4C)
TCNT1L
Timer/Counter1 - Counter Register Low Byte
123
$2B ($4B)
OCR1AH
Timer/Counter1 - Output Compare Register A High Byte
123
$2A ($4A)
OCR1AL
Timer/Counter1 - Output Compare Register A Low Byte
123
$29 ($49)
OCR1BH
Timer/Counter1 - Output Compare Register B High Byte
123
$28 ($48)
OCR1BL
Timer/Counter1 - Output Compare Register B Low Byte
123
$27 ($47)
Reserved
-
-
$26 ($46)
Reserved
-
-
$25 ($45)
ICR1H
Timer/Counter1 - Input Capture Register High Byte
124
$24 ($44)
ICR1L
Timer/Counter1 - Input Capture Register Low Byte
124
$23 ($43)
Reserved
-
-
$22 ($42)
Reserved
-
$21 ($41)
WDTCR
-
UBRRH
URSEL
-
-
-
UCSRC
URSEL
UMSEL
UPM1
$1F ($3F)
EEARH
-
-
-
$1E ($3E)
EEARL
EEPROM Address Register Low Byte
$1D ($3D)
EEDR
EEPROM Data Register
$1C ($3C)
EECR
-
-
-
-
EERIE
EEMWE
EEWE
EERE
$1B ($3B)
PORTA
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
75
$1A ($3A)
DDRA
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
75
$20(1) ($40)(1)
-
-
WDCE
WDE
WDP2
WDP1
WDP0
UPM0
USBS
UCSZ1
UCSZ0
UCPOL
157
-
-
-
-
EEAR8
19
UBRR[11:8]
51
159
19
20
20
$19 ($39)
PINA
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
75
$18 ($38)
PORTB
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
75
$17 ($37)
DDRB
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
75
$16 ($36)
PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
75
$15 ($35)
PORTC
PORTC7
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
75
$14 ($34)
DDRC
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
75
$13 ($33)
PINC
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
76
$12 ($32)
PORTD
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
76
$11 ($31)
DDRD
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
76
$10 ($30)
PIND
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
76
133
$0F ($2F)
SPDR
$0E ($2E)
SPSR
SPIF
WCOL
-
-
-
-
-
SPI2X
$0D ($2D)
SPCR
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
$0C ($2C)
UDR
$0B ($2B)
UCSRA
RXC
TXC
UDRE
FE
DOR
PE
U2X
MPCM
155
$0A ($2A)
UCSRB
RXCIE
TXCIE
UDRIE
RXEN
TXEN
UCSZ2
RXB8
TXB8
156
$09 ($29)
UBRRL
$08 ($28)
ACSR
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
164
$07 ($27)
PORTE
-
-
-
-
-
PORTE2
PORTE1
PORTE0
76
$06 ($26)
DDRE
-
-
-
-
-
DDE2
DDE1
DDE0
76
$05 ($25)
PINE
-
-
-
PINE2
PINE1
PINE0
$04 ($24)
OSCCAL
Notes:
8
Page
SPI Data Register
133
USART I/O Data Register
USART Baud Rate Register Low Byte
Oscillator Calibration Register
131
155
159
76
39
1. Refer to the USART description for details on how to access UBRRH and UCSRC.
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
ATmega8515(L)
2512JS–AVR–10/06
ATmega8515(L)
3. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.
9
2512JS–AVR–10/06
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
ADC
Rd, Rr
Add with Carry two Registers
Rd ← Rd + Rr + C
Z,C,N,V,H
1
ADIW
Rdl,K
Add Immediate to Word
Rdh:Rdl ← Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract two Registers
Rd ← Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract Constant from Register
Rd ← Rd - K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry two Registers
Rd ← Rd - Rr - C
Z,C,N,V,H
1
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd ← Rd - K - C
Z,C,N,V,H
1
SBIW
Rdl,K
Subtract Immediate from Word
Rdh:Rdl ← Rdh:Rdl - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND Registers
Rd ← Rd • Rr
Z,N,V
1
ANDI
Rd, K
Logical AND Register and Constant
Rd ← Rd • K
Z,N,V
1
OR
Rd, Rr
Logical OR Registers
Rd ← Rd v Rr
Z,N,V
1
ORI
Rd, K
Logical OR Register and Constant
Rd ← Rd v K
Z,N,V
1
EOR
Rd, Rr
Exclusive OR Registers
Rd ← Rd ⊕ Rr
Z,N,V
1
1
COM
Rd
One’s Complement
Rd ← $FF − Rd
Z,C,N,V
1
NEG
Rd
Two’s Complement
Rd ← $00 − Rd
Z,C,N,V,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd ← Rd v K
Z,N,V
1
CBR
Rd,K
Clear Bit(s) in Register
Rd ← Rd • ($FF - K)
Z,N,V
1
INC
Rd
Increment
Rd ← Rd + 1
Z,N,V
1
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
1
TST
Rd
Test for Zero or Minus
Rd ← Rd • Rd
Z,N,V
1
CLR
Rd
Clear Register
Rd ← Rd ⊕ Rd
Z,N,V
1
SER
Rd
Set Register
Rd ← $FF
None
1
MUL
Rd, Rr
Multiply Unsigned
R1:R0 ← Rd x Rr
Z,C
2
MULS
Rd, Rr
Multiply Signed
R1:R0 ← Rd x Rr
Z,C
2
MULSU
Rd, Rr
Multiply Signed with Unsigned
R1:R0 ← Rd x Rr
Z,C
2
FMUL
Rd, Rr
Fractional Multiply Unsigned
R1:R0 ← (Rd x Rr) <<
1
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
Z,C
2
Z,C
2
Z,C
2
2
FMULS
Rd, Rr
Fractional Multiply Signed
FMULSU
Rd, Rr
Fractional Multiply Signed with Unsigned
BRANCH INSTRUCTIONS
RJMP
k
IJMP
RCALL
k
Relative Jump
PC ← PC + k + 1
None
Indirect Jump to (Z)
PC ← Z
None
2
Relative Subroutine Call
PC ← PC + k + 1
None
3
3
ICALL
Indirect Call to (Z)
PC ← Z
None
RET
Subroutine Return
PC ← STACK
None
4
RETI
Interrupt Return
PC ← STACK
I
4
CPSE
Rd,Rr
Compare, Skip if Equal
if (Rd = Rr) PC ← PC + 2 or 3
None
CP
Rd,Rr
Compare
Rd − Rr
Z, N,V,C,H
1
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
Z, N,V,C,H
1
CPI
Rd,K
Compare Register with Immediate
Rd − K
Z, N,V,C,H
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC ← PC + 2 or 3
None
1/2/3
1/2/3
1
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC ← PC + 2 or 3
None
1/2/3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b)=0) PC ← PC + 2 or 3
None
1/2/3
SBIS
P, b
Skip if Bit in I/O Register is Set
if (P(b)=1) PC ← PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC←PC+k + 1
None
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC←PC+k + 1
None
1/2
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC ← PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC ← PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC ← PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC ← PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC ← PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC ← PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC ← PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC ← PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N ⊕ V= 0) then PC ← PC + k + 1
None
1/2
BRLT
k
Branch if Less Than Zero, Signed
if (N ⊕ V= 1) then PC ← PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC ← PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC ← PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC ← PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC ← PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC ← PC + k + 1
None
1/2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC ← PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC ← PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC ← PC + k + 1
None
1/2
10
ATmega8515(L)
2512JS–AVR–10/06
ATmega8515(L)
Mnemonics
Operands
Description
Operation
Flags
Rd ← Rr
Rd+1:Rd ← Rr+1:Rr
None
1
None
1
1
#Clocks
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move Between Registers
MOVW
Rd, Rr
Copy Register Word
LDI
Rd, K
Load Immediate
Rd ← K
None
LD
Rd, X
Load Indirect
Rd ← (X)
None
2
LD
Rd, X+
Load Indirect and Post-Inc.
Rd ← (X), X ← X + 1
None
2
LD
Rd, - X
Load Indirect and Pre-Dec.
X ← X - 1, Rd ← (X)
None
2
LD
Rd, Y
Load Indirect
Rd ← (Y)
None
2
LD
Rd, Y+
Load Indirect and Post-Inc.
Rd ← (Y), Y ← Y + 1
None
2
LD
Rd, - Y
Load Indirect and Pre-Dec.
Y ← Y - 1, Rd ← (Y)
None
2
LDD
Rd,Y+q
Load Indirect with Displacement
Rd ← (Y + q)
None
2
LD
Rd, Z
Load Indirect
Rd ← (Z)
None
2
LD
Rd, Z+
Load Indirect and Post-Inc.
Rd ← (Z), Z ← Z+1
None
2
LD
Rd, -Z
Load Indirect and Pre-Dec.
Z ← Z - 1, Rd ← (Z)
None
2
LDD
Rd, Z+q
Load Indirect with Displacement
Rd ← (Z + q)
None
2
LDS
Rd, k
Load Direct from SRAM
Rd ← (k)
None
2
ST
X, Rr
Store Indirect
(X) ← Rr
None
2
ST
X+, Rr
Store Indirect and Post-Inc.
(X) ← Rr, X ← X + 1
None
2
ST
- X, Rr
Store Indirect and Pre-Dec.
X ← X - 1, (X) ← Rr
None
2
ST
Y, Rr
Store Indirect
(Y) ← Rr
None
2
ST
Y+, Rr
Store Indirect and Post-Inc.
(Y) ← Rr, Y ← Y + 1
None
2
ST
- Y, Rr
Store Indirect and Pre-Dec.
Y ← Y - 1, (Y) ← Rr
None
2
STD
Y+q,Rr
Store Indirect with Displacement
(Y + q) ← Rr
None
2
ST
Z, Rr
Store Indirect
(Z) ← Rr
None
2
ST
Z+, Rr
Store Indirect and Post-Inc.
(Z) ← Rr, Z ← Z + 1
None
2
ST
-Z, Rr
Store Indirect and Pre-Dec.
Z ← Z - 1, (Z) ← Rr
None
2
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q) ← Rr
None
2
STS
k, Rr
Store Direct to SRAM
(k) ← Rr
None
2
Load Program memory
R0 ← (Z)
None
3
LPM
LPM
Rd, Z
Load Program memory
Rd ← (Z)
None
3
LPM
Rd, Z+
Load Program memory and Post-Inc
Rd ← (Z), Z ← Z+1
None
3
Store Program memory
(Z) ← R1:R0
None
-
IN
Rd, P
In Port
Rd ← P
None
1
OUT
P, Rr
Out Port
P ← Rr
None
1
PUSH
Rr
Push Register on Stack
STACK ← Rr
None
2
POP
Rd
Pop Register from Stack
Rd ← STACK
None
2
SPM
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
I/O(P,b) ← 1
None
2
CBI
P,b
Clear Bit in I/O Register
I/O(P,b) ← 0
None
2
LSL
Rd
Logical Shift Left
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
1
ROR
Rd
Rotate Right Through Carry
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s) ← 1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s) ← 0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T ← Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b) ← T
None
1
SEC
Set Carry
C←1
C
1
CLC
Clear Carry
C←0
C
1
SEN
Set Negative Flag
N←1
N
1
CLN
Clear Negative Flag
N←0
N
1
SEZ
Set Zero Flag
Z←1
Z
1
CLZ
Clear Zero Flag
Z←0
Z
1
SEI
Global Interrupt Enable
I←1
I
1
CLI
Global Interrupt Disable
I←0
I
1
SES
Set Signed Test Flag
S←1
S
1
CLS
Clear Signed Test Flag
S←0
S
1
SEV
Set Twos Complement Overflow.
V←1
V
1
CLV
Clear Twos Complement Overflow
V←0
V
1
SET
Set T in SREG
T←1
T
1
CLT
Clear T in SREG
T←0
T
1
SEH
CLH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H←1
H←0
H
H
1
1
MCU CONTROL INSTRUCTIONS
11
2512JS–AVR–10/06
Mnemonics
Operands
Description
Operation
Flags
#Clocks
NOP
No Operation
None
1
SLEEP
Sleep
(see specific descr. for Sleep function)
None
1
WDR
Watchdog Reset
(see specific descr. for WDR/timer)
None
1
12
ATmega8515(L)
2512JS–AVR–10/06
ATmega8515(L)
Ordering Information
Speed (MHz)
8
16
Note:
Power Supply
2.7 - 5.5V
4.5 - 5.5V
Ordering Code
Package(1)
ATmega8515L-8AC
ATmega8515L-8PC
ATmega8515L-8JC
ATmega8515L-8MC(2)
44A
40P6
44J
44M1
ATmega8515L-8AI
ATmega8515L-8PI
ATmega8515L-8JI
ATmega8515L-8MI
ATmega8515L-8AU(2)
ATmega8515L-8PU(2)
ATmega8515L-8JU(2)
ATmega8515L-8MU(2)
44A
40P6
44J
44M1
44A
40P6
44J
44M1
ATmega8515-16AC
ATmega8515-16PC
ATmega8515-16JC
ATmega8515-16MC
44A
40P6
44J
44M1
ATmega8515-16AI
ATmega8515-16PI
ATmega8515-16JI
ATmega8515-16MI
ATmega8515-16AU(2)
ATmega8515-16PU(2)
ATmega8515-16JU(2)
ATmega8515-16MU(2)
44A
40P6
44J
44M1
44A
40P6
44J
44MI
Operation Range
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities..
2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green.
Package Type
44A
44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
40-lead, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44J
44-lead, Plastic J-Leaded Chip Carrier (PLCC)
44M1
44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
13
2512JS–AVR–10/06
Packaging Information
44A
PIN 1
B
PIN 1 IDENTIFIER
E1
e
E
D1
D
C
0˚~7˚
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
11.75
12.00
12.25
D1
9.90
10.00
10.10
E
11.75
12.00
12.25
E1
9.90
10.00
10.10
B
0.30
–
0.45
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.80 TYP
10/5/2001
R
14
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
REV.
44A
B
ATmega8515(L)
2512JS–AVR–10/06
ATmega8515(L)
40P6
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
0º ~ 15º
C
COMMON DIMENSIONS
(Unit of Measure = mm)
REF
MIN
NOM
MAX
A
–
–
4.826
A1
0.381
–
–
D
52.070
–
52.578
E
15.240
–
15.875
E1
13.462
–
13.970
B
0.356
–
0.559
B1
1.041
–
1.651
3.556
SYMBOL
eB
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
L
3.048
–
C
0.203
–
0.381
eB
15.494
–
17.526
e
NOTE
Note 2
Note 2
2.540 TYP
09/28/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
DRAWING NO.
40P6
REV.
B
15
2512JS–AVR–10/06
44J
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
D2/E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
17.399
–
17.653
D1
16.510
–
16.662
E
17.399
–
17.653
E1
16.510
–
16.662
D2/E2
14.986
–
16.002
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
16
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
44J
B
ATmega8515(L)
2512JS–AVR–10/06
ATmega8515(L)
44M1
D
Marked Pin# 1 ID
E
SEATING PLANE
A1
TOP VIEW
A3
A
K
L
Pin #1 Corner
D2
1
2
3
Option A
SIDE VIEW
Pin #1
Triangle
COMMON DIMENSIONS
(Unit of Measure = mm)
E2
Option B
Pin #1
Chamfer
(C 0.30)
SYMBOL
MIN
NOM
MAX
A
0.80
0.90
1.00
A1
–
0.02
0.05
A3
b
K
Option C
b
e
Pin #1
Notch
(0.20 R)
BOTTOM VIEW
0.25 REF
0.18
0.23
0.30
D
6.90
7.00
7.10
D2
5.00
5.20
5.40
E
6.90
7.00
7.10
E2
5.00
5.20
5.40
e
Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3.
NOTE
0.50 BSC
L
0.59
0.64
0.69
K
0.20
0.26
0.41
5/27/06
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead Pitch 0.50 mm,
5.20 mm Exposed Pad, Micro Lead Frame Package (MLF)
DRAWING NO.
44M1
REV.
G
17
2512JS–AVR–10/06
Errata
The revision letter in this section refers to the revision of the ATmega8515 device.
ATmega8515(L)
Rev. C and D
1. First Analog Comparator conversion may be delayed
If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices.
Problem Fix/Workaround
When the device has been powered or reset, disable then enable the Analog Comparator before the first conversion.
18
ATmega8515(L)
2512JS–AVR–10/06
ATmega8515(L)
Datasheet Revision
History
Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision.
Rev. 2512J-10/06
1. Updated TOP/BOTTOM description for all Timer/Counters Fast PWM mode.
2. Updated “Errata” on page 18.
Rev. 2512I-08/06
1. Updated “Ordering Information” on page 13.
Rev. 2512H-04/06
1. Added “Resources” on page 6.
2. Updated cross reference in “Phase Correct PWM Mode” on page 113.
3. Updated “Timer/Counter Interrupt Mask Register – TIMSK(1)” on page 124.
4. Updated “Serial Peripheral Interface – SPI” on page 126.
5. Removed obsolete section of “Calibration Byte” on page 181.
6. Updated Table 10 on page 38, Table 52 on page 120, Table 94 on page 196 and
Table 96 on page 199.
Rev. 2512G-03/05
1. MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame
Package QFN/MLF”.
2. Updated “Electrical Characteristics” on page 197
3. Updated “Ordering Information” on page 13.
Rev. 2512E-09/03
1. Updated “Calibrated Internal RC Oscillator” on page 39.
Rev. 2512E-09/03
1. Removed “Preliminary” from the datasheet.
2. Updated Table 18 on page 46 and “Absolute Maximum Ratings” and “DC
Characteristics” in “Electrical Characteristics” on page 197.
3. Updated chapter “ATmega8515 Typical Characteristics” on page 207.
Rev. 2512D-02/03
1. Added “EEPROM Write During Power-down Sleep Mode” on page 23.
2. Improved the description in “Phase Correct PWM Mode” on page 88.
3. Corrected OCn waveforms in Figure 53 on page 111.
4. Added note under “Filling the Temporary Buffer (page loading)” on page 173
about writing to the EEPROM during an SPM page load.
5. Updated Table 93 on page 195.
6. Updated “Packaging Information” on page 14.
19
2512JS–AVR–10/06
Rev. 2512C-10/02
1. Added “Using all Locations of External Memory Smaller than 64 KB” on page
31.
2. Removed all TBD.
3. Added description about calibration values for 2, 4, and 8 MHz.
4. Added variation in frequency of “External Clock” on page 40.
5. Added note about VBOT, Table 18 on page 46.
6. Updated about “Unconnected pins” on page 64.
7. Updated “16-bit Timer/Counter1” on page 97, Table 51 on page 119 and Table
52 on page 120.
8. Updated “Enter Programming Mode” on page 184, “Chip Erase” on page 184,
Figure 77 on page 187, and Figure 78 on page 188.
9. Updated “Electrical Characteristics” on page 197, “External Clock Drive” on
page 199, Table 96 on page 199 and Table 97 on page 200, “SPI Timing Characteristics” on page 200 and Table 98 on page 202.
10. Added “Errata” on page 18.
Rev. 2512B-09/02
1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.
Rev. 2512A-04/02
1. Initial.
20
ATmega8515(L)
2512JS–AVR–10/06
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Atmel Operations
Memory
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
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