AT83SND2C/AT89C51SND2C - Mature

Features
• MPEG I/II-Layer 3 Hardwired Decoder
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– Stand-alone MP3 Decoder
– 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency
– Separated Digital Volume Control on Left and Right Channels (Software Control
using 31 Steps)
– Bass, Medium, and Treble Control (31 Steps)
– Bass Boost Sound Effect
– Ancillary Data Extraction
– CRC Error and MPEG Frame Synchronization Indicators
20-bit Stereo Audio DAC
– 93 dB SNR playback stereo channel
– 32 Ohm/ 20 mW stereo headset drivers
– Stereo Line Level Input, Differential Mono Auxiliary Input
Programmable Audio Output for Interfacing with External Audio System
– PCM Format Compatible
– I2S Format Compatible
Mono Audio Power Amplifier
– 440mW on 8 Ohms Load
8-bit MCU C51 Core Based (FMAX = 20 MHz)
2304 Bytes of Internal RAM
64K Bytes of Code Memory
– AT89C51SND2C and 89SND2CMP3B: Flash (100K Erase/Write Cycles)
– AT83SND2C and 83SND2CMP3B: ROM
4K Bytes of Boot Flash Memory (AT89C51SND2C and 89SND2CMP3B)
– ISP: Download from USB (standard) or UART (option)
USB Rev 1.1 Controller
– Full Speed Data Transmission
Built-in PLL
– MP3 Audio Clocks
– USB Clock
MultiMedia Card® Interface Compatibility
Atmel DataFlash® SPI Interface Compatibility
IDE/ATAPI Interface
2 Channels 10-bit ADC 8 kHz (8-true bit) for AT8XSND2CMP3B
– Battery Voltage Monitoring
– Voice Recording Controller by Software
Up to 32 Bits of General-purpose I/Os
– 1 Interrupt Keyboard
– SmartMedia® Software Interface
2 Standard 16-bit Timers/Counters
Hardware Watchdog Timer
Standard Full Duplex UART with Baud Rate Generator
Two Wire Master and Slave Modes Controller
SPI Master and Slave Modes Controller
Power Management
– Power-on Reset
– Software Programmable MCU Clock
– Idle Mode, Power-down Mode
Operating Conditions:
– 2.7 to 3.6V
– Power amplifier supply 3.2V to 5.5V
– 37mA Typical Operating at 25°C playing music on earphone
– Temperature Range: -40°C to +85°C
Packages
– CTBGA100
Single-Chip
Flash
Microcontroller
with MP3
Decoder with
Full Audio
Interface
AT83SND2C
AT89C51SND2C
AT80SND2CMP3B
AT83SND2CMP3B
AT89SND2CMP3B
4341H–MP3–10/07
1. Description
The AT8xC51SND2C has been developed for handling MP3 ringing tones in mobile phones and
can replace sound generators while adding SD/MMC card reader, MP3 music decoding, and
connection of the cell phone to a PC through USB. Cell phones can also be used as a thumb
drive extending cell phone capabilities.
The AT8xC51SND2C are fully integrated stand-alone hardwired MPEG I/II-Layer 3 decoder with
a C51 microcontroller core handling data flow, MP3-player control, Stereo Audio DAC and Mono
Audio Power Amplifier for speaker control.
The AT89C51SND2C includes 64K Bytes of Flash memory and allows In-System Programming
through an embedded 4K Bytes of Boot Flash memory.
The AT83SND2C includes 64K Bytes of ROM memory.
The AT8xC51SND2C include 2304 Bytes of RAM memory.
The AT8xC51SND2C provides the necessary features for human interface like timers, keyboard
port, serial or parallel interface (USB, TWI, SPI, IDE), I2S output, and all external memory interface (NAND or NOR Flash, SmartMedia, MultiMedia, DataFlash cards).
The AT8XSND2CMP3B provides also ADC input to the previous configuration. 89SND2CMP3B
includes 64K Bytes of Flash memory. 83SND2CMP3B includes 64K Bytes of ROM memory.
In the following of the document, AT8xC51SND2C refers to the generic product. When named
explicitly, AT8XSND2CMP3B refers to the version with A/D converter.
2. Typical Applications
• MP3-Player
• PDA, Camera, Mobile Phone MP3
• Car Audio/Multimedia MP3
• Home Audio/Multimedia MP3
2
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
3. Block Diagram
Figure 3-1.
AT8xC51SND2C / AT8XSND2CMP3B Block Diagram
ISP ALE
VDD
VSS UVDD UVSS
3
FILT
X1
X2
Clock and PLL
Unit
C51 (X2 Core)
Interrupt
Handler Unit
INT0
3
INT1
RST
(ADC is available on
8xSND2CMP3B only)
10-bit A to D
Converter
AREF
AIN1:0
D+
D-
P0-P4
USB
Controller
RAM
2304Bytes
I/OPorts
IDE
Interface
Flash
ROM
64 KBytes
Flash Boot
4 KBytes
DOUT
DCLK
DSEL
I2S/PCM
Audio
Interface
SCLK
8-Bit Internal Bus
MP3
Decoder
Unit
Keyboard
Interface
UART
and
BRG
Timers 0/1
Watchdog
HSR
HSL
AUXP
AUXN
Audio
DAC
LINEL
LINER
MONOP
MONON
SPI/DataFlash
Controller
TWI
Controller
KIN0
3
TXD
3
RXD
3
3
T0
4
4
4
4
T1
SS
MISO
MOSI
SCK
SCL
SDA
MCLK
PAINP
PAINN
HPP
HPN
Audio
PA
MMC
Interface
MDAT
MCMD
3 Alternate function of Port 3
4 Alternate function of Port 4
3
4341H–MP3–10/07
4. Pin Description
4.1
Pinouts
Figure 4-1.
10
9
8
7
6
5
4
3
2
1
NC
NC
P2.0/
A8
P4.1/
MOSI
VDD
VSS
NC
AUXP
AUXN
ALE
A
VDD
P2.2/
A10
P2.1/
A9
P4.0/
MISO
P4.2/
SCK
MONON
MONOP
P0.0/
AD0
KIN0
ISP/
NC
B
P2.4/
A12
P2.3/
A11
P2.5/
A13
P4.3/
SS
P0.6/
AD6
P0.4/
AD4
P0.3/
AD3
P0.2/
AD2
P0.1/
AD1
NC
C
P2.6/
A14
P2.7/
A15
MCLK
NC
P0.7/
AD7
P0.5/
AD5
NC
NC
NC
NC
D
EA
VSS
VDD
ESDVSS
VDD
SDA
AUDVREF
SCL
HSL
AUDVDD
E
MCMD
MDAT
NC
P3.2/
INT0
P3.1/
TXD
VSS
FILT
PVDD
HSR
HSVDD
F
RST
AUDRST
SCLK
DSEL
P3.4/
T0
P3.0/
RXD
LINER
LINEL
PVSS
HSVSS
G
NC
VSS
DOUT
DCLK
P3.5/
T1
TST
X1
INGND
AUDVSS
H
VDD
AUDVSS
CBP
LPHN
P3.7/
RD
P3.6/
WR
VSS
D-
D+
AUDVCM
J
PAINP
PAINN
HPP
AUDVBAT
HPN
AUDVSS
P3.3/
INT1
VDD
UVDD
UVSS
Notes:
4
AT8xC51SND2C 100-pin BGA Package (no ADC)
X2
K
1. ISP pin is only available in AT89C51SND2C product.
Do not connect this pin on AT83SND2C product.
2. NC is Do Not Connect.
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
4.2
Figure 4-2.
10
9
P2.2/
A10
AT8XSND2CMP3B 100-pin BGA Package (with ADC)
8
7
6
P2.1/
A9
P4.0/
MISO
ESDVSS
VDD
VSS
P2.3/
A11
P2.4/
A12
P2.0/
A8
P4.2/
SCK
P0.7/
AD7
VDD
P2.5/
A13
P4.1/
MOSI
P4.3/
SS
VSS
P2.6/
A14
P2.7/
A15
VDD
EA
FILT
MCMD
MCLK
MDAT
AIN1
SCLK
AUDRST
RST
AIN0
DCLK
DOUT
DSEL
ADCV
REFP
VSS
PAINP
PAINN
ADCV
REFN
ESDVSS
AUDVSS
HPP
Notes:
5
4
3
2
P0.0/
AD0
1
ALE
A
ISP/
NC
B
MONON
MONOP
P0.5/
AD5
P0.3/
AD3
AUXP
P0.1/
AD1
P0.6/
AD6
P0.4/
AD4
P0.2/
AD2
AUXN
KIN0
AUDVDD
C
SDA
NC
NC
NC
NC
NC
VDD
D
CBP
HSL
AUDVREF
AUDVCM
HSR
SCL
HSVDD
E
P3.7/
RD
TST
LINEL
PVDD
HSVSS
F
P3.4/
T0
P3.0/
RXD
PVSS
LINER
VSS
G
ADCVSS
P3.6/
WR
P3.1/
TXD
X2
INGND
AUDVSS
H
P3.3/
INT1
P3.5/
T1
P3.2/
INT0
X1
D+
UVDD
J
D-
VDD
UVSS
ADCVDD
LPHN
AUDVBAT AUDVBAT
HPN
AUDVSS
K
1. ISP pin is only available in 89SND2CMP3B product.
Do not connect this pin on 83SND2CMP3B product.
2. NC is Do Not Connect.
5
4341H–MP3–10/07
4.3
Signals
All the AT8xC51SND2C and AT8XSND2CMP3B signals are detailed by functionality in Table 41 to Table 14.
Table 4-1.
Ports Signal Description
Signal
Name
Type
Description
P0.7:0
I/O
Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written
to them float and can be used as high impedance inputs. To avoid any parasitic
current consumption, floating P0 inputs must be polarized to VDD or VSS.
P2.7:0
I/O
Port 2
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
Alternate
Function
AD7:0
A15:8
RXD
TXD
P3.7:0
I/O
Port 3
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
P4.3:0
I/O
Port 4
P4 is an 8-bit bidirectional I/O port with internal pull-ups.
Table 4-2.
Signal
Name
INT0
INT1
T0
T1
WR
RD
MISO
MOSI
SCK
SS
Clock Signal Description
Type
Description
Alternate
Function
X1
I
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this pin.
If an external oscillator is used, its output is connected to this pin. X1 is the
clock source for internal timing.
X2
O
Output of the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this pin.
If an external oscillator is used, leave X2 unconnected.
-
FILT
I
PLL Low Pass Filter input
FILT receives the RC network of the PLL low pass filter.
-
Table 4-3.
Signal
Name
-
Timer 0 and Timer 1 Signal Description
Type
Description
Alternate
Function
Timer 0 Gate Input
INT0 serves as external run control for timer 0, when selected by GATE0 bit in
TCON register.
INT0
6
I
External Interrupt 0
INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set, bit IE0
is set by a falling edge on INT0#. If bit IT0 is cleared, bit IE0 is set by a low
level on INT0#.
P3.2
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Signal
Name
Type
Description
Alternate
Function
Timer 1 Gate Input
INT1 serves as external run control for timer 1, when selected by GATE1 bit in
TCON register.
INT1
I
T0
I
Timer 0 External Clock Input
When timer 0 operates as a counter, a falling edge on the T0 pin increments
the count.
P3.4
T1
I
Timer 1 External Clock Input
When timer 1 operates as a counter, a falling edge on the T1 pin increments
the count.
P3.5
Table 4-4.
External Interrupt 1
INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set, bit IE1
is set by a falling edge on INT1#. If bit IT1 is cleared, bit IE1 is set by a low
level on INT1#.
P3.3
Audio Interface Signal Description
Signal
Name
Type
DCLK
O
DAC Data Bit Clock
-
DOUT
O
DAC Audio Data Output
-
DSEL
O
DAC Channel Select Signal
DSEL is the sample rate clock output.
-
SCLK
O
DAC System Clock
SCLK is the oversampling clock synchronized to the digital audio data (DOUT)
and the channel selection signal (DSEL).
-
Table 4-5.
Description
Alternate
Function
USB Controller Signal Description
Signal
Name
Type
D+
I/O
USB Positive Data Upstream Port
This pin requires an external 1.5 KΩ pull-up to VDD for full speed operation.
-
D-
I/O
USB Negative Data Upstream Port
-
Table 4-6.
Description
Alternate
Function
MutiMediaCard Interface Signal Description
Signal
Name
Type
MCLK
O
MMC Clock output
Data or command clock transfer.
-
MCMD
I/O
MMC Command line
Bidirectional command channel used for card initialization and data transfer
commands. To avoid any parasitic current consumption, unused MCMD input
must be polarized to VDD or VSS.
-
MDAT
I/O
MMC Data line
Bidirectional data channel. To avoid any parasitic current consumption, unused
MDAT input must be polarized to VDD or VSS.
-
Description
Alternate
Function
7
4341H–MP3–10/07
Table 4-7.
UART Signal Description
Signal
Name
Type
RXD
I/O
Receive Serial Data
RXD sends and receives data in serial I/O mode 0 and receives data in serial
I/O modes 1, 2 and 3.
P3.0
TXD
O
Transmit Serial Data
TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O
modes 1, 2 and 3.
P3.1
Table 4-8.
Alternate
Function
SPI Controller Signal Description
Signal
Name
Type
MISO
I/O
SPI Master Input Slave Output Data Line
When in master mode, MISO receives data from the slave peripheral. When in
slave mode, MISO outputs data to the master controller.
P4.0
MOSI
I/O
SPI Master Output Slave Input Data Line
When in master mode, MOSI outputs data to the slave peripheral. When in
slave mode, MOSI receives data from the master controller.
P4.1
SCK
I/O
SPI Clock Line
When in master mode, SCK outputs clock to the slave peripheral. When in
slave mode, SCK receives clock from the master controller.
P4.2
SS
I
SPI Slave Select Line
When in controlled slave mode, SS enables the slave mode.
P4.3
Table 4-9.
Signal
Name
Description
Alternate
Function
TWI Controller Signal Description
Type
Description
SCL
I/O
TWI Serial Clock
When TWI controller is in master mode, SCL outputs the serial clock to the
slave peripherals. When TWI controller is in slave mode, SCL receives clock
from the master controller.
SDA
I/O
TWI Serial Data
SDA is the bidirectional Two Wire data line.
Table 4-10.
8
Description
Alternate
Function
-
-
Keypad Interface Signal Description
Signal
Name
Type
KIN0
I
Description
Keypad Input Line
Holding this pin high or low for 24 oscillator periods triggers a keypad interrupt.
Alternate
Function
-
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 4-11.
A/D Converter Signal Description (AT8XSND2CMP3B only)
Signal
Name
Type
AIN1:0
I
A/D Analog Inputs
-
ADCREFP
I
Analog Positive Voltage Reference Input
-
ADCREFN
I
Analog Negative Voltage Reference Input
-
Table 4-12.
Description
Alternate
Function
External Access Signal Description
Signal
Name
Type
A15:8
I/O
Address Lines
Upper address lines for the external bus.
Multiplexed higher address and data lines for the IDE interface.
P2.7:0
AD7:0
I/O
Address/Data Lines
Multiplexed lower address and data lines for the external memory or the IDE
interface.
P0.7:0
ALE
O
Address Latch Enable Output
ALE signals the start of an external bus cycle and indicates that valid address
information is available on lines A7:0. An external latch is used to demultiplex
the address from address/data bus.
-
ISP
I/O
ISP Enable Input (AT89C51SND2C Only)
This signal must be held to GND through a pull-down resistor at the falling
reset to force execution of the internal bootloader.
-
RD
O
Read Signal
Read signal asserted during external data memory read operation.
P3.7
WR
O
Write Signal
Write signal asserted during external data memory write operation.
P3.6
EA(1)
I
External Access Enable: EA must be externally held low to enable the device
to fetch code from external program memory locations 0000H to FFFFH (RD).
Note:
Alternate
Function
-
1. For ROM/Flash/ROMless Dice product versions only.
Table 4-13.
Signal
Name
Description
System Signal Description
Type
Description
RST
I
Reset Input
Holding this pin high for 64 oscillator periods while the oscillator is running
resets the device. The Port pins are driven to their reset conditions when a
voltage lower than VIL is applied, whether or not the oscillator is running.
This pin has an internal pull-down resistor which allows the device to be reset
by connecting a capacitor between this pin and VDD.
Asserting RST when the chip is in Idle mode or Power-Down mode returns the
chip to normal operation.
TST
I
Test Input
Test mode entry signal. This pin must be set to VDD.
Alternate
Function
-
-
9
4341H–MP3–10/07
Table 4-14.
Signal
Name
Type
Description
VDD
PWR
Digital Supply Voltage
Connect these pins to +3V supply voltage.
-
VSS
GND
Circuit Ground
Connect these pins to ground.
-
ADCVDD
PWR
Analog Supply Voltage
Connect this pin to +3V supply voltage.
-
ADCVSS
PWR
Analog Ground
Connect this pin to ground.
-
PVDD
PWR
PLL Supply voltage
Connect this pin to +3V supply voltage.
-
PVSS
GND
PLL Circuit Ground
Connect this pin to ground.
-
UVDD
PWR
USB Supply Voltage
Connect this pin to +3V supply voltage.
-
UVSS
GND
USB Ground
Connect this pin to ground.
-
Table 4-15.
Alternate
Function
Audio Power Signal Description
Alternate
Function
Signal Name
Type
Description
AUDVDD
PWR
Audio Digital Supply Voltage
-
AUDVSS
GND
Audio Circuit Ground
Connect these pins to ground.
-
ESDVSS
GND
AUDVREF
PWR
Audio Voltage Reference pin for decoupling.
-
HSVDD
PWR
Headset Driver Power Supply.
-
HSVSS
GND
AUDVBAT
PWR
Table 4-16.
10
Power Signal Description
Audio Analog Circuit Ground for Electrostatic Discharge.
Connect this pin to ground.
Headset Driver Ground.
Connect this pin to ground.
Audio Amplifier Supply.
-
-
Stereo Audio Dac and Mono Power Amplifier Signal Description
Description
Alternate
Function
Signal Name
Type
LPHN
O
Low Power Audio Stage Output
-
HPN
O
Negative Speaker Output
-
HPP
O
Positivie Speaker Output
-
CBP
O
Audio Amplifier Common Mode Voltage Decoupling
-
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Description
Alternate
Function
Signal Name
Type
PAINN
I
Audio Amplifier Negative Input
-
PAINP
I
Audio Amplifier Positive Input
-
AUDRST
I
Audio Reset (Active Low)
-
MONON
O
Audio Negative Monaural Driver Output
-
MONOP
O
Audio Positive Monaural Driver Output
-
AUXP
I
Audio Mono Auxiliary Positive Input
-
AUXN
I
Audio Mono Auxiliary Negative Input
-
HSL
O
Audio Left Channel Headset Driver Output
-
HSR
O
Audio Right Channel Headset Driver Output
-
LINEL
I
Audio Left Channel Line In
-
LINER
I
Audio Right Channel Line In
-
INGND
I
Audio Line Signal Ground Pin for decoupling.
-
AUDVCM
I
Audio Common Mode reference for decoupling
-
11
4341H–MP3–10/07
4.4
Internal Pin Structure
Table 4-17.
Detailed Internal Pin Structure
Circuit(1)
Type
Pins
Input
TST
Input/Output
RST
Input/Output
P3
P4
RTST
VDD
VDD
P
RRST
Watchdog Output
VSS
2 osc
periods
Latch Output
VDD
VDD
VDD
P1
P2
P3
N
VSS
VDD
P
Input/Output
P0
MCMD
MDAT
ISP
N
PSEN
VSS
ALE
SCLK
DCLK
VDD
P
Output
DOUT
DSEL
MCLK
N
VSS
D+
Input/Output
D+
D-
D-
Notes:
12
1. For information on resistors value, input/output levels, and drive capability, refer to the
Section “DC Characteristics”, page 201.
2. When the Two Wire controller is enabled, P3 transistors are disabled allowing pseudo opendrain structure.
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
5. Clock Controller
The AT8xC51SND2C clock controller is based on an on-chip oscillator feeding an on-chip Phase
Lock Loop (PLL). All internal clocks to the peripherals and CPU core are generated by this
controller.
5.1
Oscillator
The AT8xC51SND2C X1 and X2 pins are the input and the output of a single-stage on-chip
inverter (see Figure 5-1) that can be configured with off-chip components such as a Pierce oscillator (see Figure 5-2). Value of capacitors and crystal characteristics are detailed in the section
“DC Characteristics”.
The oscillator outputs three different clocks: a clock for the PLL, a clock for the CPU core, and a
clock for the peripherals as shown in Figure 5-1. These clocks are either enabled or disabled,
depending on the power reduction mode as detailed in the section “Power Management” on
page 47. The peripheral clock is used to generate the Timer 0, Timer 1, MMC, SPI, and Port
sampling clocks.
Figure 5-1.
Oscillator Block Diagram and Symbol
X1
0
÷2
Peripheral
Clock
1
CPU Core
Clock
X2
X2
CKCON.0
IDL
PCON.0
PD
Oscillator
Clock
PCON.1
PER
CLOCK
CPU
CLOCK
Peripheral Clock Symbol
Figure 5-2.
OSC
CLOCK
CPU Core Clock Symbol
Oscillator Clock Symbol
Crystal Connection
X1
C1
Q
C2
VSS
X2
13
4341H–MP3–10/07
5.2
X2 Feature
Unlike standard C51 products that require 12 oscillator clock periods per machine cycle, the
AT8xC51SND2C need only 6 oscillator clock periods per machine cycle. This feature called the
“X2 feature” can be enabled using the X2 bit (1) in CKCON (see Table 5-1) and allows the
AT8xC51SND2C to operate in 6 or 12 oscillator clock periods per machine cycle. As shown in
Figure 5-1, both CPU and peripheral clocks are affected by this feature. Figure 5-3 shows the X2
mode switching waveforms. After reset the standard mode is activated. In standard mode the
CPU and peripheral clock frequency is the oscillator frequency divided by 2 while in X2 mode, it
is the oscillator frequency.
Note:
1. The X2 bit reset value depends on the X2B bit in the Hardware Security Byte (see Table 6-3
on page 22). Using the AT89C51SND2C (Flash Version) the system can boot either in standard or X2 mode depending on the X2B value. Using AT83SND2C (ROM Version) the system
always boots in standard mode. X2B bit can be changed to X2 mode later by software.
Figure 5-3.
Mode Switching Waveforms
X1
X1 ÷ 2
X2 Bit
Clock
STD Mode
Note:
5.3
5.3.1
X2 Mode(1)
STD Mode
1. In order to prevent any incorrect operation while operating in X2 mode, user must be aware
that all peripherals using clock frequency as time reference (timers, etc.) will have their time
reference divided by 2. For example, a free running timer generating an interrupt every 20 ms
will then generate an interrupt every 10 ms.
PLL
PLL Description
The AT8xC51SND2C PLL is used to generate internal high frequency clock (the PLL Clock) synchronized with an external low-frequency (the Oscillator Clock). The PLL clock provides the MP3
decoder, the audio interface, and the USB interface clocks. Figure 5-4 shows the internal structure of the PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. This block makes the
comparison between the reference clock coming from the N divider and the reverse clock coming from the R divider and generates some pulses on the Up or Down signal depending on the
edge position of the reverse clock. The PLLEN bit in PLLCON register is used to enable the
clock generation. When the PLL is locked, the bit PLOCK in PLLCON register (see Table 5-2) is
set.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by injecting or extracting charges from the external filter connected on PFILT pin (see Figure 5-5). Value
of the filter components are detailed in the Section “DC Characteristics”.
The VCO block is the Voltage Controlled Oscillator controlled by the voltage Vref produced by the
charge pump. It generates a square wave signal: the PLL clock.
14
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Figure 5-4.
PLL Block Diagram and Symbol
PFILT
PLLCON.1
PLLEN
N divider
OSC
CLOCK
Up
N6:0
PFLD
CHP
Vref
VCO
Down
PLOCK
PLL
Clock
R divider
PLLCON.0
R9:0
PLL
CLOCK
OSCclk × ( R + 1 )
PLLclk = ----------------------------------------------N+1
PLL Clock Symbol
Figure 5-5.
PLL Filter Connection
FILT
R
C2
C1
VSS
5.3.2
VSS
PLL Programming
The PLL is programmed using the flow shown in Figure 5-6. As soon as clock generation is
enabled, the user must wait until the lock indicator is set to ensure the clock output is stable. The
PLL clock frequency will depend on MP3 decoder clock and audio interface clock frequencies.
Figure 5-6.
PLL Programming Flow
PLL
Programming
Configure Dividers
N6:0 = xxxxxxb
R9:0 = xxxxxxxxxxb
Enable PLL
PLLRES = 0
PLLEN = 1
PLL Locked?
PLOCK = 1?
15
4341H–MP3–10/07
5.4
Registers
Table 5-1.
CKCON Register
CKCON (S:8Fh) – Clock Control Register
7
6
5
4
3
2
1
0
TWIX2
WDX2
-
SIX2
-
T1X2
T0X2
X2
Bit Number
Bit
Mnemonic
Description
7
TWIX2
Two-Wire Clock Control Bit
Set to select the oscillator clock divided by 2 as TWI clock input (X2 independent).
Clear to select the peripheral clock as TWI clock input (X2 dependent).
6
WDX2
Watchdog Clock Control Bit
Set to select the oscillator clock divided by 2 as watchdog clock input (X2 independent).
Clear to select the peripheral clock as watchdog clock input (X2 dependent).
5
-
4
SIX2
3
-
2
T1X2
Timer 1 Clock Control Bit
Set to select the oscillator clock divided by 2 as timer 1 clock input (X2 independent).
Clear to select the peripheral clock as timer 1 clock input (X2 dependent).
1
T0X2
Timer 0 Clock Control Bit
Set to select the oscillator clock divided by 2 as timer 0 clock input (X2 independent).
Clear to select the peripheral clock as timer 0 clock input (X2 dependent).
0
X2
Reserved
The values read from this bit is indeterminate. Do not set this bit.
Enhanced UART Clock (Mode 0 and 2) Control Bit
Set to select the oscillator clock divided by 2 as UART clock input (X2 independent).
Clear to select the peripheral clock as UART clock input (X2 dependent)..
Reserved
The values read from this bit is indeterminate. Do not set this bit.
System Clock Control Bit
Clear to select 12 clock periods per machine cycle (STD mode, FCPU = FPER = FOSC/2).
Set to select 6 clock periods per machine cycle (X2 mode, FCPU = FPER = FOSC).
Reset Value = 0000 000Xb (AT89C51SND2C) or 0000 0000b (AT83SND2C)
Table 5-2.
PLLCON Register
PLLCON (S:E9h) – PLL Control Register
16
7
6
5
4
3
2
1
0
R1
R0
-
-
PLLRES
-
PLLEN
PLOCK
Bit Number
Bit
Mnemonic
Description
7-6
R1:0
5-4
-
3
PLLRES
2
-
PLL Least Significant Bits R Divider
2 LSB of the 10-bit R divider.
Reserved
The values read from these bits are always 0. Do not set these bits.
PLL Reset Bit
Set this bit to reset the PLL.
Clear this bit to free the PLL and allow enabling.
Reserved
The value read from this bit is always 0. Do not set this bit.
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Bit Number
Bit
Mnemonic
1
PLLEN
PLL Enable Bit
Set to enable the PLL.
Clear to disable the PLL.
0
PLOCK
PLL Lock Indicator
Set by hardware when PLL is locked.
Clear by hardware when PLL is unlocked.
Description
Reset Value = 0000 1000b
Table 5-3.
PLLNDIV Register
PLLNDIV (S:EEh) – PLL N Divider Register
7
6
5
4
3
2
1
0
-
N6
N5
N4
N3
N2
N1
N0
Bit Number
Bit
Mnemonic
Description
7
-
6-0
N6:0
Reserved
The value read from this bit is always 0. Do not set this bit.
PLL N Divider
7 - bit N divider.
Reset Value = 0000 0000b
Table 5-4.
PLLRDIV Register
PLLRDIV (S:EFh) – PLL R Divider Register
7
6
5
4
3
2
1
0
R9
R8
R7
R6
R5
R4
R3
R2
Bit Number
Bit
Mnemonic
Description
7-0
R9:2
PLL Most Significant Bits R Divider
8 MSB of the 10-bit R divider.
Reset Value = 0000 0000b
17
4341H–MP3–10/07
6. Program/Code Memory
The AT8xC51SND2C execute up to 64K Bytes of program/code memory. Figure 6-1 shows the
split of internal and external program/code memory spaces depending on the product.
The AT83SND2C product provides the internal program/code memory in ROM memory while
the AT89C51SND2C product provides it in Flash memory. These 2 products do not allow external code memory execution.
The Flash memory increases EPROM and ROM functionality by in-circuit electrical erasure and
programming. The high voltage needed for programming or erasing Flash cells is generated onchip using the standard VDD voltage, made possible by the internal charge pump. Thus, the
AT89C51SND2C can be programmed using only one voltage and allows In-application software
programming. Hardware programming mode is also available using common programming
tools. See the application note ‘Programming T89C51x and AT89C51x with Device
Programmers’.
The AT89C51SND2C implements an additional 4K Bytes of on-chip boot Flash memory provided in Flash memory. This boot memory is delivered programmed with a standard boot loader
software allowing In-System Programming (ISP). It also contains some Application Programming Interface routines named API routines allowing In Application Programming (IAP) by using
user’s own boot loader.
Figure 6-1.
Program/Code Memory Organization
FFFFh
FFFFh
FFFFh
F000h
F000h
64K Bytes
Code ROM
0000h
18
AT83SND2C
4K Bytes
Boot Flash
64K Bytes
Code Flash
0000h
AT89C51SND2C
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
6.1
ROM Memory Architecture
As shown in Figure 6-2 the AT83SND2C ROM memory is composed of one space detailed in
the following paragraph.
Figure 6-2.
AT83SND2C Memory Architecture
FFFFh
64K Bytes
User
ROM Memory
0000h
6.1.1
User Space
This space is composed of a 64K Bytes ROM memory programmed during the manufacturing
process. It contains the user’s application code.
6.2
Flash Memory Architecture
As shown in Figure 6-3 the AT89C51SND2C Flash memory is composed of four spaces detailed
in the following paragraphs.
Figure 6-3.
AT89C51SND2C Memory Architecture
Hardware Security
Extra Row
FFFFh
FFFFh
4K Bytes
Flash
Memory
F000h
Boot
64K Bytes
User
Flash Memory
0000h
6.2.1
User Space
This space is composed of a 64K Bytes Flash memory organized in 512 pages of 128 Bytes. It
contains the user’s application code.
This space can be read or written by both software and hardware modes.
6.2.2
Boot Space
This space is composed of a 4K Bytes Flash memory. It contains the boot loader for In-System
Programming and the routines for In Application Programming.
This space can only be read or written by hardware mode using a parallel programming tool.
19
4341H–MP3–10/07
6.2.3
Hardware Security Space
This space is composed of one Byte: the Hardware Security Byte (HSB see Table 6-3) divided in
2 separate nibbles. The MSN contains the X2 mode configuration bit and the Boot Loader Jump
Bit as detailed in Section “Boot Memory Execution”, page 20 and can be written by software
while the LSN contains the lock system level to protect the memory content against piracy as
detailed in Section “Hardware Security System”, page 20 and can only be written by hardware.
6.2.4
Extra Row Space
This space is composed of 2 Bytes:
6.3
•
The Software Boot Vector (SBV, see Table 6-4).
This Byte is used by the software boot loader to build the boot address.
•
The Software Security Byte (SSB, see Table 6-5).
This Byte is used to lock the execution of some boot loader commands.
Hardware Security System
The AT89C51SND2C implements three lock bits LB2:0 in the LSN of HSB (see Table 6-3) providing three levels of security for user’s program as described in Table 6-1 while the
AT83SND2C is always set in read disabled mode.
Level 0 is the level of an erased part and does not enable any security feature.
Level 1 locks the hardware programming of both user and boot memories.
Level 2 locks also hardware verifying of both user and boot memories
Level 3 locks also the external execution.
Table 6-1.
Level
LB2
LB1
LB0
Internal
Execution
External
Execution
Hardware
Verifying
Hardware
Programming
Software
Programming
0
U
U
U
Enable
Enable
Enable
Enable
Enable
1
U
U
P
Enable
Enable
Enable
Disable
Enable
2
U
P
X
Enable
Enable
Disable
Disable
Enable
P
X
X
Enable
Disable
Disable
Disable
Enable
3(3)
Notes:
6.4
Lock Bit Features(1)
1. U means unprogrammed, P means programmed and X means don’t care (programmed or
unprogrammed).
2. AT89C51SND2C products are delivered with third level programmed to ensure that the code
programmed by software using ISP or user’s boot loader is secured from any hardware piracy.
Boot Memory Execution
As internal C51 code space is limited to 64K Bytes, some mechanisms are implemented to allow
boot memory to be mapped in the code space for execution at addresses from F000h to FFFFh.
The boot memory is enabled by setting the ENBOOT bit in AUXR1 (see Figure 6-2). The three
ways to set this bit are detailed in the following sections.
6.4.1
Software Boot Mapping
The software way to set ENBOOT consists in writing to AUXR1 from the user’s software. This
enables boot loader or API routines execution.
20
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
6.4.2
Hardware Condition Boot Mapping
The hardware condition is based on the ISP pin. When driving this pin to low level, the chip reset
sets ENBOOT and forces the reset vector to F000h instead of 0000h in order to execute the
boot loader software.
As shown in Figure 6-4 the hardware condition always allows in-system recovery when user’s
memory has been corrupted.
6.4.3
Programmed Condition Boot Mapping
The programmed condition is based on the Boot Loader Jump Bit (BLJB) in HSB. As shown in
Figure 6-4 when this bit is programmed (by hardware or software programming mode), the chip
reset set ENBOOT and forces the reset vector to F000h instead of 0000h, in order to execute
the boot loader software.
Figure 6-4.
Hardware Boot Process Algorithm
RESET
Hard Cond?
Software
Process
Hardware
Process
ISP = L?
Prog Cond?
BLJB = P?
Standard Init
ENBOOT = 0
PC = 0000h
FCON = F0h
Prog Cond Init
ENBOOT = 1
PC = F000h
FCON = F0h
User’s
Application
Atmel’s
Boot Loader
Hard Cond Init
ENBOOT = 1
PC = F000h
FCON = 00h
The software process (boot loader) is detailed in the “Boot Loader Datasheet” Document.
6.5
Preventing Flash Corruption
See Section “Reset Recommendation to Prevent Flash Corruption”, page 48.
21
4341H–MP3–10/07
6.6
Registers
Table 6-2.
AUXR1 Register
AUXR1 (S:A2h) – Auxiliary Register 1
7
6
5
4
3
2
1
0
-
-
ENBOOT
-
GF3
0
-
DPS
Bit Number
Bit
Mnemonic
Description
7-6
-
Reserved
The value read from these bits are indeterminate. Do not set these bits.
1
Enable Boot Flash
Set this bit to map the boot Flash in the code space between at addresses F000h to
FFFFh.
Clear this bit to disable boot Flash.
5
ENBOOT
4
-
3
GF3
2
0
Always Zero
This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3 flag.
1
-
Reserved for Data Pointer Extension.
0
DPS
Reserved
The value read from this bit is indeterminate. Do not set this bit.
General Flag
This bit is a general-purpose user flag.
Data Pointer Select Bit
Set to select second data pointer: DPTR1.
Clear to select first data pointer: DPTR0.
Reset Value = XXXX 00X0b
Note:
6.7
1. ENBOOT bit is only available in AT89C51SND2C product.
Hardware Bytes
Table 6-3.
22
HSB Byte – Hardware Security Byte
7
6
5
4
3
2
1
0
X2B
BLJB
-
-
-
LB2
LB1
LB0
Bit Number
Bit
Mnemonic
Description
7
X2B(1)
X2 Bit
Program this bit to start in X2 mode.
Unprogram (erase) this bit to start in standard mode.
6
BLJB(2)
Boot Loader Jump Bit
Program this bit to execute the boot loader at address F000h on next reset.
Unprogram (erase) this bit to execute user’s application at address 0000h on next reset.
5-4
-
3
-
2-0
LB2:0
Reserved
The value read from these bits is always unprogrammed. Do not program these bits.
Reserved
The value read from this bit is always unprogrammed. Do not program this bit.
Hardware Lock Bits
Refer to for bits description.
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Reset Value = XXUU UXXX, UUUU UUUU after an hardware full chip erase.
Note:
1. X2B initializes the X2 bit in CKCON during the reset phase.
2. In order to ensure boot loader activation at first power-up, AT89C51SND2C products are delivered with BLJB programmed.
3. Bits 0 to 3 (LSN) can only be programmed by hardware mode.
Table 6-4.
SBV Byte – Software Boot Vector
7
6
5
4
3
2
1
0
ADD15
ADD14
ADD13
ADD12
ADD11
ADD10
ADD9
ADD8
Bit Number
Bit
Mnemonic
Description
7-0
ADD15:8
MSB of the user’s boot loader 16-bit address location
Refer to the boot loader datasheet for usage information (boot loader dependent)
Reset Value = XXXX XXXX, UUUU UUUU after an hardware full chip erase.
Table 6-5.
SSB Byte – Software Security Byte
7
6
5
4
3
2
1
0
SSB7
SSB6
SSB5
SSB4
SSB3
SSB2
SSB1
SSB0
Bit Number
Bit
Mnemonic
Description
7-0
SSB7:0
Software Security Byte Data
Refer to the boot loader datasheet for usage information (boot loader dependent)
Reset Value = XXXX XXXX, UUUU UUUU after an hardware full chip erase.
23
4341H–MP3–10/07
7. Data Memory
The AT8xC51SND2C provides data memory access in 2 different spaces:
1. The internal space mapped in three separate segments:
–
The lower 128 Bytes RAM segment
–
The upper 128 Bytes RAM segment
–
The expanded 2048 Bytes RAM segment
2. The external space.
A fourth internal segment is available but dedicated to Special Function Registers, SFRs,
(addresses 80h to FFh) accessible by direct addressing mode. For information on this segment,
refer to the Section “Special Function Registers”, page 31.
Figure 7-1 shows the internal and external data memory spaces organization.
Figure 7-1.
Internal and External Data Memory Organization
FFFFh
64K Bytes
External XRAM
7FFh
FFh
2K Bytes
Internal ERAM
EXTRAM = 0
80h
7Fh
00h
7.1
7.1.1
FFh
Upper
128 Bytes
Internal RAM
Indirect Addressing
00h
Special
Function
Registers
Direct Addressing
80h
Lower
128 Bytes
Internal RAM
Direct or Indirect
Addressing
0800h
EXTRAM = 1
0000h
Internal Space
Lower 128 Bytes RAM
The lower 128 Bytes of RAM (see Figure 7-2) are accessible from address 00h to 7Fh using
direct or indirect addressing modes. The lowest 32 Bytes are grouped into 4 banks of 8 registers
(R0 to R7). 2 bits RS0 and RS1 in PSW register (see Table 7-4) select which bank is in use
according to Table 7-1. This allows more efficient use of code space, since register instructions
are shorter than instructions that use direct addressing, and can be used for context switching in
interrupt service routines.
Table 7-1.
24
Register Bank Selection
RS1
RS0
Description
0
0
Register bank 0 from 00h to 07h
0
1
Register bank 1 from 08h to 0Fh
1
0
Register bank 2 from 10h to 17h
1
1
Register bank 3 from 18h to 1Fh
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
The next 16 Bytes above the register banks form a block of bit-addressable memory space. The
C51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this
area can be directly addressed by these instructions. The bit addresses in this area are 00h to
7Fh.
Figure 7-2.
Lower 128 Bytes Internal RAM Organization
7Fh
30h
2Fh
20h
18h
10h
08h
00h
7.1.2
Bit-Addressable Space
(Bit Addresses 0-7Fh)
1Fh
17h
0Fh
4 Banks of
8 Registers
R0-R7
07h
Upper 128 Bytes RAM
The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect
addressing mode.
7.1.3
Expanded RAM
The on-chip 2K Bytes of expanded RAM (ERAM) are accessible from address 0000h to 07FFh
using indirect addressing mode through MOVX instructions. In this address range, EXTRAM bit
in AUXR register (see Table 7-5) is used to select the ERAM (default) or the XRAM. As shown in
Figure 7-1 when EXTRAM = 0, the ERAM is selected and when EXTRAM = 1, the XRAM is
selected (see Section “External Space”).
The ERAM memory can be resized using XRS1:0 bits in AUXR register to dynamically increase
external access to the XRAM space. Table 7-2 details the selected ERAM size and address
range.
Table 7-2.
Note:
7.2
7.2.1
ERAM Size Selection
XRS1
XRS0
ERAM Size
Address
0
0
256 Bytes
0 to 00FFh
0
1
512 Bytes
0 to 01FFh
1
0
1K Byte
0 to 03FFh
1
1
2K Bytes
0 to 07FFh
Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile memory
cells. This means that the RAM content is indeterminate after power-up and must then be initialized properly.
External Space
Memory Interface
The external memory interface comprises the external bus (port 0 and port 2) as well as the bus
control signals (RD, WR, and ALE).
25
4341H–MP3–10/07
Figure 7-3 shows the structure of the external address bus. P0 carries address A7:0 while P2
carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 7-3 describes the external memory interface signals.
Figure 7-3.
External Data Memory Interface Structure
RAM
PERIPHERAL
AT8xC51SND2C
A15:8
P2
A15:8
ALE
P0
AD7:0
Latch
A7:0
A7:0
D7:0
RD
WR
Table 7-3.
7.2.2
OE
WR
External Data Memory Interface Signals
Signal
Name
Type
Alternate
Function
A15:8
O
Address Lines
Upper address lines for the external bus.
P2.7:0
AD7:0
I/O
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
P0.7:0
ALE
O
Address Latch Enable
ALE signals indicates that valid address information are available on lines AD7:0.
RD
O
Read
Read signal output to external data memory.
P3.7
WR
O
Write
Write signal output to external memory.
P3.6
Description
-
Page Access Mode
The AT8xC51SND2C implement a feature called Page Access that disables the output of DPH
on P2 when executing MOVX @DPTR instruction. Page Access is enable by setting the DPHDIS bit in AUXR register.
Page Access is useful when application uses both ERAM and 256 Bytes of XRAM. In this case,
software modifies intensively EXTRAM bit to select access to ERAM or XRAM and must save it
if used in interrupt service routine. Page Access allows external access above 00FFh address
without generating DPH on P2. Thus ERAM is accessed using MOVX @Ri or MOVX @DPTR
with DPTR < 0100h, < 0200h, < 0400h or < 0800h depending on the XRS1:0 bits value. Then
XRAM is accessed using MOVX @DPTR with DPTR ≥ 0800h regardless of XRS1:0 bits value
while keeping P2 for general I/O usage.
7.2.3
External Bus Cycles
This section describes the bus cycles the AT8xC51SND2C executes to read (see Figure 7-4),
and write data (see Figure 7-5) in the external data memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period
26
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode,
refer to the Section “X2 Feature”, page 14.
Slow peripherals can be accessed by stretching the read and write cycles. This is done using the
M0 bit in AUXR register. Setting this bit changes the width of the RD and WR signals from 3 to
15 CPU clock periods.
For simplicity, Figure 7-4 and Figure 7-5 depict the bus cycle waveforms in idealized form and
do not provide precise timing information. For bus cycle timing parameters refer to the Section
“AC Characteristics”.
Figure 7-4.
External Data Read Waveforms
CPU Clock
ALE
RD(1)
P0
P2
Notes:
DPL or Ri
D7:0
DPH or P2(2),(3)
P2
1. RD signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 outputs SFR content instead of DPH.
Figure 7-5.
External Data Write Waveforms
CPU Clock
ALE
WR(1)
P0
P2
Notes:
7.3
7.3.1
DPL or Ri
P2
D7:0
DPH or P2(2),(3)
1. WR signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 outputs SFR content instead of DPH.
Dual Data Pointer
Description
The AT8xC51SND2C implement a second data pointer for speeding up code execution and
reducing code size in case of intensive usage of external memory accesses.
27
4341H–MP3–10/07
DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR addresses
83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Table 62) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 7-6).
Figure 7-6.
Dual Data Pointer Implementation
DPL0
0
DPL1
1
DPL
DPTR0
DPS
DPTR1
7.3.2
DPH0
0
DPH1
1
AUXR1.0
DPTR
DPH
Application
Software can take advantage of the additional data pointers to both increase speed and reduce
code size, for example, block operations (copy, compare, search …) are well served by using
one data pointer as a “source” pointer and the other one as a “destination” pointer.
Below is an example of block move implementation using the 2 pointers and coded in assembler. The latest C compiler also takes advantage of this feature by providing enhanced algorithm
libraries.
The INC instruction is a short (2 Bytes) and fast (6 CPU clocks) way to manipulate the DPS bit in
the AUXR1 register. However, note that the INC instruction does not directly force the DPS bit to
a particular state, but simply toggles it. In simple routines, such as the block move example, only
the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words,
the block move routine works the same whether DPS is '0' or '1' on entry.
;
;
;
;
ASCII block move using dual data pointers
Modifies DPTR0, DPTR1, A and PSW
Ends when encountering NULL character
Note: DPS exits opposite of entry state unless an extra INC AUXR1 is added
AUXR1
move:
EQU
mov
inc
mov
mv_loop: inc
movx
inc
inc
movx
inc
jnz
end_move:
28
0A2h
DPTR,#SOURCE
AUXR1
DPTR,#DEST
AUXR1
A,@DPTR
DPTR
AUXR1
@DPTR,A
DPTR
mv_loop
;
;
;
;
;
;
;
;
;
;
address of SOURCE
switch data pointers
address of DEST
switch data pointers
get a Byte from SOURCE
increment SOURCE address
switch data pointers
write the Byte to DEST
increment DEST address
check for NULL terminator
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
7.4
Registers
Table 7-4.
PSW Register
PSW (S:D0h) – Program Status Word Register
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
F1
P
Bit Number
Bit
Mnemonic
Description
7
CY
Carry Flag
Carry out from bit 1 of ALU operands.
6
AC
Auxiliary Carry Flag
Carry out from bit 1 of addition operands.
5
F0
User Definable Flag 0
4-3
RS1:0
Register Bank Select Bits
Refer to Table 7-1 for bits description.
2
OV
Overflow Flag
Overflow set by arithmetic operations.
1
F1
User Definable Flag 1
0
P
Parity Bit
Set when ACC contains an odd number of 1’s.
Cleared when ACC contains an even number of 1’s.
Reset Value = 0000 0000b
Table 7-5.
AUXR Register
AUXR (S:8Eh) – Auxiliary Control Register
7
6
5
4
3
2
1
0
-
EXT16
M0
DPHDIS
XRS1
XRS0
EXTRAM
AO
Bit Number
Bit
Mnemonic
Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
External 16-bit Access Enable Bit
Set to enable 16-bit access mode during MOVX instructions.
Clear to disable 16-bit access mode and enable standard 8-bit access mode during
MOVX instructions.
6
EXT16
5
M0
External Memory Access Stretch Bit
Set to stretch RD or WR signals duration to 15 CPU clock periods.
Clear not to stretch RD or WR signals and set duration to 3 CPU clock periods.
4
DPHDIS
DPH Disable Bit
Set to disable DPH output on P2 when executing MOVX @DPTR instruction.
Clear to enable DPH output on P2 when executing MOVX @DPTR instruction.
3-2
XRS1:0
Expanded RAM Size Bits
Refer to Table 7-2 for ERAM size description.
29
4341H–MP3–10/07
Bit Number
Bit
Mnemonic
1
EXTRAM
0
AO
Description
External RAM Enable Bit
Set to select the external XRAM when executing MOVX @Ri or MOVX @DPTR
instructions.
Clear to select the internal expanded RAM when executing MOVX @Ri or MOVX
@DPTR instructions.
ALE Output Enable Bit
Set to output the ALE signal only during MOVX instructions.
Clear to output the ALE signal at a constant rate of FCPU/3.
Reset Value = X000 1101b
30
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
8. Special Function Registers
The Special Function Registers (SFRs) of the AT8xC51SND2C derivatives fall into the categories detailed in Table 8-1 to Table . The relative addresses of these SFRs are provided together
with their reset values in Table 8-19. In this table, the bit-addressable registers are identified by
Note 1.
Table 8-1.
C51 Core SFRs
Mnemonic Add Name
ACC
E0h Accumulator
B
F0h B Register
PSW
D0h Program Status Word
SP
81h Stack Pointer
DPL
82h Data Pointer Low Byte
DPH
83h Data Pointer High Byte
Table 8-2.
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
F1
P
7
6
5
4
3
2
1
0
SMOD1
SMOD0
-
-
GF1
GF0
PD
IDL
M0
DPHDIS
XRS1
XRS0
EXTRAM
AO
1)
-
GF3
0
-
DPS
NV5
NV4
NV3
NV2
NV1
NV0
System Management SFRs
Mnemonic Add Name
PCON
87h Power Control
AUXR
8Eh Auxiliary Register 0
-
EXT16
AUXR1
A2h Auxiliary Register 1
-
-
NVERS
FBh Version Number
NV7
NV6
Note:
ENBOOT(
1. ENBOOT bit is only available in AT89C51SND2C product.
Table 8-3.
PLL and System Clock SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
CKCON
8Fh Clock Control
-
-
-
-
-
-
-
X2
PLLCON
E9h PLL Control
R1
R0
-
-
PLLRES
-
PLLEN
PLOCK
PLLNDIV
EEh PLL N Divider
-
N6
N5
N4
N3
N2
N1
N0
PLLRDIV
EFh PLL R Divider
R9
R8
R7
R6
R5
R4
R3
R2
7
6
5
4
3
2
1
0
Table 8-4.
Interrupt SFRs
Mnemonic Add Name
IEN0
A8h Interrupt Enable Control 0
EA
EAUD
EMP3
ES
ET1
EX1
ET0
EX0
IEN1
B1h Interrupt Enable Control 1
-
EUSB
-
EKB
-
ESPI
EI2C
EMMC
IPH0
B7h Interrupt Priority Control High 0
-
IPHAUD
IPHMP3
IPHS
IPHT1
IPHX1
IPHT0
IPHX0
IPL0
B8h Interrupt Priority Control Low 0
-
IPLAUD
IPLMP3
IPLS
IPLT1
IPLX1
IPLT0
IPLX0
IPH1
B3h Interrupt Priority Control High 1
-
IPHUSB
-
IPHKB
IPHADC
IPHSPI
IPHI2C
IPHMMC
31
4341H–MP3–10/07
Table 8-4.
Interrupt SFRs (Continued)
Mnemonic Add Name
7
6
5
4
3
2
1
0
IPL1
-
IPLUSB
-
IPLKB
IPLADC
IPLSPI
IPLI2C
IPLMMC
7
6
5
4
3
2
1
0
-
-
-
-
3
2
1
0
AUDCCL
K
AUDCCS
KIN0
B2h Interrupt Priority Control Low 1
Table 8-5.
Port SFRs
Mnemonic Add Name
P0
80h 8-bit Port 0
P2
A0h 8-bit Port 2
P3
B0h 8-bit Port 3
P4
C0h 4-bit Port 4
Table 8-6.
Auxiliary SFRs
Mnemonic Add Name
AUXCON
90h Auxiliary Control
Table 8-7.
Note:
6
5
SDA
SCL
-
4
AUDCDOU
AUDCDIN
T
Flash Memory SFR
Mnemonic Add Name
FCON(1)
7
D1h Flash Control
7
6
5
4
3
2
1
0
FPL3
FPL2
FPL1
FPL0
FPS
FMOD1
FMOD0
FBUSY
1. FCON register is only available in AT89C51SND2C product.
Table 8-8.
Timer SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
TCON
88h Timer/Counter 0 and 1 Control
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TMOD
89h Timer/Counter 0 and 1 Modes
GATE1
C/T1#
M11
M01
GATE0
C/T0#
M10
M00
TL0
8Ah Timer/Counter 0 Low Byte
TH0
8Ch Timer/Counter 0 High Byte
TL1
8Bh Timer/Counter 1 Low Byte
TH1
8Dh Timer/Counter 1 High Byte
WDTRST
A6h Watchdog Timer Reset
WDTPRG
A7h Watchdog Timer Program
-
-
-
-
-
WTO2
WTO1
WTO0
7
6
5
4
3
2
1
0
Table 8-9.
MP3 Decoder SFRs
Mnemonic Add Name
MP3CON
AAh MP3 Control
MPEN
MPBBST
CRCEN
MSKANC
MSKREQ
MSKLAY
MSKSYN
MSKCRC
MP3STA
C8h MP3 Status
MPANC
MPREQ
ERRLAY
ERRSYN
ERRCRC
MPFS1
MPFS0
MPVER
MP3STA1
AFh MP3 Status 1
-
-
-
MPFREQ
MPBREQ
-
-
-
32
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 8-9.
MP3 Decoder SFRs (Continued)
Mnemonic Add Name
7
6
5
4
3
2
1
0
MP3DAT
ACh MP3 Data
MPD7
MPD6
MPD5
MPD4
MPD3
MPD2
MPD1
MPD0
MP3ANC
ADh MP3 Ancillary Data
AND7
AND6
AND5
AND4
AND3
AND2
AND1
AND0
MP3VOL
9Eh MP3 Audio Volume Control Left
-
-
-
VOL4
VOL3
VOL2
VOL1
VOL0
MP3VOR
9Fh MP3 Audio Volume Control Right
-
-
-
VOR4
VOR3
VOR2
VOR1
VOR0
MP3BAS
B4h MP3 Audio Bass Control
-
-
-
BAS4
BAS3
BAS2
BAS1
BAS0
MP3MED
B5h MP3 Audio Medium Control
-
-
-
MED4
MED3
MED2
MED1
MED0
MP3TRE
B6h MP3 Audio Treble Control
-
-
-
TRE4
TRE3
TRE2
TRE1
TRE0
MP3CLK
EBh MP3 Clock Divider
-
-
-
MPCD4
MPCD3
MPCD2
MPCD1
MPCD0
7
6
5
4
3
2
1
0
Table 8-10.
Audio Interface SFRs
Mnemonic Add Name
AUDCON0
9Ah Audio Control 0
JUST4
JUST3
JUST2
JUST1
JUST0
POL
DSIZ
HLR
AUDCON1
9Bh Audio Control 1
SRC
DRQEN
MSREQ
MUDRN
-
DUP1
DUP0
AUDEN
AUDSTA
9Ch Audio Status
SREQ
UDRN
AUBUSY
-
-
-
-
-
AUDDAT
9Dh Audio Data
AUD7
AUD6
AUD5
AUD4
AUD3
AUD2
AUD1
AUD0
AUDCLK
ECh Audio Clock Divider
-
-
-
AUCD4
AUCD3
AUCD2
AUCD1
AUCD0
7
6
5
4
3
2
1
0
USBE
SUSPCL
K
SDRMWU
P
-
UPRSM
RMWUPE
CONFG
FADDEN
FEN
UADD6
UADD5
UADD4
UADD3
UADD2
UADD1
UADD0
Table 8-11.
USB Controller SFRs
Mnemonic Add Name
USBCON
BCh USB Global Control
USBADDR
C6h USB Address
USBINT
BDh USB Global Interrupt
-
-
WUPCPU
EORINT
SOFINT
-
-
SPINT
USBIEN
BEh USB Global Interrupt Enable
-
-
EWUPCP
U
EEORINT
ESOFINT
-
-
ESPINT
UEPNUM
C7h USB Endpoint Number
-
-
-
-
-
-
EPNUM1
EPNUM0
EPEN
NAKIEN
NAKOUT
NAKIN
DTGL
EPDIR
DIR
RXOUTB
1
STALLRQ
TXRDY
STLCRC
RXSETU
P
RXOUTB
0
TXCMP
UEPCONX D4h USB Endpoint X Control
EPTYPE1 EPTYPE0
UEPSTAX
CEh USB Endpoint X Status
UEPRST
D5h USB Endpoint Reset
-
-
-
-
-
EP2RST
EP1RST
EP0RST
UEPINT
F8h USB Endpoint Interrupt
-
-
-
-
-
EP2INT
EP1INT
EP0INT
UEPIEN
C2h USB Endpoint Interrupt Enable
-
-
-
-
-
EP2INTE
EP1INTE
EP0INTE
UEPDATX
CFh USB Endpoint X FIFO Data
FDAT7
FDAT6
FDAT5
FDAT4
FDAT3
FDAT2
FDAT1
FDAT0
UBYCTX
E2h USB Endpoint X Byte Counter
-
BYCT6
BYCT5
BYCT4
BYCT3
BYCT2
BYCT1
BYCT0
UFNUML
BAh USB Frame Number Low
FNUM7
FNUM6
FNUM5
FNUM4
FNUM3
FNUM2
FNUM1
FNUM0
UFNUMH
BBh USB Frame Number High
-
-
CRCOK
CRCERR
-
FNUM10
FNUM9
FNUM8
USBCLK
EAh USB Clock Divider
-
-
-
-
-
-
USBCD1
USBCD0
33
4341H–MP3–10/07
Table 8-12.
MMC Controller SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
MMCON0
E4h MMC Control 0
DRPTR
DTPTR
CRPTR
CTPTR
MBLOCK
DFMT
RFMT
CRCDIS
MMCON1
E5h MMC Control 1
BLEN3
BLEN2
BLEN1
BLEN0
DATDIR
DATEN
RESPEN
CMDEN
MMCON2
E6h MMC Control 2
MMCEN
DCR
CCR
-
-
DATD1
DATD0
FLOWC
MMSTA
DEh MMC Control and Status
-
-
CBUSY
CRC16S
DATFS
CRC7S
RESPFS
CFLCK
MMINT
E7h MMC Interrupt
MCBI
EORI
EOCI
EOFI
F2FI
F1FI
F2EI
F1EI
MMMSK
DFh MMC Interrupt Mask
MCBM
EORM
EOCM
EOFM
F2FM
F1FM
F2EM
F1EM
MMCMD
DD
h
MMC Command
MC7
MC6
MC5
MC4
MC3
MC2
MC1
MC0
MMDAT
DC
h
MMC Data
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MMCLK
EDh MMC Clock Divider
MMCD7
MMCD6
MMCD5
MMCD4
MMCD3
MMCD2
MMCD1
MMCD0
7
6
5
4
3
2
1
0
D15
D14
D13
D12
D11
D10
D9
D8
7
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
BRR
TBCK
RBCK
SPD
SRC
Table 8-13.
IDE Interface SFR
Mnemonic Add Name
DAT16H
F9h High Order Data Byte
Table 8-14.
Serial I/O Port SFRs
Mnemonic Add Name
SCON
98h Serial Control
SBUF
99h Serial Data Buffer
SADEN
B9h Slave Address Mask
SADDR
A9h Slave Address
BDRCON
92h Baud Rate Control
BRL
91h Baud Rate Reload
Table 8-15.
SPI Controller SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
SPCON
C3h SPI Control
SPR2
SPEN
SSDIS
MSTR
CPOL
CPHA
SPR1
SPR0
SPSTA
C4h SPI Status
SPIF
WCOL
-
MODF
-
-
-
-
SPDAT
C5h SPI Data
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
34
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 8-16.
Two Wire Controller SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
SSCON
93h Synchronous Serial Control
SSCR2
SSPE
SSSTA
SSSTO
SSI
SSAA
SSCR1
SSCR0
SSSTA
94h Synchronous Serial Status
SSC4
SSC3
SSC2
SSC1
SSC0
0
0
0
SSDAT
95h Synchronous Serial Data
SSD7
SSD6
SSD5
SSD4
SSD3
SSD2
SSD1
SSD0
SSADR
96h Synchronous Serial Address
SSA7
SSA6
SSA5
SSA4
SSA3
SSA2
SSA1
SSGC
Mnemonic Add Name
7
6
5
4
3
2
1
0
KBCON
A3h Keyboard Control
-
-
-
KINL0
-
-
-
KINM0
KBSTA
A4h Keyboard Status
KPDE
-
-
-
-
-
-
KINF0
Table 8-17.
Keyboard Interface SFRs
Table 8-18.
A/D Controller SFRs
Mnemonic
Add
Name
7
6
5
4
3
2
1
0
ADCON
F3h
ADC Control
-
ADIDL
ADEN
ADEOC
ADSST
-
-
ADCS
ADCLK
F2h
ADC Clock Divider
-
-
-
ADCD4
ADCD3
ADCD2
ADCD1
ADCD0
ADDL
F4h
ADC Data Low Byte
-
-
-
-
-
-
ADAT1
ADAT0
ADDH
F5h
ADC Data High Byte
ADAT9
ADAT8
ADAT7
ADAT6
ADAT5
ADAT4
ADAT3
ADAT2
35
4341H–MP3–10/07
Table 8-19.
SFR Addresses and Reset Values
0/8
1/9
F8h
UEPINT
0000 0000
DAT16H
XXXX XXXX
F0h
B(1)
0000 0000
PLLCON
0000 1000
E8h
ACC(1)
E0h
P5(1)
XXXX 1111
D0h
PSW(1)
0000 0000
C8h
MP3STA(1)
0000 0001
C0h
P4(1)
1111 1111
B8h
IPL0(1)
X000 0000
B0h
3/B
4/C
5/D
6/E
FFh
ADCLK
0000 0000
ADCON
0000 0000
ADDL
0000 0000
ADDH
0000 0000
USBCLK
0000 0000
MP3CLK
0000 0000
AUDCLK
0000 0000
MMCLK
0000 0000
PLLNDIV
0000 0000
PLLRDIV
0000 0000
EFh
MMCON0
0000 0000
MMCON1
0000 0000
MMCON2
0000 0000
MMINT
0000 0011
E7h
MMDAT
1111 1111
MMCMD
1111 1111
MMSTA
0000 0000
MMMSK
1111 1111
DFh
UEPCONX
1000 0000
UEPRST
0000 0000
FCON(3)
1111 0000(4)
F7h
D7h
UEPSTAX
0000 0000
UEPDATX
XXXX XXXX
CFh
UEPNUM
0000 0000
C7h
UEPIEN
0000 0000
SPCON
0001 0100
SPSTA
0000 0000
SPDAT
XXXX XXXX
USBADDR
0000 0000
SADEN
0000 0000
UFNUML
0000 0000
UFNUMH
0000 0000
USBCON
0000 0000
USBINT
0000 0000
USBIEN
0001 0000
P3(1)
1111 1111
IEN1
0000 0000
IPL1
0000 0000
IPH1
0000 0000
MP3BAS
0000 0000
MP3MED
0000 0000
MP3TRE
0000 0000
A8h
IEN0(1)
0000 0000
SADDR
0000 0000
MP3CON
0011 1111
MP3DAT
0000 0000
MP3ANC
0000 0000
A0h
P2(1)
1111 1111
98h
SCON
0000 0000
90h
B7h
MP3STA1
0100 0001
AFh
WDTRST
XXX XXXX
WDTPRG
XXXX X000
A7h
MP3VOR
0000 0000
9Fh
KBCON
0000 1111
KBSTA
0000 0000
SBUF
XXXX XXXX
AUDCON0
0000 1000
AUDCON1
1011 0010
AUDSTA
1100 0000
AUDDAT
1111 1111
MP3VOL
0000 0000
AUXCON(1)
1111 1111
BRL
0000 0000
BDRCON
XXX0 0000
SSCON
0000 0000
SSSTA
1111 1000
SSDAT
1111 1111
SSADR
1111 1110
TCON(1)
0000 0000
TMOD
0000 0000
TL0
0000 0000
TL1
0000 0000
TH0
0000 0000
TH1
0000 0000
AUXR
X000 1101
P0(1)
1111 1111
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
0/8
1/9
2/A
3/B
80h
4/C
5/D
BFh
IPH0
X000 0000
AUXR1
XXXX 00X0
88h
7/F
NVERS
XXXX XXXX(2)
UBYCTLX
0000 0000
0000 0000
D8h
2/A
6/E
97h
CKCON
0000 000X(5)
8Fh
PCON
00XX 0000
87h
7/F
Reserved
Notes:
36
1. SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable.
2. NVERS reset value depends on the silicon version: 1000 0100 for AT89C51SND2C product and 0000 0001 for AT83SND2C
product.
3. FCON register is only available in AT89C51SND2C product.
4. FCON reset value is 00h in case of reset with hardware condition.
5. CKCON reset value depends on the X2B bit (programmed or unprogrammed) in the Hardware Byte.
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
9. Interrupt System
The AT8xC51SND2C, like other control-oriented computer architectures, employ a program
interrupt method. This operation branches to a subroutine and performs some service in
response to the interrupt. When the subroutine completes, execution resumes at the point where
the interrupt occurred. Interrupts may occur as a result of internal AT8xC51SND2C activity (e.g.,
timer overflow) or at the initiation of electrical signals external to the microcontroller (e.g., keyboard). In all cases, interrupt operation is programmed by the system designer, who determines
priority of interrupt service relative to normal code execution and other interrupt service routines.
All of the interrupt sources are enabled or disabled by the system designer and may be manipulated dynamically.
A typical interrupt event chain occurs as follows:
•
An internal or external device initiates an interrupt-request signal. The AT8xC51SND2C,
latches this event into a flag buffer.
•
The priority of the flag is compared to the priority of other interrupts by the interrupt handler.
A high priority causes the handler to set an interrupt flag.
•
This signals the instruction execution unit to execute a context switch. This context switch
breaks the current flow of instruction sequences. The execution unit completes the current
instruction prior to a save of the program counter (PC) and reloads the PC with the start
address of a software service routine.
•
The software service routine executes assigned tasks and as a final activity performs a RETI
(return from interrupt) instruction. This instruction signals completion of the interrupt, resets
the interrupt-in-progress priority and reloads the program counter. Program operation then
continues from the original point of interruption.
Table 9-1.
Interrupt System Signals
Signal
Name
Type
INT0
I
External Interrupt 0
See section "External Interrupts", page 40.
P3.2
INT1
I
External Interrupt 1
See section “External Interrupts”, page 40.
P3.3
KIN0
I
Keyboard Interrupt Input
See section “Keyboard Interface”, page 204.
Description
Alternate
Function
-
Six interrupt registers are used to control the interrupt system. 2 8-bit registers are used to
enable separately the interrupt sources: IEN0 and IEN1 registers (see Table 9-4 and Table 9-5).
Four 8-bit registers are used to establish the priority level of the different sources: IPH0, IPL0,
IPH1 and IPL1 registers (see Table 9-6 to Table 9-9).
9.1
Interrupt System Priorities
Each of the interrupt sources on the AT8xC51SND2C can be individually programmed to one of
four priority levels. This is accomplished by one bit in the Interrupt Priority High registers (IPH0
and IPH1) and one bit in the Interrupt Priority Low registers (IPL0 and IPL1). This provides each
interrupt source four possible priority levels according to Table 9-2.
37
4341H–MP3–10/07
Table 9-2.
Priority Levels
IPHxx
IPLxx
Priority Level
0
0
0 Lowest
0
1
1
1
0
2
1
1
3 Highest
A low-priority interrupt is always interrupted by a higher priority interrupt but not by another interrupt of lower or equal priority. Higher priority interrupts are serviced before lower priority
interrupts. The response to simultaneous occurrence of equal priority interrupts is determined by
an internal hardware polling sequence detailed in Table 9-3. Thus, within each priority level
there is a second priority structure determined by the polling sequence. The interrupt control
system is shown in Figure 9-1.
Table 9-3.
Priority within Same Level
Priority Number
Interrupt Address Vectors
Interrupt Request Flag
Cleared by Hardware (H)
or by Software (S)
0 (Highest Priority)
C:0003h
H if edge, S if level
Timer 0
1
C:000Bh
H
INT1
2
C:0013h
H if edge, S if level
Timer 1
3
C:001Bh
H
Serial Port
4
C:0023h
S
MP3 Decoder
5
C:002Bh
S
Audio Interface
6
C:0033h
S
MMC Interface
7
C:003Bh
S
Two Wire Controller
8
C:0043h
S
SPI Controller
9
C:004Bh
S
A to D Converter
10
C:0053h
S
Keyboard
11
C:005Bh
S
Reserved
12
C:0063h
-
USB
13
C:006Bh
S
14 (Lowest Priority)
C:0073h
-
Interrupt Name
INT0
Reserved
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AT8xC51SND2C/MP3B
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AT8xC51SND2C/MP3B
Figure 9-1.
Interrupt Control System
INT0
00
01
10
11
External
Interrupt 0
Highest
Priority
Interrupts
EX0
00
01
10
11
IEN0.0
Timer 0
ET0
INT1
External
Interrupt 1
00
01
10
11
IEN0.1
EX1
00
01
10
11
IEN0.2
Timer 1
ET1
TXD
RXD
Serial
Port
00
01
10
11
IEN0.3
ES
MP3
Decoder
00
01
10
11
IEN0.4
EMP3
Audio
Interface
00
01
10
11
IEN0.5
EAUD
MCLK
MDAT
MCMD
MMC
Controller
00
01
10
11
IEN0.6
EMMC
SCL
SDA
TWI
Controller
00
01
10
11
IEN1.0
EI2C
SCK
SI
SO
SPI
Controller
00
01
10
11
IEN1.1
ESPI
AIN1:0
A to D
Converter
00
01
10
11
IEN1.2
EADC
00
01
10
11
IEN1.3
KIN0
Keyboard
EKB
D+
D-
USB
Controller
00
01
10
11
IEN1.4
EUSB
EA
IEN1.6
IEN0.7
Interrupt Enable
IPH/L
Priority Enable
Lowest Priority Interrupts
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4341H–MP3–10/07
9.2
9.2.1
External Interrupts
INT1:0 Inputs
External interrupts INT0 and INT1 (INTn, n = 0 or 1) pins may each be programmed to be leveltriggered or edge-triggered, dependent upon bits IT0 and IT1 (ITn, n = 0 or 1) in TCON register
as shown in Figure 9-2. If ITn = 0, INTn is triggered by a low level at the pin. If ITn = 1, INTn is
negative-edge triggered. External interrupts are enabled with bits EX0 and EX1 (EXn, n = 0 or 1)
in IEN0. Events on INTn set the interrupt request flag IEn in TCON register. If the interrupt is
edge-triggered, the request flag is cleared by hardware when vectoring to the interrupt service
routine. If the interrupt is level-triggered, the interrupt service routine must clear the request flag
and the interrupt must be deasserted before the end of the interrupt service routine.
INT0 and INT1 inputs provide both the capability to exit from Power-down mode on low level signals as detailed in section “Exiting Power-down Mode”, page 50.
Figure 9-2.
INT1:0 Input Circuitry
INT0/1
INT0/1
Interrupt
Request
0
IE0/1
1
TCON.1/3
EX0/1
IEN0.0/2
IT0/1
TCON.0/2
9.2.2
KIN0 Inputs
External interrupts KIN0 provides the capability to connect a keyboard. For detailed information
on this inputs, refer to section “Keyboard Interface”, page 204.
9.2.3
Input Sampling
External interrupt pins (INT1:0 and KIN0) are sampled once per peripheral cycle (6 peripheral
clock periods) (see Figure 9-3). A level-triggered interrupt pin held low or high for more than 6
peripheral clock periods (12 oscillator in standard mode or 6 oscillator clock periods in X2 mode)
guarantees detection. Edge-triggered external interrupts must hold the request pin low for at
least 6 peripheral clock periods.
Figure 9-3.
Minimum Pulse Timings
Level-Triggered Interrupt
> 1 Peripheral Cycle
1 cycle
Edge-Triggered Interrupt
> 1 Peripheral Cycle
1 cycle
40
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AT8xC51SND2C/MP3B
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AT8xC51SND2C/MP3B
9.3
Registers
Table 9-4.
IEN0 Register
IEN0 (S:A8h) – Interrupt Enable Register 0
7
6
5
4
3
2
1
0
EA
EAUD
EMP3
ES
ET1
EX1
ET0
EX0
Bit Number
Bit
Mnemonic
Description
7
EA
Enable All Interrupt Bit
Set to enable all interrupts.
Clear to disable all interrupts.
If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing
its interrupt enable bit.
6
EAUD
Audio Interface Interrupt Enable Bit
Set to enable audio interface interrupt.
Clear to disable audio interface interrupt.
5
EMP3
MP3 Decoder Interrupt Enable Bit
Set to enable MP3 decoder interrupt.
Clear to disable MP3 decoder interrupt.
4
ES
Serial Port Interrupt Enable Bit
Set to enable serial port interrupt.
Clear to disable serial port interrupt.
3
ET1
Timer 1 Overflow Interrupt Enable Bit
Set to enable timer 1 overflow interrupt.
Clear to disable timer 1 overflow interrupt.
2
EX1
External Interrupt 1 Enable bit
Set to enable external interrupt 1.
Clear to disable external interrupt 1.
1
ET0
Timer 0 Overflow Interrupt Enable Bit
Set to enable timer 0 overflow interrupt.
Clear to disable timer 0 overflow interrupt.
0
EX0
External Interrupt 0 Enable Bit
Set to enable external interrupt 0.
Clear to disable external interrupt 0.
Reset Value = 0000 0000b
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4341H–MP3–10/07
Table 9-5.
IEN1 Register
IEN1 (S:B1h) – Interrupt Enable Register 1
7
6
5
4
3
2
1
0
-
EUSB
-
EKB
-
ESPI
EI2C
EMMC
Bit Number
Bit
Mnemonic
Description
7
-
6
EUSB
5
-
4
EKB
3
EADC
A to D Converter Interrupt Enable Bit
Set to enable ADC interrupt.
Clear to disable ADC interrupt.
2
ESPI
SPI Controller Interrupt Enable Bit
Set to enable SPI interrupt.
Clear to disable SPI interrupt.
1
EI2C
Two Wire Controller Interrupt Enable Bit
Set to enable Two Wire interrupt.
Clear to disable Two Wire interrupt.
0
EMMC
Reserved
The value read from this bit is always 0. Do not set this bit.
USB Interface Interrupt Enable Bit
Set this bit to enable USB interrupts.
Clear this bit to disable USB interrupts.
Reserved
The value read from this bit is always 0. Do not set this bit.
Keyboard Interface Interrupt Enable Bit
Set to enable Keyboard interrupt.
Clear to disable Keyboard interrupt.
MMC Interface Interrupt Enable Bit
Set to enable MMC interrupt.
Clear to disable MMC interrupt.
Reset Value = 0000 0000b
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AT8xC51SND2C/MP3B
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AT8xC51SND2C/MP3B
Table 9-6.
IPH0 Register
IPH0 (S:B7h) – Interrupt Priority High Register 0
7
6
5
4
3
2
1
0
-
IPHAUD
IPHMP3
IPHS
IPHT1
IPHX1
IPHT0
IPHX0
Bit Number
Bit
Mnemonic
Description
7
-
6
IPHAUD
Audio Interface Interrupt Priority Level MSB
Refer to Table 9-2 for priority level description.
5
IPHMP3
MP3 Decoder Interrupt Priority Level MSB
Refer to Table 9-2 for priority level description.
4
IPHS
Serial Port Interrupt Priority Level MSB
Refer to Table 9-2 for priority level description.
3
IPHT1
Timer 1 Interrupt Priority Level MSB
Refer to Table 9-2 for priority level description.
2
IPHX1
External Interrupt 1 Priority Level MSB
Refer to Table 9-2 for priority level description.
1
IPHT0
Timer 0 Interrupt Priority Level MSB
Refer to Table 9-2 for priority level description.
0
IPHX0
External Interrupt 0 Priority Level MSB
Refer to Table 9-2 for priority level description.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = X000 0000b
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4341H–MP3–10/07
Table 9-7.
IPH1 Register
IPH1 (S:B3h) – Interrupt Priority High Register 1
7
6
5
4
3
2
1
0
-
IPHUSB
-
IPHKB
-
IPHSPI
IPHI2C
IPHMMC
Bit Number
Bit
Mnemonic
Description
7
-
6
IPHUSB
5
-
4
IPHKB
3
IPHADC
A to D Converter Interrupt Priority Level MSB
Refer to Table 9-2 for priority level description.
2
IPHSPI
SPI Interrupt Priority Level MSB
Refer to Table 9-2 for priority level description.
1
IPHI2C
Two Wire Controller Interrupt Priority Level MSB
Refer to Table 9-2 for priority level description.
0
IPHMMC
Reserved
The value read from this bit is always 0. Do not set this bit.
USB Interrupt Priority Level MSB
Refer to Table 9-2 for priority level description.
Reserved
The value read from this bit is always 0. Do not set this bit.
Keyboard Interrupt Priority Level MSB
Refer to Table 9-2 for priority level description.
MMC Interrupt Priority Level MSB
Refer to Table 9-2 for priority level description.
Reset Value = 0000 0000b
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AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 9-8.
IPL0 Register
IPL0 (S:B8h) - Interrupt Priority Low Register 0
7
6
5
4
3
2
1
0
-
IPLAUD
IPLMP3
IPLS
IPLT1
IPLX1
IPLT0
IPLX0
Bit Number
Bit
Mnemonic
Description
7
-
6
IPLAUD
Audio Interface Interrupt Priority Level LSB
Refer to Table 9-2 for priority level description.
5
IPLMP3
MP3 Decoder Interrupt Priority Level LSB
Refer to Table 9-2 for priority level description.
4
IPLS
Serial Port Interrupt Priority Level LSB
Refer to Table 9-2 for priority level description.
3
IPLT1
Timer 1 Interrupt Priority Level LSB
Refer to Table 9-2 for priority level description.
2
IPLX1
External Interrupt 1 Priority Level LSB
Refer to Table 9-2 for priority level description.
1
IPLT0
Timer 0 Interrupt Priority Level LSB
Refer to Table 9-2 for priority level description.
0
IPLX0
External Interrupt 0 Priority Level LSB
Refer to Table 9-2 for priority level description.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = X000 0000b
45
4341H–MP3–10/07
Table 9-9.
IPL1 Register
IPL1 (S:B2h) – Interrupt Priority Low Register 1
7
6
5
4
3
2
1
0
-
IPLUSB
-
IPLKB
-
IPLSPI
IPLI2C
IPLMMC
Bit Number
Bit
Mnemonic
Description
7
-
6
IPLUSB
5
-
4
IPLKB
3
IPLADC
A to D Converter Interrupt Priority Level LSB
Refer to Table 9-2 for priority level description.
2
IPLSPI
SPI Interrupt Priority Level LSB
Refer to Table 9-2 for priority level description.
1
IPLI2C
Two Wire Controller Interrupt Priority Level LSB
Refer to Table 9-2 for priority level description.
0
IPLMMC
Reserved
The value read from this bit is always 0. Do not set this bit.
USB Interrupt Priority Level LSB
Refer to Table 9-2 for priority level description.
Reserved
The value read from this bit is always 0. Do not set this bit.
Keyboard Interrupt Priority Level LSB
Refer to Table 9-2 for priority level description.
MMC Interrupt Priority Level LSB
Refer to Table 9-2 for priority level description.
Reset Value = 0000 0000b
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AT8xC51SND2C/MP3B
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AT8xC51SND2C/MP3B
10. Power Management
2 power reduction modes are implemented in the AT8xC51SND2C: the Idle mode and the
Power-down mode. These modes are detailed in the following sections. In addition to these
power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2
using the X2 mode detailed in section “X2 Feature”, page 14.
10.1
Reset
In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an high
level has to be applied on the RST pin. A bad level leads to a wrong initialization of the internal
registers like SFRs, Program Counter… and to unpredictable behavior of the microcontroller. A
proper device reset initializes the AT8xC51SND2C and vectors the CPU to address 0000h. RST
input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to VDD as shown in Figure 10-1. A warm reset can be applied either directly on the RST pin or
indirectly by an internal reset source such as the watchdog timer. Resistor value and input characteristics are discussed in the Section “DC Characteristics” of the AT8xC51SND2C datasheet.
The status of the Port pins during reset is detailed in Table 10-1.
Figure 10-1. Reset Circuitry and Power-On Reset
From Internal
Reset Source
VDD
P
VDD
To CPU Core
and Peripherals
+
RRST
RST
RST
VSS
RST input circuitry
Table 10-1.
Pin Conditions in Special Operating Modes
Mode
Reset
Idle
Power-down
Note:
10.1.1
Power-on Reset
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
MMC
Audio
Floating
High
High
High
High
High
Floating
1
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
1. Refer to section “Audio Output Interface”, page 74.
Cold Reset
2 conditions are required before enabling a CPU start-up:
•
VDD must reach the specified VDD range
•
The level on X1 input pin must be outside the specification (VIH, VIL)
If one of these 2 conditions are not met, the microcontroller does not start correctly and can execute an instruction fetch from anywhere in the program space. An active level applied on the
RST pin must be maintained till both of the above conditions are met. A reset is active when the
level VIH1 is reached and when the pulse width covers the period of time where VDD and the
oscillator are not stabilized. 2 parameters have to be taken into account to determine the reset
pulse width:
•
VDD rise time,
•
Oscillator startup time.
47
4341H–MP3–10/07
To determine the capacitor value to implement, the highest value of these 2 parameters has to
be chosen. Table 10-2 gives some capacitor values examples for a minimum RRST of 50 KΩ and
different oscillator startup and VDD rise times.
Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor(1)
Table 10-2.
Note:
10.1.2
VDD Rise Time
Oscillator
Start-Up Time
1 ms
10 ms
100 ms
5 ms
820 nF
1.2 µF
12 µF
20 ms
2.7 µF
3.9 µF
12 µF
1. These values assume VDD starts from 0V to the nominal value. If the time between 2 on/off
sequences is too fast, the power-supply de-coupling capacitors may not be fully discharged,
leading to a bad reset sequence.
Warm Reset
To achieve a valid reset, the reset signal must be maintained for at least 2 machine cycles (24
oscillator clock periods) while the oscillator is running. The number of clock periods is mode
independent (X2 or X1).
10.1.3
Watchdog Reset
As detailed in section “Watchdog Timer”, page 60, the WDT generates a 96-clock period pulse
on the RST pin. In order to properly propagate this pulse to the rest of the application in case of
external capacitor or power-supply supervisor circuit, a 1 kΩ resistor must be added as shown in
Figure 10-2.
Figure 10-2. Reset Circuitry for WDT Reset-out Usage
VDD
VDD
+
RST
RST
VSS
10.2
1K
To CPU Core
and Peripherals
RRST
VDD
P
From WDT
Reset Source
VSS
To Other
On-board
Circuitry
Reset Recommendation to Prevent Flash Corruption
An example of bad initialization situation may occur in an instance where the bit ENBOOT in
AUXR1 register is initialized from the hardware bit BLJB upon reset. Since this bit allows mapping of the bootloader in the code area, a reset failure can be critical.
If one wants the ENBOOT cleared in order to unmap the boot from the code area (yet due to a
bad reset) the bit ENBOOT in SFRs may be set. If the value of Program Counter is accidently in
the range of the boot memory addresses then a Flash access (write or erase) may corrupt the
Flash on-chip memory.
It is recommended to use an external reset circuitry featuring power supply monitoring to prevent
system malfunction during periods of insufficient power supply voltage (power supply failure,
power supply switched off).
48
AT8xC51SND2C/MP3B
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AT8xC51SND2C/MP3B
10.3
Idle Mode
Idle mode is a power reduction mode that reduces the power consumption. In this mode, program execution halts. Idle mode freezes the clock to the CPU at known states while the
peripherals continue to be clocked (refer to section “Oscillator”, page 13). The CPU status
before entering Idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of Idle mode. The contents of the SFRs and RAM are also
retained. The status of the Port pins during Idle mode is detailed in Table 10-1.
10.3.1
Entering Idle Mode
To enter Idle mode, the user must set the IDL bit in PCON register (see Table 10-3). The
AT8xC51SND2C enters Idle mode upon execution of the instruction that sets IDL bit. The
instruction that sets IDL bit is the last instruction executed.
Note:
10.3.2
If IDL bit and PD bit are set simultaneously, the AT8xC51SND2C enter Power-down mode. Then it
does not go in Idle mode when exiting Power-down mode.
Exiting Idle Mode
There are 2 ways to exit Idle mode:
1. Generate an enabled interrupt.
–
Hardware clears IDL bit in PCON register which restores the clock to the CPU.
Execution resumes with the interrupt service routine. Upon completion of the
interrupt service routine, program execution resumes with the instruction
immediately following the instruction that activated Idle mode. The general-purpose
flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt
occurred during normal operation or during Idle mode. When Idle mode is exited by
an interrupt, the interrupt service routine may examine GF1 and GF0.
2. Generate a reset.
–
Note:
10.4
A logic high on the RST pin clears IDL bit in PCON register directly and
asynchronously. This restores the clock to the CPU. Program execution momentarily
resumes with the instruction immediately following the instruction that activated the
Idle mode and may continue for a number of clock cycles before the internal reset
algorithm takes control. Reset initializes the AT8xC51SND2C and vectors the CPU
to address C:0000h.
During the time that execution resumes, the internal RAM cannot be accessed; however, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction
immediately following the instruction that activated Idle mode should not write to a Port pin or to
the external RAM.
Power-down Mode
The Power-down mode places the AT8xC51SND2C in a very low power state. Power-down
mode stops the oscillator and freezes all clocks at known states (refer to the Section "Oscillator",
page 13). The CPU status prior to entering Power-down mode is preserved, i.e., the program
counter, program status word register retain their data for the duration of Power-down mode. In
addition, the SFRs and RAM contents are preserved. The status of the Port pins during Powerdown mode is detailed in Table 10-1.
Note:
VDD may be reduced to as low as VRET during Power-down mode to further reduce power dissipation. Notice, however, that VDD is not reduced until Power-down mode is invoked.
49
4341H–MP3–10/07
10.4.1
Entering Power-down Mode
To enter Power-down mode, set PD bit in PCON register. The AT8xC51SND2C enters the
Power-down mode upon execution of the instruction that sets PD bit. The instruction that sets
PD bit is the last instruction executed.
10.4.2
Exiting Power-down Mode
If VDD was reduced during the Power-down mode, do not exit Power-down mode until VDD is
restored to the normal operating level.
There are 2 ways to exit the Power-down mode:
1. Generate an enabled external interrupt.
–
Note:
The AT8xC51SND2C provides capability to exit from Power-down using INT0, INT1,
and KIN0 inputs. In addition, using KIN input provides high or low level exit capability
(see section “Keyboard Interface”, page 204).
Hardware clears PD bit in PCON register which starts the oscillator and restores the
clocks to the CPU and peripherals. Using INTn input, execution resumes when the
input is released (see Figure 10-3) while using KINx input, execution resumes after
counting 1024 clock ensuring the oscillator is restarted properly (see Figure 10-4).
This behavior is necessary for decoding the key while it is still pressed. In both
cases, execution resumes with the interrupt service routine. Upon completion of the
interrupt service routine, program execution resumes with the instruction
immediately following the instruction that activated Power-down mode.
1. The external interrupt used to exit Power-down mode must be configured as level sensitive
(INT0 and INT1) and must be assigned the highest priority. In addition, the duration of the
interrupt must be long enough to allow the oscillator to stabilize. The execution will only
resume when the interrupt is deasserted.
2. Exit from power-down by external interrupt does not affect the SFRs nor the internal RAM
content.
Figure 10-3. Power-down Exit Waveform Using INT1:0
INT1:0
OSC
Active phase
Power-down Phase
Oscillator Restart
Active Phase
Figure 10-4. Power-down Exit Waveform Using KIN0
KIN01
OSC
Active phase
Note:
Power-down
1024 clock count
Active phase
1. KIN0 can be high or low-level triggered.
2. Generate a reset.
50
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
–
A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU and
peripherals. Program execution momentarily resumes with the instruction
immediately following the instruction that activated Power-down mode and may
continue for a number of clock cycles before the internal reset algorithm takes
control. Reset initializes the AT8xC51SND2C and vectors the CPU to address
0000h.
Notes:
10.5
1. During the time that execution resumes, the internal RAM cannot be accessed; however, it is
possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the
instruction immediately following the instruction that activated the Power-down mode should
not write to a Port pin or to the external RAM.
2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal RAM
content.
Registers
Table 10-3.
PCON Register
PCON (S:87h) – Power Configuration Register
7
6
5
4
3
2
1
0
SMOD1
SMOD0
-
-
GF1
GF0
PD
IDL
Bit Number
Bit
Mnemonic
Description
7
SMOD1
Serial Port Mode Bit 1
Set to select double baud rate in mode 1,2 or 3.
6
SMOD0
Serial Port Mode Bit 0
Set to select FE bit in SCON register.
Clear to select SM0 bit in SCON register.
5-4
-
3
GF1
General-Purpose Flag 1
One use is to indicate whether an interrupt occurred during normal operation or during
Idle mode.
2
GF0
General-Purpose Flag 0
One use is to indicate whether an interrupt occurred during normal operation or during
Idle mode.
1
PD
Power-Down Mode Bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Power-down mode.
If IDL and PD are both set, PD takes precedence.
0
IDL
Idle Mode Bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Idle mode.
If IDL and PD are both set, PD takes precedence.
Reserved
The value read from these bits is indeterminate. Do not set these bits.
Reset Value = 00XX 0000b
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4341H–MP3–10/07
11. Timers/Counters
The AT8xC51SND2C implement 2 general-purpose, 16-bit Timers/Counters. They are identified
as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes
as a Timer or as an event Counter. When operating as a Timer, the Timer/Counter runs for a
programmed length of time, then issues an interrupt request. When operating as a Counter, the
Timer/Counter counts negative transitions on an external pin. After a preset number of counts,
the Counter issues an interrupt request.
The various operating modes of each Timer/Counter are described in the following sections.
11.1
Timer/Counter Operations
For instance, a basic operation is Timer registers THx and TLx (x = 0, 1) connected in cascade
to form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (see Table 11-1) turns
the Timer on by allowing the selected input to increment TLx. When TLx overflows it increments
THx; when THx overflows it sets the Timer overflow flag (TFx) in TCON register. Setting the TRx
does not clear the THx and TLx Timer registers. Timer registers can be accessed to obtain the
current count or to enter preset values. They can be read at any time but TRx bit must be
cleared to preset their values, otherwise, the behavior of the Timer/Counter is unpredictable.
The C/Tx# control bit selects Timer operation or Counter operation by selecting the divideddown peripheral clock or external pin Tx as the source for the counted signal. TRx bit must be
cleared when changing the mode of operation, otherwise the behavior of the Timer/Counter is
unpredictable.
For Timer operation (C/Tx# = 0), the Timer register counts the divided-down peripheral clock.
The Timer register is incremented once every peripheral cycle (6 peripheral clock periods). The
Timer clock rate is FPER/6, i.e., FOSC/12 in standard mode or FOSC/6 in X2 mode.
For Counter operation (C/Tx# = 1), the Timer register counts the negative transitions on the Tx
external input pin. The external input is sampled every peripheral cycles. When the sample is
high in one cycle and low in the next one, the Counter is incremented. Since it takes 2 cycles (12
peripheral clock periods) to recognize a negative transition, the maximum count rate is FPER/12,
i.e., FOSC/24 in standard mode or FOSC/12 in X2 mode. There are no restrictions on the duty
cycle of the external input signal, but to ensure that a given level is sampled at least once before
it changes, it should be held for at least one full peripheral cycle.
11.2
Timer Clock Controller
As shown in Figure 11-1, the Timer 0 (FT0) and Timer 1 (FT1) clocks are derived from either the
peripheral clock (FPER) or the oscillator clock (FOSC) depending on the T0X2 and T1X2 bits in
CKCON register. These clocks are issued from the Clock Controller block as detailed in
Section “Clock Controller”, page 13. When T0X2 or T1X2 bit is set, the Timer 0 or Timer 1 clock
frequency is fixed and equal to the oscillator clock frequency divided by 2. When cleared, the
Timer clock frequency is equal to the oscillator clock frequency divided by 2 in standard mode or
to the oscillator clock frequency in X2 mode.
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AT8xC51SND2C/MP3B
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AT8xC51SND2C/MP3B
Figure 11-1. Timer 0 and Timer 1 Clock Controller and Symbols
PER
CLOCK
0
Timer 0 Clock
PER
CLOCK
0
Timer 1 Clock
1
OSC
CLOCK
1
OSC
CLOCK
÷2
T0X2
T1X2
CKCON.1
CKCON.2
TIM0
CLOCK
TIM1
CLOCK
Timer 0 Clock Symbol
11.3
÷2
Timer 1 Clock Symbol
Timer 0
Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 11-2
through Figure 11-8 show the logical configuration of each mode.
Timer 0 is controlled by the four lower bits of TMOD register (see Table 11-2) and bits 0, 1, 4 and
5 of TCON register (see Table 11-1). TMOD register selects the method of Timer gating
(GATE0), Timer or Counter operation (C/T0#) and mode of operation (M10 and M00). TCON
register provides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt
flag (IE0) and interrupt type control bit (IT0).
For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by the
selected input. Setting GATE0 and TR0 allows external pin INT0 to control Timer operation.
Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an interrupt
request.
It is important to stop Timer/Counter before changing mode.
11.3.1
Mode 0 (13-bit Timer)
Mode 0 configures Timer 0 as a 13-bit Timer which is set up as an 8-bit Timer (TH0 register) with
a modulo 32 prescaler implemented with the lower five bits of TL0 register (see Figure 11-2).
The upper three bits of TL0 register are indeterminate and should be ignored. Prescaler overflow
increments TH0 register. Figure 11-3 gives the overflow period calculation formula.
Figure 11-2. Timer/Counter x (x = 0 or 1) in Mode 0
TIMx
CLOCK
÷6
0
1
TLx
(5 Bits)
THx
(8 Bits)
Overflow
TFx
TCON reg
Timer x
Interrupt
Request
Tx
C/Tx#
TMOD Reg
INTx
GATEx
TMOD Reg
TRx
TCON Reg
53
4341H–MP3–10/07
Figure 11-3. Mode 0 Overflow Period Formula
TFxPER=
11.3.2
6 ⋅ (16384 – (THx, TLx))
FTIMx
Mode 1 (16-bit Timer)
Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in cascade
(see Figure 11-4). The selected input increments TL0 register. Figure 11-5 gives the overflow
period calculation formula when in timer mode.
Figure 11-4. Timer/Counter x (x = 0 or 1) in Mode 1
TIMx
CLOCK
÷6
0
THx
(8 bits)
1
TLx
(8 bits)
Overflow
TFx
TCON Reg
Tx
Timer x
Interrupt
Request
C/Tx#
TMOD Reg
INTx
GATEx
TRx
TMOD Reg
TCON Reg
Figure 11-5. Mode 1 Overflow Period Formula
TFxPER=
11.3.3
6 ⋅ (65536 – (THx, TLx))
FTIMx
Mode 2 (8-bit Timer with Auto-Reload)
Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads from TH0
register (see Table 11-2). TL0 overflow sets TF0 flag in TCON register and reloads TL0 with the
contents of TH0, which is preset by software. When the interrupt request is serviced, hardware
clears TF0. The reload leaves TH0 unchanged. The next reload value may be changed at any
time by writing it to TH0 register. Figure 11-7 gives the autoreload period calculation formula
when in timer mode.
Figure 11-6. Timer/Counter x (x = 0 or 1) in Mode 2
TIMx
CLOCK
÷6
0
TLx
(8 bits)
1
Tx
Overflow
TFx
TCON reg
Timer x
Interrupt
Request
C/Tx#
TMOD reg
INTx
GATEx
TMOD reg
THx
(8 bits)
TRx
TCON reg
Figure 11-7. Mode 2 Autoreload Period Formula
TFxPER=
54
6 ⋅ (256 – THx)
FTIMx
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
11.3.4
Mode 3 (2 8-bit Timers)
Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit Timers
(see Figure 11-8). This mode is provided for applications requiring an additional 8-bit Timer or
Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD register, and TR0 and
TF0 in TCON register in the normal manner. TH0 is locked into a Timer function (counting
FTF1/6) and takes over use of the Timer 1 interrupt (TF1) and run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode 3. Figure 11-7 gives the autoreload period
calculation formulas for both TF0 and TF1 flags.
Figure 11-8. Timer/Counter 0 in Mode 3: 2 8-bit Counters
TIM0
CLOCK
÷6
0
1
TL0
(8 bits)
Overflow
TH0
(8 bits)
Overflow
TF0
TCON.5
T0
Timer 0
Interrupt
Request
C/T0#
TMOD.2
INT0
GATE0
TR0
TMOD.3
TIM0
CLOCK
TCON.4
÷6
TF1
TCON.7
Timer 1
Interrupt
Request
TR1
TCON.6
Figure 11-9. Mode 3 Overflow Period Formula
TF0PER =
11.4
6 ⋅ (256 – TL0)
FTIM0
TF1PER =
6 ⋅ (256 – TH0)
FTIM0
Timer 1
Timer 1 is identical to Timer 0 except for Mode 3 which is a hold-count mode. The following comments help to understand the differences:
•
Timer 1 functions as either a Timer or event Counter in three modes of operation. Figure 112 through Figure 11-6 show the logical configuration for modes 0, 1, and 2. Timer 1’s mode 3
is a hold-count mode.
•
Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 11-2) and bits
2, 3, 6 and 7 of TCON register (see Figure 11-1). TMOD register selects the method of Timer
gating (GATE1), Timer or Counter operation (C/T1#) and mode of operation (M11 and M01).
TCON register provides Timer 1 control functions: overflow flag (TF1), run control bit (TR1),
interrupt flag (IE1) and interrupt type control bit (IT1).
•
Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best suited for
this purpose.
•
For normal Timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented by the
selected input. Setting GATE1 and TR1 allows external pin INT1 to control Timer operation.
•
Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an
interrupt request.
55
4341H–MP3–10/07
11.4.1
•
When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1).
For this situation, use Timer 1 only for applications that do not require an interrupt (such as a
Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it
off and on.
•
It is important to stop the Timer/Counter before changing modes.
Mode 0 (13-bit Timer)
Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 register)
with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (see Figure 112). The upper 3 bits of TL1 register are ignored. Prescaler overflow increments TH1 register.
11.4.2
Mode 1 (16-bit Timer)
Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade
(see Figure 11-4). The selected input increments TL1 register.
11.4.3
Mode 2 (8-bit Timer with Auto-Reload)
Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from TH1 register on overflow (see Figure 11-6). TL1 overflow sets TF1 flag in TCON register and reloads
TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged.
11.4.4
Mode 3 (Halt)
Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1
when TR1 run control bit is not available i.e. when Timer 0 is in mode 3.
11.5
Interrupt
Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is
set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes interrupts are
globally enabled by setting EA bit in IEN0 register.
Figure 11-10. Timer Interrupt System
Timer 0
Interrupt Request
TF0
TCON.5
ET0
IEN0.1
Timer 1
Interrupt Request
TF1
TCON.7
ET1
IEN0.3
56
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
11.6
Registers
Table 11-1.
TCON Register
TCON (S:88h) – Timer/Counter Control Register
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Bit Number
Bit
Mnemonic
Description
7
TF1
Timer 1 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on Timer/Counter overflow, when Timer 1 register overflows.
6
TR1
Timer 1 Run Control Bit
Clear to turn off Timer/Counter 1.
Set to turn on Timer/Counter 1.
5
TF0
Timer 0 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on Timer/Counter overflow, when Timer 0 register overflows.
4
TR0
Timer 0 Run Control Bit
Clear to turn off Timer/Counter 0.
Set to turn on Timer/Counter 0.
3
IE1
Interrupt 1 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (see IT1).
Set by hardware when external interrupt is detected on INT1 pin.
2
IT1
Interrupt 1 Type Control Bit
Clear to select low level active (level triggered) for external interrupt 1 (INT1).
Set to select falling edge active (edge triggered) for external interrupt 1.
1
IE0
Interrupt 0 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (see IT0).
Set by hardware when external interrupt is detected on INT0 pin.
0
IT0
Interrupt 0 Type Control Bit
Clear to select low level active (level triggered) for external interrupt 0 (INT0).
Set to select falling edge active (edge triggered) for external interrupt 0.
Reset Value = 0000 0000b
57
4341H–MP3–10/07
7
6
5
4
3
2
1
0
GATE1
C/T1#
M11
M01
GATE0
C/T0#
M10
M00
Bit
Number
Bit
Mnemonic
7
GATE1
Timer 1 Gating Control Bit
Clear to enable Timer 1 whenever TR1 bit is set.
Set to enable Timer 1 only while INT1 pin is high and TR1 bit is set.
6
C/T1#
Timer 1 Counter/Timer Select Bit
Clear for Timer operation: Timer 1 counts the divided-down system clock.
Set for Counter operation: Timer 1 counts negative transitions on external pin T1.
5
M11
4
M01
Description
Timer 1 Mode Select Bits
M11 M01
Operating mode
0
0
Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1).
0
1
Mode 1: 16-bit Timer/Counter.
1
0
Mode 2: 8-bit auto-reload Timer/Counter (TL1).(1)
1 1 Mode 3: Timer 1 halted. Retains count.
3
GATE0
Timer 0 Gating Control Bit
Clear to enable Timer 0 whenever TR0 bit is set.
Set to enable Timer/Counter 0 only while INT0 pin is high and TR0 bit is set.
2
C/T0#
Timer 0 Counter/Timer Select Bit
Clear for Timer operation: Timer 0 counts the divided-down system clock.
Set for Counter operation: Timer 0 counts negative transitions on external pin T0.
Timer 0 Mode Select Bit
M10 M00
Operating mode
0
0
Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0).
0
1
Mode 1: 16-bit Timer/Counter.
1
0
Mode 2: 8-bit auto-reload Timer/Counter (TL0).(2)
M10
1
M00
0
1 1Mode 3: TL0 is an 8-bit Timer/Counter.
TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits.
Notes:
1. Reloaded from TH1 at overflow.
2. Reloaded from TH0 at overflow.
Reset Value = 0000 0000b
Table 11-2.
TH0 Register
TH0 (S:8Ch) – Timer 0 High Byte Register
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit Number
Bit
Mnemonic
Description
7:0
High Byte of Timer 0
Reset Value = 0000 0000b
Table 11-3.
58
TL0 Register
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
TL0 (S:8Ah) – Timer 0 Low Byte Register
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit Number
Bit
Mnemonic
Description
Low Byte of Timer 0
7:0
Reset Value = 0000 0000b
Table 11-4.
TH1 Register
TH1 (S:8Dh) – Timer 1 High Byte Register
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit Number
Bit
Mnemonic
Description
High Byte of Timer 1
7:0
Reset Value = 0000 0000b
Table 11-5.
TL1 Register
TL1 (S:8Bh) – Timer 1 Low Byte Register
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit Number
Bit
Mnemonic
Description
7:0
Low Byte of Timer 1
Reset Value = 0000 0000b
59
4341H–MP3–10/07
12. Watchdog Timer
The AT8xC51SND2C implement a hardware Watchdog Timer (WDT) that automatically resets
the chip if it is allowed to time out. The WDT provides a means of recovering from routines that
do not complete successfully due to software or hardware malfunctions.
12.1
Description
The WDT consists of a 14-bit prescaler followed by a 7-bit programmable counter. As shown in
Figure 12-1, the 14-bit prescaler is fed by the WDT clock detailed in Section “Watchdog Clock
Controller”, page 60.
The Watchdog Timer Reset register (WDTRST, see Table 12-2) provides control access to the
WDT, while the Watchdog Timer Program register (WDTPRG, see Figure 12-4) provides timeout period programming.
Three operations control the WDT:
•
Chip reset clears and disables the WDT.
•
Programming the time-out value to the WDTPRG register.
•
Writing a specific 2-Byte sequence to the WDTRST register clears and enables the WDT.
Figure 12-1. WDT Block Diagram
14-bit Prescaler
WDT
CLOCK
7-bit Counter
÷6
OV
RST
RST
To internal reset
SET
WTO2:0
1Eh-E1h Decoder
System Reset
RST
WDTPRG.2:0
EN
MATCH
OSC
CLOCK
Pulse Generator
RST
WDTRST
12.2
Watchdog Clock Controller
As shown in Figure 12-2 the WDT clock (FWDT) is derived from either the peripheral clock (FPER)
or the oscillator clock (FOSC) depending on the WTX2 bit in CKCON register. These clocks are
issued from the Clock Controller block as detailed in Section "Clock Controller", page 13. When
WTX2 bit is set, the WDT clock frequency is fixed and equal to the oscillator clock frequency
divided by 2. When cleared, the WDT clock frequency is equal to the oscillator clock frequency
divided by 2 in standard mode or to the oscillator clock frequency in X2 mode.
Figure 12-2. WDT Clock Controller and Symbol
PER
CLOCK
0
WDT Clock
1
OSC
CLOCK
÷2
WDT
CLOCK
WDT Clock Symbol
WTX2
CKCON.6
60
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
12.3
Watchdog Operation
After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh and E1h into
the WDTRST register. As soon as it is enabled, there is no way except the chip reset to disable
it. If it is not cleared using the previous sequence, the WDT overflows and forces a chip reset.
This overflow generates a high level 96 oscillator periods pulse on the RST pin to globally reset
the application (refer to Section “Power Management”, page 47).
The WDT time-out period can be adjusted using WTO2:0 bits located in the WDTPRG register
accordingly to the formula shown in Figure 12-3. In this formula, WTOval represents the decimal
value of WTO2:0 bits. Table 12-1 reports the time-out period depending on the WDT frequency.
Figure 12-3. WDT Time-Out Formula
WDTTO=
Table 12-1.
6 ⋅ ((214 ⋅ 2WTOval) – 1)
FWDT
WDT Time-Out Computation
FWDT (ms)
10 MHz(1)
12 MHz(2)
16 MHz(2)
20 MHz(2)
12.28
9.83
8.19
6.14
4.92
32.77
24.57
19.66
16.38
12.28
9.83
0
65.54
49.14
39.32
32.77
24.57
19.66
1
1
131.07
98.28
78.64
65.54
49.14
39.32
1
0
0
262.14
196.56
157.29
131.07
98.28
78.64
1
0
1
524.29
393.1
314.57
262.14
196.56
157.29
1
1
0
1049
786.24
629.15
524.29
393.12
314.57
1
1
1
2097
1572
1258
1049
786.24
629.15
WTO2
WTO1
WTO0
0
0
0
16.38
0
0
1
0
1
0
Notes:
12.3.1
6 MHz
(1)
8 MHz
(1)
1. These frequencies are achieved in X1 mode or in X2 mode when WTX2 = 1:
FWDT = FOSC ÷ 2.
2. These frequencies are achieved in X2 mode when WTX2 = 0: FWDT = FOSC.
WDT Behavior during Idle and Power-down Modes
Operation of the WDT during power reduction modes deserves special attention.
The WDT continues to count while the AT8xC51SND2C is in Idle mode. This means that you
must dedicate some internal or external hardware to service the WDT during Idle mode. One
approach is to use a peripheral Timer to generate an interrupt request when the Timer overflows. The interrupt service routine then clears the WDT, reloads the peripheral Timer for the
next service period and puts the AT8xC51SND2C back into Idle mode.
The Power-down mode stops all phase clocks. This causes the WDT to stop counting and to
hold its count. The WDT resumes counting from where it left off if the Power-down mode is terminated by INT0, INT1 or keyboard interrupt. To ensure that the WDT does not overflow shortly
after exiting the Power-down mode, it is recommended to clear the WDT just before entering
Power-down mode.
The WDT is cleared and disabled if the Power-down mode is terminated by a reset.
61
4341H–MP3–10/07
12.4
Registers
Table 12-2.
WDTRST Register
WDTRST (S:A6h Write only) – Watchdog Timer Reset Register
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit Number
Bit
Mnemonic
Description
7-0
-
Watchdog Control Value
Reset Value = XXXX XXXXb
Figure 12-4. WDTPRG Register
WDTPRG (S:A7h) – Watchdog Timer Program Register
7
6
5
4
3
2
1
0
-
-
-
-
-
WTO2
WTO1
WTO0
Bit Number
Bit
Mnemonic
Description
7-3
-
2-0
WTO2:0
Reserved
The value read from these bits is indeterminate. Do not set these bits.
Watchdog Timer Time-Out Selection Bits
Refer to Table 12-1 for time-out periods.
Reset Value = XXXX X000b
62
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
13. MP3 Decoder
The AT8xC51SND2C implement a MPEG I/II audio layer 3 decoder better known as MP3
decoder.
In MPEG I (ISO 11172-3) three layers of compression have been standardized supporting three
sampling frequencies: 48, 44.1, and 32 kHz. Among these layers, layer 3 allows highest compression rate of about 12:1 while still maintaining CD audio quality. For example, 3 minutes of
CD audio (16-bit PCM, 44.1 kHz) data, which needs about 32M bytes of storage, can be
encoded into only 2.7M bytes of MPEG I audio layer 3 data.
In MPEG II (ISO 13818-3), three additional sampling frequencies: 24, 22.05, and 16 kHz are
supported for low bit rates applications.
The AT8xC51SND2C can decode in real-time the MPEG I audio layer 3 encoded data into a
PCM audio data, and also supports MPEG II audio layer 3 additional frequencies.
Additional features are supported by the AT8xC51SND2C MP3 decoder such as volume control,
bass, medium, and treble controls, bass boost effect and ancillary data extraction.
13.1
13.1.1
Decoder
Description
The C51 core interfaces to the MP3 decoder through nine special function registers: MP3CON,
the MP3 Control register (see Table 13-5); MP3STA, the MP3 Status register (see Table 13-6);
MP3DAT, the MP3 Data register (see Table 13-7); MP3ANC, the Ancillary Data register (see
Table 13-9); MP3VOL and MP3VOR, the MP3 Volume Left and Right Control registers (see
Table 13-10 and Table 13-11); MP3BAS, MP3MED, and MP3TRE, the MP3 Bass, Medium, and
Treble Control registers (see Table 13-12, Table 13-13, and Table 13-14); and MPCLK, the MP3
Clock Divider register (see Table 13-15).
Figure 13-1 shows the MP3 decoder block diagram.
Figure 13-1. MP3 Decoder Block Diagram
Audio Data
From C51
8
1K Bytes
Frame Buffer
MP3DAT
Header Checker
Huffman Decoder
MPxREQ
ERRxxx MPFS1:0 MPVER
MP3STA1.n
MP3STA.5:3 MP3STA.2:1 MP3STA.0
Dequantizer
Stereo Processor
Side Information
MP3
CLOCK
Ancillary Buffer
MP3ANC
MPEN
MP3CON.7
Anti-Aliasing
MPBBST
MP3CON.6
MP3VOL
IMDCT
MP3VOR
MP3BAS
Sub-band
Synthesis
MP3MED
16
Decoded Data
To Audio Interface
MP3TRE
63
4341H–MP3–10/07
13.1.2
MP3 Data
The MP3 decoder does not start any frame decoding before having a complete frame in its input
buffer(1). In order to manage the load of MP3 data in the frame buffer, a hardware handshake
consisting of data request and data acknowledgment is implemented. Each time the MP3
decoder needs MP3 data, it sets the MPREQ, MPFREQ and MPBREQ flags respectively in
MP3STA and MP3STA1 registers. MPREQ flag can generate an interrupt if enabled as
explained in Section “Interrupt”. The CPU must then load data in the buffer by writing it through
MP3DAT register thus acknowledging the previous request. As shown in Figure 13-2, the
MPFREQ flag remains set while data (i.e a frame) is requested by the decoder. It is cleared
when no more data is requested and set again when new data are requested. MPBREQ flag
toggles at every Byte writing.
Note:
1. The first request after enable, consists in 1024 Bytes of data to fill in the input buffer.
Figure 13-2. Data Timing Diagram
MPREQ Flag
Cleared when Reading MP3STA
MPFREQ Flag
MPBREQ Flag
Write to MP3DAT
13.1.3
MP3 Clock
The MP3 decoder clock is generated by division of the PLL clock. The division factor is given by
MPCD4:0 bits in MP3CLK register. Figure 13-3 shows the MP3 decoder clock generator and its
calculation formula. The MP3 decoder clock frequency depends only on the incoming MP3
frames.
Figure 13-3. MP3 Clock Generator and Symbol
MP3CLK
PLL
CLOCK
MPCD4:0
MP3
CLOCK
MP3 Decoder Clock
MP3 Clock Symbol
PLLclk
MP3clk = ---------------------------MPCD + 1
As soon as the frame header has been decoded and the MPEG version extracted, the minimum
MP3 input frequency must be programmed according to Table 13-1.
Table 13-1.
64
MP3 Clock Frequency
MPEG Version
Minimum MP3 Clock (MHz)
I
21
II
10.5
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
13.2
13.2.1
Audio Controls
Volume Control
The MP3 decoder implements volume control on both right and left channels. The MP3VOR and
MP3VOL registers allow a 32-step volume control according to Table 13-2.
Table 13-2.
13.2.2
Volume Control
VOL4:0 or VOR4:0
Volume Gain (dB)
00000
Mute
00001
-33
00010
-27
11110
-1.5
11111
0
Equalization Control
Sound can be adjusted using a 3-band equalizer: a bass band under 750 Hz, a medium band
from 750 Hz to 3300 Hz and a treble band over 3300 Hz. The MP3BAS, MP3MED, and
MP3TRE registers allow a 32-step gain control in each band according to Table 13-3.
Table 13-3.
13.2.3
Bass, Medium, Treble Control
BAS4:0 or MED4:0 or TRE4:0
Gain (dB)
00000
-∞
00001
-14
00010
-10
11110
+1
11111
+1.5
Special Effect
The MPBBST bit in MP3CON register allows enabling of a bass boost effect with the following
characteristics: gain increase of +9 dB in the frequency under 375 Hz.
13.3
Decoding Errors
The three different errors that can appear during frame processing are detailed in the following
sections. All these errors can trigger an interrupt as explained in Section "Interrupt", page 66.
13.3.1
Layer Error
The ERRSYN flag in MP3STA is set when a non-supported layer is decoded in the header of the
frame that has been sent to the decoder.
13.3.2
Synchronization Error
The ERRSYN flag in MP3STA is set when no synchronization pattern is found in the data that
have been sent to the decoder.
65
4341H–MP3–10/07
13.3.3
CRC Error
When the CRC of a frame does not match the one calculated, the flag ERRCRC in MP3STA is
set. In this case, depending on the CRCEN bit in MP3CON, the frame is played or rejected. In
both cases, noise may appear at audio output.
13.4
Frame Information
The MP3 frame header contains information on the audio data contained in the frame. These
informations is made available in the MP3STA register for you information. MPVER and
MPFS1:0 bits allow decoding of the sampling frequency according to Table 13-4. MPVER bit
gives the MPEG version (2 or 1).
Table 13-4.
13.5
MP3 Frame Frequency Sampling
MPVER
MPFS1
MPFS0
Fs (kHz)
0
0
0
22.05 (MPEG II)
0
0
1
24 (MPEG II)
0
1
0
16 (MPEG II)
0
1
1
Reserved
1
0
0
44.1 (MPEG I)
1
0
1
48 (MPEG I)
1
1
0
32 (MPEG I)
1
1
1
Reserved
Ancillary Data
MP3 frames also contain data bits called ancillary data. These data are made available in the
MP3ANC register for each frame. As shown in Figure 13-4, the ancillary data are available by
Bytes when MPANC flag in MP3STA register is set. MPANC flag is set when the ancillary buffer
is not empty (at least one ancillary data is available) and is cleared only when there is no more
ancillary data in the buffer. This flag can generate an interrupt as explained in Section "Interrupt", page 66. When set, software must read all Bytes to empty the ancillary buffer.
Figure 13-4. Ancillary Data Block Diagram
Ancillary
Data To C51
13.6
13.6.1
8
MP3ANC
8
7-Byte
Ancillary Buffer
MPANC
MP3STA.7
Interrupt
Description
As shown in Figure 13-5, the MP3 decoder implements five interrupt sources reported in ERRCRC, ERRSYN, ERRLAY, MPREQ, and MPANC flags in MP3STA register.
All these sources are maskable separately using MSKCRC, MSKSYN, MSKLAY, MSKREQ, and
MSKANC mask bits respectively in MP3CON register.
The MP3 interrupt is enabled by setting EMP3 bit in IEN0 register. This assumes interrupts are
globally enabled by setting EA bit in IEN0 register.
66
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4341H–MP3–10/07
AT8xC51SND2C/MP3B
All interrupt flags but MPANC are cleared when reading MP3STA register. The MPANC flag is
cleared by hardware when the ancillary buffer becomes empty..
Figure 13-5. MP3 Decoder Interrupt System
MPANC
MP3STA.7
MSKANC
MP3CON.4
MPREQ
MP3STA.6
MSKREQ
ERRLAY
MP3 Decoder
Interrupt Request
MP3CON.3
MP3STA.5
ERRSYN
MSKLAY
EMP3
MP3CON.2
IEN0.5
MP3STA.4
MSKSYN
ERRCRC
MP3CON.1
MP3STA.3
MSKCRC
MP3CON.0
67
4341H–MP3–10/07
13.6.2
Management
Reading the MP3STA register automatically clears the interrupt flags (acknowledgment) except
the MPANC flags. This implies that register content must be saved and tested, interrupt flag by
interrupt flag to be sure not to forget any interrupts.
Figure 13-6. MP3 Interrupt Service Routine Flow
MP3 Decoder
ISR
Read MP3STA
Data Request?
MPFREQ = 1?
Data Request
Handler
Write MP3 Data
to MP3DAT
Ancillary Data?(1)
MPANC = 1?
Ancillary Data
Handler
Sync Error?(1)
ERRSYN = 1?
Read ANN2:0 Ancillary
Bytes From MP3ANC
Synchro Error
Handler
Reload MP3 Frame
Through MP3DAT
Layer Error?(1)
ERRSYN = 1?
Layer Error
Handler
CRC Error
Handler
Load New MP3 Frame
Through MP3DAT
Note:
68
1. Test these bits only if needed (unmasked interrupt).
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
13.7
Registers
Table 13-5.
MP3CON Register
MP3CON (S:AAh) – MP3 Decoder Control Register
7
6
5
4
3
2
1
0
MPEN
MPBBST
CRCEN
MSKANC
MSKREQ
MSKLAY
MSKSYN
MSKCRC
Bit Number
Bit
Mnemonic
Description
7
MPEN
6
MPBBST
Bass Boost Bit
Set to enable the bass boost sound effect.
Clear to disable the bass boost sound effect.
5
CRCEN
CRC Check Enable Bit
Set to enable processing of frame that contains CRC error. Frame is played whatever
the error.
Clear to disable processing of frame that contains CRC error. Frame is skipped.
4
MSKANC
MPANC Flag Mask Bit
Set to prevent the MPANC flag from generating a MP3 interrupt.
Clear to allow the MPANC flag to generate a MP3 interrupt.
3
MSKREQ
MPREQ Flag Mask Bit
Set to prevent the MPREQ flag from generating a MP3 interrupt.
Clear to allow the MPREQ flag to generate a MP3 interrupt.
2
MSKLAY
ERRLAY Flag Mask Bit
Set to prevent the ERRLAY flag from generating a MP3 interrupt.
Clear to allow the ERRLAY flag to generate a MP3 interrupt.
1
MSKSYN
ERRSYN Flag Mask Bit
Set to prevent the ERRSYN flag from generating a MP3 interrupt.
Clear to allow the ERRSYN flag to generate a MP3 interrupt.
0
MSKCRC
ERRCRC Flag Mask Bit
Set to prevent the ERRCRC flag from generating a MP3 interrupt.
Clear to allow the ERRCRC flag to generate a MP3 interrupt.
MP3 Decoder Enable Bit
Set to enable the MP3 decoder.
Clear to disable the MP3 decoder.
Reset Value = 0011 1111b
69
4341H–MP3–10/07
Table 13-6.
MP3STA Register
MP3STA (S:C8h Read Only) – MP3 Decoder Status Register
7
6
5
4
3
2
1
0
MPANC
MPREQ
ERRLAY
ERRSYN
ERRCRC
MPFS1
MPFS0
MPVER
Bit Number
Bit
Mnemonic
Description
7
MPANC
Ancillary Data Available Flag
Set by hardware as soon as one ancillary data is available (buffer not empty).
Cleared by hardware when no more ancillary data is available (buffer empty).
6
MPREQ
MP3 Data Request Flag
Set by hardware when MP3 decoder request data.
Cleared when reading MP3STA.
5
ERRLAY
Invalid Layer Error Flag
Set by hardware when an invalid layer is encountered.
Cleared when reading MP3STA.
4
ERRSYN
Frame Synchronization Error Flag
Set by hardware when no synchronization pattern is encountered in a frame.
Cleared when reading MP3STA.
3
ERRCRC
CRC Error Flag
Set by hardware when a frame handling CRC is corrupted.
Cleared when reading MP3STA.
2-1
MPFS1:0
Frequency Sampling Bits
Refer to Table 13-4 for bits description.
0
MPVER
MPEG Version Bit
Set by the MP3 decoder when the loaded frame is a MPEG I frame.
Cleared by the MP3 decoder when the loaded frame is a MPEG II frame.
Reset Value = 0000 0001b
Table 13-7.
MP3DAT Register
MP3DAT (S:ACh) – MP3 Data Register
7
6
5
4
3
2
1
0
MPD7
MPD6
MPD5
MPD4
MPD3
MPD2
MPD1
MPD0
Bit Number
Bit
Mnemonic
Description
7-0
MPD7:0
Input Stream Data Buffer
8-bit MP3 stream data input buffer.
Reset Value = 0000 0000b
70
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4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 13-8.
MP3STA1 Register
MP3STA1 (S:AFh) – MP3 Decoder Status Register 1
7
6
5
4
3
2
1
0
-
-
-
MPFREQ
MPFREQ
-
-
-
Bit Number
Bit
Mnemonic
Description
7-5
-
4
MPFREQ
MP3 Frame Data Request Flag
Set by hardware when MP3 decoder request data.
Cleared when MP3 decoder no more request data .
3
MPBREQ
MP3 Byte Data Request Flag
Set by hardware when MP3 decoder request data.
Cleared when writing to MP3DAT.
2-0
-
Reserved
The value read from these bits is always 0. Do not set these bits.
Reserved
The value read from these bits is always 0. Do not set these bits.
Reset Value = 0001 0001b
Table 13-9.
MP3ANC Register
MP3ANC (S:ADh Read Only) – MP3 Ancillary Data Register
7
6
5
4
3
2
1
0
AND7
AND6
AND5
AND4
AND3
AND2
AND1
AND0
Bit Number
Bit
Mnemonic
Description
7-0
AND7:0
Ancillary Data Buffer
MP3 ancillary data Byte buffer.
Reset Value = 0000 0000b
Table 13-10. MP3VOL Register
MP3VOL (S:9Eh) – MP3 Volume Left Control Register
7
6
5
4
3
2
1
0
-
-
-
VOL4
VOL3
VOL2
VOL1
VOL0
Bit Number
Bit
Mnemonic
Description
7-5
-
Reserved
The value read from these bits is always 0. Do not set these bits.
4-0
VOL4:0
Volume Left Value
Refer to Table 13-2 for the left channel volume control description.
Reset Value = 0000 0000b
71
4341H–MP3–10/07
Table 13-11. MP3VOR Register
MP3VOR (S:9Fh) – MP3 Volume Right Control Register
7
6
5
4
3
2
1
0
-
-
-
VOR4
VOR3
VOR2
VOR1
VOR0
Bit Number
Bit
Mnemonic
Description
7-5
-
4-0
VOR4:0
Reserved
The value read from these bits is always 0. Do not set these bits.
Volume Right Value
Refer to Table 13-2 for the right channel volume control description.
Reset Value = 0000 0000b
Table 13-12. MP3BAS Register
MP3BAS (S:B4h) – MP3 Bass Control Register
7
6
5
4
3
2
1
0
-
-
-
BAS4
BAS3
BAS2
BAS1
BAS0
Bit Number
Bit
Mnemonic
Description
7-5
-
4-0
BAS4:0
Reserved
The value read from these bits is always 0. Do not set these bits.
Bass Gain Value
Refer to Table 13-3 for the bass control description.
Reset Value = 0000 0000b
Table 13-13. MP3MED Register
MP3MED (S:B5h) – MP3 Medium Control Register
7
6
5
4
3
2
1
0
-
-
-
MED4
MED3
MED2
MED1
MED0
Bit Number
Bit
Mnemonic
Description
7-5
-
4-0
MED4:0
Reserved
The value read from these bits is always 0. Do not set these bits.
Medium Gain Value
Refer to Table 13-3 for the medium control description.
Reset Value = 0000 0000b
72
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4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 13-14. MP3TRE Register
MP3TRE (S:B6h) – MP3 Treble Control Register
7
6
5
4
3
2
1
0
-
-
-
TRE4
TRE3
TRE2
TRE1
TRE0
Bit Number
Bit
Mnemonic
Description
7-5
-
4-0
TRE4:0
Reserved
The value read from these bits is always 0. Do not set these bits.
Treble Gain Value
Refer to Table 13-3 for the treble control description.
Reset Value = 0000 0000b
Table 13-15. MP3CLK Register
MP3CLK (S:EBh) – MP3 Clock Divider Register
7
6
5
4
3
2
1
0
-
-
-
MPCD4
MPCD3
MPCD2
MPCD1
MPCD0
Bit Number
Bit
Mnemonic
Description
7-5
-
4-0
MPCD4:0
Reserved
The value read from these bits is always 0. Do not set these bits.
MP3 Decoder Clock Divider
5-bit divider for MP3 decoder clock generation.
Reset Value = 0000 0000b
73
4341H–MP3–10/07
14. Audio Output Interface
The AT8xC51SND2C implement an audio output interface allowing the audio bitstream to be
output in various formats. It is compatible with right and left justification PCM and I2S formats
and thanks to the on-chip PLL (see Section “Clock Controller”, page 13) allows connection of
almost all of the commercial audio DAC families available on the market.
The audio bitstream can be from 2 different types:
14.1
•
The MP3 decoded bitstream coming from the MP3 decoder for playing songs.
•
The audio bitstream coming from the MCU for outputting voice or sounds.
Description
The C51 core interfaces to the audio interface through five special function registers: AUDCON0
and AUDCON1, the Audio Control registers (see Table 14-3 and Table 14-4); AUDSTA, the
Audio Status register (see Table 14-5); AUDDAT, the Audio Data register (see Table 14-6); and
AUDCLK, the Audio Clock Divider register (see Table 14-7).
Figure 14-1 shows the audio interface block diagram, blocks are detailed in the following
sections.
Figure 14-1. Audio Interface Block Diagram
SCLK
AUD
CLOCK
DCLK
Clock Generator
0
DSEL
AUDEN
1
AUDCON1.0
Data Ready
HLR
DSIZ
AUDCON0.0
AUDCON0.1
POL
AUDCON0.2
Audio Data
From MP3
Decoder
16
MP3 Buffer
16
0
16
Sample
Request To
MP3 Decoder
Data Converter
DOUT
1
JUST4:0
DRQEN
SRC
AUDCON1.6
AUDCON0.7:3
AUDCON1.7
SREQ
Audio Data
From C51
8
Audio Buffer
AUDDAT
AUDSTA.7
UDRN
AUDSTA.6
To DAC
AUBUSY
DUP1:0
AUDSTA.5
AUDCON1.2:1
74
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4341H–MP3–10/07
AT8xC51SND2C/MP3B
14.2
Clock Generator
The audio interface clock is generated by division of the PLL clock. The division factor is given
by AUCD4:0 bits in CLKAUD register. Figure 14-2 shows the audio interface clock generator
and its calculation formula. The audio interface clock frequency depends on the incoming MP3
frames and the audio DAC used.
Figure 14-2. Audio Clock Generator and Symbol
AUDCLK
PLL
CLOCK
AUCD4:0
AUD
CLOCK
Audio Interface Clock
Audio Clock Symbol
PLLclk
AUDclk = --------------------------AUCD + 1
As soon as audio interface is enabled by setting AUDEN bit in AUDCON1 register, the master
clock generated by the PLL is output on the SCLK pin which is the DAC system clock. This clock
is output at 256 or 384 times the sampling frequency depending on the DAC capabilities. HLR bit
in AUDCON0 register must be set according to this rate for properly generating the audio bit
clock on the DCLK pin and the word selection clock on the DSEL pin. These clocks are not generated when no data is available at the data converter input.
For DAC compatibility, the bit clock frequency is programmable for outputting 16 bits or 32 bits
per channel using the DSIZ bit in AUDCON0 register (see Section "Data Converter", page 75),
and the word selection signal is programmable for outputting left channel on low or high level
according to POL bit in AUDCON0 register as shown in Figure 14-3.
Figure 14-3. DSEL Output Polarity
14.3
POL = 0
Left Channel
Right Channel
POL = 1
Left Channel
Right Channel
Data Converter
The data converter block converts the audio stream input from the 16-bit parallel format to a
serial format. For accepting all PCM formats and I2S format, JUST4:0 bits in AUDCON0 register
are used to shift the data output point. As shown in Figure 14-4, these bits allow MSB justification by setting JUST4:0 = 00000, LSB justification by setting JUST4:0 = 10000, I2S justification
by setting JUST4:0 = 00001, and more than 16-bit LSB justification by filling the low significant
bits with logic 0.
Table 14-1. DAC Format Programing Examples
Dac Format
POL
DSIZ
JUST4:0
16-bit I2S
0
0
00001
2
> 16-bit I S
0
1
00001
16-bit PCM
1
0
00000
18-bit PCM LSB justified
1
1
01110
20-bit PCM LSB justified
1
1
01100
20-bit PCM MSB justified
1
1
00000
75
4341H–MP3–10/07
Figure 14-4. Audio Output Format
DSEL
DCLK
DOUT
Left Channel
1
2
3
Right Channel
13
14
15
LSB MSB B14
16
B1
1
2
3
13
14
15
LSB MSB B14
16
B1
I2S Format with DSIZ = 0 and JUST4:0 = 00001.
DSEL
DCLK
Left Channel
1
DOUT
2
Right Channel
3
17
MSB B14
LSB
18
32
1
2
3
17
MSB B14
LSB
18
32
I2S Format with DSIZ = 1 and JUST4:0 = 00001.
DSEL
DCLK
DOUT
Left Channel
1
2
3
Right Channel
13
14
MSB B14
15
B1
16
1
2
3
13
14
LSB MSB B15
15
B1
16
LSB
MSB/LSB Justified Format with DSIZ = 0 and JUST4:0 = 00000.
DSEL
DCLK
Left Channel
1
16
DOUT
17
Right Channel
18
31
MSB B14
B1
32
1
16
LSB
17
18
31
MSB B14
B1
32
LSB
16-bit LSB Justified Format with DSIZ = 1 and JUST4:0 = 10000.
DSEL
DCLK
Left Channel
1
DOUT
15
16
MSB B16
Right Channel
30
B2
31
B1
32
LSB
1
15
16
MSB B16
30
B2
31
B1
32
LSB
18-bit LSB Justified Format with DSIZ = 1 and JUST4:0 = 01110.
The data converter receives its audio stream from 2 sources selected by the SRC bit in
AUDCON1 register. When cleared, the audio stream comes from the MP3 decoder (see
Section “MP3 Decoder”, page 63) for song playing. When set, the audio stream is coming from
the C51 core for voice or sound playing.
As soon as first audio data is input to the data converter, it enables the clock generator for generating the bit and word clocks.
14.4
Audio Buffer
In voice or sound playing mode, the audio stream comes from the C51 core through an audio
buffer. The data is in 8-bit format and is sampled at 8 kHz. The audio buffer adapts the sample
format and rate. The sample format is extended to 16 bits by filling the LSB to 00h. Rate is
adapted to the DAC rate by duplicating the data using DUP1:0 bits in AUDCON1 register
according to Table 14-2.
The audio buffer interfaces to the C51 core through three flags: the sample request flag (SREQ
in AUDSTA register), the under-run flag (UNDR in AUDSTA register) and the busy flag
(AUBUSY in AUDSTA register). SREQ and UNDR can generate an interrupt request as
explained in Section "Interrupt Request", page 77. The buffer size is 8 Bytes large. SREQ is set
when the samples number switches from 4 to 3 and reset when the samples number switches
from 4 to 5; UNDR is set when the buffer becomes empty signaling that the audio interface ran
out of samples; and AUBUSY is set when the buffer is full.
76
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4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 14-2.
14.5
Sample Duplication Factor
DUP1
DUP0
Factor
0
0
No sample duplication, DAC rate = 8 kHz (C51 rate).
0
1
One sample duplication, DAC rate = 16 kHz (2 x C51 rate).
1
0
2 samples duplication, DAC rate = 32 kHz (4 x C51 rate).
1
1
Three samples duplication, DAC rate = 48 kHz (6 x C51 rate).
MP3 Buffer
In song playing mode, the audio stream comes from the MP3 decoder through a buffer. The
MP3 buffer is used to store the decoded MP3 data and interfaces to the decoder through a 16bit data input and data request signal. This signal asks for data when the buffer has enough
space to receive new data. Data request is conditioned by the DREQEN bit in AUDCON1 register. When set, the buffer requests data to the MP3 decoder. When cleared no more data is
requested but data are output until the buffer is empty. This bit can be used to suspend the audio
generation (pause mode).
14.6
Interrupt Request
The audio interrupt request can be generated by 2 sources when in C51 audio mode: a sample
request when SREQ flag in AUDSTA register is set to logic 1, and an under-run condition when
UDRN flag in AUDSTA register is set to logic 1. Both sources can be enabled separately by
masking one of them using the MSREQ and MUDRN bits in AUDCON1 register. A global enable
of the audio interface is provided by setting the EAUD bit in IEN0 register.
The interrupt is requested each time one of the 2 sources is set to one. The source flags are
cleared by writing some data in the audio buffer through AUDDAT, but the global audio interrupt
flag is cleared by hardware when the interrupt service routine is executed.
Figure 14-5. Audio Interface Interrupt System
UDRN
AUDSTA.6
Audio
Interrupt
Request
MUDRN
AUDCON1.4
SREQ
EAUD
AUDSTA.7
IEN0.6
MSREQ
AUDCON1.5
14.7
MP3 Song Playing
In MP3 song playing mode, the operations to do are to configure the PLL and the audio interface
according to the DAC selected. The audio clock is programmed to generate the 256·Fs or
384·Fs as explained in Section "Clock Generator", page 75. Figure 14-6 shows the configuration
flow of the audio interface when in MP3 song mode.
77
4341H–MP3–10/07
Figure 14-6. MP3 Mode Audio Configuration Flow
MP3 Mode
Configuration
Program Audio Clock
Configure Interface
HLR = X
DSIZ = X
POL = X
JUST4:0 = XXXXXb
SRC = 0
14.8
Enable DAC System
Clock
AUDEN = 1
Wait For
DAC Set-up Time
Enable Data Request
DRQEN = 1
Registers
Table 14-3.
AUDCON0 Register
AUDCON0 (S:9Ah) – Audio Interface Control Register 0
7
6
5
4
3
2
1
0
JUST4
JUST3
JUST2
JUST1
JUST0
POL
DSIZ
HLR
Bit Number
Bit
Mnemonic
Description
7-3
JUST4:0
2
POL
DSEL Signal Output Polarity
Set to output the left channel on high level of DSEL output (PCM mode).
Clear to output the left channel on the low level of DSEL output (I2S mode).
1
DSIZ
Audio Data Size
Set to select 32-bit data output format.
Clear to select 16-bit data output format.
0
HLR
High/Low Rate Bit
Set by software when the PLL clock frequency is 384·Fs.
Clear by software when the PLL clock frequency is 256·Fs.
Audio Stream Justification Bits
Refer to Section "Data Converter", page 75 for bits description.
Reset Value = 0000 1000b
Table 14-4.
AUDCON1 Register
AUDCON1 (S:9Bh) – Audio Interface Control Register 1
78
7
6
5
4
3
2
1
0
SRC
DRQEN
MSREQ
MUDRN
-
DUP1
DUP0
AUDEN
Bit Number
Bit
Mnemonic
Description
7
SRC
Audio Source Bit
Set to select C51 as audio source for voice or sound playing.
Clear to select the MP3 decoder output as audio source for song playing.
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Bit Number
Bit
Mnemonic
6
DRQEN
MP3 Decoded Data Request Enable Bit
Set to enable data request to the MP3 decoder and to start playing song.
Clear to disable data request to the MP3 decoder.
5
MSREQ
Audio Sample Request Flag Mask Bit
Set to prevent the SREQ flag from generating an audio interrupt.
Clear to allow the SREQ flag to generate an audio interrupt.
4
MUDRN
Audio Sample Under-run Flag Mask Bit
Set to prevent the UDRN flag from generating an audio interrupt.
Clear to allow the UDRN flag to generate an audio interrupt.
3
-
2-1
DUP1:0
Audio Duplication Factor
Refer to Table 14-2 for bits description.
0
AUDEN
Audio Interface Enable Bit
Set to enable the audio interface.
Clear to disable the audio interface.
Description
Reserved
The value read from this bit is always 0. Do not set this bit.
Reset Value = 1011 0010b
Table 14-5.
AUDSTA Register
AUDSTA (S:9Ch Read Only) – Audio Interface Status Register
7
6
5
4
3
2
1
0
SREQ
UDRN
AUBUSY
-
-
-
-
-
Bit Number
Bit
Mnemonic
Description
7
6
SREQ
Audio Sample Request Flag
Set in C51 audio source mode when the audio interface request samples (buffer half
empty). This bit generates an interrupt if not masked and if enabled in IEN0.
Cleared by hardware when samples are loaded in AUDDAT.
UDRN
Audio Sample Under-run Flag
Set in C51 audio source mode when the audio interface runs out of samples (buffer
empty). This bit generates an interrupt if not masked and if enabled in IEN0.
Cleared by hardware when samples are loaded in AUDDAT.
5
AUBUSY
4-0
-
Audio Interface Busy Bit
Set in C51 audio source mode when the audio interface can not accept more sample
(buffer full).
Cleared by hardware when buffer is no more full.
Reserved
The value read from these bits is always 0. Do not set these bits.
Reset Value = 1100 0000b
79
4341H–MP3–10/07
Table 14-6.
AUDDAT Register
AUDDAT (S:9Dh) – Audio Interface Data Register
7
6
5
4
3
2
1
0
AUD7
AUD6
AUD5
AUD4
AUD3
AUD2
AUD1
AUD0
Bit Number
Bit
Mnemonic
Description
7-0
AUD7:0
Audio Data
8-bit sampling data for voice or sound playing.
Reset Value = 1111 1111b
Table 14-7.
AUDCLK Register
AUDCLK (S:ECh) – Audio Clock Divider Register
7
6
5
4
3
2
1
0
-
-
-
AUCD4
AUCD3
AUCD2
AUCD1
AUCD0
Bit Number
Bit
Mnemonic
Description
7-5
-
4-0
AUCD4:0
Reserved
The value read from these bits is always 0. Do not set these bits.
Audio Clock Divider
5-bit divider for audio clock generation.
Reset Value = 0000 0000b
80
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
15. DAC and PA Interface
The AT8xC51SND2C implements a stereo Audio Digital-to-Analog Converter and Audio Power
Amplifier targeted for Li-Ion or Ni-Mh battery powered devices.
Figure 15-1. Audio Interface Block Diagram
MP3
Decoder
Unit
DOUT
DCLK
DSEL
I2S/PCM
Audio
Interface
HSR
HSL
AUXP
AUXN
Audio
DAC
LINEL
LINER
MONOP
MONON
PAINP
PAINN
HPP
HPN
15.1
Serial Audio Interface
SCLK
AUDCDIN
AUDCDOUT
AUDCCLK
AUDCCS
Audio
PA
DAC
The Stereo DAC section is a complete high performance, stereo, audio digital-to-analog converter delivering 93 dB Dynamic Range. It comprises a multibit sigma-delta modulator with
dither, continuous time analog filters and analog output drive circuitry. This architecture provides
a high insensitivity to clock jitter. The digital interpolation filter increases the sample rate by a
factor of 8 using 3 linear phase half-band filters cascaded, followed by a first order SINC interpolator with a factor of 8. This filter eliminates the images of baseband audio, remaining only the
image at 64x the input sample rate, which is eliminated by the analog post filter. Optionally, a
dither signal can be added that may reduce eventual noise tones at the output. However, the
use of a multibit sigma-delta modulator already provides extremely low noise tones energy.
Master clock is 128 up to 512 times the input data rate allowing choice of input data rate up to 50
kHz, including standard audio rates of 48, 44.1, 32, 16 and 8 kHz. The DAC section is followed
by a volume and mute control and can be simultaneously played back directly through a Stereo
32Ω Headset pair of drivers. The Stereo 32Ω Headset pair of drivers also includes a mixer of a
LINEL and LINER pair of stereo inputs as well as a differential monaural auxiliary input (line
level).
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4341H–MP3–10/07
15.1.1
DAC Features
•
•
•
•
•
•
•
•
20 bit D/A Conversion
72dB Dynamic Range, -75dB THD Stereo line-in or microphone interface with 20dB amplification
93dB Dynamic Range, -80dB THD Stereo D/A conversion
74dB Dynamic Range / -65dB THD for 20mW output power over 32 Ohm loads
Stereo, Mono and Reverse Stereo Mixer
Left/Right speaker short-circuit detection flag
Differential mono auxiliary input amplifier and PA driver
Audio sampling rates (Fs): 16, 22.05, 24, 32, 44.1 and 48 kHz.
Figure 15-2. Stereo DAC functional diagram
PA Gain
MONOP
PADRV
+
MONON
AUXP
AUX
AUXN
AUXG Gain
LINEL
PGA
LLIG,RLIG Gain
20,12 to -33 dB
(3dB)
LINER
PGA
Line Out Gain
LLOG, RLOG
0 to -46.5dB
(1.5dB)
Master Playback
Gain
12 to -34dB (1.5dB)
Volume
Control
Volume
Control
DSEL
HSL
SPKR
DRV
32
+
DAC
+
Digital Filter
SCLK
Serial to
Parallel
Interface
DAC_OLC Gain
6 to -6dB (3dB)
HSR
82
SPKR
DRV
32
+
DAC
Volume
Control
+
Volume
Control
Digital Filter
DCLK
DOUT
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
15.1.2
15.1.2.1
Digital Signals Timing
Data Interface
To avoid noises at the output, the reset state is maintained until proper synchronism is achieved
in the DAC serial interface:
•
DSEL
•
SCLK
•
DCLK
•
DOUT
The data interface allows three different data transfer modes:
Figure 15-3. 20 bit I2S justified mode
SCLK
DSEL
DOUT
R1
R0
L(N-1)
L(N-2)
L(N-3)
...
L2
L1
L0
R(N-1)
R(N-2)
R(N-3)
...
R2
R1
R0
...
L2
L1
L0
R(N-1)
R(N-2)
R(N-3)
...
R2
R1
R0
L(N-1)
...
L1
L0
Figure 15-4. 20 bit MSB justified mode
SCLK
DSEL
DOUT
R0
L(N-1)
L(N-2)
L(N-3)
Figure 15-5. 20 bit LSB justified mode
SCLK
DSEL
DOUT
R0
L(N-1)
L(N-2)
R(N-1)
R(N-2)
...
R1
R0
L(N-1)
The selection between modes is done using the DINTSEL 1:0 in DAC_MISC register (Table 1522.) according with the following table:
DINTSEL 1:0
Format
00
I2S Justified
01
MSB Justified
1x
LSB Justified
The data interface always works in slave mode. This means that the DSEL and the DCLK signals are provided by microcontroller audio data interface.
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4341H–MP3–10/07
15.1.3
Serial Audio DAC Interface
The serial audio DAC interface is a Synchronous Peripheral Interface (SPI) in slave mode:
•
AUDCDIN: is used to transfer data in series from the master to the slave DAC.
It is driven by the master.
•
AUDCDOUT: is used to transfer data in series from the slave DAC to the master.
It is driven by the selected slave DAC.
•
Serial Clock (AUDCCLK): it is used to synchronize the data transmission both in and out the
devices through the AUDCDIN and AUDCDOUT lines.
Note:
Refer to Table 15-11. for DAC SPI Interface Description
Audio
DAC
Serial Audio Interface
Figure 15-6. Serial Audio Interface
AUDCDIN
AUDCDOUT
AUDCCLK
AUDCCS
Audio
PA
Protocol is as following to access DAC registers:
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AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Figure 15-7. Dac SPI Interface
AUDCCS
AUDCCLK
AUDCDIN
rw a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0
d7 d6 d5 d4 d3 d2 d1 d0
AUDCDOUT
15.1.4
DAC Interface SPI Protocol
On AUDCDIN, the first bit is a read/write bit. 0 indicates a write operation while 1 is for a read
operation. The 7 following bits are used for the register address and the 8 last ones are the write
data. For both address and data, the most significant bit is the first one.
In case of a read operation, AUDCDOUT provides the contents of the read register, MSB first.
The transfer is enabled by the AUDCCS signal active low. The interface is resetted at every rising edge of AUDCCS in order to come back to an idle state, even if the transfer does not
succeed. The DAC Interface SPI is synchronized with the serial clock AUDCCLK. Falling edge
latches AUDCDIN input and rising edge shifts AUDCDOUT output bits.
Note that the DLCK must run during any DAC SPI interface access (read or write).
Figure 15-8. DAC SPI Interface Timings
AUDCCS
Tc
Tssen
Thsen
Twl
AUDCCLK
Twh
Tssdi
Thsdi
AUDCDIN
Tdsdo
Thsdo
AUDCDOUT
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4341H–MP3–10/07
Table 15-1.
15.1.5
15.1.6
Dac SPI Interface Timings
Timing parameter
Description
Tc
AUDCCLK min period
150 ns
-
Twl
AUDCCLK min pulse width low
50 ns
-
Twh
AUDCCLK min pulse width high
50 ns
-
Tssen
Setup time AUDCCS falling to AUDCCLK rising
50 ns
-
Thsen
Hold time AUDCCLK falling to AUDCCS rising
50 ns
-
Tssdi
Setup time AUDCDIN valid to AUDCCLK falling
20 ns
-
Thsdi
Hold time AUDCCLK falling to AUDCDIN not valid
20 ns
-
Tdsdo
Delay time AUDCCLK rising to AUDCDOUT valid
-
20 ns
Thsdo
Hold time AUDCCLK rising to AUDCDOUT not valid
0 ns
-
DAC Register Tables
Table 15-2.
Min
Max
DAC Register Address
Address
Register
Name
Access
Reset state
00h
DAC_CTRL
Dac Control
Read/Write
00h
01h
DAC_LLIG
Dac Left Line in Gain
Read/Write
05h
02h
DAC_RLIG
Dac Right Line in Gain
Read/Write
05h
03h
DAC_LPMG
Dac Left Master Playback Gain
Read/Write
08h
04h
DAC_RPMG
Dac Right Master Playback Gain
Read/Write
08h
05h
DAC_LLOG
Dac Left Line Out Gain
Read/Write
00h
06h
DAC_RLOG
Dac Right Line Out Gain
Read/Write
00h
07h
DAC_OLC
Dac Output Level Control
Read/Write
22h
08h
DAC_MC
Dac Mixer Control
Read/Write
09h
09h
DAC_CSFC
Dac Clock and Sampling Frequency
Control
Read/Write
00h
0Ah
DAC_MISC
Dac Miscellaneous
Read/Write
00h
0Ch
DAC_PRECH
Dac Precharge Control
Read/Write
00h
0Dh
DAC_AUXG
Dac Auxilary input gain Control
Read/Write
05h
10h
DAC_RST
Dac Reset
Read/Write
00h
11h
PA_CRTL
Power Amplifier Control
Read/Write
00h
DAC Gain
The DAC implements severals gain control: line-in (Table 15-3.), master playback (), line-out
(Table 15-6.).
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AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 15-3.
Line-in gain
LLIG 4:0
Table 15-4.
RLIG 4:0
Gain (dB)
00000
20
00001
12
00010
9
00011
6
00100
3
00101
0
00110
-3
00111
-6
01000
-9
01001
-12
01010
-15
01011
-18
01100
-21
01101
-24
01110
-27
01111
-30
10000
-33
10001
< -60
Master Playback Gain
LMPG 5:0
RMPG 5:0
Gain (dB)
000000
12.0
000001
10.5
000010
9.0
000011
7.5
000100
6.0
000101
4.5
000110
3.0
000111
1.5
001000
0.0
001001
-1.5
001010
-3.0
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4341H–MP3–10/07
Table 15-4.
Master Playback Gain (Continued)
LMPG 5:0
Table 15-5.
RMPG 5:0
Gain (dB)
001011
-4.5
001100
-6.0
001101
-7.5
001110
-9.0
001111
-10.5
010000
-12.0
010001
-13.5
010010
-15.0
010011
-16.5
010100
-18.0
010101
-19.5
010110
-21.0
010111
-22.5
011000
-24.0
011001
-25.5
011010
-27.0
011011
-28.5
011100
-30.0
011101
-31.5
011110
-33.0
011111
-34.5
100000
mute
Line-out Gain
LLOG 5:0
88
RLOG 5:0
Gain (dB)
000000
0.0
000001
-1.5
000010
-3.0
000011
-4.5
000100
-6.0
000101
-7.5
000110
-9.0
000111
-10.5
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 15-5.
Table 15-6.
Line-out Gain (Continued)
001000
-12.0
001001
-13.5
001010
-15.0
001011
-16.5
001100
-18.0
001101
-19.5
001110
-21.0
001111
-22.5
010000
-24.0
010001
-25.5
010010
-27.0
010011
-28.5
010100
-30.0
010101
-31.5
010110
-33.0
010111
-34.5
011000
-36.0
011001
-37.5
011010
-39.0
011011
-40.5
011100
-42.0
011101
-43.5
011110
-45.0
011111
-46.5
100000
mute
DAC Output Level Control
LOLC 2:0
ROLC 2:0
Gain (dB)
000
6
001
3
010
0
011
-3
100
-6
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4341H–MP3–10/07
15.1.7
Digital Mixer Control
The Audio DAC features a digital mixer that allows the mixing and selection of multiple input
sources.
The mixing / multiplexing functions are described in the following table according with the next
figure:
Figure 15-9. Mixing / Multiplexing functions
Left channel
Volume
Control
1
+
Volume
Control
2
From digital
filters
To DACs
1
Volume
Control
+
2
Volume
Control
Right channel
Note:
Signal
Description
LMSMIN1
Left Channel Mono/Stereo Mixer Left Mixed input enable – High to enable, Low to disable
LMSMIN2
Left Channel Mono/Stereo Mixer Right Mixed input enable – High to enable, Low to disable
RMSMIN1
Right Channel Mono/Stereo Mixer Left Mixed input enable – High to enable, Low to disable
RMSMIN2
Right Channel Mono/Stereo Mixer Right Mixed input enable – High to enable, Low to disable
Note:
15.1.8
Whenever the two mixer inputs are selected, a –6 dB gain is applied to the output signal. Whenever only one input is selected, no gain is applied.
Refer to DAC_MC register Table 15-20. for signal description
Master Clock and Sampling Frequency Selection
The following table describes the different modes available for master clock and sampling frequency selection by setting OVRSEL bit in DAC_CSFC register (refer to Table 15-21.).
Table 15-7. Master Clock selection
OVRSEL
Master Clock
0
256 x FS
1
384 x FS
The selection of input sample size is done using the NBITS 1:0 in DAC_MISC register (refer to
Table 15-22.) according to Table 15-8.
Table 15-8. Input Sample Size Selection
90
NBITS 1:0
Format
00
16 bits
01
18 bits
10
20 bits
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
The selection between modes is done using DINTSEL 1:0 in DAC_MISC register (refer to Table
15-22.) according to Table 15-9.
Table 15-9. Format Selection
15.1.9
DINTSEL 1:0
Format
00
I2S Justified
01
MSB Justified
1x
LSB Justified
De-emphasis and dither enable
The circuit features a de-emphasis filter for the playback channel. To enable the de-emphasis filtering, DEEMPEN must be set to high.
Likewise, the dither option (added in the playback channel) is enabled by setting the DITHEN
signal to High.
Table 15-10. DAC Auxlilary Input Gain
AUXG 4:0
Gain (dB)
00000
20
00001
12
00010
9
00011
6
00100
3
00101
0
00110
-3
00111
-6
01000
-9
01001
-12
01010
-15
01011
-18
01100
-21
01101
-24
01110
-27
01111
-30
10000
-33
10001
<-60
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4341H–MP3–10/07
15.1.10
Register
Table 15-11. AUXCON Register
AUXCON (S:90h) – Auxiliary Control Register
7
6
5
4
3
2
1
0
SDA
SCL
-
AUDCDOUT
AUDCDIN
AUDCCLK
AUDCCS
KIN0
Bit
Number
Bit Mnemonic
7
SDA
Description
TWI Serial Data
SDA is the bidirectional Two Wire data line.
TWI Serial Clock
When TWI controller is in master mode, SCL outputs the serial clock to the slave
peripherals. When TWI controller is in slave mode, SCL receives clock from the master
controller.
6
SCL
5
-
4
AUDCDOUT
3
AUDCDIN
Audio Dac SPI Data Input
2
AUDCCLK
Audio Dac SPI clock
1
AUDCCS
Not used.
Audio Dac SPI Data Output.
Audio Dac Chip select
Set to deselect DAC
Clear to select DAC
0
KIN0
Keyboard Input Interrupt.
Reset Value = 1111 1111b
Table 15-12. Dac Control Register Register - DAC_CTRL (00h)
92
7
6
5
4
3
2
1
0
ONPADRV
ONAUXIN
ONDACR
ONDACL
ONLNOR
ONLNOL
ONLNIR
ONLNIL
Bit
Bit
Number
Mnemonic
7
ONPADRV
6
ONAUXIN
5
ONDACR
4
ONDACL
3
ONLNOR
2
ONLNOL
1
ONLNIR
Description
Differential mono PA driver
Clear to power down. Set to power up.
Differential mono auxiliary input amplifier
Clear to power down. Set to power up.
Right channel DAC
Clear to power down. Set to power up.
Left channel DAC
Clear to power down. Set to power up.
Right channel line out driver
Clear to power down. Set to power up.
Left channel line out driver
Clear to power down. Set to power up.
Right channel line in amplifier
Clear to power down. Set to power up.
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
0
Left channel line in amplifier
ONLNIL
Clear to power down. Set to power up.
Reset Value = 00000000b
Table 15-13. DAC Left Line In Gain Register - DAC_LLIG (01h)
7
6
5
4
3
2
1
0
-
-
-
LLIG4
LLIG3
LLIG2
LLIG1
LLIG0
Bit
Bit
Number
Mnemonic
7:5
-
4:0
LLIG 4:0
Description
Not used
Left channel line in analog gain selector
Reset Value = 00000101b
Table 15-14. DAC Right Line In Gain Register - DAC_RLIG (02h)
7
6
5
4
3
2
1
0
-
-
-
RLIG4
RLIG3
RLIG2
RLIG1
RLIG0
Bit
Number
Description
Bit Mnemonic
7:5
-
Not used
4:0
RLIG 4:0
Right channel line in analog gain selector
Reset Value = 0000101b
Table 15-15. DAC Left Master Playback Gain Register - DAC_LMPG (03h)
7
6
5
4
3
2
1
0
-
-
LMPG5
LMPG4
LMPG3
LMPG2
LMPG1
LMPG0
Bit
Number
Description
Bit Mnemonic
7:6
-
5:0
LMPG 5:0
Not used
Left channel master playback digital gain selector
Reset Value = 00001000b
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4341H–MP3–10/07
Table 15-16. DAC Right Master Playback Gain Register - DAC_RMPG (04h)
7
6
5
4
3
2
1
0
-
-
RMPG5
RMPG4
RMPG3
RMPG2
RMPG1
RMPG0
Bit
Number
Description
Bit Mnemonic
7:6
-
Not used
5:0
RMPG 5:0
Right channel master playback digital gain selector
Reset Value = 00001000b
Table 15-17. DAC Left Line Out Gain Register - DAC_LLOG (05h)
7
6
5
4
3
2
1
0
-
-
LLOG5
LLOG4
LLOG3
LLOG2
LLOG1
LLOG0
Bit
Number
Description
Bit Mnemonic
7:6
-
5:0
LLOG 5:0
Not used
Left channel line out digital gain selector
Reset Value = 00000000b
Table 15-18. DAC Rigth Line Out Gain Register - DAC_RLOG (06h)
7
6
5
4
3
2
1
0
-
-
RLOG5
RLOG4
RLOG3
RLOG2
RLOG1
RLOG0
Bit
Number
7:6
5:0
Description
Bit Mnemonic
RLOG 5:0
Not used
Right channel line out digital gain selector
Reset Value = 00000000b
94
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 15-19. DAC Output Level Control Register - DAC_OLC (07h)
7
6
5
4
3
2
1
0
RSHORT
ROLC2
RLOC1
RLOC0
LSHORT
LOLC2
LOLC1
LOLC0
Bit
Number
Bit Mnemonic Description
Right channel short circuit indicator (persistent; after being set, bit is not cleared
7
RSHORT
automatically even after the short circuit is eliminated; must be cleared by reset
cycle or direct register write operation)
6:4
ROLC 2:0
Right channel output level control selector
3
LSHORT
automatically even after the short circuit is eliminated; must be cleared by reset
Left channel short circuit indicator (persistent; after being set, bit is not cleared
cycle or direct register write operation)
2:0
LOLC 2:0
Left channel output level control selector
Reset Value = 00100010b
Table 15-20. Dac Mixer Control Register - DAC_MC (08h)
7
6
5
4
3
2
1
0
-
-
INVR
INVL
RMSMIN2
RMSMIN1
LMSMIN2
LMSMIN1
Bit
Number
Bit Mnemonic
7:6
-
5
INVR
4
INVL
3
RMSMIN2
2
RMSMIN1
1
LMSMIN2
0
LMSMIN1
Description
Not used
Right channel mixer output invert
Set to enable. Clear to disable.
Left channel mixer output invert.
Set to enable. Clear to disable.
Right Channel Mono/Stereo Mixer Right Mixed input enable
Set to enable. Clear to disable.
Right Channel Mono/Stereo Mixer Left Mixed input enable
Set to enable. Clear to disable.
Left Channel Mono/Stereo Mixer Right Mixed input enable
Set to enable. Clear to disable.
Left Channel Mono/Stereo Mixer Left Mixed input enable
Set to enable. Clear to disable.
Reset Value = 00001001b
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4341H–MP3–10/07
Table 15-21. DAC Mixer Control Register - DAC_CSFC (09h)
7
6
5
4
3
2
1
0
-
-
-
OVRSEL
-
-
-
-
Bit
Bit Mnemonic
Description
7:5
-
Not used
4
OVRSEL
Number
Master clock selector
Clear for 256 x Fs.
Set for 384 x Fs.
3:0
-
Not Used
Reset Value = 00000000b
Table 15-22. Dac Miscellaneous Register - DAC_ MISC (0Ah)
7
6
5
4
3
2
1
0
-
-
DINTSEL1
DINTSEL0
DITHEN
DEEMPEN
NBITS1
NBITS0
Bit
Number
Bit Mnemonic
Description
7
-
Not used
6
-
Not used
5:4
DINTSEL1:0
I2S data format selector
3
DITHEN
Dither enable (Clear this bit to disable, set to enable)
2
DEEMPEN
De-emphasis enable (clear this bit to disable, set to enable)
1:0
NBITS 1:0
Data interface word length
Reset Value = 00000010b
96
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 15-23. DAC Precharge Control Register - DAC_ PRECH (0Ch)
7
6
5
4
3
2
1
PRCHARGE
PRCHARGE PRCHARGE PRCHARGE
PRCHARGE PRCHARGE
PRCHARGE
PADRV
LNOL
LNIL
LNIL
AUXIN
LNOR
Bit
Bit
Number
Mnemonic
7
PRCHARGEPADR
V
6
PRCHARGEAUXIN
5
PRCHARGELNOR
4
PRCHARGELNOL
3
PRCHARGELNIR
2
PRCHARGELNIL
1
PRCHARGE
0
ONMSTR
0
ONMSTR
Description
Differential mono PA driver pre-charge.
Set to charge.
Differential mono auxiliary input pre-charge.
Set to charge.
Right channel line out pre-charge.
Set to charge.
Left channel line out pre-charge.
Set to charge.
Right channel line in pre-charge.
Set to charge.
Left channel line in pre-charge
Set to charge.
Master pre-charge
Set to charge.
Master power on control
Clear to power down. Set to to power up.
Reset Value = 00000000b
Table 15-24. DAC Auxilary input gain Register - DAC_ AUXG (0Dh)l
7
6
5
4
3
2
1
0
-
-
-
AUXG4
AUXG3
AUXG2
AUXG1
AUXG0
Bit
Number
Bit Mnemonic
Description
7:5
-
Not used
4:0
AUXG 4:0
Differential mono auxiliary input analog gain selector
Reset Value = 0000101b
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4341H–MP3–10/07
Table 15-25. DAC Reset Register - DAC_ RST (10h)
7
6
5
4
3
2
1
0
-
-
-
-
-
RESMASK
RESFILZ
RSTZ
Bit
Number
Description
Bit Mnemonic
7:3
-
2
RESMASK
1
RESFILZ
0
RSTZ
Not Used.
Active high reset mask of the audio codec
Active low reset of the audio codec filter
Active low reset of the audio codec
Reset Value = 00000000b
Note:
15.2
Refer to Audio DAC Startup sequence.
Power Amplifier
High quality mono output is provided. The DAC output is connected through a buffer stage to the
input of the Audio Power Amplifier, using two coupling capacitors The mono buffer stage also
includes a mixer of the LINEL and LINER inputs as well as a differential monaural auxiliary input
(line level) which can be, for example, the output of a voice CODEC output driver in mobile
phones.
In the full power mode, the Power Amplifier is capable of driving an 8Ω Loudspeaker at maximum power of 440mW, making it suitable as a handsfree speaker driver in Wireless Handset
Application.
The Low Power Mode is designed to be switched from the handsfree mode to the normal earphone/speaker mode of a telephone handset.
The audio power amplifier is not internally protected against short-circuit. The user should avoid
any short-circuit on the load.
15.2.1
PA Features
•
•
•
•
0.44W on 8Ω Load
Low Power Mode for Earphone
Programmable Gain (-22 to +20 dB)
Fully Differential Structure, Input and Output
Table 15-26. PA Gain
98
APAGAIN 3:0
Gain (db)
0000
-22
0001
20
0010
17
0011
14
0100
11
0101
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AT8xC51SND2C/MP3B
0110
5
0111
2
1000
-1
1001
-4
1010
-7
1011
-10
1100
-13
1101
-16
1110
-19
1111
-22
Table 15-27. PA Operating Mode
APAON
APAPRECH
Operating Mode
0
0
Stand-By
0
1
Input Capacitors Precharge
1
0
Active Mode
1
1
Forbidden State
Table 15-28. PA Low Power Mode
APALP
15.3
Power Mode
0
Low power mode
1
High power mode
Audio Supplies and Start-up
In operating mode AUDVBAT (supply of the audio power amplifier) must be between 3.2V and
5,5V.
AUDVDD, HSVDD and VDD must be inferior or equal to AUDVBAT.
A typical application is AUDVBAT connected to a battery and AUDVDD, HSVDD and VDD supplied by regulators.
AUDVBAT must be present at the same time or before AUDVDD, HSVDD and VDD.
AUDRST must be active low (0) until the voltages are not etablished and reach the proper
values.
To avoid noise issues, it is recommended to use ceramic decoupling capacitors for each supply
closed to the package. The track of the supplies must be optimized to minimize the resistance
especially on AUDVBAT where all the current from the power amplifier comes from.
Note:
Refer to the application diagram.
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15.3.1
Audio DAC Start-up Sequence
In order to minimize any audio output noise during the start-up, the following sequence should
be applied.
15.3.1.1
15.3.1.2
15.3.1.3
15.3.1.4
15.3.2
15.3.2.1
Example of power-on: Path DAC to Headset Output
•
Desassert the Reset: write 07h at address 10h.
•
All precharge and Master on: write FFh at address 0Ch.
•
Line Out On: write 30h at address 00h.
•
Delay 500 ms.
•
Precharge off: write 0Ch at address 01h.
•
Delay 1 ms.
•
Line Out on, DAC On: write 3Ch at address 00h.
Example of power-off: Path DAC to Headset Output
•
DAC off: write 30h at address 00h.
•
Master off: write 00h at address 0Ch.
•
Delay 1 ms.
•
All off: write 00h at address 00h
Example Start I2S
•
Start DCLK.
•
RSTMASK=1.
•
RESFILZ=0 and RSTZ=0.
•
RESFILZ=1 and RSTZ=1.
•
RSTMASK=0.
•
Delay 5 ms.
•
ONDACL=1 and ONDACR=1.
•
Program all DAC settings: audio format, gains...
Example Stop I2S:
•
DAC off: ONDACL=0 and ONDACR=0.
•
Stop I2S and DLCK.
Audio PA Sequence
PA Power-On Sequence
To avoid an audible ‘click’ at start-up, the input capacitors have to be pre-charged before the
Power Amplifier.
15.3.2.2
PA Power-Off Sequence
To avoid an audible ‘click’ at power-off, the gain should be set to the minimum gain (-22dB)
before setting the Power Amplifier.
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15.3.3
Precharge Control
The power up of the circuit can be performed independently for several blocks. The sequence
flow starts by setting to High the block specific fastcharge control bit and subsequently the associated power control bit. Once the power control bit is set to High, the fast charging starts. This
action begins a user controlled fastcharge cycle. When the fastcharge period is over, the user
must reset the associated fastcharge bit and the block is ready for use. If a power control bit is
cleared a new power up sequence is needed.
The several blocks with independent power control are identified in Table 15-29. The table
describes the power on control and fastcharge bits for each block.
Table 15-29. Precharge and Power Control
Note:
Powered up block
Power on control bit
Precharge Control Bit
Vref & Vcm generator
ONMSTR
Left line in amplifier
ONLNIL
PRCHARGELNIL
Right line in amplifier
ONLNIR
PRCHARGELNIR
Left line out amplifier
ONLNOL
PRCHARGELNOL
Right line out amplifier
ONLNOR
PRCHARGELNOR
Left D-to-A converter
ONDACL
Not needed
Right D-to-A converter
ONDACR
Not needed
Auxiliary input amplifier
ONAUXIN
PRCHARGEAUXIN
PA Driver output
ONPADRV
PRCHARGEPADRV
PRCHARGE
(reg 12; bit 1)
Note that all block can be precharged simultaneously.
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15.3.4
Register
Table 15-30. PA Control Register - PA_CTRL (11h)l
7
6
5
4
3
2
1
0
-
APAON
APAPRECH
APALP
APAGAIN3
APAGAIN2
APAGAIN1
APAGAIN0
Bit
Number
Bit Mnemonic
Description
7
-
6
APAON
5
APAPRECH
Audio power amplifier precharge bit
4
APALP
Audio power amplifier low power bit
3:0
APAGAIN3:0
Not used
Audio power amplifier on bit
Audio power amplifier gain
Reset Value = 00000000b
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16. Universal Serial Bus
The AT8xC51SND2C implements a USB device controller supporting full speed data transfer. In
addition to the default control endpoint 0, it provides 2 other endpoints, which can be configured
in control, bulk, interrupt or isochronous modes:
•
Endpoint 0: 32-Byte FIFO, default control endpoint
•
Endpoint 1, 2: 64-Byte Ping-pong FIFO,
This allows the firmware to be developed conforming to most USB device classes, for example:
16.1
•
USB Mass Storage Class Bulk-only Transport, Revision 1.0 - September 31, 1999
•
USB Human Interface Device Class, Version 1.1 - April 7, 1999
•
USB Device Firmware Upgrade Class, Revision 1.0 - May 13, 1999
USB Mass Storage Class Bulk-Only Transport
Within the Bulk-only framework, the Control endpoint is only used to transport class-specific and
standard USB requests for device set-up and configuration. One Bulk-out endpoint is used to
transport commands and data from the host to the device. One Bulk in endpoint is used to transport status and data from the device to the host.
The following AT8xC51SND2C configuration adheres to those requirements:
16.2
•
Endpoint 0: 32 Bytes, Control In-Out
•
Endpoint 1: 64 Bytes, Bulk-in
•
Endpoint 2: 64 Bytes, Bulk-out
USB Device Firmware Upgrade (DFU)
The USB Device Firmware Update (DFU) protocol can be used to upgrade the on-chip Flash
memory of the AT89C51SND2C. This allows installing product enhancements and patches to
devices that are already in the field. 2 different configurations and descriptor sets are used to
support DFU functions. The Run-Time configuration co-exist with the usual functions of the
device, which is USB Mass Storage for AT89C51SND2C. It is used to initiate DFU from the normal operating mode. The DFU configuration is used to perform the firmware update after device
re-configuration and USB reset. It excludes any other function. Only the default control pipe
(endpoint 0) is used to support DFU services in both configurations.
The only possible value for the MaxPacketSize in the DFU configuration is 32 Bytes, which is the
size of the FIFO implemented for endpoint 0.
16.3
Description
The USB device controller provides the hardware that the AT8xC51SND2C needs to interface a
USB link to a data flow stored in a double port memory.
It requires a 48 MHz reference clock provided by the clock controller as detailed in Section "",
page 104. This clock is used to generate a 12 MHz Full Speed bit clock from the received USB
differential data flow and to transmit data according to full speed USB device tolerance. Clock
recovery is done by a Digital Phase Locked Loop (DPLL) block.
The Serial Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuffing, CRC
generation and checking, and the serial-parallel data conversion.
The Universal Function Interface (UFI) controls the interface between the data flow and the Dual
Port RAM, but also the interface with the C51 core itself.
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Figure 16-3 shows how to connect the AT8xC51SND2C to the USB connector. D+ and D- pins
are connected through 2 termination resistors. A pull-up resistor is implemented on D+ to inform
the host of a full speed device connection. Value of these resistors is detailed in the section “DC
Characteristics”.
Figure 16-1. USB Device Controller Block Diagram
USB
CLOCK
D+
D-
48 MHz
12 MHz
DPLL
USB
Buffer
UFI
To/From
C51 Core
SIE
Figure 16-2. USB Connection
VDD
VBUS
To Power
Supply
RFS
D+
RUSB
D-
RUSB
D+
D-
GND
VSS
16.3.1
Clock Controller
The USB controller clock is generated by division of the PLL clock. The division factor is given by
USBCD1:0 bits in USBCLK register (see Table 16-16). Figure 16-3 shows the USB controller
clock generator and its calculation formula. The USB controller clock frequency must always be
48 MHz.
Figure 16-3. USB Clock Generator and Symbol
USBCLK
PLL
CLOCK
USBCD1:0
48 MHz USB Clock
PLLclk
USBclk = -------------------------------USBCD + 1
104
USB
CLOCK
USB Clock Symbol
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AT8xC51SND2C/MP3B
16.3.2
Serial Interface Engine (SIE)
The SIE performs the following functions:
•
NRZI data encoding and decoding.
•
Bit stuffing and unstuffing.
•
CRC generation and checking.
•
ACKs and NACKs automatic generation.
•
TOKEN type identifying.
•
Address checking.
•
Clock recovery (using DPLL).
Figure 16-4. SIE Block Diagram
End of Packet
Detector
SYNC Detector
Start of Packet
Detector
NRZI ‘ NRZ
Bit Unstuffing
Packet Bit Counter
Address Decoder
Serial to Parallel
Converter
D+
DUSB 48 MHz
CLOCK
Clock
Recover
PID Decoder
8
Data Out
SysClk
(12 MHz)
CRC5 & CRC16
Generator/Check
USB Pattern Generator
Parallel to Serial Converter
Bit Stuffing
NRZI Converter
CRC16 Generator
16.3.3
8
Data In
Function Interface Unit (UFI)
The Function Interface Unit provides the interface between the AT8xC51SND2C and the SIE. It
manages transactions at the packet level with minimal intervention from the device firmware,
which reads and writes the endpoint FIFOs.
Figure 16-6 shows typical USB IN and OUT transactions reporting the split in the hardware (UFI)
and software (C51) load.
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Figure 16-5. UFI Block Diagram
12 MHz DPLL
Transfer
Control
FSM
To/From SIE
Endpoint Control
USB side
Asynchronous Information
Endpoint 2
USBCON
USBADDR
USBINT
USBIEN
UEPNUM
UEPCONX
UEPSTAX
UEPRST
UEPINT
UEPIEN
UEPDATX
UBYCTX
UFNUMH
UFNUML
To/From C51 Core
Endpoint Control
C51 side
Endpoint 1
Endpoint 0
Figure 16-6. USB Typical Transaction Load
OUT Transactions:
HOST
OUT
DATA0 (n Bytes)
UFI
C51
OUT
ACK
DATA1
C51 interrupt
OUT
DATA1
NACK
ACK
Endpoint FIFO read (n Bytes)
IN Transactions:
HOST
UFI
C51
106
IN
IN
NACK
Endpoint FIFO Write
IN
DATA1
ACK
DATA1
C51 interrupt
Endpoint FIFO write
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AT8xC51SND2C/MP3B
16.4
16.4.1
Configuration
General Configuration
•
USB controller enable
Before any USB transaction, the 48 MHz required by the USB controller must be correctly
generated (See “Clock Controller” on page 19).
The USB controller should be then enabled by setting the EUSB bit in the USBCON register.
•
Set address
After a Reset or a USB reset, the software has to set the FEN (Function Enable) bit in the
USBADDR register. This action will allow the USB controller to answer to the requests sent
at the address 0.
When a SET_ADDRESS request has been received, the USB controller must only answer
to the address defined by the request. The new address should be stored in the USBADDR
register. The FEN bit and the FADDEN bit in the USBCON register should be set to allow
the USB controller to answer only to requests sent at the new address.
•
Set configuration
The CONFG bit in the USBCON register should be set after a SET_CONFIGURATION
request with a non-zero value. Otherwise, this bit should be cleared.
16.4.2
Endpoint Configuration
•
Selection of an Endpoint
The endpoint register access is performed using the UEPNUM register. The registers
–
UEPSTAX
–
UEPCONX
–
UEPDATX
–
UBYCTX
Theses registers correspond to the endpoint whose number is stored in the UEPNUM register. To select an Endpoint, the firmware has to write the endpoint number in the UEPNUM
register.
Figure 16-7. Endpoint Selection
Endpoint 0
UEPSTA0
UEPCON0
UEPDAT0
SFR Registers
0
UBYCT0
1
X
UEPSTAX
UEPCONX
UEPDATX
UBYCTX
Endpoint 2
UEPSTA2
UEPCON2
UEPDAT2
2
UBYCT2
UEPNUM
•
Endpoint enable
Before using an endpoint, this must be enabled by setting the EPEN bit in the UEPCONX
register.
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An endpoint which is not enabled won’t answer to any USB request. The Default Control
Endpoint (Endpoint 0) should always be enabled in order to answer to USB standard
requests.
•
Endpoint type configuration
All Standard Endpoints can be configured in Control, Bulk, Interrupt or Isochronous mode.
The Ping-pong Endpoints can be configured in Bulk, Interrupt or Isochronous mode. The
configuration of an endpoint is performed by setting the field EPTYPE with the following
values:
–
Control:
EPTYPE = 00b
–
Isochronous: EPTYPE = 01b
–
Bulk:
EPTYPE = 10b
–
Interrupt:
EPTYPE = 11b
The Endpoint 0 is the Default Control Endpoint and should always be configured in Control
type.
•
Endpoint direction configuration
For Bulk, Interrupt and Isochronous endpoints, the direction is defined with the EPDIR bit of
the UEPCONX register with the following values:
–
IN:
EPDIR = 1b
–
OUT:
EPDIR = 0b
For Control endpoints, the EPDIR bit has no effect.
•
Summary of Endpoint Configuration:
Do not forget to select the correct endpoint number in the UEPNUM register before accessing endpoint specific registers.
Table 16-1.
Summary of Endpoint Configuration
Endpoint Configuration
EPEN
EPDIR
EPTYPE
UEPCONX
Disabled
0b
Xb
XXb
0XXX XXXb
Control
1b
Xb
00b
80h
Bulk-in
1b
1b
10b
86h
Bulk-out
1b
0b
10b
82h
Interrupt-In
1b
1b
11b
87h
Interrupt-Out
1b
0b
11b
83h
Isochronous-In
1b
1b
01b
85h
Isochronous-Out
1b
0b
01b
81h
•
Endpoint FIFO reset
Before using an endpoint, its FIFO should be reset. This action resets the FIFO pointer to its
original value, resets the Byte counter of the endpoint (UBYCTX register), and resets the
data toggle bit (DTGL bit in UEPCONX).
The reset of an endpoint FIFO is performed by setting to 1 and resetting to 0 the corresponding bit in the UEPRST register.
For example, in order to reset the Endpoint number 2 FIFO, write 0000 0100b then 0000
0000b in the UEPRST register.
Note that the endpoint reset doesn’t reset the bank number for ping-pong endpoints.
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16.5
16.5.1
Read/Write Data FIFO
Read Data FIFO
The read access for each OUT endpoint is performed using the UEPDATX register.
After a new valid packet has been received on an Endpoint, the data are stored into the FIFO
and the Byte counter of the endpoint is updated (UBYCTX registers). The firmware has to store
the endpoint Byte counter before any access to the endpoint FIFO. The Byte counter is not
updated when reading the FIFO.
To read data from an endpoint, select the correct endpoint number in UEPNUM and read the
UEPDATX register. This action automatically decreases the corresponding address vector, and
the next data is then available in the UEPDATX register.
16.5.2
Write Data FIFO
The write access for each IN endpoint is performed using the UEPDATX register.
To write a Byte into an IN endpoint FIFO, select the correct endpoint number in UEPNUM and
write into the UEPDATX register. The corresponding address vector is automatically increased,
and another write can be carried out.
Warning 1: The Byte counter is not updated.
Warning 2: Do not write more Bytes than supported by the corresponding endpoint.
16.5.3
FIFO Mapping
Figure 16-8. Endpoint FIFO Configuration
Endpoint 0
UEPSTA0
UEPCON0
UEPDAT0
SFR Registers
0
UBYCT0
1
X
UEPSTAX
UEPCONX
UEPDATX
UBYCTX
Endpoint 2
UEPSTA2
UEPCON2
UEPDAT2
2
UBYCT2
UEPNUM
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16.6
Bulk/Interrupt Transactions
Bulk and Interrupt transactions are managed in the same way.
16.6.1
Bulk/Interrupt OUT Transactions in Standard Mode
Figure 16-9. Bulk/Interrupt OUT transactions in Standard Mode
HOST
OUT
UFI
C51
DATA0 (n Bytes)
ACK
RXOUTB0
Endpoint FIFO Read Byte 1
OUT
DATA1
Endpoint FIFO Read Byte 2
NAK
OUT
Endpoint FIFO Read Byte n
DATA1
Clear RXOUTB0
NAK
OUT
DATA1
ACK
RXOUTB0
Endpoint FIFO Read Byte 1
An endpoint should be first enabled and configured before being able to receive Bulk or Interrupt
packets.
When a valid OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the corresponding
endpoint, store the number of data Bytes by reading the UBYCTX register. If the received packet
is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be
read.
When all the endpoint FIFO Bytes have been read, the firmware should clear the RXOUTB0 bit
to allow the USB controller to accept the next OUT packet on this endpoint. Until the RXOUTB0
bit has been cleared by the firmware, the USB controller will answer a NAK handshake for each
OUT requests.
If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won’t be
stored, but the USB controller will consider that the packet is valid if the CRC is correct and the
endpoint Byte counter contains the number of Bytes sent by the Host.
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16.6.2
Bulk/Interrupt OUT Transactions in Ping-pong Mode
Figure 16-10. Bulk/Interrupt OUT Transactions in Ping-pong Mode
HOST
OUT
C51
UFI
DATA0 (n Bytes)
ACK
RXOUTB0
Endpoint FIFO bank 0 - Read Byte 1
OUT
Endpoint FIFO bank 0 - Read Byte 2
DATA1 (m Bytes)
ACK
Endpoint FIFO bank 0 - Read Byte n
Clear RXOUTB0
OUT
RXOUTB1
DATA0 (p Bytes)
Endpoint FIFO bank 1 - Read Byte 1
ACK
Endpoint FIFO bank 1 - Read Byte 2
Endpoint FIFO bank 1 - Read Byte m
Clear RXOUTB1
RXOUTB0
Endpoint FIFO bank 0 - Read Byte 1
Endpoint FIFO bank 0 - Read Byte 2
Endpoint FIFO bank 0 - Read Byte p
Clear RXOUTB0
An endpoint should be first enabled and configured before being able to receive Bulk or Interrupt
packets.
When a valid OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the
USB controller. This triggers an interrupt if enabled. The firmware has to select the corresponding endpoint, store the number of data Bytes by reading the UBYCTX register. If the received
packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has
to be read.
When all the endpoint FIFO Bytes have been read, the firmware should clear the RXOUB0 bit to
allow the USB controller to accept the next OUT packet on the endpoint bank 0. This action
switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has been cleared by the firmware,
the USB controller will answer a NAK handshake for each OUT requests on the bank 0 endpoint
FIFO.
When a new valid OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by
the USB controller. This triggers an interrupt if enabled. The firmware empties the bank 1 endpoint FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been cleared by the
firmware, the USB controller will answer a NAK handshake for each OUT requests on the bank 1
endpoint FIFO.
The RXOUTB0 and RXOUTB1 bits are, alternatively, set by the USB controller at each new valid
packet receipt.
The firmware has to clear one of these 2 bits after having read all the data FIFO to allow a new
valid packet to be stored in the corresponding bank.
A NAK handshake is sent by the USB controller only if the banks 0 and 1 has not been released
by the firmware.
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4341H–MP3–10/07
If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won’t be
stored, but the USB controller will consider that the packet is valid if the CRC is correct.
16.6.3
Bulk/Interrupt IN Transactions in Standard Mode
Figure 16-11. Bulk/Interrupt IN Transactions in Standard Mode
HOST
C51
UFI
Endpoint FIFO Write Byte 1
IN
Endpoint FIFO Write Byte 2
NAK
Endpoint FIFO Write Byte n
Set TXRDY
IN
DATA0 (n Bytes)
ACK
TXCMPL
Clear TXCMPL
Endpoint FIFO Write Byte 1
An endpoint should be first enabled and configured before being able to send Bulk or Interrupt
packets.
The firmware should fill the FIFO with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request
concerning this endpoint. To send a Zero Length Packet, the firmware should set the TXRDY bit
without writing any data into the endpoint FIFO.
Until the TXRDY bit has been set by the firmware, the USB controller will answer a NAK handshake for each IN requests.
To cancel the sending of this packet, the firmware has to reset the TXRDY bit. The packet stored
in the endpoint FIFO is then cleared and a new packet can be written and sent.
When the IN packet has been sent and acknowledged by the Host, the TXCMPL bit in the UEPSTAX register is set by the USB controller. This triggers a USB interrupt if enabled. The firmware
should clear the TXCMPL bit before filling the endpoint FIFO with new data.
The firmware should never write more Bytes than supported by the endpoint FIFO.
All USB retry mechanisms are automatically managed by the USB controller.
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16.6.4
Bulk/Interrupt IN Transactions in Ping-pong Mode
Figure 16-12. Bulk/Interrupt IN transactions in Ping-pong mode
HOST
C51
UFI
Endpoint FIFO bank 0 - Write Byte 1
IN
Endpoint FIFO bank 0 - Write Byte 2
NACK
Endpoint FIFO bank 0 - Write Byte n
Set TXRDY
IN
Endpoint FIFO bank 1 - Write Byte 1
DATA0 (n Bytes)
Endpoint FIFO bank 1 - Write Byte 2
ACK
Endpoint FIFO bank 1 - Write Byte m
TXCMPL
Clear TXCMPL
Set TXRDY
IN
DATA1 (m Bytes)
Endpoint FIFO bank 0 - Write Byte 1
Endpoint FIFO bank 0 - Write Byte 2
ACK
Endpoint FIFO bank 0 - Write Byte p
TXCMPL
Clear TXCMPL
Set TXRDY
IN
DATA0 (p Bytes)
Endpoint FIFO bank 1 - Write Byte 1
ACK
An endpoint should be first enabled and configured before being able to send Bulk or Interrupt
packets.
The firmware should fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the
UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN
request concerning the endpoint. The FIFO banks are automatically switched, and the firmware
can immediately write into the endpoint FIFO bank 1.
When the IN packet concerning the bank 0 has been sent and acknowledged by the Host, the
TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware
should clear the TXCMPL bit before filling the endpoint FIFO bank 0 with new data. The FIFO
banks are then automatically switched.
When the IN packet concerning the bank 1 has been sent and acknowledged by the Host, the
TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware
should clear the TXCMPL bit before filling the endpoint FIFO bank 1 with new data.
The bank switch is performed by the USB controller each time the TXRDY bit is set by the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller
will answer a NAK handshake for each IN requests concerning this bank.
Note that in the example above, the firmware clears the Transmit Complete bit (TXCBulk-outMPL) before setting the Transmit Ready bit (TXRDY). This is done in order to avoid the firmware
to clear at the same time the TXCMPL bit for for bank 0 and the bank 1.
The firmware should never write more Bytes than supported by the endpoint FIFO.
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16.7
16.7.1
Control Transactions
Setup Stage
The DIR bit in the UEPSTAX register should be at 0.
Receiving Setup packets is the same as receiving Bulk Out packets, except that the RXSETUP
bit in the UEPSTAX register is set by the USB controller instead of the RXOUTB0 bit to indicate
that an Out packet with a Setup PID has been received on the Control endpoint. When the
RXSETUP bit has been set, all the other bits of the UEPSTAX register are cleared and an interrupt is triggered if enabled.
The firmware has to read the Setup request stored in the Control endpoint FIFO before clearing
the RXSETUP bit to free the endpoint FIFO for the next transaction.
16.7.2
Data Stage: Control Endpoint Direction
The data stage management is similar to Bulk management.
A Control endpoint is managed by the USB controller as a full-duplex endpoint: IN and OUT. All
other endpoint types are managed as half-duplex endpoint: IN or OUT. The firmware has to
specify the control endpoint direction for the data stage using the DIR bit in the UEPSTAX
register.
•
If the data stage consists of INs, the firmware has to set the DIR bit in the UEPSTAX register
before writing into the FIFO and sending the data by setting to 1 the TXRDY bit in the
UEPSTAX register. The IN transaction is complete when the TXCMPL has been set by the
hardware. The firmware should clear the TXCMPL bit before any other transaction.
•
If the data stage consists of OUTs, the firmware has to leave the DIR bit at 0. The RXOUTB0
bit is set by hardware when a new valid packet has been received on the endpoint. The
firmware must read the data stored into the FIFO and then clear the RXOUTB0 bit to reset
the FIFO and to allow the next transaction.
To send a STALL handshake, see “STALL Handshake” on page 116.
16.7.3
Status Stage
The DIR bit in the UEPSTAX register should be reset at 0 for IN and OUT status stage.
The status stage management is similar to Bulk management.
16.8
16.8.1
•
For a Control Write transaction or a No-Data Control transaction, the status stage consists of
a IN Zero Length Packet (see “Bulk/Interrupt IN Transactions in Standard Mode” on page
112). To send a STALL handshake, see “STALL Handshake” on page 116.
•
For a Control Read transaction, the status stage consists of a OUT Zero Length Packet (see
“Bulk/Interrupt OUT Transactions in Standard Mode” on page 110).
Isochronous Transactions
Isochronous OUT Transactions in Standard Mode
An endpoint should be first enabled and configured before being able to receive Isochronous
packets.
When an OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB controller.
This triggers an interrupt if enabled. The firmware has to select the corre Bulk-outsponding endpoint, store the number of data Bytes by reading the UBYCTX register. If the received packet is
a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be
read.
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The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in
FIFO has a corrupted CRC. This bit is updated after each new packet receipt.
When all the endpoint FIFO Bytes have been read, the firmware should clear the RXOUTB0 bit
to allow the USB controller to store the next OUT packet data into the endpoint FIFO. Until the
RXOUTB0 bit has been cleared by the firmware, the data sent by the Host at each OUT transaction will be lost.
If the RXOUTB0 bit is cleared while the Host is sending data, the USB controller will store only
the remaining Bytes into the FIFO.
If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won’t be
stored, but the USB controller will consider that the packet is valid if the CRC is correct.
16.8.2
Isochronous OUT Transactions in Ping-pong Mode
An endpoint should be first enabled and configured before being able to receive Isochronous
packets.
When a OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the USB
controller. This triggers an interrupt if enabled. The firmware has to select the corresponding
endpoint, store the number of data Bytes by reading the UBYCTX register. If the received packet
is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be
read.
The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in
FIFO has a corrupted CRC. This bit is updated after each new packet receipt.
When all the endpoint FIFO Bytes have been read, the firmware should clear the RXOUB0 bit to
allow the USB controller to store the next OUT packet data into the endpoint FIFO bank 0. This
action switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has been cleared by the firmware, the data sent by the Host on the bank 0 endpoint FIFO will be lost.
If the RXOUTB0 bit is cleared while the Host is sending data on the endpoint bank 0, the USB
controller will store only the remaining Bytes into the FIFO.
When a new OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by the
USB controller. This triggers an interrupt if enabled. The firmware empties the bank 1 endpoint
FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been cleared by the firmware, the data sent by the Host on the bank 1 endpoint FIFO will be lost.
The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each new
packet receipt.
The firmware has to clear one of these 2 bits after having read all the data FIFO to allow a new
packet to be stored in the corresponding bank.
If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won’t be
stored, but the USB controller will consider that the packet is valid if the CRC is correct.
16.8.3
Isochronous IN Transactions in Standard Mode
An endpoint should be first enabled and configured before being able to send Isochronous
packets.
The firmware should fill the FIFO with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request
concerning this endpoint.
If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB
controller.
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When the IN packet has been sent, the TXCMPL bit in the UEPSTAX register is set by the USB
controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit
before filling the endpoint FIFO with new data.
The firmware should never write more Bytes than supported by the endpoint FIFO
16.8.4
Isochronous IN Transactions in Ping-pong Mode
An endpoint should be first enabled and configured before being able to send Isochronous
packets.
The firmware should fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the
UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN
request concerning the endpoint. The FIFO banks are automatically switched, and the firmware
can immediately write into the endpoint FIFO bank 1.
If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB
controller.
When the IN packet concerning the bank 0 has been sent, the TXCMPL bit is set by the USB
controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit
before filling the endpoint FIFO bank 0 with new data. The FIFO banks are then automatically
switched.
When the IN packet concerning the bank 1 has been sent, the TXCMPL bit is set by the USB
controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit
before filling the endpoint FIFO bank 1 with new data.
The bank switch is performed by the USB controller each time the TXRDY bit is set by the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller
won’t send anything at each IN requests concerning this bank.
The firmware should never write more Bytes than supported by the endpoint FIFO.
16.9
16.9.1
Miscellaneous
USB Reset
The EORINT bit in the USBINT register is set by hardware when a End Of Reset has been
detected on the USB bus. This triggers a USB interrupt if enabled. The USB controller is still
enabled, but all the USB registers are reset by hardware. The firmware should clear the EORINT
bit to allow the next USB reset detection.
16.9.2
STALL Handshake
This function is only available for Control, Bulk, and Interrupt endpoints.
The firmware has to set the STALLRQ bit in the UEPSTAX register to send a STALL handshake
at the next request of the Host on the endpoint selected with the UEPNUM register. The
RXSETUP, TXRDY, TXCMPL, RXOUTB0 and RXOUTB1 bits must be first resseted to 0. The
bit STLCRC is set at 1 by the USB controller when a STALL has been sent. This triggers an
interrupt if enabled.
The firmware should clear the STALLRQ and STLCRC bits after each STALL sent.
The STALLRQ bit is cleared automatically by hardware when a valid SETUP PID is received on
a CONTROL type endpoint.
Important note: when a Clear Halt Feature occurs for an endpoint, the firmware should reset this
endpoint using the UEPRST resgister in order to reset the data toggle management.
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16.9.3
Start of Frame Detection
The SOFINT bit in the USBINT register is set when the USB controller detects a Start Of Frame
PID. This triggers an interrupt if enabled. The firmware should clear the SOFINT bit to allow the
next Start of Frame detection.
16.9.4
Frame Number
When receiving a Start Of Frame, the frame number is automatically stored in the UFNUML and
UFNUMH registers. The CRCOK and CRCERR bits indicate if the CRC of the last Start Of
Frame is valid (CRCOK set at 1) or corrupted (CRCERR set at 1). The UFNUML and UFNUMH
registers are automatically updated when receiving a new Start of Frame.
16.9.5
Data Toggle Bit
The Data Toggle bit is set by hardware when a DATA0 packet is received and accepted by the
USB controller and cleared by hardware when a DATA1 packet is received and accepted by the
USB controller. This bit is reset when the firmware resets the endpoint FIFO using the UEPRST
register.
For Control endpoints, each SETUP transaction starts with a DATA0 and data toggling is then
used as for Bulk endpoints until the end of the Data stage (for a control write transfer). The Status stage completes the data transfer with a DATA1 (for a control read transfer).
For Isochronous endpoints, the device firmware should ignore the data-toggle.
16.10 Suspend/Resume Management
16.10.1
Suspend
The Suspend state can be detected by the USB controller if all the clocks are enabled and if the
USB controller is enabled. The bit SPINT is set by hardware when an idle state is detected for
more than 3 ms. This triggers a USB interrupt if enabled.
In order to reduce current consumption, the firmware can put the USB PAD in idle mode, stop
the clocks and put the C51 in Idle or Power-down mode. The Resume detection is still active.
The USB PAD is put in idle mode when the firmware clear the SPINT bit. In order to avoid a new
suspend detection 3ms later, the firmware has to disable the USB clock input using the SUSPCLK bit in the USBCON Register. The USB PAD automatically exits of idle mode when a wakeup event is detected.
The stop of the 48 MHz clock from the PLL should be done in the following order:
1. Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUSPCLK bit
in the USBCON register.
2. Disable the PLL by clearing the PLLEN bit in the PLLCON register.
16.10.2
Resume
When the USB controller is in Suspend state, the Resume detection is active even if all the
clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit is set by
hardware when a non-idle state occurs on the USB bus. This triggers an interrupt if enabled.
This interrupt wakes up the CPU from its Idle or Power-down state and the interrupt function is
then executed. The firmware will first enable the 48 MHz generation and then reset to 0 the
SUSPCLK bit in the USBCON register if needed.
The firmware has to clear the SPINT bit in the USBINT register before any other USB operation
in order to wake up the USB controller from its Suspend mode.
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The USB controller is then re-activated.
Figure 16-13. Example of a Suspend/Resume Management
USB Controller Init
SPINT
Detection of a SUSPEND State
Clear SPINT
Set SUSPCLK
Disable PLL
microcontroller in Power-down
WUPCPU
Detection of a RESUME State
Enable PLL
Clear SUSPCLK
Clear WUPCPU Bit
16.10.3
Upstream Resume
A USB device can be allowed by the Host to send an upstream resume for Remote Wake-up
purpose.
When the USB controller receives the SET_FEATURE request: DEVICE_REMOTE_WAKEUP,
the firmware should set to 1 the RMWUPE bit in the USBCON register to enable this functionality. RMWUPE value should be 0 in the other cases.
If the device is in SUSPEND mode, the USB controller can send an upstream resume by clearing first the SPINT bit in the USBINT register and by setting then to 1 the SDRMWUP bit in the
USBCON register. The USB controller sets to 1 the UPRSM bit in the USBCON register. All
clocks must be enabled first. The Remote Wake is sent only if the USB bus was in Suspend
state for at least 5ms. When the upstream resume is completed, the UPRSM bit is reset to 0 by
hardware. The firmware should then clear the SDRMWUP bit.
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Figure 16-14. Example of REMOTE WAKEUP Management
USB Controller Init
SET_FEATURE: DEVICE_REMOTE_WAKEUP
Set RMWUPE
SPINT
Detection of a SUSPEND state
Suspend Management
need USB resume
enable clocks
Clear SPINT
UPRSM = 1
Set SDMWUP
UPRSM
upstream RESUME sent
Clear SDRMWUP
16.11 USB Interrupt System
16.11.1
Interrupt System Priorities
Figure 16-15. USB Interrupt Control System
D+
D-
00
01
10
11
USB
Controller
EUSB
EA
IE1.6
IE0.7
Interrupt Enable
IPH/L
Priority Enable
Lowest Priority Interrupts
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Table 16-2.
16.11.2
Priority Levels
IPHUSB
IPLUSB
USB Priority Level
0
0
0..................Lowest
0
1
1
1
0
2
1
1
3..................Highest
USB Interrupt Control System
As shown in Figure 16-16, many events can produce a USB interrupt:
120
•
TXCMPL: Transmitted In Data (Table 1 on page 126). This bit is set by hardware when the
Host accept a In packet.
•
RXOUTB0: Received Out Data Bank 0 (Table 1 on page 126). This bit is set by hardware
when an Out packet is accepted by the endpoint and stored in bank 0.
•
RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints) (Table 1 on page
126). This bit is set by hardware when an Out packet is accepted by the endpoint and stored
in bank 1.
•
RXSETUP: Received Setup (Table 1 on page 126). This bit is set by hardware when an
SETUP packet is accepted by the endpoint.
•
STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (Table 1 on page 126).
This bit is set by hardware when a STALL handshake has been sent as requested by
STALLRQ, and is reset by hardware when a SETUP packet is received.
•
SOFINT: Start of Frame Interrupt (Table 16-5 on page 123). This bit is set by hardware when
a USB start of frame packet has been received.
•
WUPCPU: Wake-Up CPU Interrupt (Table 16-5 on page 123). This bit is set by hardware
when a USB resume is detected on the USB bus, after a SUSPEND state.
•
SPINT: Suspend Interrupt (Table 16-5 on page 123). This bit is set by hardware when a USB
suspend is detected on the USB bus.
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Figure 16-16. USB Interrupt Control Block Diagram
Endpoint X (X = 0..2)
TXCMP
UEPSTAX.0
RXOUTB0
UEPSTAX.1
RXOUTB1
EPXINT
UEPSTAX.6
UEPINT.X
RXSETUP
EPXIE
UEPSTAX.2
UEPIEN.X
STLCRC
UEPSTAX.3
NAKOUT
UEPCONX.5
NAKIN
UEPCONX.4
NAKIEN
UEPCONX.6
WUPCPU
EUSB
USBINT.5
EWUPCPU
IE1.6
USBIEN.5
EORINT
USBINT.4
EEORINT
USBIEN.4
SOFINT
USBINT.3
ESOFINT
USBIEN.3
SPINT
USBINT.0
ESPINT
USBIEN.0
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16.12 Registers
Table 16-3.
USBCON Register
USBCON (S:BCh) – USB Global Control Register
7
6
5
4
3
2
1
0
USBE
SUSPCLK
SDRMWUP
-
UPRSM
RMWUPE
CONFG
FADDEN
Bit Number
Bit
Mnemonic
Description
7
USBE
6
SUSPCLK
5
SDRMWUP
4
-
3
UPRSM
2
RMWUPE
USB Enable Bit
Set this bit to enable the USB controller.
Clear this bit to disable and reset the USB controller, to disable the USB transceiver an
to disable the USB controllor clock inputs.
Suspend USB Clock Bit
Set to disable the 48 MHz clock input (Resume Detection is still active).
Clear to enable the 48 MHz clock input.
Send Remote Wake-Up Bit
Set to force an external interrupt on the USB controller for Remote Wake UP purpose.
An upstream resume is send only if the bit RMWUPE is set, all USB clocks are enabled
AND the USB bus was in SUSPEND state for at least 5 ms. See UPRSM below.
Cleared by software.
Reserved
The value read from this bit is always 0. Do not set this bit.
Upstream Resume Bit (read only)
Set by hardware when SDRMWUP has been set and if RMWUPE is enabled.
Cleared by hardware after the upstream resume has been sent.
Remote Wake-Up Enable Bit
Set to enabled request an upstream resume signaling to the host.
Clear after the upstream resume has been indicated by RSMINPR.
Note: Do not set this bit if the host has not set the DEVICE_REMOTE_WAKEUP feature
for the device.
1
0
CONFG
Configuration Bit
This bit should be set by the device firmware after a SET_CONFIGURATION request
with a non-zero value has been correctly processed.
It should be cleared by the device firmware when a SET_CONFIGURATION request
with a zero value is received. It is cleared by hardware on hardware reset or when an
USB reset is detected on the bus (SE0 state for at least 32 Full Speed bit times: typically
2.7 µs).
FADDEN
Function Address Enable Bit
This bit should be set by the device firmware after a successful status phase of a
SET_ADDRESS transaction.
It should not be cleared afterwards by the device firmware. It is cleared by hardware on
hardware reset or when an USB reset is received (see above). When this bit is cleared,
the default function address is used (0).
Reset Value = 0000 0000b
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Table 16-4.
USBADDR Register
USBADDR (S:C6h) – USB Address Register
7
6
5
4
3
2
1
0
FEN
UADD6
UADD5
UADD4
UADD3
UADD2
UADD1
UADD0
Bit Number
Bit
Mnemonic
Description
7
6-0
FEN
UADD6:0
Function Enable Bit
Set to enable the function. The device firmware should set this bit after it has received a
USB reset and participate in the following configuration process with the default address
(FEN is reset to 0).
Cleared by hardware at power-up, should not be cleared by the device firmware once
set.
USB Address Bits
This field contains the default address (0) after power-up or USB bus reset.
It should be written with the value set by a SET_ADDRESS request received by the
device firmware.
Reset Value = 0000 0000b
Table 16-5.
USBINT Register
USBINT (S:BDh) – USB Global Interrupt Register
7
6
5
4
3
2
1
0
-
-
WUPCPU
EORINT
SOFINT
-
-
SPINT
Bit Number
Bit
Mnemonic
Description
7-6
-
5
WUPCPU
Reserved
The value read from these bits is always 0. Do not set these bits.
Wake Up CPU Interrupt Flag
Set by hardware when the USB controller is in SUSPEND state and is re-activated by a
non-idle signal from USB line (not by an upstream resume). This triggers a USB interrupt
when EWUPCPU is set in the USBIEN.
Cleared by software after re-enabling all USB clocks.
EORINT
End of Reset Interrupt Flag
Set by hardware when a End of Reset has been detected by the USB controller. This
triggers a USB interrupt when EEORINT is set in USBIEN.
Cleared by software.
3
SOFINT
Start of Frame Interrupt Flag
Set by hardware when an USB Start of Frame packet (SOF) has been properly received.
This triggers a USB interrupt when ESOFINT is set in USBIEN.
Cleared by software.
2-1
-
4
0
SPINT
Reserved
The value read from these bits is always 0. Do not set these bits.
Suspend Interrupt Flag
Set by hardware when a USB Suspend (Idle bus for three frame periods: a J state for 3
ms) is detected. This triggers a USB interrupt when ESPINT is set in USBIEN.
Cleared by software.
Reset Value = 0000 0000b
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Table 16-6.
USBIEN Register
USBIEN (S:BEh) – USB Global Interrupt Enable Register
7
6
5
4
3
2
1
0
-
-
EWUPCPU
EEORINT
ESOFINT
-
-
ESPINT
Bit Number
Bit
Mnemonic
Description
7-6
-
5
EWUPCPU
4
EEOFINT
End Of Reset Interrupt Enable Bit
Set to enable the End Of Reset interrupt. This bit is set after reset.
Clear to disable End Of Reset interrupt.
3
ESOFINT
Start Of Frame Interrupt Enable Bit
Set to enable the SOF interrupt.
Clear to disable the SOF interrupt.
2-1
-
0
ESPINT
Reserved
The value read from these bits is always 0. Do not set these bits.
Wake Up CPU Interrupt Enable Bit
Set to enable the Wake Up CPU interrupt.
Clear to disable the Wake Up CPU interrupt.
Reserved
The value read from these bits is always 0. Do not set these bits.
Suspend Interrupt Enable Bit
Set to enable Suspend interrupt.
Clear to disable Suspend interrupt.
Reset Value = 0001 0000b
Table 16-7.
UEPNUM Register
UEPNUM (S:C7h) – USB Endpoint Number
7
6
5
4
3
2
1
0
-
-
-
-
-
-
EPNUM1
EPNUM0
Bit Number
Bit
Mnemonic
Description
7-2
-
1-0
EPNUM1:0
Reserved
The value read from these bits is always 0. Do not set these bits.
Endpoint Number Bits
Set this field with the number of the endpoint which should be accessed when reading or
writing to registers UEPSTAX, UEPDATX, UBYCTX or UEPCONX.
Reset Value = 0000 0000b
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Table 16-8.
UEPCONX Register
UEPCONX (S:D4h) – USB Endpoint X Control Register (X = EPNUM set in UEPNUM)
7
6
5
4
3
2
1
0
EPEN
NAKIEN
NAKOUT
NAKIN
DTGL
EPDIR
EPTYPE1
EPTYPE0
Bit Number
Bit
Mnemonic
Description
Endpoint Enable Bit
Set to enable the endpoint according to the device configuration. Endpoint 0 should
always be enabled after a hardware or USB bus reset and participate in the device
configuration.
Clear to disable the endpoint according to the device configuration.
7
EPEN
6
NAKIEN
NAK Interrupt enable
Set this bit to enable NAK IN or NAK OUT interrupt.
Clear this bit to disable NAK IN or NAK OUT Interrupt.
NAKOUT
NAK OUT received
This bit is set by hardware when an NAK handshake has been sent in response of a
OUT request from the Host. This triggers a USB interrupt when NAKIEN is set.
This bit should be cleared by software.
5
4
NAKIN
NAK IN received
This bit is set by hardware when an NAK handshake has been sent in response of a IN
request from the Host. This triggers a USB interrupt when NAKIEN is set.
This bit should be cleared by software.
3
DTGL
Data Toggle Status Bit (Read-only)
Set by hardware when a DATA1 packet is received.
Cleared by hardware when a DATA0 packet is received.
EPDIR
Endpoint Direction Bit
Set to configure IN direction for Bulk, Interrupt and Isochronous endpoints.
Clear to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.
This bit has no effect for Control endpoints.
2
1-0
EPTYPE1:0
Endpoint Type Bits
Set this field according to the endpoint configuration (Endpoint 0 should always be
configured as Control):
00 Control endpoint
01 Isochronous endpoint
10 Bulk endpoint
11 Interrupt endpoint
Reset Value = 1000 0000b
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Table 1. UEPSTAX Register
UEPSTAX (S:CEh) – USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM)
7
6
5
4
3
2
1
0
DIR
RXOUTB1
STALLRQ
TXRDY
STLCRC
RXSETUP
RXOUTB0
TXCMP
Bit Number
Bit Mnemonic
7
Description
Control Endpoint Direction Bit
This bit is relevant only if the endpoint is configured in Control type.
Set for the data stage. Clear otherwise.
DIR
Note: This bit should be configured on RXSETUP interrupt before any other bit is changed. This also determines
the status phase (IN for a control write and OUT for a control read). This bit should be cleared for status stage of
a Control Out transaction.
6
RXOUTB1
Received OUT Data Bank 1 for Endpoints 1 and 2 (Ping-pong mode)
This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 1 (only in Pingpong mode). Then, the endpoint interrupt is triggered if enabled and all the following OUT packets to the endpoint
bank 1 are rejected (NAK’ed) until this bit has been cleared, excepted for Isochronous Endpoints.
This bit should be cleared by the device firmware after reading the OUT data from the endpoint FIFO.
5
STALLRQ
Stall Handshake Request Bit
Set to send a STALL answer to the host for the next handshake. Clear otherwise.
4
3
2
1
0
TXRDY
TX Packet Ready Control Bit
Set after a packet has been written into the endpoint FIFO for IN data transfers. Data should be written into the
endpoint FIFO only after this bit has been cleared. Set this bit without writing data to the endpoint FIFO to send a
Zero Length Packet, which is generally recommended and may be required to terminate a transfer when the
length of the last data packet is equal to MaxPacketSize (e.g. for control read transfers).
Cleared by hardware, as soon as the packet has been sent for Isochronous endpoints, or after the host has
acknowledged the packet for Control, Bulk and Interrupt endpoints.
STLCRC
Stall Sent Interrupt Flag/CRC Error Interrupt Flag
For Control, Bulk and Interrupt Endpoints:
Set by hardware after a STALL handshake has been sent as requested by STALLRQ. Then, the endpoint interrupt
is triggered if enabled in UEPIEN.
Cleared by hardware when a SETUP packet is received (see RXSETUP).
For Isochronous Endpoints:
Set by hardware if the last data received is corrupted (CRC error on data). Then, the endpoint interrupt is
triggered if enabled in UEPIEN.
Cleared by hardware when a non corrupted data is received.
RXSETUP
Received SETUP Interrupt Flag
Set by hardware when a valid SETUP packet has been received from the host. Then, all the other bits of the
register are cleared by hardware and the endpoint interrupt is triggered if enabled in UEPIEN.
Clear by software after reading the SETUP data from the endpoint FIFO.
RXOUTB0
Received OUT Data Bank 0 (see also RXOUTB1 bit for Ping-pong Endpoints)
This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 0. Then, the
endpoint interrupt is triggered if enabled and all the following OUT packets to the endpoint bank 0 are rejected
(NAK’ed) until this bit has been cleared, excepted for Isochronous Endpoints. However, for control endpoints, an
early SETUP transaction may overwrite the content of the endpoint FIFO, even if its Data packet is received while
this bit is set.
This bit should be cleared by the device firmware after reading the OUT data from the endpoint FIFO.
TXCMP
Transmitted IN Data Complete Interrupt Flag
Set by hardware after an IN packet has been transmitted for Isochronous endpoints and after it has been
accepted (ACK’ed) by the host for Control, Bulk and Interrupt endpoints. Then, the endpoint interrupt is triggered
if enabled in UEPIEN.
Clear by software before setting again TXRDY.
Reset Value = 0000 0000b
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Table 16-9.
UEPRST Register
UEPRST (S:D5h) – USB Endpoint FIFO Reset Register
7
6
5
4
3
2
1
0
-
-
-
-
-
EP2RST
EP1RST
EP0RST
Bit Number
Bit
Mnemonic
Description
7-3
-
2
EP2RST
Endpoint 2 FIFO Reset
Set and clear to reset the endpoint 2 FIFO prior to any other operation, upon hardware
reset or when an USB bus reset has been received.
1
EP1RST
Endpoint 1 FIFO Reset
Set and clear to reset the endpoint 1 FIFO prior to any other operation, upon hardware
reset or when an USB bus reset has been received.
0
EP0RST
Endpoint 0 FIFO Reset
Set and clear to reset the endpoint 0 FIFO prior to any other operation, upon hardware
reset or when an USB bus reset has been received.
Reserved
The value read from these bits is always 0. Do not set these bits.
Reset Value = 0000 0000b
Table 16-10. UEPIEN Register
UEPIEN (S:C2h) – USB Endpoint Interrupt Enable Register
7
6
5
4
3
2
1
0
-
-
-
-
-
EP2INTE
EP1INTE
EP0INTE
Bit Number
Bit
Mnemonic
Description
7-3
-
2
EP2INTE
Endpoint 2 Interrupt Enable Bit
Set to enable the interrupts for endpoint 2.
Clear this bit to disable the interrupts for endpoint 2.
1
EP1INTE
Endpoint 1 Interrupt Enable Bit
Set to enable the interrupts for the endpoint 1.
Clear to disable the interrupts for the endpoint 1.
0
EP0INTE
Endpoint 0 Interrupt Enable Bit
Set to enable the interrupts for the endpoint 0.
Clear to disable the interrupts for the endpoint 0.
Reserved
The value read from these bits is always 0. Do not set these bits.
Reset Value = 0000 0000b
127
4341H–MP3–10/07
Table 16-11. UEPINT Register
UEPINT (S:F8h Read-only) – USB Endpoint Interrupt Register
7
6
5
4
3
2
1
0
-
-
-
-
-
EP2INT
EP1INT
EP0INT
Bit Number
Bit
Mnemonic
Description
7-3
-
2
EP2INT
Reserved
The value read from these bits is always 0. Do not set these bits.
Endpoint 2 Interrupt Flag
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 2. The endpoint interrupt sources are in the UEPSTAX register and can be:
TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP2IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared.
1
EP1INT
Endpoint 1 Interrupt Flag
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 1. The endpoint interrupt sources are in the UEPSTAX register and can be:
TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP1IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared.
0
EP0INT
Endpoint 0 Interrupt Flag
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 0. The endpoint interrupt sources are in the UEPSTAX register and can be:
TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP0IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared.
Reset Value = 0000 0000b
Table 16-12. UEPDATX Register
UEPDATX (S:CFh) – USB Endpoint X FIFO Data Register (X = EPNUM set in UEPNUM)
7
6
5
4
3
2
1
0
FDAT7
FDAT6
FDAT5
FDAT4
FDAT3
FDAT2
FDAT1
FDAT0
Bit Number
Bit
Mnemonic
Description
7-0
FDAT7:0
Endpoint X FIFO Data
Data Byte to be written to FIFO or data Byte to be read from the FIFO, for the Endpoint X
(see EPNUM).
Reset Value = XXh
128
AT8xC51SND2C/MP3B
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AT8xC51SND2C/MP3B
Table 16-13. UBYCTX Register
UBYCTX (S:E2h) – USB Endpoint X Byte Count Register (X = EPNUM set in UEPNUM)
7
6
5
4
3
2
1
0
-
BYCT6
BYCT5
BYCT4
BYCT3
BYCT2
BYCT1
BYCT0
Bit Number
Bit
Mnemonic
Description
7
-
6-0
BYCT7:0
Reserved
The value read from this bits is always 0. Do not set this bit.
Byte Count
Byte count of a received data packet. This Byte count is equal to the number of data
Bytes received after the Data PID.
Reset Value = 0000 0000b
Table 16-14. UFNUML Register
UFNUML (S:BAh, Read-only) – USB Frame Number Low Register
7
6
5
4
3
2
1
0
FNUM7
FNUM6
FNUM5
FNUM4
FNUM3
FNUM2
FNUM1
FNUM0
Bit Number
Bit
Mnemonic
Description
7-0
FNUM7:0
Frame Number
Lower 8 bits of the 11-bit Frame Number.
Reset Value = 00h
129
4341H–MP3–10/07
Table 16-15. UFNUMH Register
UFNUMH (S:BBh, Read-only) – USB Frame Number High Register
7
6
5
4
3
2
1
0
-
-
CRCOK
CRCERR
-
FNUM10
FNUM9
FNUM8
Bit Number
Bit
Mnemonic
Description
7-3
-
5
CRCOK
Reserved
The value read from these bits is always 0. Do not set these bits.
Frame Number CRC OK Bit
Set by hardware after a non corrupted Frame Number in Start of Frame Packet is
received.
Updated after every Start Of Frame packet reception.
Note: The Start Of Frame interrupt is generated just after the PID receipt.
4
CRCERR
Frame Number CRC Error Bit
Set by hardware after a corrupted Frame Number in Start of Frame Packet is received.
Updated after every Start Of Frame packet reception.
Note: The Start Of Frame interrupt is generated just after the PID receipt.
3
-
2-0
FNUM10:8
Reserved
The value read from this bits is always 0. Do not set this bit.
Frame Number
Upper 3 bits of the 11-bit Frame Number. It is provided in the last received SOF packet.
FNUM does not change if a corrupted SOF is received.
Reset Value = 00h
Table 16-16. USBCLK Register
USBCLK (S:EAh) – USB Clock Divider Register
7
6
5
4
3
2
1
0
-
-
-
-
-
-
USBCD1
USBCD0
Bit Number
Bit
Mnemonic
Description
7-2
-
1-0
USBCD1:0
Reserved
The value read from these bits is always 0. Do not set these bits.
USB Controller Clock Divider
2-bit divider for USB controller clock generation.
Reset Value = 0000 0000b
130
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AT8xC51SND2C/MP3B
17. IDE/ATAPI Interface
The AT8xC51SND2C provides an IDE/ATAPI interface allowing connection of devices such as
CD-ROM reader, CompactFlash cards, Hard Disk Drive, etc. It consists of a 16-bit data transfer
(read or write) between the AT8xC51SND2C and the IDE device.
17.1
Description
The IDE interface mode is enabled by setting the EXT16 bit in AUXR (see Figure 7-5, page 29).
As soon as this bit is set, all MOVX instructions read or write are done in a 16-bit mode compare
to the standard 8-bit mode. P0 carries the low order multiplexed address and data bus (A7:0,
D7:0) while P2 carries the high order multiplexed address and data bus (A15:8, D15:8). When
writing data in IDE mode, the ACC contains D7:0 data (as in 8-bit mode) while DAT16H register
(see Table 17-2) contains D15:8 data. When reading data in IDE mode, D7:0 data is returned in
ACC while D15:8 data is returned in DAT16H.
Figure 17-1 shows the IDE read bus cycle while Figure 17-2 shows the IDE write bus cycle. For
simplicity, these figures depict the bus cycle waveforms in idealized form and do not provide precise timing information. For IDE bus cycle timing parameters refer to the Section “AC
Characteristics”.
IDE cycle takes 6 CPU clock periods which is equivalent to 12 oscillator clock periods in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode, refer to
the Section “X2 Feature”, page 14.
Slow IDE devices can be accessed by stretching the read and write cycles. This is done using
the M0 bit in AUXR. Setting this bit changes the width of the RD and WR signals from 3 to 15
CPU clock periods.
Figure 17-1. IDE Read Waveforms
CPU Clock
ALE
RD(1)
P0
P2
Notes:
P2
DPL or Ri
D7:0
DPH or P2(2),(3)
D15:8
P2
1. RD signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 outputs SFR content instead of DPH.
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Figure 17-2. IDE Write Waveforms
CPU Clock
ALE
WR(1)
P0
P2
Notes:
17.1.1
P2
DPL or Ri
D7:0
DPH or P2(2),(3)
D15:8
P2
1. WR signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 outputs SFR content instead of DPH.
IDE Device Connection
Figure 17-3 and Figure 17-4 show 2 examples on how to interface up to 2 IDE devices to the
AT8xC51SND2C. In both examples P0 carries IDE low order data bits D7:0, P2 carries IDE high
order data bits D15:8, while RD and WR signals are respectively connected to the IDE nIOR and
nIOW signals. Other IDE control signals are generated by the external address latch outputs in
the first example while they are generated by some port I/Os in the second one. Using an external latch will achieve higher transfer rate.
Figure 17-3. IDE Device Connection Example 1
AT8xC51SND2C
IDE Device 0
P2
IDE Device 1
D15-8
D15-8
D7:0
D7:0
A2:0
A2:0
ALE
nCS1:0
nCS1:0
Px.y
nRESET
nRESET
RD
WR
nIOR
nIOW
nIOR
nIOW
P0
Latch
Figure 17-4. IDE Device Connection Example 2
AT8xC51SND2C
IDE Device 1
P2/A15:8
D15-8
D15-8
P0/AD7:0
D7:0
D7:0
A2:0
nCS1:0
nRESET
nIOR
nIOW
A2:0
nCS1:0
nRESET
nIOR
nIOW
P4.2:0
P4.4:3
P4.5
RD
WR
132
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AT8xC51SND2C/MP3B
Table 17-1.
17.2
External Data Memory Interface Signals
Signal
Name
Type
Alternate
Function
A15:8
I/O
Address Lines
Upper address lines for the external bus.
Multiplexed higher address and data lines for the IDE interface.
P2.7:0
AD7:0
I/O
Address/Data Lines
Multiplexed lower address and data lines for the IDE interface.
P0.7:0
ALE
O
Address Latch Enable
ALE signals indicates that valid address information is available on lines AD7:0.
RD
O
Read
Read signal output to external data memory.
P3.7
WR
O
Write
Write signal output to external memory.
P3.6
Description
-
Registers
Table 17-2.
DAT16H Register
DAT16H (S:F9h) – Data 16 High Order Byte
7
6
5
4
3
2
1
0
D15
D14
D13
D12
D11
D10
D9
D8
Bit Number
Bit
Mnemonic
Description
7-0
D15:8
Data 16 High Order Byte
When EXT16 bit is set, DAT16H is set by software with the high order data Byte prior any
MOVX write instruction.
When EXT16 bit is set, DAT16H contains the high order data Byte after any MOVX read
instruction.
Reset Value =XXXX XXXXb
133
4341H–MP3–10/07
18. MultiMedia Card Controller
The AT8xC51SND2C implements a MultiMedia Card (MMC) controller. The MMC is used to
store MP3 encoded audio files in removable Flash memory cards that can be easily plugged or
removed from the application.
18.1
Card Concept
The basic MultiMedia Card concept is based on transferring data via a minimum number of
signals.
18.1.1
Card Signals
The communication signals are:
18.1.2
•
CLK: with each cycle of this signal a one bit transfer on the command and data lines is done.
The frequency may vary from zero to the maximum clock frequency.
•
CMD: is a bi-directional command channel used for card initialization and data transfer
commands. The CMD signal has 2 operation modes: open-drain for initialization mode and
push-pull for fast command transfer. Commands are sent from the MultiMedia Card bus
master to the card and responses from the cards to the host.
•
DAT: is a bi-directional data channel. The DAT signal operates in push-pull mode. Only one
card or the host is driving this signal at a time.
Card Registers
Within the card interface five registers are defined: OCR, CID, CSD, RCA and DSR. These can
be accessed only by the corresponding commands.
The 32-bit Operation Conditions Register (OCR) stores the VDD voltage profile of the card. The
register is optional and can be read only.
The 128-bit wide CID register carries the card identification information (Card ID) used during
the card identification procedure.
The 128-bit wide Card-Specific Data register (CSD) provides information on how to access the
card contents. The CSD defines the data format, error correction type, maximum data access
time, data transfer speed, and whether the DSR register can be used.
The 16-bit Relative Card Address register (RCA) carries the card address assigned by the host
during the card identification. This address is used for the addressed host-card communication
after the card identification procedure.
The 16-bit Driver Stage Register (DSR) can be optionally used to improve the bus performance
for extended operating conditions (depending on parameters like bus length, transfer rate or
number of cards).
18.2
Bus Concept
The MultiMedia Card bus is designed to connect either solid-state mass-storage memory or I/Odevices in a card format to multimedia applications. The bus implementation allows the coverage of application fields from low-cost systems to systems with a fast data transfer rate. It is a
single master bus with a variable number of slaves. The MultiMedia Card bus master is the bus
controller and each slave is either a single mass storage card (with possibly different technologies such as ROM, OTP, Flash etc.) or an I/O-card with its own controlling unit (on card) to
perform the data transfer.
The MultiMedia Card bus also includes power connections to supply the cards.
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AT8xC51SND2C/MP3B
The bus communication uses a special protocol (MultiMedia Card bus protocol) which is applicable for all devices. Therefore, the payload data transfer between the host and the cards can be
bi-directional.
18.2.1
Bus Lines
The MultiMedia Card bus architecture requires all cards to be connected to the same set of
lines. No card has an individual connection to the host or other devices, which reduces the connection costs of the MultiMedia Card system.
The bus lines can be divided into three groups:
18.2.2
•
Power supply: VSS1 and VSS2, VDD – used to supply the cards.
•
Data transfer: MCMD, MDAT – used for bi-directional communication.
•
Clock: MCLK – used to synchronize data transfer across the bus.
Bus Protocol
After a power-on reset, the host must initialize the cards by a special message-based MultiMedia Card bus protocol. Each message is represented by one of the following tokens:
•
Command: a command is a token which starts an operation. A command is transferred
serially from the host to the card on the MCMD line.
•
Response: a response is a token which is sent from an addressed card (or all connected
cards) to the host as an answer to a previously received command. It is transferred serially
on the MCMD line.
•
Data: data can be transferred from the card to the host or vice-versa. Data is transferred
serially on the MDAT line.
Card addressing is implemented using a session address assigned during the initialization
phase, by the bus controller to all currently connected cards. Individual cards are identified by
their CID number. This method requires that every card will have an unique CID number. To
ensure uniqueness of CIDs the CID register contains 24 bits (MID and OID fields) which are
defined by the MMCA. Every card manufacturers is required to apply for an unique MID (and
optionally OID) number.
MultiMedia Card bus data transfers are composed of these tokens. One data transfer is a bus
operation. There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token, the others transfer
their information directly within the command or response structure. In this case no data token is
present in an operation. The bits on the MDAT and the MCMD lines are transferred synchronous
to the host clock.
2 types of data transfer commands are defined:
•
Sequential commands: These commands initiate a continuous data stream, they are
terminated only when a stop command follows on the MCMD line. This mode reduces the
command overhead to an absolute minimum.
•
Block-oriented commands: These commands send a data block succeeded by CRC bits.
Both read and write operations allow either single or multiple block transmission. A multiple
block transmission is terminated when a stop command follows on the MCMD line similarly
to the stream read.
Figure 18-1 through Figure 18-5 show the different types of operations, on these figures, grayed
tokens are from host to card(s) while white tokens are from card(s) to host.
135
4341H–MP3–10/07
Figure 18-1. Sequential Read Operation
Stop Command
MCMD
Command
Response
Command
MDAT
Response
Data Stream
Data Transfer Operation
Data Stop Operation
Figure 18-2. (Multiple) Block Read Operation
Stop Command
MCMD
Command
MDAT
Response
Command
Response
Data Block CRC Data Block CRC Data Block CRC
Block Read Operation
Data Stop Operation
Multiple Block Read Operation
As shown in Figure 18-3 and Figure 18-4 the data write operation uses a simple busy signalling
of the write operation duration on the data line (MDAT).
Figure 18-3. Sequential Write Operation
Stop Command
MCMD
Command
Response
Command
MDAT
Data Stream
Data Transfer Operation
Response
Busy
Data Stop Operation
Figure 18-4. Multiple Block Write Operation
Stop Command
MCMD
Command
Response
MDAT
Command
Data Block CRC Status Busy
Response
Data Block CRC Status Busy
Block Write Operation
Data Stop Operation
Multiple Block Write Operation
Figure 18-5. No Response and No Data Operation
MCMD
Command
Command
Response
MDAT
No Response Operation
136
No Data Operation
AT8xC51SND2C/MP3B
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AT8xC51SND2C/MP3B
18.2.3
Command Token Format
As shown in Figure 18-6, commands have a fixed code length of 48 bits. Each command token
is preceded by a Start bit: a low level on MCMD line and succeeded by an End bit: a high level
on MCMD line. The command content is preceded by a Transmission bit: a high level on MCMD
line for a command token (host to card) and succeeded by a 7 - bit CRC so that transmission
errors can be detected and the operation may be repeated.
Command content contains the command index and address information or parameters.
Figure 18-6. Command Token Format
0
1
Content
CRC
1
Total Length = 48 bits
Table 18-1.
Bit Position
47
46
45:40
39:8
7:1
0
Width (Bits)
1
1
6
32
7
1
Value
‘0’
‘1’
-
-
-
‘1’
Start bit
Transmission bit
Command
Index
Argument
CRC7
End bit
Description
18.2.4
Command Token Format
Response Token Format
There are five types of response tokens (R1 to R5). As shown in Figure 18-7, responses have a
code length of 48 bits or 136 bits. A response token is preceded by a Start bit: a low level on
MCMD line and succeeded by an End bit: a high level on MCMD line. The command content is
preceded by a Transmission bit: a low level on MCMD line for a response token (card to host)
and succeeded (R1,R2,R4,R5) or not (R3) by a 7 - bit CRC.
Response content contains mirrored command and status information (R1 response), CID register or CSD register (R2 response), OCR register (R3 response), or RCA register (R4 and R5
response).
Figure 18-7. Response Token Format
R1, R4, R5
0
0
Content
CRC
1
Total Length = 48 bits
R3
0
0
Content
1
Total Length = 48 bits
R2
0
0
Content = CID or CSD
CRC
1
Total Length = 136 bits
137
4341H–MP3–10/07
Table 18-2.
Bit Position
47
46
45:40
39:8
7:1
0
Width (bits)
1
1
6
32
7
1
Value
‘0’
‘0’
-
-
-
‘1’
Start bit
Transmission bit
Command
Index
Card Status
CRC7
End bit
Description
Table 18-3.
R2 Response Format (CID and CSD registers)
Bit Position
135
134
[133:128]
[127:1]
0
Width (bits)
1
1
6
32
1
Value
‘0’
‘0’
‘111111’
-
‘1’
Description
Start bit
Transmission bit
Reserved
Argument
End bit
Table 18-4.
R3 Response Format (OCR Register)
Bit Position
47
46
[45:40]
[39:8]
[7:1]
0
Width (bits)
1
1
6
32
7
1
Value
‘0’
‘0’
‘111111’
-
‘1111111’
‘1’
Description
Start bit
Transmission bit
Reserved
OCR register
Reserved
End bit
Table 18-5.
R4 Response Format (Fast I/O)
Bit Position
47
46
[45:40]
[39:8]
[7:1]
0
Width (bits)
1
1
6
32
7
1
Value
‘0’
‘0’
‘100111’
-
-
‘1’
Start bit
Transmission bit
Command
Index
Argument
CRC7
End bit
Description
Table 18-6.
R5 Response Format
Bit Position
47
46
[45:40]
[39:8]
[7:1]
0
Width (bits)
1
1
6
32
7
1
Value
‘0’
‘0’
‘101000’
-
-
‘1’
Start bit
Transmission bit
Command
Index
Argument
CRC7
End bit
Description
18.2.5
R1 Response Format (Normal Response)
Data Packet Format
There are 2 types of data packets: stream and block. As shown in Figure 18-8, stream data
packets have an indeterminate length while block packets have a fixed length depending on the
block length. Each data packet is preceded by a Start bit: a low level on MCMD line and succeeded by an End bit: a high level on MCMD line. Due to the fact that there is no predefined end
in stream packets, CRC protection is not included in this case. The CRC protection algorithm for
block data is a 16-bit CCITT polynomial.
138
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AT8xC51SND2C/MP3B
Figure 18-8. Data Token Format
Sequential Data
0
Block Data
0
Content
Content
1
CRC
1
Block Length
18.2.6
Clock Control
The MMC bus clock signal can be used by the host to turn the cards into energy saving mode or
to control the data flow (to avoid under-run or over-run conditions) on the bus. The host is
allowed to lower the clock frequency or shut it down.
There are a few restrictions the host must follow:
18.3
•
The bus frequency can be changed at any time (under the restrictions of maximum data
transfer frequency, defined by the cards, and the identification frequency defined by the
specification document).
•
It is an obvious requirement that the clock must be running for the card to output data or
response tokens. After the last MultiMedia Card bus transaction, the host is required, to
provide 8 (eight) clock cycles for the card to complete the operation before shutting down
the clock. Following is a list of the various bus transactions:
•
A command with no response. 8 clocks after the host command End bit.
•
A command with response. 8 clocks after the card command End bit.
•
A read data transaction. 8 clocks after the End bit of the last data block.
•
A write data transaction. 8 clocks after the CRC status token.
•
The host is allowed to shut down the clock of a “busy” card. The card will complete the
programming operation regardless of the host clock. However, the host must provide a clock
edge for the card to turn off its busy signal. Without a clock edge the card (unless previously
disconnected by a deselect command-CMD7) will force the MDAT line down, forever.
Description
The MMC controller interfaces to the C51 core through the following eight special function
registers:
MMCON0, MMCON1, MMCON2, the three MMC control registers (see Table 18-8 to Table 1816); MMSTA, the MMC status register (see Table 18-11); MMINT, the MMC interrupt register
(see Table 18-12); MMMSK, the MMC interrupt mask register (see Table 18-13); MMCMD, the
MMC command register (see Table 18-14); MMDAT, the MMC data register (see Table 18-15);
and MMCLK, the MMC clock register (see Table 18-16).
As shown in Figure 18-9, the MMC controller is divided in four blocks: the clock generator that
handles the MCLK (formally the MMC CLK) output to the card, the command line controller that
handles the MCMD (formally the MMC CMD) line traffic to or from the card, the data line controller that handles the MDAT (formally the MMC DAT) line traffic to or from the card, and the
interrupt controller that handles the MMC controller interrupt sources. These blocks are detailed
in the following sections.
139
4341H–MP3–10/07
Figure 18-9. MMC Controller Block Diagram
MCLK
Clock
Generator
OSC
CLOCK
Command Line
Controller
MCMD
MMC
Interrupt
Request
Interrupt
Controller
Data Line
Controller
Internal
Bus
18.4
MDAT
8
Clock Generator
The MMC clock is generated by division of the oscillator clock (FOSC) issued from the Clock Controller block as detailed in Section "Oscillator", page 13. The division factor is given by MMCD7:0
bits in MMCLK register, a value of 0x00 stops the MMC clock. Figure 18-10 shows the MMC
clock generator and its output clock calculation formula.
Figure 18-10. MMC Clock Generator and Symbol
OSC
CLOCK
Controller Clock
OSCclk
MMCclk = ----------------------------MMCD + 1
MMCLK
MMCEN
MMCON2.7
MMCD7:0
MMC Clock
MMC
CLOCK
MMC Clock Symbol
As soon as MMCEN bit in MMCON2 is set, the MMC controller receives its system clock. The
MMC command and data clock is generated on MCLK output and sent to the command line and
data line controllers. Figure 18-11 shows the MMC controller configuration flow.
As exposed in Section “Clock Control”, page 139, MMCD7:0 bits can be used to dynamically
increase or reduce the MMC clock.
Figure 18-11. Configuration Flow
MMC Controller
Configuration
Configure MMC Clock
MMCLK = XXh
MMCEN = 1
FLOWC = 0
18.5
Command Line Controller
As shown in Figure 18-12, the command line controller is divided in 2 channels: the command
transmitter channel that handles the command transmission to the card through the MCMD line
and the command receiver channel that handles the response reception from the card through
the MCMD line. These channels are detailed in the following sections.
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Figure 18-12. Command Line Controller Block Diagram
TX Pointer
5-Byte FIFO
CTPTR
MMCMD
Write
MMCON0.4
Data Converter
// -> Serial
CRC7
Generator
TX COMMAND Line
Finished State Machine
CFLCK
MMSTA.0
Command Transmitter
RX Pointer
17 - Byte FIFO
EOCI
CMDEN
MCMD
MMCON1.0
Data Converter
Serial -> //
MMSTA.2
MMSTA.1
CRC7S
RESPFS
CRC7 and Format
Checker
MMCMD
Read
CRPTR
MMCON0.5
RX COMMAND Line
Finished State Machine
RESPEN
Command Receiver
18.5.1
MMINT.5
RFMT
MMINT.6
EORI
CRCDIS
MMCON1.1 MMCON0.1 MMCON0.0
Command Transmitter
For sending a command to the card, user must load the command index (1 Byte) and argument
(4 Bytes) in the command transmit FIFO using the MMCMD register. Before starting transmission by setting and clearing the CMDEN bit in MMCON1 register, user must first configure:
•
RESPEN bit in MMCON1 register to indicate whether a response is expected or not.
•
RFMT bit in MMCON0 register to indicate the response size expected.
•
CRCDIS bit in MMCON0 register to indicate whether the CRC7 included in the response will
be computed or not. In order to avoid CRC error, CRCDIS may be set for response that do
not include CRC7.
Figure 18-13 summarizes the command transmission flow.
As soon as command transmission is enabled, the CFLCK flag in MMSTA is set indicating that
write to the FIFO is locked. This mechanism is implemented to avoid command overrun.
The end of the command transmission is signalled to you by the EOCI flag in MMINT register
becoming set. This flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 148. The end of the command transmission also resets the CFLCK flag.
User may abort command loading by setting and clearing the CTPTR bit in MMCON0 register
which resets the write pointer to the transmit FIFO.
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Figure 18-13. Command Transmission Flow
Command
Transmission
Configure Response
RESPEN = X
RFMT = X
CRCDIS = X
Load Command in
Buffer
MMCMD = index
MMCMD = argument
Transmit Command
CMDEN = 1
CMDEN = 0
18.5.2
Command Receiver
The end of the response reception is signalled to you by the EORI flag in MMINT register. This
flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 148. When
this flag is set, 2 other flags in MMSTA register: RESPFS and CRC7S give a status on the
response received. RESPFS indicates if the response format is correct or not: the size is the one
expected (48 bits or 136 bits) and a valid End bit has been received, and CRC7S indicates if the
CRC7 computation is correct or not. These Flags are cleared when a command is sent to the
card and updated when the response has been received.
User may abort response reading by setting and clearing the CRPTR bit in MMCON0 register
which resets the read pointer to the receive FIFO.
According to the MMC specification delay between a command and a response (formally NCR
parameter) can not exceed 64 MMC clock periods. To avoid any locking of the MMC controller
when card does not send its response (e.g. physically removed from the bus), user must launch
a time-out period to exit from such situation. In case of time-out user may reset the command
controller and its internal state machine by setting and clearing the CCR bit in MMCON2
register.
This time-out may be disarmed when receiving the response.
18.6
Data Line Controller
The data line controller is based on a 16-Byte FIFO used both by the data transmitter channel
and by the data receiver channel.
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Figure 18-14. Data Line Controller Block Diagram
MMINT.0
MMINT.2
MMSTA.3
MMSTA.4
F1EI
F1FI
DATFS
CRC16S
CRC16 and Format
Checker
Data Converter
Serial -> //
8-Byte
TX Pointer
FIFO 1
DTPTR
MMCON0.6
RX Pointer
DRPTR
MMCON0.7
18.6.1
MCBI
CBUSY
MMINT.1
MMSTA.5
16-Byte FIFO
MMDAT
MDAT
Data Converter
// -> Serial
CRC16
Generator
8-Byte
MMINT.4
DATA Line
Finished State Machine
FIFO 2
F2EI
F2FI
MMINT.1
MMINT.3
DFMT
MBLOCK
DATEN
MMCON0.2
MMCON0.3
MMCON1.2
DATDIR
EOFI
BLEN3:0
MMCON1.3 MMCON1.7:4
FIFO Implementation
The 16-Byte FIFO is based on a dual 8-Byte FIFOs managed using 2 pointers and four flags
indicating the status full and empty of each FIFO.
Pointers are not accessible to user but can be reset at any time by setting and clearing DRPTR
and DTPTR bits in MMCON0 register. Resetting the pointers is equivalent to abort the writing or
reading of data.
F1EI and F2EI flags in MMINT register signal when set that respectively FIFO1 and FIFO2 are
empty. F1FI and F2FI flags in MMINT register signal when set that respectively FIFO1 and
FIFO2 are full. These flags may generate an MMC interrupt request as detailed in
Section “Interrupt”.
18.6.2
Data Configuration
Before sending or receiving any data, the data line controller must be configured according to
the type of the data transfer considered. This is achieved using the Data Format bit: DFMT in
MMCON0 register. Clearing DFMT bit enables the data stream format while setting DFMT bit
enables the data block format. In data block format, user must also configure the single or multiblock mode by clearing or setting the MBLOCK bit in MMCON0 register and the block length
using BLEN3:0 bits in MMCON1 according to Table 18-7. Figure 18-15 summarizes the data
modes configuration flows.
Table 18-7.
Block Length Programming
BLEN3:0
BLEN = 0000 to 1011
> 1011
Block Length (Byte)
Length = 2BLEN: 1 to 2048
Reserved: do not program BLEN3:0 > 1011
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Figure 18-15. Data Controller Configuration Flows
18.6.3
18.6.3.1
Data Stream
Configuration
Data Single Block
Configuration
Data Multi-Block
Configuration
Configure Format
DFMT = 0
Configure Format
DFMT = 1
MBLOCK = 0
BLEN3:0 = XXXXb
Configure Format
DFMT = 1
MBLOCK = 1
BLEN3:0 = XXXXb
Data Transmitter
Configuration
For transmitting data to the card user must first configure the data controller in transmission
mode by setting the DATDIR bit in MMCON1 register.
Figure 18-16 summarizes the data stream transmission flows in both polling and interrupt modes
while Figure 18-17 summarizes the data block transmission flows in both polling and interrupt
modes, these flows assume that block length is greater than 16 data.
18.6.3.2
Data Loading
Data is loaded in the FIFO by writing to MMDAT register. Number of data loaded may vary from
1 to 16 Bytes. Then if necessary (more than 16 Bytes to send) user must wait that one FIFO
becomes empty (F1EI or F2EI set) before loading 8 new data.
18.6.3.3
Data Transmission
Transmission is enabled by setting and clearing DATEN bit in MMCON1 register.
Data is transmitted immediately if the response has already been received, or is delayed after
the response reception if its status is correct. In both cases transmission is delayed if a card
sends a busy state on the data line until the end of this busy condition.
According to the MMC specification, the data transfer from the host to the card may not start
sooner than 2 MMC clock periods after the card response was received (formally NWR parameter). To address all card types, this delay can be programmed using DATD1:0 bits in MMCON2
register from 3 MMC clock periods when DATD1:0 bits are cleared to 9 MMC clock periods
when DATD1:0 bits are set, by step of 2 MMC clock periods.
18.6.3.4
End of Transmission
The end of a data frame (block or stream) transmission is signalled to you by the EOFI flag in
MMINT register. This flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 148.
In data stream mode, EOFI flag is set, after reception of the End bit. This assumes user has previously sent the STOP command to the card, which is the only way to stop stream transfer.
In data block mode, EOFI flag is set, after reception of the CRC status token (see Figure 18-7).
2 other flags in MMSTA register: DATFS and CRC16S report a status on the frame sent. DATFS
indicates if the CRC status token format is correct or not, and CRC16S indicates if the card has
found the CRC16 of the block correct or not.
18.6.3.5
Busy Status
As shown in Figure 18-7 the card uses a busy token during a block write operation. This busy
status is reported to you by the CBUSY flag in MMSTA register and by the MCBI flag in MMINT
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which is set every time CBUSY toggles, i.e. when the card enters and exits its busy state. This
flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 148.
Figure 18-16. Data Stream Transmission Flows
Data Stream
Transmission
Data Stream
Initialization
Data Stream
Transmission ISR
FIFOs Filling
write 16 data to MMDAT
FIFOs Filling
write 16 data to MMDAT
Start Transmission
DATEN = 1
DATEN = 0
Unmask FIFOs Empty
F1EM = 0
F2EM = 0
FIFO Empty?
F1EI or F2EI = 1?
Start Transmission
DATEN = 1
DATEN = 0
FIFO Empty?
F1EI or F2EI = 1?
FIFO Filling
write 8 data to MMDAT
FIFO Filling
write 8 data to MMDAT
Mask FIFOs Empty
F1EM = 1
F2EM = 1
No More Data
To Send?
Send
STOP Command
No More Data
To Send?
Send
STOP Command
b. Interrupt mode
a. Polling mode
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Figure 18-17. Data Block Transmission Flows
Data Block
Transmission
Data Block
Initialization
FIFOs Filling
write 16 data to MMDAT
FIFOs Filling
write 16 data to MMDAT
Start Transmission
DATEN = 1
DATEN = 0
Unmask FIFOs Empty
F1EM = 0
F2EM = 0
FIFO Empty?
F1EI or F2EI = 1?
Start Transmission
DATEN = 1
DATEN = 0
FIFO Filling
write 8 data to MMDAT
No More Data
To Send?
Data Block
Transmission ISR
FIFO Empty?
F1EI or F2EI = 1?
FIFO Filling
write 8 data to MMDAT
No More Data
To Send?
Mask FIFOs Empty
F1EM = 1
F2EM = 1
b. Interrupt mode
a. Polling mode
18.6.4
18.6.4.1
Data Receiver
Configuration
To receive data from the card you must first configure the data controller in reception mode by
clearing the DATDIR bit in MMCON1 register.
Figure 18-18 summarizes the data stream reception flows in both polling and interrupt modes
while Figure 18-19 summarizes the data block reception flows in both polling and interrupt
modes, these flows assume that block length is greater than 16 Bytes.
18.6.4.2
Data Reception
The end of a data frame (block or stream) reception is signalled to you by the EOFI flag in
MMINT register. This flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 148. When this flag is set, 2 other flags in MMSTA register: DATFS and CRC16S
give a status on the frame received. DATFS indicates if the frame format is correct or not: a valid
End bit has been received, and CRC16S indicates if the CRC16 computation is correct or not. In
case of data stream CRC16S has no meaning and stays cleared.
According to the MMC specification data transmission from the card starts after the access time
delay (formally NAC parameter) beginning from the End bit of the read command. To avoid any
locking of the MMC controller when card does not send its data (e.g. physically removed from
the bus), you must launch a time-out period to exit from such situation. In case of time-out you
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may reset the data controller and its internal state machine by setting and clearing the DCR bit in
MMCON2 register.
This time-out may be disarmed after receiving 8 data (F1FI flag set) or after receiving end of
frame (EOFI flag set) in case of block length less than 8 data (1, 2 or 4).
18.6.4.3
Data Reading
Data is read from the FIFO by reading to MMDAT register. Each time one FIFO becomes full
(F1FI or F2FI set), user is requested to flush this FIFO by reading 8 data.
Figure 18-18. Data Stream Reception Flows
Data Stream
Reception
Data Stream
Initialization
Data Stream
Reception ISR
FIFO Full?
F1FI or F2FI = 1?
Unmask FIFOs Full
F1FM = 0
F2FM = 0
FIFO Full?
F1FI or F2FI = 1?
FIFO Reading
read 8 data from MMDAT
FIFO Reading
read 8 data from MMDAT
No More Data
To Receive?
No More Data
To Receive?
Send
STOP Command
Mask FIFOs Full
F1FM = 1
F2FM = 1
a. Polling mode
Send
STOP Command
b. Interrupt mode
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Figure 18-19. Data Block Reception Flows
Data Block
Reception
Data Block
Initialization
Data Block
Reception ISR
Start Transmission
DATEN = 1
DATEN = 0
Unmask FIFOs Full
F1FM = 0
F2FM = 0
FIFO Full?
F1EI or F2EI = 1?
FIFO Full?
F1EI or F2EI = 1?
Start Transmission
DATEN = 1
DATEN = 0
FIFO Reading
read 8 data from MMDAT
No More Data
To Receive?
FIFO Reading
read 8 data from MMDAT
No More Data
To Receive?
a. Polling mode
18.6.5
Mask FIFOs Full
F1FM = 1
F2FM = 1
b. Interrupt mode
Flow Control
To allow transfer at high speed without taking care of CPU oscillator frequency, the FLOWC bit
in MMCON2 allows control of the data flow in both transmission and reception.
During transmission, setting the FLOWC bit has the following effects:
•
MMCLK is stopped when both FIFOs become empty: F1EI and F2EI set.
•
MMCLK is restarted when one of the FIFOs becomes full: F1EI or F2EI cleared.
During reception, setting the FLOWC bit has the following effects:
•
MMCLK is stopped when both FIFOs become full: F1FI and F2FI set.
•
MMCLK is restarted when one of the FIFOs becomes empty: F1FI or F2FI cleared.
As soon as the clock is stopped, the MMC bus is frozen and remains in its state until the clock is
restored by writing or reading data in MMDAT.
18.7
18.7.1
Interrupt
Description
As shown in Figure 18-20, the MMC controller implements eight interrupt sources reported in
MCBI, EORI, EOCI, EOFI, F2FI, F1FI, and F2EI flags in MMCINT register. These flags are
detailed in the previous sections.
All these sources are maskable separately using MCBM, EORM, EOCM, EOFM, F2FM, F1FM,
and F2EM mask bits respectively in MMMSK register.
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The interrupt request is generated each time an unmasked flag is set, and the global MMC controller interrupt enable bit is set (EMMC in IEN1 register).
Reading the MMINT register automatically clears the interrupt flags (acknowledgment). This
implies that register content must be saved and tested interrupt flag by interrupt flag to be sure
not to forget any interrupts.
Figure 18-20. MMC Controller Interrupt System
MCBI
MMINT.7
MCBM
MMMSK.7
EORI
MMINT.6
EORM
EOCI
MMMSK.6
MMINT.5
EOCM
MMMSK.5
EOFI
MMINT.4
MMC Interface
Interrupt Request
EOFM
F2FI
MMMSK.4
EMMC
MMINT.3
F2FM
IEN1.0
MMMSK.3
F1FI
MMINT.2
F1FM
F2EI
MMMSK.2
MMINT.1
F2EM
MMMSK.1
F1EI
MMINT.0
F1EM
MMMSK.0
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18.8
Registers
Table 18-8.
MMCON0 Register
MMCON0 (S:E4h) – MMC Control Register 0
7
6
5
4
3
2
1
0
DRPTR
DTPTR
CRPTR
CTPTR
MBLOCK
DFMT
RFMT
CRCDIS
Bit Number
Bit
Mnemonic
Description
7
DRPTR
Data Receive Pointer Reset Bit
Set to reset the read pointer of the data FIFO.
Clear to release the read pointer of the data FIFO.
6
DTPTR
Data Transmit Pointer Reset Bit
Set to reset the write pointer of the data FIFO.
Clear to release the write pointer of the data FIFO.
5
CRPTR
Command Receive Pointer Reset Bit
Set to reset the read pointer of the receive command FIFO.
Clear to release the read pointer of the receive command FIFO.
4
CTPTR
Command Transmit Pointer Reset Bit
Set to reset the write pointer of the transmit command FIFO.
Clear to release the read pointer of the transmit command FIFO.
3
MBLOCK
2
DFMT
Data Format Bit
Set to select the block-oriented data format.
Clear to select the stream data format.
1
RFMT
Response Format Bit
Set to select the 48-bit response format.
Clear to select the 136-bit response format.
0
CRCDIS
Multi-block Enable Bit
Set to select multi-block data format.
Clear to select single block data format.
CRC7 Disable Bit
Set to disable the CRC7 computation when receiving a response.
Clear to enable the CRC7 computation when receiving a response.
Reset Value = 0000 0000b
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Table 18-9.
MMCON1 Register
MMCON1 (S:E5h) – MMC Control Register 1
7
6
5
4
3
2
1
0
BLEN3
BLEN2
BLEN1
BLEN0
DATDIR
DATEN
RESPEN
CMDEN
Bit Number
Bit
Mnemonic
Description
7-4
BLEN3:0
Block Length Bits
Refer to Table 18-7 for bits description. Do not program value > 1011b
3
DATDIR
Data Direction Bit
Set to select data transfer from host to card (write mode).
Clear to select data transfer from card to host (read mode).
2
DATEN
Data Transmission Enable Bit
Set and clear to enable data transmission immediately or after response has been
received.
1
RESPEN
Response Enable Bit
Set and clear to enable the reception of a response following a command transmission.
0
CMDEN
Command Transmission Enable Bit
Set and clear to enable transmission of the command FIFO to the card.
Reset Value = 0000 0000b
Table 18-10. MMCON2 Register
MMCON2 (S:E6h) – MMC Control Register 2
7
6
5
4
3
2
1
0
MMCEN
DCR
CCR
-
-
DATD1
DATD0
FLOWC
Bit Number
Bit
Mnemonic
Description
7
MMCEN
6
DCR
Data Controller Reset Bit
Set and clear to reset the data line controller in case of transfer abort.
5
CCR
Command Controller Reset Bit
Set and clear to reset the command line controller in case of transfer abort.
4-3
-
2-1
DATD1:0
Data Transmission Delay Bits
Used to delay the data transmission after a response from 3 MMC clock periods (all bits
cleared) to 9 MMC clock periods (all bits set) by step of 2 MMC clock periods.
0
FLOWC
MMC Flow Control Bit
Set to enable the flow control during data transfers.
Clear to disable the flow control during data transfers.
MMC Clock Enable Bit
Set to enable the MCLK clocks and activate the MMC controller.
Clear to disable the MMC clocks and freeze the MMC controller.
Reserved
The value read from these bits is always 0. Do not set these bits.
Reset Value = 0000 0000b
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Table 18-11. MMSTA Register
MMSTA (S:DEh Read Only) – MMC Control and Status Register
7
6
5
4
3
2
1
0
-
-
CBUSY
CRC16S
DATFS
CRC7S
RESPFS
CFLCK
Bit Number
Bit
Mnemonic
Description
7-6
-
5
CBUSY
Card Busy Flag
Set by hardware when the card sends a busy state on the data line.
Cleared by hardware when the card no more sends a busy state on the data line.
CRC16S
CRC16 Status Bit
Transmission mode
Set by hardware when the token response reports a good CRC.
Cleared by hardware when the token response reports a bad CRC.
Reception mode
Set by hardware when the CRC16 received in the data block is correct.
Cleared by hardware when the CRC16 received in the data block is not correct.
4
3
2
DATFS
CRC7S
Reserved
The value read from these bits is always 0. Do not set these bits.
Data Format Status Bit
Transmission mode
Set by hardware when the format of the token response is correct.
Cleared by hardware when the format of the token response is not correct.
Reception mode
Set by hardware when the format of the frame is correct.
Cleared by hardware when the format of the frame is not correct.
CRC7 Status Bit
Set by hardware when the CRC7 computed in the response is correct.
Cleared by hardware when the CRC7 computed in the response is not correct.
This bit is not relevant when CRCDIS is set.
1
RESPFS
0
CFLCK
Response Format Status Bit
Set by hardware when the format of a response is correct.
Cleared by hardware when the format of a response is not correct.
Command FIFO Lock Bit
Set by hardware to signal user not to write in the transmit command FIFO: busy state.
Cleared by hardware to signal user the transmit command FIFO is available: idle state.
Reset Value = 0000 0000b
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Table 18-12. MMINT Register
MMINT (S:E7h Read Only) – MMC Interrupt Register
7
6
5
4
3
2
1
0
MCBI
EORI
EOCI
EOFI
F2FI
F1FI
F2EI
F1EI
Bit Number
Bit
Mnemonic
Description
7
MCBI
MMC Card Busy Interrupt Flag
Set by hardware when the card enters or exits its busy state (when the busy signal is
asserted or deasserted on the data line).
Cleared when reading MMINT.
6
EORI
End of Response Interrupt Flag
Set by hardware at the end of response reception.
Cleared when reading MMINT.
5
EOCI
End of Command Interrupt Flag
Set by hardware at the end of command transmission.
Clear when reading MMINT.
4
EOFI
End of Frame Interrupt Flag
Set by hardware at the end of frame (stream or block) transfer.
Clear when reading MMINT.
3
F2FI
FIFO 2 Full Interrupt Flag
Set by hardware when second FIFO becomes full.
Cleared by hardware when second FIFO becomes empty.
2
F1FI
FIFO 1 Full Interrupt Flag
Set by hardware when first FIFO becomes full.
Cleared by hardware when first FIFO becomes empty.
1
F2EI
FIFO 2 Empty Interrupt Flag
Set by hardware when second FIFO becomes empty.
Cleared by hardware when second FIFO becomes full.
0
F1EI
FIFO 1 Empty Interrupt Flag
Set by hardware when first FIFO becomes empty.
Cleared by hardware when first FIFO becomes full.
Reset Value = 0000 0011b
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Table 18-13. MMMSK Register
MMMSK (S:DFh) – MMC Interrupt Mask Register
7
6
5
4
3
2
1
0
MCBM
EORM
EOCM
EOFM
F2FM
F1FM
F2EM
F1EM
Bit Number
Bit
Mnemonic
Description
7
MCBM
MMC Card Busy Interrupt Mask Bit
Set to prevent MCBI flag from generating an MMC interrupt.
Clear to allow MCBI flag to generate an MMC interrupt.
6
EORM
End Of Response Interrupt Mask Bit
Set to prevent EORI flag from generating an MMC interrupt.
Clear to allow EORI flag to generate an MMC interrupt.
5
EOCM
End Of Command Interrupt Mask Bit
Set to prevent EOCI flag from generating an MMC interrupt.
Clear to allow EOCI flag to generate an MMC interrupt.
4
EOFM
End Of Frame Interrupt Mask Bit
Set to prevent EOFI flag from generating an MMC interrupt.
Clear to allow EOFI flag to generate an MMC interrupt.
3
F2FM
FIFO 2 Full Interrupt Mask Bit
Set to prevent F2FI flag from generating an MMC interrupt.
Clear to allow F2FI flag to generate an MMC interrupt.
2
F1FM
FIFO 1 Full Interrupt Mask Bit
Set to prevent F1FI flag from generating an MMC interrupt.
Clear to allow F1FI flag to generate an MMC interrupt.
1
F2EM
FIFO 2 Empty Interrupt Mask Bit
Set to prevent F2EI flag from generating an MMC interrupt.
Clear to allow F2EI flag to generate an MMC interrupt.
0
F1EM
FIFO 1 Empty Interrupt Mask Bit
Set to prevent F1EI flag from generating an MMC interrupt.
Clear to allow F1EI flag to generate an MMC interrupt.
Reset Value = 1111 1111b
Table 18-14. MMCMD Register
MMCMD (S:DDh) – MMC Command Register
7
6
5
4
3
2
1
0
MC7
MC6
MC5
MC4
MC3
MC2
MC1
MC0
Bit Number
Bit
Mnemonic
Description
7-0
MC7:0
MMC Command Receive Byte
Output (read) register of the response FIFO.
MMC Command Transmit Byte
Input (write) register of the command FIFO.
Reset Value = 1111 1111b
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Table 18-15. MMDAT Register
MMDAT (S:DCh) – MMC Data Register
7
6
5
4
3
2
1
0
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
Bit Number
Bit
Mnemonic
Description
7-0
MD7:0
MMC Data Byte
Input (write) or output (read) register of the data FIFO.
Reset Value = 1111 1111b
Table 18-16. MMCLK Register
MMCLK (S:EDh) – MMC Clock Divider Register
7
6
5
4
3
2
1
0
MMCD7
MMCD6
MMCD5
MMCD4
MMCD3
MMCD2
MMCD1
MMCD0
Bit Number
Bit
Mnemonic
Description
7-0
MMCD7:0
MMC Clock Divider
8-bit divider for MMC clock generation.
Reset Value = 0000 0000b
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19. Synchronous Peripheral Interface
The AT8xC51SND2C implements a Synchronous Peripheral Interface with master and slave
modes capability.
Figure 19-1 shows an SPI bus configuration using the AT8xC51SND2C as master connected to
slave peripherals while Figure 19-2 shows an SPI bus configuration using the AT8xC51SND2C
as slave of an other master.
The bus is made of three wires connecting all the devices together:
•
Master Output Slave Input (MOSI): it is used to transfer data in series from the master to a
slave.
It is driven by the master.
•
Master Input Slave Output (MISO): it is used to transfer data in series from a slave to the
master.
It is driven by the selected slave.
•
Serial Clock (SCK): it is used to synchronize the data transmission both in and out the
devices through their MOSI and MISO lines. It is driven by the master for eight clock cycles
which allows to exchange one Byte on the serial lines.
Each slave peripheral is selected by one Slave Select pin (SS). If there is only one slave, it may
be continuously selected with SS tied to a low level. Otherwise, the AT8xC51SND2C may select
each device by software through port pins (Pn.x). Special care should be taken not to select 2
slaves at the same time to avoid bus conflicts.
Figure 19-1. Typical Master SPI Bus Configuration
Pn.z
Pn.y
Pn.x
SS
AT8xC51SND2C
P4.0
P4.1
P4.2
SO
DataFlash 1
SI
SCK
SS DataFlash 2
SO
SI
SCK
SS
SO
LCD
Controller
SI
SCK
MISO
MOSI
SCK
Figure 19-2. Typical Slave SPI Bus Configuration
SSn
SS
SS1
SS0
MASTER
SS
SO
Slave 1
SI
SCK
SS
SO
Slave 2
AT8xC51SND2C
Slave n
SI
MISO MOSI SCK
SCK
MISO
MOSI
SCK
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19.1
Description
The SPI controller interfaces with the C51 core through three special function registers: SPCON,
the SPI control register (see Table 19-2); SPSTA, the SPI status register (see Table 19-3); and
SPDAT, the SPI data register (see Table 19-4).
19.1.1
Master Mode
The SPI operates in master mode when the MSTR bit in SPCON is set.
Figure 19-3 shows the SPI block diagram in master mode. Only a master SPI module can initiate
transmissions. Software begins the transmission by writing to SPDAT. Writing to SPDAT writes
to the shift register while reading SPDAT reads an intermediate register updated at the end of
each transfer.
The Byte begins shifting out on the MOSI pin under the control of the bit rate generator. This
generator also controls the shift register of the slave peripheral through the SCK output pin. As
the Byte shifts out, another Byte shifts in from the slave peripheral on the MISO pin. The Byte is
transmitted most significant bit (MSB) first. The end of transfer is signaled by SPIF being set.
When the AT8xC51SND2C is the only master on the bus, it can be useful not to use SS# pin
and get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON.
Figure 19-3. SPI Master Mode Block Diagram
MOSI/P4.1
I
8-bit Shift Register
SPDAT WR
SCK/P4.2
SPDAT RD
Q
Internal Bus
MISO/P4.0
SS#/P4.3
SSDIS
SPCON.5
MODF
Control and Clock Logic
SPSTA.4
WCOL
SPSTA.6
PER
CLOCK
Bit Rate Generator
SPIF
SPSTA.7
SPEN
SPCON.6
Note:
19.1.2
SPR2:0
CPHA
CPOL
SPCON
SPCON.2
SPCON.3
MSTR bit in SPCON is set to select master mode.
Slave Mode
The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has been
loaded in SPDAT.
Figure 19-4 shows the SPI block diagram in slave mode. In slave mode, before a data transmission occurs, the SS pin of the slave SPI must be asserted to low level. SS must remain low until
the transmission of the Byte is complete. In the slave SPI module, data enters the shift register
through the MOSI pin under the control of the serial clock provided by the master SPI module on
the SCK input pin. When the master starts a transmission, the data in the shift register begins
shifting out on the MISO pin. The end of transfer is signaled by SPIF being set.
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When the AT8xC51SND2C is the only slave on the bus, it can be useful not to use SS# pin and
get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON. This bit has no
effect when CPHA is cleared (see Section "SS Management", page 159).
Figure 19-4. SPI Slave Mode Block Diagram
MISO/P4.2
I
8-bit Shift Register
SPDAT WR
SPDAT RD
SCK/P4.2
Q
Internal Bus
MOSI/P4.1
Control and Clock Logic
SS/P4.3
SPIF
SPSTA.7
SSDIS
SPCON.5
Note:
19.1.3
CPHA
CPOL
SPCON.2
SPCON.3
1. MSTR bit in SPCON is cleared to select slave mode.
Bit Rate
The bit rate can be selected from seven predefined bit rates using the SPR2, SPR1 and SPR0
control bits in SPCON according to Table 19-1. These bit rates are derived from the peripheral
clock (FPER) issued from the Clock Controller block as detailed in Section "Oscillator", page 13.
Table 19-1. Serial Bit Rates
Bit Rate (kHz) Vs FPER
SPR2
SPR1
SPR0
6 MHz(1)
8 MHz(1)
10 MHz(1)
12 MHz(2)
16 MHz(2)
20 MHz(2)
FPER Divider
0
0
0
3000
4000
5000
6000
8000
10000
2
0
0
1
1500
2000
2500
3000
4000
5000
4
0
1
0
750
1000
1250
1500
2000
2500
8
0
1
1
375
500
625
750
1000
1250
16
1
0
0
187.5
250
312.5
375
500
625
32
1
0
1
93.75
125
156.25
187.5
250
312.5
64
1
1
0
46.875
62.5
78.125
93.75
125
156.25
128
1
1
1
6000
8000
10000
12000
16000
20000
1
Notes:
19.1.4
1. These frequencies are achieved in X1 mode, FPER = FOSC ÷ 2.
2. These frequencies are achieved in X2 mode, FPER = FOSC.
Data Transfer
The Clock Polarity bit (CPOL in SPCON) defines the default SCK line level in idle state(1) while
the Clock Phase bit (CPHA in SPCON) defines the edges on which the input data are sampled
and the edges on which the output data are shifted (see Figure 19-5 and Figure 19-6). The SI
signal is output from the selected slave and the SO signal is the output from the master. The
AT8xC51SND2C captures data from the SI line while the selected slave captures data from the
SO line.
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For simplicity, Figure 19-5 and Figure 19-6 depict the SPI waveforms in idealized form and do
not provide precise timing information. For timing parameters refer to the Section “AC
Characteristics”.
Note:
1. When the peripheral is disabled (SPEN = 0), default SCK line is high level.
Figure 19-5. Data Transmission Format (CPHA = 0)
SCK Cycle Number
1
2
3
4
5
6
7
8
MSB
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
LSB
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
LSB
SPEN (Internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI (From Master)
MISO (From Slave)
MSB
SS (to slave)
Capture point
Figure 19-6. Data Transmission Format (CPHA = 1)
1
2
3
4
5
6
7
8
MOSI (from master)
MSB
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
LSB
MISO (from slave)
MSB
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
SCK cycle number
SPEN (internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
LSB
SS (to slave)
Capture point
19.1.5
SS Management
Figure 19-5 shows an SPI transmission with CPHA = 0, where the first SCK edge is the MSB
capture point. Therefore the slave starts to output its MSB as soon as it is selected: SS asserted
to low level. SS must then be deasserted between each Byte transmission (see Figure 19-7).
SPDAT must be loaded with a data before SS is asserted again.
Figure 19-6 shows an SPI transmission with CPHA = 1, where the first SCK edge is used by the
slave as a start of transmission signal. Therefore, SS may remain asserted between each Byte
transmission (see Figure 19-7).
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Figure 19-7. SS Timing Diagram
SI/SO
Byte 1
Byte 2
Byte 3
SS (CPHA = 0)
SS (CPHA = 1)
19.1.6
Error Conditions
The following flags signal the SPI error conditions:
19.2
•
MODF in SPSTA signals a mode fault.
MODF flag is relevant only in master mode when SS usage is enabled (SSDIS bit cleared).
It signals when set that an other master on the bus has asserted SS pin and so, may create
a conflict on the bus with 2 master sending data at the same time.
•
A mode fault automatically disables the SPI (SPEN cleared) and configures the SPI in slave
mode (MSTR cleared).
MODF flag can trigger an interrupt as explained in Section "Interrupt", page 160.
MODF flag is cleared by reading SPSTA and re-configuring SPI by writing to SPCON.
•
WCOL in SPSTA signals a write collision.
WCOL flag is set when SPDAT is loaded while a transfer is on-going. In this case data is not
written to SPDAT and transfer continue uninterrupted. WCOL flag does not trigger any
interrupt and is relevant jointly with SPIF flag.
WCOL flag is cleared after reading SPSTA and writing new data to SPDAT while no transfer
is on-going.
Interrupt
The SPI handles 2 interrupt sources that are the “end of transfer” and the “mode fault” flags.
As shown in Figure 19-8, these flags are combined toghether to appear as a single interrupt
source for the C51 core. The SPIF flag is set at the end of an 8-bit shift in and out and is cleared
by reading SPSTA and then reading from or writing to SPDAT.
The MODF flag is set in case of mode fault error and is cleared by reading SPSTA and then writing to SPCON.
The SPI interrupt is enabled by setting ESPI bit in IEN1 register. This assumes interrupts are
globally enabled by setting EA bit in IEN0 register.
Figure 19-8. SPI Interrupt System
SPIF
SPI Controller
Interrupt Request
SPSTA.7
MODF
SPSTA.4
ESPI
IEN1.2
19.3
Configuration
The SPI configuration is made through SPCON.
19.3.1
Master Configuration
The SPI operates in master mode when the MSTR bit in SPCON is set.
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19.3.2
Slave Configuration
The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has been
loaded is SPDAT.
19.3.3
Data Exchange
There are 2 possible methods to exchange data in master and slave modes:
19.3.4
•
polling
•
interrupts
Master Mode with Polling Policy
Figure 19-9 shows the initialization phase and the transfer phase flows using the polling method.
Using this flow prevents any overrun error occurrence.
The bit rate is selected according to Table 19-1. The transfer format depends on the slave
peripheral.
SS may be deasserted between transfers depending also on the slave peripheral.
SPIF flag is cleared when reading SPDAT (SPSTA has been read before by the “end of transfer”
check).
This polling method provides the fastest effective transmission and is well adapted when communicating at high speed with other microcontrollers. However, the procedure may then be
interrupted at any time by higher priority tasks.
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Figure 19-9. Master SPI Polling Flows
SPI Initialization
Polling Policy
SPI Transfer
Polling Policy
Disable interrupt
SPIE = 0
Select Slave
Pn.x = L
Select Master Mode
MSTR = 1
Start Transfer
write data in SPDAT
Select Bit Rate
program SPR2:0
End Of Transfer?
SPIF = 1?
Select Format
program CPOL & CPHA
Get Data Received
read SPDAT
Enable SPI
SPEN = 1
Last Transfer?
Deselect Slave
Pn.x = H
19.3.5
Master Mode with Interrupt
Figure 19-10 shows the initialization phase and the transfer phase flows using the interrupt.
Using this flow prevents any overrun error occurrence.
The bit rate is selected according to Table 19-1.
The transfer format depends on the slave peripheral.
SS may be deasserted between transfers depending also on the slave peripheral.
Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag. Clear is
effective when reading SPDAT.
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Figure 19-10. Master SPI Interrupt Flows
SPI Initialization
Interrupt Policy
SPI Interrupt
Service Routine
Select Master Mode
MSTR = 1
Read Status
Read SPSTA
Select Bit Rate
program SPR2:0
Get Data Received
read SPDAT
Select Format
program CPOL & CPHA
Start New Transfer
write data in SPDAT
Enable interrupt
ESPI =1
Last Transfer?
Enable SPI
SPEN = 1
Deselect Slave
Pn.x = H
Select Slave
Pn.x = L
Disable interrupt
SPIE = 0
Start Transfer
write data in SPDAT
19.3.6
Slave Mode with Polling Policy
Figure 19-11 shows the initialization phase and the transfer phase flows using the polling.
The transfer format depends on the master controller.
SPIF flag is cleared when reading SPDAT (SPSTA has been read before by the “end of reception” check).
This provides the fastest effective transmission and is well adapted when communicating at high
speed with other Microcontrollers. However, the process may then be interrupted at any time by
higher priority tasks.
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Figure 19-11. Slave SPI Polling Flows
SPI Initialization
Polling Policy
Disable interrupt
SPIE = 0
SPI Transfer
Polling Policy
Data Received?
SPIF = 1?
Select Slave Mode
MSTR = 0
Get Data Received
read SPDAT
Select Format
program CPOL & CPHA
Prepare Next Transfer
write data in SPDAT
Enable SPI
SPEN = 1
Prepare Transfer
write data in SPDAT
19.3.7
Slave Mode with Interrupt Policy
Figure 19-10 shows the initialization phase and the transfer phase flows using the interrupt.
The transfer format depends on the master controller.
Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag. Clear is
effective when reading SPDAT.
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Figure 19-12. Slave SPI Interrupt Policy Flows
SPI Initialization
Interrupt Policy
SPI Interrupt
Service Routine
Select Slave Mode
MSTR = 0
Get Status
Read SPSTA
Select Format
program CPOL & CPHA
Get Data Received
read SPDAT
Enable interrupt
ESPI =1
Prepare New Transfer
write data in SPDAT
Enable SPI
SPEN = 1
Prepare Transfer
write data in SPDAT
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19.4
Registers
Table 19-2.
SPCON Register
SPCON (S:C3h) – SPI Control Register
7
6
5
4
3
2
1
0
SPR2
SPEN
SSDIS
MSTR
CPOL
CPHA
SPR1
SPR0
Bit Number
Bit
Mnemonic
Description
7
SPR2
SPI Rate Bit 2
Refer to Table 19-1 for bit rate description.
6
SPEN
SPI Enable Bit
Set to enable the SPI interface.
Clear to disable the SPI interface.
5
SSDIS
Slave Select Input Disable Bit
Set to disable SS in both master and slave modes. In slave mode this bit has no effect if
CPHA = 0.
Clear to enable SS in both master and slave modes.
4
MSTR
Master Mode Select
Set to select the master mode.
Clear to select the slave mode.
3
CPOL
2
CPHA
1-0
SPR1:0
SPI Clock Polarity Bit(1)
Set to have the clock output set to high level in idle state.
Clear to have the clock output set to low level in idle state.
SPI Clock Phase Bit
Set to have the data sampled when the clock returns to idle state (see CPOL).
Clear to have the data sampled when the clock leaves the idle state (see CPOL).
SPI Rate Bits 0 and 1
Refer to Table 19-1 for bit rate description.
Reset Value = 0001 0100b
Note:
166
1. When the SPI is disabled, SCK outputs high level.
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Table 19-3.
SPSTA Register
SPSTA (S:C4h) – SPI Status Register
7
6
5
4
3
2
1
0
SPIF
WCOL
-
MODF
-
-
-
-
Bit Number
Bit
Mnemonic
Description
7
SPIF
6
WCOL
5
-
4
MODF
3-0
-
SPI Interrupt Flag
Set by hardware when an 8-bit shift is completed.
Cleared by hardware when reading or writing SPDAT after reading SPSTA.
Write Collision Flag
Set by hardware to indicate that a collision has been detected.
Cleared by hardware to indicate that no collision has been detected.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Mode Fault
Set by hardware to indicate that the SS pin is at an appropriate level.
Cleared by hardware to indicate that the SS pin is at an inappropriate level.
Reserved
The value read from these bits is indeterminate. Do not set these bits.
Reset Value = 00000 0000b
Table 19-4.
SPDAT Register
SPDAT (S:C5h) – Synchronous Serial Data Register
7
6
5
4
3
2
1
0
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
Bit Number
Bit
Mnemonic
Description
7-0
SPD7:0
Synchronous Serial Data.
Reset Value = XXXX XXXXb
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20. Serial I/O Port
The serial I/O port in the AT8xC51SND2C provides both synchronous and asynchronous communication modes. It operates as a Synchronous Receiver and Transmitter in one single mode
(Mode 0) and operates as an Universal Asynchronous Receiver and Transmitter (UART) in three
full-duplex modes (Modes 1, 2 and 3). Asynchronous modes support framing error detection and
multiprocessor communication with automatic address recognition.
20.1
Mode Selection
SM0 and SM1 bits in SCON register (see Figure 20-3) are used to select a mode among the single synchronous and the three asynchronous modes according to Table 20-1.
Table 20-1.
20.2
Serial I/O Port Mode Selection
SM0
SM1
Mode
Description
Baud Rate
0
0
0
Synchronous Shift Register
Fixed/Variable
0
1
1
8-bit UART
Variable
1
0
2
9-bit UART
Fixed
1
1
3
9-bit UART
Variable
Baud Rate Generator
Depending on the mode and the source selection, the baud rate can be generated from either
the Timer 1 or the Internal Baud Rate Generator. The Timer 1 can be used in Modes 1 and 3
while the Internal Baud Rate Generator can be used in Modes 0, 1
and 3.
The addition of the Internal Baud Rate Generator allows freeing of the Timer 1 for other purposes in the application. It is highly recommended to use the Internal Baud Rate Generator as it
allows higher and more accurate baud rates than Timer 1.
Baud rate formulas depend on the modes selected and are given in the following mode sections.
20.2.1
Timer 1
When using Timer 1, the Baud Rate is derived from the overflow of the timer. As shown in
Figure 20-1 Timer 1 is used in its 8-bit auto-reload mode (detailed in Section "Mode 2 (8-bit
Timer with Auto-Reload)", page 54). SMOD1 bit in PCON register allows doubling of the generated baud rate.
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Figure 20-1. Timer 1 Baud Rate Generator Block Diagram
PER
CLOCK
÷6
0
TL1
(8 bits)
1
Overflow
÷2
T1
0
1
To serial
Port
C/T1#
TMOD.6
SMOD1
INT1
PCON.7
TH1
(8 bits)
GATE1
T1
CLOCK
TMOD.7
TR1
TCON.6
20.2.2
Internal Baud Rate Generator
When using the Internal Baud Rate Generator, the Baud Rate is derived from the overflow of the
timer. As shown in Figure 20-2 the Internal Baud Rate Generator is an 8-bit auto-reload timer
fed by the peripheral clock or by the peripheral clock divided by 6 depending on the SPD bit in
BDRCON register (see Table 20-7). The Internal Baud Rate Generator is enabled by setting
BBR bit in BDRCON register. SMOD1 bit in PCON register allows doubling of the generated
baud rate.
Figure 20-2. Internal Baud Rate Generator Block Diagram
PER
CLOCK
÷6
0
BRG
(8 bits)
1
Overflow
÷2
0
1
SPD
BRR
BDRCON.1
BDRCON.4
BRL
(8 bits)
20.3
To serial
Port (M0)
IBRG0
CLOCK
To serial
Port
SMOD1
PCON.7
IBRG
CLOCK
Synchronous Mode (Mode 0)
Mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the I/0 capabilities of a device with shift registers. The transmit data (TXD) pin outputs a set of eight clock
pulses while the receive data (RXD) pin transmits or receives a Byte of data. The 8-bit data are
transmitted and received least-significant bit (LSB) first. Shifts occur at a fixed Baud Rate (see
Section "Baud Rate Selection (Mode 0)", page 171). Figure 20-3 shows the serial port block diagram in Mode 0.
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Figure 20-3. Serial I/O Port Block Diagram (Mode 0)
SCON.6
SCON.7
SM1
SM0
SBUF Tx SR
Mode Decoder
RXD
M3 M2 M1 M0
SBUF Rx SR
Mode
Controller
PER
CLOCK
20.3.1
TI
RI
SCON.1
SCON.0
Baud Rate
Controller
BRG
CLOCK
TXD
Transmission (Mode 0)
To start a transmission mode 0, write to SCON register clearing bits SM0, SM1.
As shown in Figure 20-4, writing the Byte to transmit to SBUF register starts the transmission.
Hardware shifts the LSB (D0) onto the RXD pin during the first clock cycle composed of a high
level then low level signal on TXD. During the eighth clock cycle the MSB (D7) is on the RXD
pin. Then, hardware drives the RXD pin high and asserts TI to indicate the end of the
transmission.
Figure 20-4. Transmission Waveforms (Mode 0)
TXD
Write to SBUF
RXD
D0
D1
D2
D3
D4
D5
D6
D7
TI
20.3.2
Reception (Mode 0)
To start a reception in mode 0, write to SCON register clearing SM0, SM1 and RI bits and setting
the REN bit.
As shown in Figure 20-5, Clock is pulsed and the LSB (D0) is sampled on the RXD pin. The D0
bit is then shifted into the shift register. After eight samplings, the MSB (D7) is shifted into the
shift register, and hardware asserts RI bit to indicate a completed reception. Software can then
read the received Byte from SBUF register.
Figure 20-5. Reception Waveforms (Mode 0)
TXD
Write to SCON
RXD
Set REN, Clear RI
D0
D1
D2
D3
D4
D5
D6
D7
RI
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20.3.3
Baud Rate Selection (Mode 0)
In mode 0, the baud rate can be either, fixed or variable.
As shown in Figure 20-6, the selection is done using M0SRC bit in BDRCON register.
Figure 20-7 gives the baud rate calculation formulas for each baud rate source.
Figure 20-6. Baud Rate Source Selection (mode 0)
PER
CLOCK
÷6
0
To Serial Port
1
IBRG0
CLOCK
M0SRC
BDRCON.0
Figure 20-7. Baud Rate Formulas (Mode 0)
Baud_Rate=
Baud_Rate=
FPER
6
BRL= 256 -
a. Fixed Formula
20.4
FPER
6(1-SPD) ⋅ 16 ⋅ (256 -BRL)
FPER
6(1-SPD) ⋅ 16 ⋅ Baud_Rate
b. Variable Formula
Asynchronous Modes (Modes 1, 2 and 3)
The Serial Port has one 8-bit and 2 9-bit asynchronous modes of operation. Figure 20-8 shows
the Serial Port block diagram in such asynchronous modes.
Figure 20-8. Serial I/O Port Block Diagram (Modes 1, 2 and 3)
SCON.6
SCON.7
SCON.3
SM1
SM0
TB8
Mode Decoder
SBUF Tx SR
TXD
Rx SR
RXD
M3 M2 M1 M0
T1
CLOCK
Mode & Clock
Controller
IBRG
CLOCK
PER
CLOCK
20.4.0.1
SBUF Rx
SM2
TI
RI
SCON.4
SCON.1
SCON.0
RB8
SCON.2
Mode 1
Mode 1 is a full-duplex, asynchronous mode. The data frame (see Figure 20-9) consists of 10
bits: one start, eight data bits and one stop bit. Serial data is transmitted on the TXD pin and
received on the RXD pin. When a data is received, the stop bit is read in the RB8 bit in SCON
register.
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Figure 20-9. Data Frame Format (Mode 1)
Mode 1
D0
D1
D2
Start bit
20.4.0.2
D3
D4
D5
D6
D7
8-bit data
Stop bit
Modes 2 and 3
Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (see Figure 20-10) consists of 11 bits: one start bit, eight data bits (transmitted and received LSB first), one
programmable ninth data bit and one stop bit. Serial data is transmitted on the TXD pin and
received on the RXD pin. On receive, the ninth bit is read from RB8 bit in SCON register. On
transmit, the ninth data bit is written to TB8 bit in SCON register. Alternatively, you can use the
ninth bit can be used as a command/data flag.
Figure 20-10. Data Frame Format (Modes 2 and 3)
D0
D1
D2
D3
Start bit
20.4.1
D4
D5
D6
D7
9-bit data
D8
Stop bit
Transmission (Modes 1, 2 and 3)
To initiate a transmission, write to SCON register, set the SM0 and SM1 bits according to
Table 20-1, and set the ninth bit by writing to TB8 bit. Then, writing the Byte to be transmitted to
SBUF register starts the transmission.
20.4.2
Reception (Modes 1, 2 and 3)
To prepare for reception, write to SCON register, set the SM0 and SM1 bits according to
Table 20-1, and set the REN bit. The actual reception is then initiated by a detected high-to-low
transition on the RXD pin.
20.4.3
Framing Error Detection (Modes 1, 2 and 3)
Framing error detection is provided for the three asynchronous modes. To enable the framing bit
error detection feature, set SMOD0 bit in PCON register as shown in Figure 20-11.
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by
2 devices. If a valid stop bit is not found, the software sets FE bit in SCON register.
Software may examine FE bit after each reception to check for data errors. Once set, only software or a chip reset clear FE bit. Subsequently received frames with valid stop bits cannot clear
FE bit. When the framing error detection feature is enabled, RI rises on stop bit instead of the
last data bit as detailed in Figure 20-17.
Figure 20-11. Framing Error Block Diagram
Framing Error
Controller
FE
1
SM0/FE
0
SCON.7
SM0
SMOD0
PCON.6
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20.4.4
Baud Rate Selection (Modes 1 and 3)
In modes 1 and 3, the Baud Rate is derived either from the Timer 1 or the Internal Baud Rate
Generator and allows different baud rate in reception and transmission.
As shown in Figure 20-12 the selection is done using RBCK and TBCK bits in BDRCON register.
Figure 20-13 gives the baud rate calculation formulas for each baud rate source while Table 202 details Internal Baud Rate Generator configuration for different peripheral clock frequencies
and giving baud rates closer to the standard baud rates.
Figure 20-12. Baud Rate Source Selection (Modes 1 and 3)
T1
CLOCK
0
÷ 16
1
IBRG
CLOCK
To Serial
Rx Port
RBCK
BDRCON.2
T1
CLOCK
0
÷ 16
IBRG
CLOCK
1
To Serial
Tx Port
TBCK
BDRCON.3
Figure 20-13. Baud Rate Formulas (Modes 1 and 3)
Baud_Rate=
BRL= 256 -
6
6
2SMOD1 ⋅ FPER
⋅ 32 ⋅ (256 -BRL)
(1-SPD)
2SMOD1 ⋅ FPER
⋅ 32 ⋅ Baud_Rate
(1-SPD)
a. IBRG Formula
Baud_Rate=
TH1= 256 -
2SMOD1 ⋅ FPER
6 ⋅ 32 ⋅ (256 -TH1)
2SMOD1 ⋅ FPER
192 ⋅ Baud_Rate
b. T1 Formula
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Table 20-2.
Internal Baud Rate Generator Value
FPER = 6 MHz(1)
FPER = 8 MHz(1)
Baud
Rate
SPD
SMOD
1
BRL
Error
%
SPD
SMOD
1
BRL
Error
%
SPD
SMOD
1
BRL
Error
%
115200
-
-
-
-
-
-
-
-
-
-
-
-
57600
-
-
-
-
1
1
247
3.55
1
1
245
1.36
38400
1
1
246
2.34
1
1
243
0.16
1
1
240
1.73
19200
1
1
236
2.34
1
1
230
0.16
1
1
223
1.36
9600
1
1
217
0.16
1
1
204
0.16
1
1
191
0.16
4800
1
1
178
0.16
1
1
152
0.16
1
1
126
0.16
FPER = 12 MHz(2)
Notes:
20.4.5
FPER = 10 MHz(1)
FPER = 16 MHz(2)
FPER = 20 MHz(2)
Baud
Rate
SPD
SMOD
1
BRL
Error
%
SPD
SMOD
1
BRL
Error
%
SPD
SMOD
1
BRL
Error
%
115200
-
-
-
-
1
1
247
3.55
1
1
245
1.36
57600
1
1
243
0.16
1
1
239
2.12
1
1
234
1.36
38400
1
1
236
2.34
1
1
230
0.16
1
1
223
1.36
19200
1
1
217
0.16
1
1
204
0.16
1
1
191
0.16
9600
1
1
178
0.16
1
1
152
0.16
1
1
126
0.16
4800
1
1
100
0.16
1
1
48
0.16
1
0
126
0.16
1. These frequencies are achieved in X1 mode, FPER = FOSC ÷ 2.
2. These frequencies are achieved in X2 mode, FPER = FOSC.
Baud Rate Selection (Mode 2)
In mode 2, the baud rate can only be programmed to 2 fixed values: 1/16 or 1/32 of the peripheral clock frequency.
As shown in Figure 20-14 the selection is done using SMOD1 bit in PCON register.
Figure 20-15 gives the baud rate calculation formula depending on the selection.
Figure 20-14. Baud Rate Generator Selection (Mode 2)
PER
CLOCK
÷2
0
÷ 16
To Serial Port
1
SMOD1
PCON.7
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AT8xC51SND2C/MP3B
Figure 20-15. Baud Rate Formula (Mode 2)
Baud_Rate=
20.5
2SMOD1 ⋅ FPER
32
Multiprocessor Communication (Modes 2 and 3)
Modes 2 and 3 provide a ninth-bit mode to facilitate multiprocessor communication. To enable
this feature, set SM2 bit in SCON register. When the multiprocessor communication feature is
enabled, the serial Port can differentiate between data frames (ninth bit clear) and address
frames (ninth bit set). This allows the AT8xC51SND2C to function as a slave processor in an
environment where multiple slave processors share a single serial line.
When the multiprocessor communication feature is enabled, the receiver ignores frames with
the ninth bit clear. The receiver examines frames with the ninth bit set for an address match. If
the received address matches the slaves address, the receiver hardware sets RB8 and RI bits in
SCON register, generating an interrupt.
The addressed slave’s software then clears SM2 bit in SCON register and prepares to receive
the data Bytes. The other slaves are unaffected by these data Bytes because they are waiting to
respond to their own addresses.
20.6
Automatic Address Recognition
The automatic address recognition feature is enabled when the multiprocessor communication
feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the Serial Port to examine the address of each incoming command
frame. Only when the Serial Port recognizes its own address, the receiver sets RI bit in SCON
register to generate an interrupt. This ensures that the CPU is not interrupted by command
frames addressed to other devices.
If desired, the automatic address recognition feature in mode 1 may be enabled. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received
command frame address matches the device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broadcast address.
Note:
20.6.1
The multiprocessor communication and automatic address recognition features cannot be
enabled in mode 0 (i.e, setting SM2 bit in SCON register in mode 0 has no effect).
Given Address
Each device has an individual address that is specified in SADDR register; the SADEN register
is a mask Byte that contains don’t care bits (defined by zeros) to form the device’s given
address. The don’t care bits provide the flexibility to address one or more slaves at a time. The
following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask Byte must be 1111 1111b.
For example:
SADDR = 0101 0110b
SADEN = 1111 1100b
Given = 0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR = 1111 0001b
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SADEN = 1111 1010b
Given = 1111 0X0Xb
Slave B:SADDR = 1111 0011b
SADEN = 1111 1001b
Given = 1111 0XX1b
Slave C:SADDR = 1111 0011b
SADEN = 1111 1101b
Given = 1111 00X1b
The SADEN Byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate
with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000B).
For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves
A and B, but not slave C, the master must send an address with bits 0 and 1 both set (e.g.
1111 0011B).
To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1
clear, and bit 2 clear (e.g. 1111 0001B).
20.6.2
Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with
zeros defined as don’t-care bits, e.g.:
SADDR = 0101 0110b
SADEN = 1111 1100b
(SADDR | SADEN)=1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however in most
applications, a broadcast address is FFh.
The following is an example of using broadcast addresses:
Slave A:SADDR = 1111 0001b
SADEN = 1111 1010b
Given = 1111 1X11b,
Slave B:SADDR = 1111 0011b
SADEN = 1111 1001b
Given = 1111 1X11b,
Slave C:SADDR = 1111 0010b
SADEN = 1111 1101b
Given = 1111 1111b,
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of
the slaves, the master must send the address FFh.
To communicate with slaves A and B, but not slave C, the master must send the address FBh.
20.6.3
Reset Address
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast
addresses are XXXX XXXXb (all don’t care bits). This ensures that the Serial Port is backwards
compatible with the 80C51 microcontrollers that do not support automatic address recognition.
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20.7
Interrupt
The Serial I/O Port handles 2 interrupt sources that are the “end of reception” (RI in SCON) and
“end of transmission” (TI in SCON) flags. As shown in Figure 20-16 these flags are combined
together to appear as a single interrupt source for the C51 core. Flags must be cleared by software when executing the serial interrupt service routine.
The serial interrupt is enabled by setting ES bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register.
Depending on the selected mode and weather the framing error detection is enabled or disabled, RI flag is set during the stop bit or during the ninth bit as detailed in Figure 20-17.
Figure 20-16. Serial I/O Interrupt System
SCON.0
RI
Serial I/O
Interrupt Request
TI
SCON.1
ES
IEN0.4
Figure 20-17. Interrupt Waveforms
a. Mode 1
RXD
D0
D1
D2
Start Bit
D3
D4
D5
D6
D7
8-bit Data
Stop Bit
RI
SMOD0 = X
FE
SMOD0 = 1
b. Mode 2 and 3
RXD
D0
Start bit
D1
D2
D3
D4
9-bit data
D5
D6
D7
D8
Stop bit
RI
SMOD0 = 0
RI
SMOD0 = 1
FE
SMOD0 = 1
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20.8
Registers
Table 20-3.
SCON Register
SCON (S:98h) – Serial Control Register
7
6
5
4
3
2
1
0
FE/SM0
OVR/SM1
SM2
REN
TB8
RB8
TI
RI
Bit Number
Bit
Mnemonic
Description
FE
7
Framing Error Bit
To select this function, set SMOD0 bit in PCON register.
Set by hardware to indicate an invalid stop bit.
Must be cleared by software.
SM0
Serial Port Mode Bit 0
Refer to Table 20-1 for mode selection.
SM1
Serial Port Mode Bit 1
Refer to Table 20-1 for mode selection.
5
SM2
Serial Port Mode Bit 2
Set to enable the multiprocessor communication and automatic address recognition
features.
Clear to disable the multiprocessor communication and automatic address recognition
features.
4
REN
Receiver Enable Bit
Set to enable reception.
Clear to disable reception.
3
TB8
Transmit Bit 8
Modes 0 and 1: Not used.
Modes 2 and 3: Software writes the ninth data bit to be transmitted to TB8.
2
RB8
Receiver Bit 8
Mode 0: Not used.
Mode 1 (SM2 cleared): Set or cleared by hardware to reflect the stop bit received.
Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth bit received.
1
TI
Transmit Interrupt Flag
Set by the transmitter after the last data bit is transmitted.
Must be cleared by software.
0
RI
Receive Interrupt Flag
Set by the receiver after the stop bit of a frame has been received.
Must be cleared by software.
6
Reset Value = 0000 0000b
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Table 20-4.
SBUF Register
SBUF (S:99h) – Serial Buffer Register
7
6
5
4
3
2
1
0
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
Bit Number
Bit
Mnemonic
Description
7-0
SD7:0
Serial Data Byte
Read the last data received by the serial I/O Port.
Write the data to be transmitted by the serial I/O Port.
Reset value = XXXX XXXXb
Table 20-5.
SADDR Register
SADDR (S:A9h) – Slave Individual Address Register
7
6
5
4
3
2
1
0
SAD7
SAD6
SAD5
SAD4
SAD3
SAD2
SAD1
SAD0
Bit Number
Bit
Mnemonic
Description
7-0
SAD7:0
Slave Individual Address
Reset Value = 0000 0000b
Table 20-6.
SADEN Register
SADEN (S:B9h) – Slave Individual Address Mask Byte Register
7
6
5
4
3
2
1
0
SAE7
SAE6
SAE5
SAE4
SAE3
SAE2
SAE1
SAE0
Bit Number
Bit
Mnemonic
Description
7-0
SAE7:0
Slave Address Mask Byte
Reset Value = 0000 0000b
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Table 20-7.
BDRCON Register
BDRCON (S:92h) – Baud Rate Generator Control Register
7
6
5
4
3
2
1
0
-
-
-
BRR
TBCK
RBCK
SPD
M0SRC
Bit Number
Bit
Mnemonic
Description
7-5
-
4
BRR
Baud Rate Run Bit
Set to enable the baud rate generator.
Clear to disable the baud rate generator.
3
TBCK
Transmission Baud Rate Selection Bit
Set to select the baud rate generator as transmission baud rate generator.
Clear to select the Timer 1 as transmission baud rate generator.
2
RBCK
Reception Baud Rate Selection Bit
Set to select the baud rate generator as reception baud rate generator.
Clear to select the Timer 1 as reception baud rate generator.
1
SPD
0
M0SRC
Reserved
The value read from these bits are indeterminate. Do not set these bits.
Baud Rate Speed Bit
Set to select high speed baud rate generation.
Clear to select low speed baud rate generation.
Mode 0 Baud Rate Source Bit
Set to select the variable baud rate generator in Mode 0.
Clear to select fixed baud rate in Mode 0.
Reset Value = XXX0 0000b
Table 20-8.
BRL Register
BRL (S:91h) – Baud Rate Generator Reload Register
7
6
5
4
3
2
1
0
BRL7
BRL6
BRL5
BRL4
BRL3
BRL2
BRL1
BRL0
Bit Number
Bit
Mnemonic
Description
7-0
BRL7:0
Baud Rate Reload Value
Reset Value = 0000 0000b
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AT8xC51SND2C/MP3B
21. Two-wire Interface (TWI) Controller
The AT8xC51SND2C implements a TWI controller supporting the four standard master and
slave modes with multimaster capability. Thus, it allows connection of slave devices like LCD
controller, audio DAC, etc., but also external master controlling where the AT8xC51SND2C is
used as a peripheral of a host.
The TWI bus is a bi-directional TWI serial communication standard. It is designed primarily for
simple but efficient integrated circuit control. The system is comprised of 2 lines, SCL (Serial
Clock) and SDA (Serial Data) that carry information between the ICs connected to them. The
serial data transfer is limited to 100 Kbit/s in low speed mode, however, some higher bit rates
can be achieved depending on the oscillator frequency. Various communication configurations
can be designed using this bus. Figure 21-1 shows a typical TWI bus configuration using the
AT8xC51SND2C in master and slave modes. All the devices connected to the bus can be master and slave.
Figure 21-1. Typical TWI Bus Configuration
AT8xC51SND2C
Master/Slave
LCD
Display
Rp
Audio
DAC
Rp
SCL
SDA
21.1
HOST
Microprocessor
SCL
SDA
Description
The CPU interfaces to the TWI logic via the following four 8-bit special function registers: the
Synchronous Serial Control register (SSCON SFR, see Table 21-9), the Synchronous Serial
Data register (SSDAT SFR, see Table 21-11), the Synchronous Serial Status register (SSSTA
SFR, see Table 21-10) and the Synchronous Serial Address register (SSADR SFR, see
Table 21-12).
SSCON is used to enable the controller, to program the bit rate (see Table 21-9), to enable slave
modes, to acknowledge or not a received data, to send a START or a STOP condition on the
TWI bus, and to acknowledge a serial interrupt. A hardware reset disables the TWI controller.
SSSTA contains a status code which reflects the status of the TWI logic and the TWI bus. The
three least significant bits are always zero. The five most significant bits contains the status
code. There are 26 possible status codes. When SSSTA contains F8h, no relevant state information is available and no serial interrupt is requested. A valid status code is available in SSSTA
after SSI is set by hardware and is still present until SSI has been reset by software. Table 21-2
to Table 21-6 give the status for both master and slave modes and miscellaneous states.
SSDAT contains a Byte of serial data to be transmitted or a Byte which has just been received. It
is addressable while it is not in process of shifting a Byte. This occurs when TWI logic is in a
defined state and the serial interrupt flag is set. Data in SSDAT remains stable as long as SSI is
set. While data is being shifted out, data on the bus is simultaneously shifted in; SSDAT always
contains the last Byte present on the bus.
SSADR may be loaded with the 7 - bit slave address (7 most significant bits) to which the controller will respond when programmed as a slave transmitter or receiver. The LSB is used to
enable general call address (00h) recognition.
Figure 21-2 shows how a data transfer is accomplished on the TWI bus.
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4341H–MP3–10/07
Figure 21-2. Complete Data Transfer on TWI Bus
SDA
MSB
Slave Address
SCL
1
R/W
ACK
direction signal
bit
from
receiver
2
8
Nth data Byte
9
S
1
2
ACK
signal
from
receiver
8
9
Clock Line Held Low While Serial Interrupts Are Serviced
P/S
The four operating modes are:
•
Master transmitter
•
Master receiver
•
Slave transmitter
•
Slave receiver
Data transfer in each mode of operation are shown in Figure 21-3 through Figure 21-6. These
figures contain the following abbreviations:
A
Acknowledge bit (low level at SDA)
A
Not acknowledge bit (high level on SDA)
Data
8-bit data Byte
S
START condition
P
STOP condition
MR
Master Receive
MT
Master Transmit
SLA
Slave Address
GCA
General Call Address (00h)
R
Read bit (high level at SDA)
W
Write bit (low level at SDA)
In Figure 21-3 through Figure 21-6, circles are used to indicate when the serial interrupt flag is
set. The numbers in the circles show the status code held in SSSTA. At these points, a service
routine must be executed to continue or complete the serial transfer. These service routines are
not critical since the serial transfer is suspended until the serial interrupt flag is cleared by
software.
When the serial interrupt routine is entered, the status code in SSSTA is used to branch to the
appropriate service routine. For each status code, the required software action and details of the
following serial transfer are given in Table 21-2 through Table 21-6.
21.1.1
Bit Rate
The bit rate can be selected from seven predefined bit rates or from a programmable bit rate
generator using the SSCR2, SSCR1, and SSCR0 control bits in SSCON (see Table 21-9). The
predefined bit rates are derived from the peripheral clock (FPER) issued from the Clock Controller
block as detailed in section "Oscillator", page 13, while bit rate generator is based on timer 1
overflow output.
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Table 21-1.
Serial Clock Rates
SSCRx
2
1
0
FPER = 6 MHz
FPER = 8 MHz
FPER = 10 MHz
FPER Divided By
0
0
0
47
62.5
78.125
128
0
0
1
53.5
71.5
89.3
112
0
1
0
62.5
83
104.2(1)
96
(1)
0
1
1
75
100
125
1
0
0
12.5
16.5
20.83
1
0
1
100
1
1
0
200(1)
1
1
Note:
21.1.2
Bit Frequency (kHz)
1
0.5 < ⋅ < 125
133.3
(1)
166.7
266.7(1)
(1)
0.67 < ⋅ < 166.7
80
480
(1)
60
333.3(1)
(1)
0.81 < ⋅ < 208.3
30
(1)
96 ⋅ (256 – reload value Timer 1)
1. These bit rates are outside of the low speed standard specification limited to 100 kHz but can
be used with high speed TWI components limited to 400 kHz.
Master Transmitter Mode
In the master transmitter mode, a number of data Bytes are transmitted to a slave receiver (see
Figure 21-3). Before the master transmitter mode can be entered, SSCON must be initialized as
follows:
SSCR2
SSPE
SSSTA
SSSTO
SSI
SSAA
SSCR1
SSCR0
Bit Rate
1
0
0
0
X
Bit Rate
Bit Rate
SSCR2:0 define the serial bit rate (see Table 21-1). SSPE must be set to enable the controller.
SSSTA, SSSTO and SSI must be cleared.
The master transmitter mode may now be entered by setting the SSSTA bit. The TWI logic will
now monitor the TWI bus and generate a START condition as soon as the bus becomes free.
When a START condition is transmitted, the serial interrupt flag (SSI bit in SSCON) is set, and
the status code in SSSTA is 08h. This status must be used to vector to an interrupt routine that
loads SSDAT with the slave address and the data direction bit (SLA+W). The serial interrupt flag
(SSI) must then be cleared before the serial transfer can continue.
When the slave address and the direction bit have been transmitted and an acknowledgment bit
has been received, SSI is set again and a number of status code in SSSTA are possible. There
are 18h, 20h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was
enabled (SSAA = logic 1). The appropriate action to be taken for each of these status code is
detailed in Table 21-2. This scheme is repeated until a STOP condition is transmitted.
SSPE and SSCR2:0 are not affected by the serial transfer and are not referred to in Table 21-2.
After a repeated START condition (state 10h) the controller may switch to the master receiver
mode by loading SSDAT with SLA+R.
21.1.3
Master Receiver Mode
In the master receiver mode, a number of data Bytes are received from a slave transmitter (see
Figure 21-4). The transfer is initialized as in the master transmitter mode. When the START condition has been transmitted, the interrupt routine must load SSDAT with the 7 - bit slave address
and the data direction bit (SLA+R). The serial interrupt flag (SSI) must then be cleared before
the serial transfer can continue.
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4341H–MP3–10/07
When the slave address and the direction bit have been transmitted and an acknowledgment bit
has been received, the serial interrupt flag is set again and a number of status code in SSSTA
are possible. There are 40h, 48h or 38h for the master mode and also 68h, 78h or B0h if the
slave mode was enabled (SSAA = logic 1). The appropriate action to be taken for each of these
status code is detailed in Table 21-6. This scheme is repeated until a STOP condition is
transmitted.
SSPE and SSCR2:0 are not affected by the serial transfer and are not referred to in Table 21-6.
After a repeated START condition (state 10h) the controller may switch to the master transmitter
mode by loading SSDAT with SLA+W.
21.1.4
Slave Receiver Mode
In the slave receiver mode, a number of data Bytes are received from a master transmitter (see
Figure 21-5). To initiate the slave receiver mode, SSADR and SSCON must be loaded as
follows:
SSA6
SSA5
SSA4
SSA3
SSA2
Own Slave Address
←
SSA1
SSA0
SSGC
→
X
The upper 7 bits are the addresses to which the controller will respond when addressed by a
master. If the LSB (SSGC) is set, the controller will respond to the general call address (00h);
otherwise, it ignores the general call address.
SSCR2
SSPE
SSSTA
SSSTO
SSI
SSAA
SSCR1
SSCR0
X
1
0
0
0
1
X
X
SSCR2:0 have no effect in the slave mode. SSPE must be set to enable the controller. The
SSAA bit must be set to enable the own slave address or the general call address acknowledgment. SSSTA, SSSTO and SSI must be cleared.
When SSADR and SSCON have been initialized, the controller waits until it is addressed by its
own slave address followed by the data direction bit which must be logic 0 (W) for operating in
the slave receiver mode. After its own slave address and the W bit has been received, the serial
interrupt flag is set and a valid status code can be read from SSSTA. This status code is used to
vector to an interrupt service routine, and the appropriate action to be taken for each of these
status code is detailed in Table 21-6 and Table 21-6. The slave receiver mode may also be
entered if arbitration is lost while the controller is in the master mode (see states 68h and 78h).
If the SSAA bit is reset during a transfer, the controller will return a not acknowledge (logic 1) to
SDA after the next received data Byte. While SSAA is reset, the controller does not respond to
its own slave address. However, the TWI bus is still monitored and address recognition may be
resumed at any time by setting SSAA. This means that the SSAA bit may be used to temporarily
isolate the controller from the TWI bus.
21.1.5
Slave Transmitter Mode
In the slave transmitter mode, a number of data Bytes are transmitted to a master receiver (see
Figure 21-6). Data transfer is initialized as in the slave receiver mode. When SSADR and
SSCON have been initialized, the controller waits until it is addressed by its own slave address
followed by the data direction bit which must be logic 1 (R) for operating in the slave transmitter
mode. After its own slave address and the R bit have been received, the serial interrupt flag is
set and a valid status code can be read from SSSTA. This status code is used to vector to an
interrupt service routine, and the appropriate action to be taken for each of these status code is
detailed in Table 21-6. The slave transmitter mode may also be entered if arbitration is lost while
the controller is in the master mode (see state B0h).
184
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
If the SSAA bit is reset during a transfer, the controller will transmit the last Byte of the transfer
and enter state C0h or C8h. The controller is switched to the not addressed slave mode and will
ignore the master receiver if it continues the transfer. Thus the master receiver receives all 1’s
as serial data. While SSAA is reset, the controller does not respond to its own slave address.
However, the TWI bus is still monitored and address recognition may be resumed at any time by
setting SSAA. This means that the SSAA bit may be used to temporarily isolate the controller
from the TWI bus.
21.1.6
Miscellaneous States
There are 2 SSSTA codes that do not correspond to a defined TWI hardware state (see
Table 21-7). These are discussed below.
Status F8h indicates that no relevant information is available because the serial interrupt flag is
not yet set. This occurs between other states and when the controller is not involved in a serial
transfer.
Status 00h indicates that a bus error has occurred during a serial transfer. A bus error is caused
when a START or a STOP condition occurs at an illegal position in the format frame. Examples
of such illegal positions are during the serial transfer of an address Byte, a data Byte, or an
acknowledge bit. When a bus error occurs, SSI is set. To recover from a bus error, the SSSTO
flag must be set and SSI must be cleared. This causes the controller to enter the not addressed
slave mode and to clear the SSSTO flag (no other bits in S1CON are affected). The SDA and
SCL lines are released and no STOP condition is transmitted.
Note:
The TWI controller interfaces to the external TWI bus via 2 port 1 pins: P1.6/SCL (serial clock line)
and P1.7/SDA (serial data line). To avoid low level asserting and conflict on these lines when the
TWI controller is enabled, the output latches of P1.6 and P1.7 must be set to logic 1.
185
4341H–MP3–10/07
Figure 21-3. Format and States in the Master Transmitter Mode
MT
Successful transmission to a slave receiver
S
SLA
W
A
08h
Data
18h
A
P
28h
Next transfer started with
a repeated start condition
S
SLA
W
10h
R
Not acknowledge received
after the slave address
A
P
MR
20h
Not acknowledge received
after a data Byte
A
P
30h
Arbitration lost in slave
address or data Byte
A or A
Other master
continues
38h
Arbitration lost and
addressed as slave
A
Data
From slave to master
186
nnh
Other master
continues
38h
Other master
continues
68h 78h B0h
From master to slave
A or A
A
To corresponding
states in slave mode
Any number of data Bytes and their associated
acknowledge bits
This number (contained in SSSTA) corresponds
to a defined state of the TWI bus
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Figure 21-4. Format and States in the Master Receiver Mode
MR
Successful reception
from a slave transmitter
S
SLA
08h
R
A
Data
A
40h
50h
Data
A
P
58h
Next transfer started with
a repeated start condition
S
SLA
R
10h
W
Not acknowledge received
after the slave address
A
P
MT
48h
Arbitration lost in slave
address or data Byte
A or A
Other master
continues
38h
Arbitration lost and
addressed as slave
A
From slave to master
Data
nnh
Other master
continues
38h
Other master
continues
68h 78h B0h
From master to slave
A
A
To corresponding
states in slave mode
Any number of data Bytes and their associated
acknowledge bits
This number (contained in SSSTA) corresponds
to a defined state of the TWI bus
187
4341H–MP3–10/07
Figure 21-5. Format and States in the Slave Receiver Mode
Reception of the own slave
address and one or more
data Bytes.
All are acknowledged
S
SLA
W
A
Data
60h
A
Data
80h
Last data Byte received
is not acknowledged
A
P or S
80h
A0h
A
P or S
88h
Arbitration lost as master and
addressed as slave
A
68h
Reception of the general call
address and one or more data Bytes
General Call
A
Data
70h
Last data Byte received
is not acknowledged
A
90h
Data
A
P or S
90h
A0h
A
P or S
98h
Arbitration lost as master and
addressed as slave by general call
A
78h
From master to slave
From slave to master
188
Data
nnh
A
Any number of data Bytes and their associated
acknowledge bits
This number (contained in SSSTA) corresponds
to a defined state of the TWI bus
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Figure 21-6. Format and States in the Slave Transmitter Mode
Reception of the own slave
address and transmission
of one or more data Bytes.
S
SLA
R
A
Data
A8h
Arbitration lost as master and
addressed as slave
A
B8h
Data
A
P or S
C0h
A
B0h
Last data Byte transmitted.
Switched to not addressed
slave (SSAA = 0).
A
All 1’s
P or S
C8h
From master to slave
From slave to master
Data
nnh
A
Any number of data Bytes and their associated
acknowledge bits
This number (contained in SSSTA) corresponds
to a defined state of the TWI bus
189
4341H–MP3–10/07
Table 21-2.
Status for Master Transmitter Mode
Application Software Response
Status
Code
SSSTA
To SSCON
Status of the TWI Bus
and TWI Hardware
To/From SSDAT
SSSTA
SSSTO
SSI
SSAA
Next Action Taken by TWI Hardware
08h
A START condition has
Write SLA+W
been transmitted
X
0
0
X
Write SLA+W
X
0
0
X
10h
A repeated START
condition has been
transmitted
Write SLA+R
X
0
0
X
Write data Byte
0
0
0
X
No SSDAT action
1
0
0
X
No SSDAT action
0
1
0
X
STOP condition will be transmitted and SSSTO flag
will be reset.
No SSDAT action
1
1
0
X
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Write data Byte
0
0
0
X
No SSDAT action
1
0
0
X
No SSDAT action
0
1
0
X
STOP condition will be transmitted and SSSTO flag
will be reset.
No SSDAT action
1
1
0
X
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Write data Byte
0
0
0
X
No SSDAT action
1
0
0
X
No SSDAT action
0
1
0
X
STOP condition will be transmitted and SSSTO flag
will be reset.
No SSDAT action
1
1
0
X
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Write data Byte
0
0
0
X
No SSDAT action
1
0
0
X
No SSDAT action
0
1
0
X
STOP condition will be transmitted and SSSTO flag
will be reset.
No SSDAT action
1
1
0
X
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
No SSDAT action
0
0
0
X
TWI bus will be released and not addressed slave
mode will be entered.
No SSDAT action
1
0
0
X
A START condition will be transmitted when the bus
becomes free.
18h
20h
28h
30h
38h
190
SLA+W has been
transmitted; ACK has
been received
SLA+W has been
transmitted; NOT ACK
has been received
Data Byte has been
transmitted; ACK has
been received
Data Byte has been
transmitted; NOT ACK
has been received
Arbitration lost in
SLA+W or data Bytes
SLA+W will be transmitted.
SLA+W will be transmitted.
SLA+R will be transmitted.
Logic will switch to master receiver mode
Data Byte will be transmitted.
Repeated START will be transmitted.
Data Byte will be transmitted.
Repeated START will be transmitted.
Data Byte will be transmitted.
Repeated START will be transmitted.
Data Byte will be transmitted.
Repeated START will be transmitted.
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 21-3.
Status for Master Receiver Mode
Application Software Response
Status
Code
SSSTA
To SSCON
Status of the TWI Bus
and TWI Hardware
To/From SSDAT
SSSTA
SSSTO
SSI
SSAA
Next Action Taken by TWI Hardware
08h
A START condition has
Write SLA+R
been transmitted
X
0
0
X
Write SLA+R
X
0
0
X
10h
A repeated START
condition has been
transmitted
Write SLA+W
X
0
0
X
SLA+W will be transmitted.
Logic will switch to master transmitter mode.
Arbitration lost in
SLA+R or NOT ACK
bit
No SSDAT action
0
0
0
X
TWI bus will be released and not addressed slave
mode will be entered.
No SSDAT action
1
0
0
X
A START condition will be transmitted when the bus
becomes free.
SLA+R has been
transmitted; ACK has
been received
No SSDAT action
0
0
0
0
Data Byte will be received and NOT ACK will be
returned.
No SSDAT action
0
0
0
1
Data Byte will be received and ACK will be returned.
No SSDAT action
1
0
0
X
No SSDAT action
0
1
0
X
STOP condition will be transmitted and SSSTO flag
will be reset.
No SSDAT action
1
1
0
X
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Read data Byte
0
0
0
0
Data Byte will be received and NOT ACK will be
returned.
Read data Byte
0
0
0
1
Data Byte will be received and ACK will be returned.
Read data Byte
1
0
0
X
Read data Byte
0
1
0
X
STOP condition will be transmitted and SSSTO flag
will be reset.
Read data Byte
1
1
0
X
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
38h
40h
48h
50h
58h
SLA+R has been
transmitted; NOT ACK
has been received
Data Byte has been
received; ACK has
been returned
Data Byte has been
received; NOT ACK
has been returned
SLA+R will be transmitted.
SLA+R will be transmitted.
Repeated START will be transmitted.
Repeated START will be transmitted.
191
4341H–MP3–10/07
Table 21-4.
Status for Slave Receiver Mode with Own Slave Address
Application Software Response
Status
Code
SSSTA
60h
68h
80h
88h
To SSCON
Status of the TWI Bus
and TWI Hardware
To/From SSDAT
Own SLA+W has been
received; ACK has
been returned
Arbitration lost in
SLA+R/W as master;
own SLA+W has been
received; ACK has
been returned
Previously addressed
with own SLA+W; data
has been received;
ACK has been
returned
Previously addressed
with own SLA+W; data
has been received;
NOT ACK has been
returned
SSSTA
SSSTO
SSI
SSAA
No SSDAT action
X
0
0
0
Data Byte will be received and NOT ACK will be
returned.
No SSDAT action
X
0
0
1
Data Byte will be received and ACK will be returned.
No SSDAT action
X
0
0
0
Data Byte will be received and NOT ACK will be
returned.
No SSDAT action
X
0
0
1
Data Byte will be received and ACK will be returned.
Read data Byte
X
0
0
0
Data Byte will be received and NOT ACK will be
returned.
Read data Byte
X
0
0
1
Data Byte will be received and ACK will be returned.
Read data Byte
0
0
0
0
Read data Byte
0
0
0
1
Read data Byte
Read data Byte
A0h
A STOP condition or
repeated START
condition has been
received while still
addressed as slave
1
0
0
0
0
0
1
No SSDAT action
0
0
0
0
No SSDAT action
0
0
0
1
No SSDAT action
No SSDAT action
192
1
1
1
0
0
0
0
0
1
Next Action Taken by TWI Hardware
Switched to the not addressed slave mode; no
recognition of own SLA or GCA.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START condition
will be transmitted when the bus becomes free.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1. A START condition will be
transmitted when the bus becomes free.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START condition
will be transmitted when the bus becomes free.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1. A START condition will be
transmitted when the bus becomes free.
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 21-5.
Status for Slave Receiver Mode with General Call Address
Application Software Response
Status
Code
SSSTA
70h
78h
90h
98h
To SSCON
Status of the TWI Bus
and TWI Hardware
To/From SSDAT
General call address
has been received;
ACK has been
returned
Arbitration lost in
SLA+R/W as master;
general call address
has been received;
ACK has been
returned
Previously addressed
with general call; data
has been received;
ACK has been
returned
Previously addressed
with general call; data
has been received;
NOT ACK has been
returned
SSSTA
SSSTO
SSI
SSAA
No SSDAT action
X
0
0
0
Data Byte will be received and NOT ACK will be
returned.
No SSDAT action
X
0
0
1
Data Byte will be received and ACK will be returned.
No SSDAT action
X
0
0
0
Data Byte will be received and NOT ACK will be
returned.
No SSDAT action
X
0
0
1
Data Byte will be received and ACK will be returned.
Read data Byte
X
0
0
0
Data Byte will be received and NOT ACK will be
returned.
Read data Byte
X
0
0
1
Data Byte will be received and ACK will be returned.
Read data Byte
0
0
0
0
Read data Byte
0
0
0
1
Read data Byte
Read data Byte
A0h
A STOP condition or
repeated START
condition has been
received while still
addressed as slave
1
1
0
0
0
0
0
1
No SSDAT action
0
0
0
0
No SSDAT action
0
0
0
1
No SSDAT action
No SSDAT action
1
1
0
0
0
0
0
1
Next Action Taken by TWI Hardware
Switched to the not addressed slave mode; no
recognition of own SLA or GCA.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START condition
will be transmitted when the bus becomes free.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1. A START condition will be
transmitted when the bus becomes free.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START condition
will be transmitted when the bus becomes free.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1. A START condition will be
transmitted when the bus becomes free.
193
4341H–MP3–10/07
Table 21-6.
Status for Slave Transmitter Mode
Application Software Response
Status
Code
SSSTA
A8h
B0h
B8h
C0h
Status of the TWI Bus
and TWI Hardware
To SSCON
To/From SSDAT
Own SLA+R has been
received; ACK has
been returned
Arbitration lost in
SLA+R/W as master;
own SLA+R has been
received; ACK has
been returned
Data Byte in SSDAT
has been transmitted;
ACK has been
received
Data Byte in SSDAT
has been transmitted;
NOT ACK has been
received
SSSTA
SSSTO
SSI
SSAA
Write data Byte
X
0
0
0
Last data Byte will be transmitted.
Write data Byte
X
0
0
1
Data Byte will be transmitted.
Write data Byte
X
0
0
0
Last data Byte will be transmitted.
Write data Byte
X
0
0
1
Data Byte will be transmitted.
Write data Byte
X
0
0
0
Last data Byte will be transmitted.
Write data Byte
X
0
0
1
Data Byte will be transmitted.
No SSDAT action
0
0
0
0
No SSDAT action
0
0
0
1
No SSDAT action
No SSDAT action
C8h
Last data Byte in
SSDAT has been
transmitted
(SSAA= 0); ACK has
been received
1
0
0
0
0
0
1
No SSDAT action
0
0
0
0
No SSDAT action
0
0
0
1
No SSDAT action
No SSDAT action
Table 21-7.
1
1
1
0
0
0
0
0
1
Next Action Taken by TWI Hardware
Switched to the not addressed slave mode; no
recognition of own SLA or GCA.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START condition
will be transmitted when the bus becomes free.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1. A START condition will be
transmitted when the bus becomes free.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START condition
will be transmitted when the bus becomes free.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1. A START condition will be
transmitted when the bus becomes free.
Status for Miscellaneous States
Application Software Response
Status
Code
SSSTA
To SSCON
Status of the TWI Bus
and TWI Hardware
To/From SSDAT
F8h
No relevant state
information available;
SSI = 0
No SSDAT action
00h
Bus error due to an
illegal START or STOP
condition
No SSDAT action
194
SSSTA
SSSTO
SSI
SSAA
No SSCON action
0
1
0
Next Action Taken by TWI Hardware
Wait or proceed current transfer.
X
Only the internal hardware is affected, no STOP
condition is sent on the bus. In all cases, the bus is
released and SSSTO is reset.
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
21.2
Registers
Table 21-8.
AUXCON Register
AUXCON (S:90h) – Auxiliary Control Register
7
6
5
4
3
2
1
0
SDA
SCL
-
AUDCDOUT
AUDCDIN
AUDCCLK
AUDCCS
KIN0
Bit
Number
Bit Mnemonic
7
SDA
Description
TWI Serial Data
SDA is the bidirectional Two Wire data line.
6
SCL
Audio DAC Control
5:1
0
TWI Serial Clock
When TWI controller is in master mode, SCL outputs the serial clock to the slave
peripherals. When TWI controller is in slave mode, SCL receives clock from the master
controller.
Refer to Audio DAC interface section
KIN0
Keyboard Input Line
Reset Value = 1111 1111b
195
4341H–MP3–10/07
Table 21-9.
SSCON Register
SSCON (S:93h) – Synchronous Serial Control Register
7
6
5
4
3
2
1
0
SSCR2
SSPE
SSSTA
SSSTO
SSI
SSAA
SSCR1
SSCR0
Bit Number
Bit
Mnemonic
Description
7
SSCR2
6
SSPE
Synchronous Serial Peripheral Enable Bit
Set to enable the controller.
Clear to disable the controller.
5
SSSTA
Synchronous Serial Start Flag
Set to send a START condition on the bus.
Clear not to send a START condition on the bus.
4
SSSTO
Synchronous Serial Stop Flag
Set to send a STOP condition on the bus.
Clear not to send a STOP condition on the bus.
3
SSI
Synchronous Serial Control Rate Bit 2
Refer to Table 21-1 for rate description.
Synchronous Serial Interrupt Flag
Set by hardware when a serial interrupt is requested.
Must be cleared by software to acknowledge interrupt.
Synchronous Serial Assert Acknowledge Flag
Set to enable slave modes. Slave modes are entered when SLA or GCA (if SSGC set) is
recognized.
Clear to disable slave modes.
Master Receiver Mode in progress
Clear to force a not acknowledge (high level on SDA).
Set to force an acknowledge (low level on SDA).
Master Transmitter Mode in progress
This bit has no specific effect when in master transmitter mode.
Slave Receiver Mode in progress
Clear to force a not acknowledge (high level on SDA).
Set to force an acknowledge (low level on SDA).
Slave Transmitter Mode in progress
Clear to isolate slave from the bus after last data Byte transmission.
Set to enable slave mode.
2
SSAA
1
SSCR1
Synchronous Serial Control Rate Bit 1
Refer to Table 21-1 for rate description.
0
SSCR0
Synchronous Serial Control Rate Bit 0
Refer to Table 21-1 for rate description.
Reset Value = 0000 0000b
196
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 21-10. SSSTA Register
SSSTA (S:94h) – Synchronous Serial Status Register
7
6
5
4
3
2
1
0
SSC4
SSC3
SSC2
SSC1
SSC0
0
0
0
Bit Number
Bit
Mnemonic
Description
7:3
SSC4:0
2:0
0
Synchronous Serial Status Code Bits 0 to 4
Refer to Table 21-2 to Table 21-6 for status description.
Always 0.
Reset Value = F8h
Table 21-11. SSDAT Register
SSDAT (S:95h) – Synchronous Serial Data Register
7
6
5
4
3
2
1
0
SSD7
SSD6
SSD5
SSD4
SSD3
SSD2
SSD1
SSD0
Bit Number
Bit
Mnemonic
Description
7:1
SSD7:1
0
SSD0
Synchronous Serial Address bits 7 to 1 or Synchronous Serial Data Bits 7 to 1
Synchronous Serial Address bit 0 (R/W) or Synchronous Serial Data Bit 0
Reset Value = 1111 1111b
Table 21-12. SSADR Register
SSADR (S:96h) – Synchronous Serial Address Register
7
6
5
4
3
2
1
0
SSA7
SSA6
SSA5
SSA4
SSA3
SSA2
SSA1
SSGC
Bit Number
Bit
Mnemonic
Description
7:1
SSA7:1
Synchronous Serial Slave Address Bits 7 to 1
0
SSGC
Synchronous Serial General Call Bit
Set to enable the general call address recognition.
Clear to disable the general call address recognition.
Reset Value = 1111 1110b
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AT8xC51SND2C/MP3B
22. Analog to Digital Converter
The AT8XSND2CMP3B implement a 2-channel 10-bit (8 true bits) analog to digital converter
(ADC). First channel of this ADC can be used for battery monitoring while the second one can
be used for voice sampling at 8 kHz.
The AT8xC51SND2C does not include the A/D converter.
22.1
Description
The A/D converter interfaces with the C51 core through four special function registers: ADCON,
the ADC control register (see Table 3); ADDH and ADDL, the ADC data registers (see Table 5
and Table 6); and ADCLK, the ADC clock register (see Table 4).
As shown in Figure 22-1, the ADC is composed of a 10-bit cascaded potentiometric digital to
analog converter, connected to the negative input of a comparator. The output voltage of this
DAC is compared to the analog voltage stored in the Sample and Hold and coming from AIN0 or
AIN1 input depending on the channel selected (see Table 2). The 10-bit ADDAT converted
value (see formula in Figure 22-1) is delivered in ADDH and ADDL registers, ADDH is giving the
8 most significant bits while ADDL is giving the 2 least significant bits.
Figure 22-1. ADC Structure
ADCON.5
ADCON.3
ADEN
ADSST
ADC
Interrupt
Request
ADCON.4
ADEOC
ADC
CLOCK
CONTROL
EADC
IEN1.3
AIN1
0
AIN0
1
8
ADDH
2
ADDL
+
SAR
AVSS
ADCS
Sample and Hold
10
ADCON.0
R/2R DAC
1023 ⋅ V IN
ADDAT = -------------------------V REF
AREFP AREFN
Figure 22-2 shows the timing diagram of a complete conversion. For simplicity, the figure depicts
the waveforms in idealized form and do not provide precise timing information. For ADC characteristics and timing parameters refer to the section “AC Characteristics”.
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4341H–MP3–10/07
Figure 22-2. Timing Diagram
CLK
TADCLK
ADEN
TSETUP
ADSST
TCONV
ADEOC
22.1.1
Clock Generator
The ADC clock is generated by division of the peripheral clock (see details in section “X2 Feature”, page 14). The division factor is then given by ADCP4:0 bits in ADCLK register. Figure 223 shows the ADC clock generator and its calculation formula(1).
Figure 22-3. ADC Clock Generator and Symbol Caution:
ADCLK
PER
CLOCK
÷2
ADCD4:0
ADC
CLOCK
ADC Clock
ADC Clock Symbol
PERclk
ADCclk = ------------------------2 ⋅ ADCD
Note:
1. In all cases, the ADC clock frequency may be higher than the maximum FADCLK parameter
reported in the section “Analog to Digital Converter”, page 202.
2. The ADCD value of 0 is equivalent to an ADCD value of 32.
22.1.2
Channel Selection
The channel on which conversion is performed is selected by the ADCS bit in ADCON register
according to Table 2.
Table 2. ADC Channel Selection
22.1.3
ADCS
Channel
0
AIN1
1
AIN0
Conversion Precision
The 10-bit precision conversion is achieved by stopping the CPU core activity during conversion
for limiting the digital noise induced by the core. This mode called the Pseudo-Idle mode(1),(2) is
enabled by setting the ADIDL bit in ADCON register(3). Thus, when conversion is launched (see
Section "Conversion Launching", page 201), the CPU core is stopped until the end of the con-
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AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
version (see Section "End Of Conversion", page 201). This bit is cleared by hardware at the end
of the conversion.
Notes:
22.1.4
1. Only the CPU activity is frozen, peripherals are not affected by the Pseudo-Idle mode.
2. If some interrupts occur during the Pseudo-Idle mode, they will be delayed and processed,
according to their priority after the end of the conversion.
3. Concurrently with ADSST bit.
Configuration
The ADC configuration consists in programming the ADC clock as detailed in the Section "Clock
Generator", page 200. The ADC is enabled using the ADEN bit in ADCON register. As shown in
Figure 93, user must wait the setup time (TSETUP) before launching any conversion.
Figure 22-4. ADC Configuration Flow
ADC
Configuration
Program ADC Clock
ADCD4:0 = xxxxxb
Enable ADC
ADIDL = x
ADEN = 1
Wait Setup Time
22.1.5
Conversion Launching
The conversion is launched by setting the ADSST bit in ADCON register, this bit remains set
during the conversion. As soon as the conversion is started, it takes 11 clock periods (TCONV)
before the data is available in ADDH and ADDL registers.
Figure 22-5. ADC Conversion Launching Flow
ADC
Conversion Start
Select Channel
ADCS = 0-1
Start Conversion
ADSST = 1
22.1.6
End Of Conversion
The end of conversion is signalled by the ADEOC flag in ADCON register becoming set or by the
ADSST bit in ADCON register becoming cleared. ADEOC flag can generate an interrupt if
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4341H–MP3–10/07
enabled by setting EADC bit in IEN1 register. This flag is set by hardware and must be reset by
software.
22.2
Registers
Table 3. ADCON Register
ADCON (S:F3h) – ADC Control Register
7
6
5
4
3
2
1
0
-
ADIDL
ADEN
ADEOC
ADSST
-
-
ADCS
Bit Number
Bit
Mnemonic
Description
7
-
6
ADIDL
ADC Pseudo-Idle Mode
Set to suspend the CPU core activity (pseudo-idle mode) during conversion.
Clear by hardware at the end of conversion.
5
ADEN
ADC Enable Bit
Set to enable the A to D converter.
Clear to disable the A to D converter and put it in low power stand by mode.
Reserved
The value read from this bit is always 0. Do not set this bit.
4
ADEOC
End Of Conversion Flag
Set by hardware when ADC result is ready to be read. This flag can generate an
interrupt.
Must be cleared by software.
3
ADSST
Start and Status Bit
Set to start an A to D conversion on the selected channel.
Cleared by hardware at the end of conversion.
2-1
-
0
ADCS
Reserved
The value read from these bits is always 0. Do not set these bits.
Channel Selection Bit
Set to select channel 0 for conversion.
Clear to select channel 1 for conversion.
Reset Value = 0000 0000b
Table 4. ADCLK Register
ADCLK (S:F2h) – ADC Clock Divider Register
7
6
5
4
3
2
1
0
-
-
-
ADCD4
ADCD3
ADCD2
ADCD1
ADCD0
Bit Number
Bit
Mnemonic
Description
7-5
-
4-0
ADCD4:0
Reserved
The value read from these bits is always 0. Do not set these bits.
ADC Clock Divider
5-bit divider for ADC clock generation.
Reset Value = 0000 0000b
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AT8xC51SND2C/MP3B
Table 5. ADDH Register
ADDH (S:F5h Read Only) – ADC Data High Byte Register
7
6
5
4
3
2
1
0
ADAT9
ADAT8
ADAT7
ADAT6
ADAT5
ADAT4
ADAT3
ADAT2
Bit Number
Bit
Mnemonic
Description
7-0
ADAT9:2
ADC Data
8 Most Significant Bits of the 10-bit ADC data.
Reset Value = 0000 0000b
Table 6. ADDL Register
ADDL (S:F4h Read Only) – ADC Data Low Byte Register
7
6
5
4
3
2
1
0
-
-
-
-
-
-
ADAT1
ADAT0
Bit Number
Bit
Mnemonic
Description
7-2
-
1-0
ADAT1:0
Reserved
The value read from these bits is always 0. Do not set these bits.
ADC Data
2 Least Significant Bits of the 10-bit ADC data.
Reset Value = 0000 0000b
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23. Keyboard Interface
The AT8xC51SND2C implement a keyboard interface allowing the connection of a keypad. It is
based on one input with programmable interrupt capability on both high or low level. This input
allows exit from idle and power down modes.
23.1
Description
The keyboard interfaces with the C51 core through 2 special function registers: KBCON, the
keyboard control register (see Table 23-2); and KBSTA, the keyboard control and status register
(see Table 23-3).
An interrupt enable bit (EKB in IEN1 register) allows global enable or disable of the keyboard
interrupt (see Figure 23-1). As detailed in Figure 23-2 this keyboard input has the capability to
detect a programmable level according to KINL0 bit value in KBCON register. Level detection is
then reported in interrupt flag KINF0 in KBSTA register.
A keyboard interrupt is requested each time this flag is set. This flag can be masked by software
using KINM0 bits in KBCON register and is cleared by reading KBSTA register.
Figure 23-1. Keyboard Interface Block Diagram
KIN0
Keyboard Interface
Interrupt Request
Input Circuitry
EKB
IEN1.4
Figure 23-2. Keyboard Input Circuitry
0
KIN0
KINF0
1
KBSTA.0
KINM0
KINL0
KBCON.0
KBCON.4
23.1.1
Power Reduction Mode
KIN0 inputs allow exit from idle and power-down modes as detailed in section “Power Management”, page 47. To enable this feature, KPDE bit in KBSTA register must be set to logic 1.
Due to the asynchronous keypad detection in power down mode (all clocks are stopped), exit
may happen on parasitic key press. In this case, no key is detected and software must enter
power down again.
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AT8xC51SND2C/MP3B
23.2
Registers
Table 23-1.
AUXCON Register
AUXCON (S:90h) – Auxiliary Control Register
7
6
5
4
3
2
1
0
SDA
SCL
-
AUDCDOUT
AUDCDIN
AUDCCLK
AUDCCS
KIN0
Bit
Number
Bit Mnemonic
Description
TWI Lines
7:6
Refer to TWI section.
Audio DAC Control
5:1
0
Refer to Audio DAC section.
KIN0
Keyboard Input Interrupt.
Reset Value = 1111 1111b
Table 23-2.
KBCON Register
KBCON (S:A3h) – Keyboard Control Register
7
6
5
4
3
2
1
0
-
-
-
KINL0
-
-
-
KINM0
Bit Number
Bit
Mnemonic
Description
7-5
-
4
KINL0
3-1
-
0
KINM0
Reserved
Do not set these bits.
Keyboard Input Level Bit
Set to enable a high level detection on the respective KIN0 input.
Clear to enable a low level detection on the respective KIN0 input.
Reserved
Do not reset these bits.
Keyboard Input Mask Bit
Set to prevent the KINF0 flag from generating a keyboard interrupt.
Clear to allow the KINF0 flag to generate a keyboard interrupt.
Reset Value = 0000 1111b
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Table 23-3.
KBSTA Register
KBSTA (S:A4h) – Keyboard Control and Status Register
7
6
5
4
3
2
1
0
KPDE
-
-
-
-
-
-
KINF0
Bit Number
Bit
Mnemonic
Description
7
KPDE
6-1
-
0
KINF0
Keyboard Power Down Enable Bit
Set to enable exit of power down mode by the keyboard interrupt.
Clear to disable exit of power down mode by the keyboard interrupt.
Reserved
The value read from these bits is always 0. Do not set these bits.
Keyboard Input Interrupt Flag
Set by hardware when the KIN0 input detects a programmed level.
Cleared when reading KBSTA.
Reset Value = 0000 0000b
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AT8xC51SND2C/MP3B
24. Electrical Characteristics
24.1
Absolute Maximum Rating
Storage Temperature ......................................... -65 to +150°C
Voltage on any other Pin to VSS
.................................... -0.3
*NOTICE:
to +4.0 V
IOL per I/O Pin ................................................................. 5 mA
Power Dissipation ............................................................. 1 W
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond
the “operating conditions” is not recommended
and extended exposure beyond the “Operating
Conditions” may affect device reliability.
Operating Conditions
Ambient Temperature Under Bias........................ -40 to +85°C
VDD ......................................................................................................... 2.7 to 3.3V
24.2
DC Characteristics
24.2.1
Digital Logic
Table 24-1.
Symbol
VIL
VIH1
(2)
Digital DC Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Parameter
Min
Input Low Voltage
Input High Voltage (except RST, X1)
Typ(1)
Max
Units
-0.5
0.2·VDD - 0.1
V
0.2·VDD + 1.1
VDD
V
0.7·VDD
VDD + 0.5
V
Test Conditions
VIH2
Input High Voltage (RST, X1)
VOL1
Output Low Voltage
(except P0, ALE, MCMD, MDAT, MCLK,
SCLK, DCLK, DSEL, DOUT)
0.45
V
IOL= 1.6 mA
VOL2
Output Low Voltage
(P0, ALE, MCMD, MDAT, MCLK, SCLK,
DCLK, DSEL, DOUT)
0.45
V
IOL= 3.2 mA
VOH1
Output High Voltage
(P1, P2, P3, P4 and P5)
VDD - 0.7
V
IOH= -30 µA
VOH2
Output High Voltage
(P0, P2 address mode, ALE, MCMD,
MDAT, MCLK, SCLK, DCLK, DSEL,
DOUT, D+, D-)
VDD - 0.7
V
IOH= -3.2 mA
IIL
Logical 0 Input Current (P1, P2, P3, P4
and P5)
-50
µA
VIN= 0.45 V
ILI
Input Leakage Current (P0, ALE, MCMD,
MDAT, MCLK, SCLK, DCLK, DSEL,
DOUT)
10
µA
0.45< VIN< VDD
ITL
Logical 1 to 0 Transition Current
(P1, P2, P3, P4 and P5)
-650
µA
VIN= 2.0 V
200
kΩ
RRST
CIO
VRET
Pull-Down Resistor
Pin Capacitance
VDD Data Retention Limit
50
90
10
pF
1.8
TA= 25°C
V
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4341H–MP3–10/07
Table 24-1.
Symbol
Digital DC Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Parameter
Min
AT89C51SND2C
Operating Current
Typ(1)
Max
(3)
X1 / X2 mode
7/ 11.5
9/ 14.5
10.5 / 18
Units
VDD < 3.3 V
mA
IDD
X1 / X2 mode
7/ 11.5
9/ 14.5
10.5 / 18
AT83SND2C
Operating Current
AT89C51SND2C
(3)
Idle Mode Current
X1 / X2 mode
6.3 / 9.1
7.4 / 11.3
8.5 / 14
Test Conditions
12 MHz
16 MHz
20 MHz
VDD < 3.3 V
mA
12 MHz
16 MHz
20 MHz
VDD < 3.3 V
mA
12 MHz
16 MHz
20 MHz
IDL
AT83SND2C
Idle Mode Current
VDD < 3.3 V
X1 / X2 mode
6.3 / 9.1
7.4 / 11.3
8.5 / 14
mA
12 MHz
16 MHz
20 MHz
AT89C51SND2C
Power-Down Mode Current
20
500
µA
VRET < VDD < 3.3 V
AT83SND2C
Power-Down Mode Current
20
500
µA
VRET < VDD < 3.3 V
+15
mA
VDD < 3.3 V
IPD
IFP
AT89C51SND2C
Flash Programming Current
Notes:
1. Typical values are obtained using VDD= 3 V and TA= 25°C. They are not tested and there is no
guarantee on these values.
2. Flash retention is guaranteed with the same formula for VDD min down to 0V.
3. See Table 24-2 for typical consumption in player mode.
Table 24-2.
Typical Reference Design AT89C51SND2C Power Consumption
Player Mode
IDD
Stop
10 mA
Test Conditions
AT89C51SND2C at 16 MHz, X2 mode, VDD= 3 V
No song playing.
This consumption does not include AUDVBAT current.
Playing
37 mA
AT89C51SND2C at 16 MHz, X2 mode, VDD= 3 V
MP3 Song with Fs= 44.1 KHz, at any bit rates (Variable Bit Rate)
This consumption does not include AUDVBAT current.
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AT8xC51SND2C/MP3B
24.2.1.1
IDD, IDL and IPD Test Conditions
Figure 24-1. IDD Test Condition, Active Mode
VDD
VDD
RST
(NC)
Clock Signal
VDD
PVDD
UVDD
AUDVDD
X2
X1
IDD
VDD
P0
VSS
PVSS
UVSS
AUDVSS
VSS
TST
All other pins are unconnected
Figure 24-2. IDL Test Condition, Idle Mode
VDD
RST
VSS
(NC)
Clock Signal
VDD
PVDD
UVDD
AUDVDD
X2
X1
IDL
VDD
P0
VSS
PVSS
UVSS
AUDVSS
VSS
TST
All other pins are unconnected
Figure 24-3. IPD Test Condition, Power-Down Mode
VDD
RST
VSS
(NC)
X2
X1
VSS
PVSS
UVSS
AUDVSS
VSS
VDD
PVDD
UVDD
AUDVDD
IPD
VDD
P0
MCMD
MDAT
TST
All other pins are unconnected
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24.2.2
24.2.2.1
Oscillator & Crystal
Schematic
Figure 24-4. Crystal Connection
X1
C1
Q
C2
VSS
Note:
24.2.2.2
X2
For operation with most standard crystals, no external components are needed on X1 and X2. It
may be necessary to add external capacitors on X1 and X2 to ground in special cases (max 10
pF). X1 and X2 may not be used to drive other circuits.
Parameters
Table 24-3.
Oscillator & Crystal Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
24.2.3.1
Min
Typ
Max
Unit
CX1
Internal Capacitance (X1 - VSS)
10
pF
CX2
Internal Capacitance (X2 - VSS)
10
pF
CL
Equivalent Load Capacitance (X1 - X2)
5
pF
DL
Drive Level
50
µW
Crystal Frequency
20
MHz
RS
Crystal Series Resistance
40
Ω
CS
Crystal Shunt Capacitance
6
pF
F
24.2.3
Parameter
Phase Lock Loop
Schematic
Figure 24-5. PLL Filter Connection
FILT
R
C2
C1
VSS
24.2.3.2
Parameters
Table 24-4.
210
VSS
PLL Filter Characteristics
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
24.2.4
24.2.4.1
Parameter
Min
Typ
Max
Unit
R
Filter Resistor
100
Ω
C1
Filter Capacitance 1
10
nF
C2
Filter Capacitance 2
2.2
nF
USB Connection
Schematic
Figure 24-6. USB Connection
VDD
VBUS
To Power
Supply
D+
RFS
D+
RUSB
D-
D-
RUSB
GND
VSS
24.2.4.2
Parameters
Table 24-5.
USB Termination Characteristics
VDD = 3 to 3.3 V, TA = -40 to +85°C
Symbol
Parameter
Typ
Max
Unit
RUSB
USB Termination Resistor
27
Ω
RFS
USB Full Speed Resistor
1.5
KΩ
24.2.5
DAC and PA
24.2.6
Electrical Specifications
24.2.6.1
Min
PA
AUDVBAT = 3.6V, TA = 25°C unless otherwise noted.
High power mode, 100nF capacitor connected between CBP and AUDVSS, 470nF input capacitors, Load = 8 ohms.
Figure 24-7. PA Specification
Symbol
Parameter
Conditions
AUDVBA
Supply Voltage
T
IDD
Min
Typ
Max
Unit
3.2
-
5.5
V
Quiescent Current
Inputs shorted, no load
-
6
8
mA
IDDstby
Standby Current
Capacitance
-
-
2
µA
VCBP
DC Reference
-
AUDVBA
T/2
-
V
211
4341H–MP3–10/07
Symbol
VOS
Parameter
Conditions
Min
Typ
Max
Unit
Output differential offset
full gain
-20
0
20
mV
Input impedance
Active state
12K
20k
30k
W
ZLFP
Output load
Full Power mode
6
8
32
W
ZLLP
Output load
Low-Power mode
100
150
300
W
-
-
100
pF
-
60
-
dB
50
-
20000
Hz
-
-
10
ms
ZIN
CL
PSRR
BW
tUP
Capacitive load
Power supply rejection
ratio
Output Frequency
bandwidth
Output setup time
200 – 2kHz
Differential output
1KHz reference frequency
3dB attenuation.
470nF input coupling capacitors
Off to on mode. Voltage already
settled.
Input capacitors precharged
VN
THDHP
THDLP
Output noise
Max gain, A weighted
-
120
500
µVRMS
Output distortion
High power mode, VDD = 3.2V,
1KHz, Pout=100mW, gain=0dB
-
50
-
dB
Output distortion
Low power mode, VDD = 3.2V ,
1KHz, Vout= 100mVpp, Max gain,
load 8 ohms in serie with 200
ohms
-
1
-
%
-2
0
2
dB
-0.7
0
0.7
dB
GACC
Overall Gain accuracy
GSTEP
Gain Step Accuracy
Figure 24-8. Maximum Dissipated Power Versus Power Supply
600
Dissipated Power [mW]
550
500
450
8 Ohms load
400
6.5 Ohms load
350
300
250
200
3,2
212
3,4
3,6
3,8
4
Supply Voltage AUDVBAT [V]
4,2
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Figure 24-9. Dissipated Power vs Output Power, AUDVBAT = 3.2V
600
550
Dissipated Power [mW]
500
450
400
350
8 Ohms load
300
6.5 Ohms load
250
200
150
100
50
0
0
100
200
300
400
500
600
700
800
Output Power [mW]
24.2.6.2
DAC
AUDVDD, HSVDD = 2.8 V, Ta=25°C, typical case, unless otherwise noted
All noise and distortion specifications are measured in the 20 Hz to 0.425xFs and A-weighted
filtered.
Full Scale levels scale proportionally with the analog supply voltage.
Table 24-6.
Audio DAC Specification
OVERALL
MIN
TYP
MAX
UNITS
Operating Temperature
-40
+25
+125
°C
Analog Supply Voltage (AUDVDD, HSVDD)
2.7
2.8
3.3
V
Digital Supply Voltage (VDD)
2.4
2.8
3.3
V
Audio Amplifier Supply (AUDVBAT)
3.2
-
5.5
V
DIGITAL INPUTS/OUTPUTS
Resolution
20
Logic Family
CMOS
Logic Coding
2’s Complement
Bits
ANALOG PERFORMANCE – DAC to Line-out/Headphone Output
Output level for full scale input
(for AUDVDD, HSVDD = 2.8 V)
Output common mode voltage
1.65
Vpp
0.5xHSVDD
V
32
Ohm
10
kOhm
Output load resistance (on HSL, HSR)
- Headphone load
- Line load
16
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4341H–MP3–10/07
Table 24-6.
Audio DAC Specification (Continued)
OVERALL
MIN
TYP
MAX
UNITS
- Headphone load
30
1000
pF
- Line load
30
150
pF
Output load capacitance (on HSL, HSR)
Signal to Noise Ratio
(–1dBFS @ 1kHz input and 0dB Gain)
- Line and Headphone loads
87
92
dB
Total Harmonic Distortion (–1dBFS @ 1kHz input and 0dB Gain)
- Line Load
-80
- Headphone Load
-65
- Headphone Load (16 Ohm)
-40
-76
-60
dB
dB
dB
Dynamic Range (measured with -60 dBFS @ 1kHz input, extrapolated to full-scale)
- Line Load
- Headphone Load
88
93
dB
70
74
dB
Interchannel mismatch
0.1
1
dB
Left-channel to right-channel crosstalk (@ 1kHz)
-90
-80
dB
-
6
dB
Output Power Level Control Range
-6
Output Power Level Control Step
3
dB
- 1kHz
55
dB
- 20kHz
50
dB
PSRR
Maximum output slope at power up (100 to 220F coupling capacitor)
3
V/s
ANALOG PERFORMANCE – Line-in/Microphone Input to Line-out/Headphone Output
Input level for full scale output - 0dBFS Level
@ AUDVDD, HSVDD = 2.8 V and 0 dB gain
@ AUDVDD, HSVDD = 2.8 V and 20 dB gain
Input common mode voltage
Input impedance
7
1.65
Vpp
583
mVrms
0.165
Vpp
58.3
mVrms
0.5xAUDVDD
V
10
kOhm
85
dB
Signal to Noise Ratio
-1 dBFS @ 1kHz input and 0 dB gain
81
-21 dBFS @ 1kHz input and 20 dB gain
71
Dynamic Range (extrapolated to full scale level)
-60 dBFS @ 1kHz input and 0 dB gain
-60 dBFS @ 1kHz input and 20 dB gain
82
86
dB
72
Total Harmonic Distortion
–1dBFS @ 1kHz input and 0 dB gain
-80
-76
–1dBFS @ 1kHz input and 20 dB gain
-75
-68
Interchannel mismatch
0.1
1
214
dB
dB
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 24-6.
Audio DAC Specification (Continued)
OVERALL
MIN
Left-channel to right-channel crosstalk (@ 1kHz)
TYP
MAX
UNITS
-90
-80
dB
ANALOG PERFORMANCE – Differential mono input amplifier
Differential input level for full scale output - 0dBFS Level
@ AUDVDD, HSVDD = 2.8 V and 0 dB gain
Input common mode voltage
1.65
Vppdif
583
mVrms
0.5xAUDVDD
V
Input impedance
7
10
kOhm
Signal to Noise Ratio (-1 dBFS @ 1kHz input and 0 dB gain)
76
80
dB
Total Harmonic Distortion (–1dBFS @ 1kHz input and 0 dB gain)
-85
-81
dB
ANALOG PERFORMANCE – PA Driver
Differential output level for full scale input (for AUDVDD, HSVDD = 3 V)
3.3
Vppdif
Output common mode voltage
0.5xHSVDD
V
Output load
10
Signal to Noise Ratio (–1dBFS @ 1kHz input and 0dB Gain)
76
Total Harmonic Distortion (–1dBFS @ 1kHz input and 0dB Gain)
kOhm
30
80
pF
dB
-75
-71
dB
1.5
nspp
MASTER CLOCK
Master clock Maximum Long Term Jitter
DIGITAL FILTER PERFORMANCE
Frequency response (10 Hz to 20 kHz)
+/- 0.1
dB
Deviation from linear phase (10 Hz to 20 kHz)
+/- 0.1
deg
Passband 0.1 dB corner
0.4535
Fs
Stopband
0.5465
Fs
Stopband Attenuation
65
dB
DE-EMPHASIS FILTER PERFORMANCE (for 44.1kHz Fs)
Frequency
Gain
Margin
Pass band
0Hz to 3180Hz
-1dB
1dB
Transition band
3180Hz to 10600Hz
Logarithm decay
1dB
Stop Band
10600Hz to 20kHz
-10.45dB
1dB
Power Performance
Current consumption from Audio Analog supply AVDD, HSVDD in power on
9.5
Current consumption from Audio Analog supply AVDD, HSVDD in power down
mA
10
µA
Power on Settling Time
- From full Power Down to Full Power Up (AUDVREF and AUDVCM decoupling
capacitors charge)
- Linein amplifier (Line-in coupling capacitors charge)
- Driver amplifier (out driver DC blocking capacitors charge)
500
ms
50
ms
500
ms
215
4341H–MP3–10/07
24.2.7
Digital Filters Transfer Function
Figure 24-10. Channel Filter
Figure 24-11. De-emphasis Filter
0
-2
-4
Gain
(dB)
-6
-8
-10
-12
3
4
10
10
Frequency (Hz)
216
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
24.2.7.1
Audio DAC and PA Connection
Figure 24-12. DAC and PA Connection
PAINN
Battery
AUDVSS
3.2V
to
5.5V
Audio Dac and
PA Connection
3V from LDO
VDD
AUDVBAT
C17
C16
CBP
AUDVDD
VSS
3V from LDO
AUDVSS C7
HPP
AUDVSS
C18
8 Ohm
Loud Speaker
HPN
HSVDD
AUDVSS
C19
LPHN
C15
R1
HSVSS
PAINP
C9
MONOP
AUDVREF
C11
MONON
C12
R
AUDVCM
C8
C3
L
LINEL
Mono
AUDVSS
Differential
Input
32 Ohm
mono input
(+)
AUXP
mono input
C1
(-)
AUXN
C6
C4
HSR
32 Ohm
C5
Headset
or Line Out
AUDVSS
LINER
Stereo
Line Input
VSS
HSL
32 Ohm
INGND
AUDVSS
C10
AUDVSS
ESDVSS
VSS
VSS
ESDVSS
217
4341H–MP3–10/07
Table 24-7.
DAC and PA Characteristics
Symbol
24.2.8
24.2.8.1
Parameter
Typ
Unit
C1
Capacitance
470
nF
C3
Capacitance
470
nF
C4
Capacitance
470
nF
C5
Capacitance
100
µF
C6
Capacitance
100
µF
C7
Capacitance
100
nF
C8
Capacitance
470
nF
C9
Capacitance
100n
µF
C10
Capacitance
10
µF
C11
Capacitance
10
µF
C12
Capacitance
470
nF
C15
Capacitance
470
nF
C16
Capacitance
22
µF
C17
Capacitance
100
nF
C18
Capacitance
100
nF
C19
Capacitance
100
nF
R1
Resistor
200
Ω
In System Programming
Schematic
Figure 24-13. ISP Pull-Down Connection
ISP
RISP
VSS
24.2.8.2
Parameters
Table 24-8.
ISP Pull-Down Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
RISP
218
Parameter
ISP Pull-Down Resistor
Min
Typ
2.2
Max
Unit
KΩ
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
24.3
AC Characteristics
24.3.1
24.3.1.1
External Program Bus Cycles
Definition of Symbols
Table 24-9.
External Program Bus Cycles Timing Symbol Definitions
Signals
24.3.1.2
Conditions
A
Address
H
High
I
Instruction In
L
Low
L
ALE
V
Valid
P
PSEN
X
No Longer Valid
Z
Floating
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 24-10. External Program Bus Cycle - Read AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Variable Clock
Standard Mode
Symbol
Parameter
TCLCL
Clock Period
TLHLL
ALE Pulse Width
TAVLL
Min
Max
Variable Clock
X2 Mode
Min
Max
Unit
50
50
ns
2·TCLCL-15
TCLCL-15
ns
Address Valid to ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLAX
Address hold after ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLIV
ALE Low to Valid Instruction
4·TCLCL-35
2·TCLCL-35
ns
TPLPH
PSEN Pulse Width
3·TCLCL-25
1.5·TCLCL-25
ns
TPLIV
PSEN Low to Valid Instruction
TPXIX
Instruction Hold After PSEN High
TPXIZ
Instruction Float After PSEN High
TCLCL-10
0.5·TCLCL-10
ns
TAVIV
Address Valid to Valid Instruction
5·TCLCL-35
2.5·TCLCL-35
ns
TPLAZ
PSEN Low to Address Float
10
10
ns
3·TCLCL-35
0
1.5·TCLCL-35
0
ns
ns
219
4341H–MP3–10/07
24.3.1.3
Waveforms
Figure 24-14. External Program Bus Cycle - Read Waveforms
ALE
TLHLL
TPLPH
TLLPL
PSEN
TPLIV
TPLAZ
TAVLL TLLAX
P0
D7:0
TPXAV
TPXIZ
TPXIX
A7:0
D7:0
A7:0
D7:0
Instruction In
P2
24.3.2
24.3.2.1
Instruction In
A15:8
A15:8
External Data 8-bit Bus Cycles
Definition of Symbols
Table 24-11. External Data 8-bit Bus Cycles Timing Symbol Definitions
Signals
24.3.2.2
Conditions
A
Address
H
High
D
Data In
L
Low
L
ALE
V
Valid
Q
Data Out
X
No Longer Valid
R
RD
Z
Floating
W
WR
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 24-12. External Data 8-bit Bus Cycle - Read AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Variable Clock
Standard Mode
Symbol
220
Parameter
TCLCL
Clock Period
TLHLL
ALE Pulse Width
TAVLL
Min
Max
Variable Clock
X2 Mode
Min
Max
Unit
50
50
ns
2·TCLCL-15
TCLCL-15
ns
Address Valid to ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLAX
Address hold after ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLRL
ALE Low to RD Low
3·TCLCL-30
1.5·TCLCL-30
ns
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Variable Clock
Standard Mode
Symbol
Parameter
TRLRH
RD Pulse Width
TRHLH
RD high to ALE High
TAVDV
Address Valid to Valid Data In
TAVRL
Address Valid to RD Low
TRLDV
RD Low to Valid Data
TRLAZ
RD Low to Address Float
TRHDX
Data Hold After RD High
TRHDZ
Instruction Float After RD High
Min
Max
6·TCLCL-25
TCLCL-20
Variable Clock
X2 Mode
Min
Max
3·TCLCL-25
TCLCL+20
0.5·TCLCL-20
9·TCLCL-65
4·TCLCL-30
Unit
ns
0.5·TCLCL+20
ns
4.5·TCLCL-65
ns
2·TCLCL-30
ns
5·TCLCL-30
2.5·TCLCL-30
ns
0
0
ns
0
0
2·TCLCL-25
ns
TCLCL-25
ns
Table 24-13. External Data 8-bit Bus Cycle - Write AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Variable Clock
Standard Mode
Symbol
Parameter
TCLCL
Clock Period
TLHLL
ALE Pulse Width
TAVLL
Min
Max
Variable Clock
X2 Mode
Min
Max
Unit
50
50
ns
2·TCLCL-15
TCLCL-15
ns
Address Valid to ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLAX
Address hold after ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLWL
ALE Low to WR Low
3·TCLCL-30
1.5·TCLCL-30
ns
TWLWH
WR Pulse Width
6·TCLCL-25
3·TCLCL-25
ns
TWHLH
WR High to ALE High
TAVWL
Address Valid to WR Low
4·TCLCL-30
2·TCLCL-30
ns
TQVWH
Data Valid to WR High
7·TCLCL-20
3.5·TCLCL-20
ns
TWHQX
Data Hold after WR High
TCLCL-15
0.5·TCLCL-15
ns
TCLCL-20
TCLCL+20
0.5·TCLCL-20
0.5·TCLCL+20
ns
221
4341H–MP3–10/07
24.3.2.3
Waveforms
Figure 24-15. External Data 8-bit Bus Cycle - Read Waveforms
ALE
TLHLL
TLLRL
TRLRH
TRHLH
RD
TRLDV
TRHDZ
TRLAZ
TAVLL
P0
TLLAX
TRHDX
A7:0
D7:0
TAVRL
Data In
TAVDV
P2
A15:8
Figure 24-16. External Data 8-bit Bus Cycle - Write Waveforms
ALE
TLHLL
TLLWL
TWHLH
TWLWH
WR
TAVWL
TAVLL
P0
TLLAX
TQVWH
A7:0
TWHQX
D7:0
Data Out
P2
24.3.3
24.3.3.1
A15:8
External IDE 16-bit Bus Cycles
Definition of Symbols
Table 24-14. External IDE 16-bit Bus Cycles Timing Symbol Definitions
Signals
222
Conditions
A
Address
H
High
D
Data In
L
Low
L
ALE
V
Valid
Q
Data Out
X
No Longer Valid
R
RD
Z
Floating
W
WR
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
24.3.3.2
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 24-15. External IDE 16-bit Bus Cycle - Data Read AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Variable Clock
Standard Mode
Symbol
Parameter
TCLCL
Clock Period
TLHLL
ALE Pulse Width
TAVLL
Min
Max
Variable Clock
X2 Mode
Min
Max
Unit
50
50
ns
2·TCLCL-15
TCLCL-15
ns
Address Valid to ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLAX
Address hold after ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLRL
ALE Low to RD Low
3·TCLCL-30
1.5·TCLCL-30
ns
TRLRH
RD Pulse Width
6·TCLCL-25
3·TCLCL-25
ns
TRHLH
RD high to ALE High
TAVDV
Address Valid to Valid Data In
TAVRL
Address Valid to RD Low
TRLDV
RD Low to Valid Data
TRLAZ
RD Low to Address Float
TRHDX
Data Hold After RD High
TRHDZ
Instruction Float After RD High
TCLCL-20
TCLCL+20
0.5·TCLCL-20
9·TCLCL-65
4·TCLCL-30
0.5·TCLCL+20
ns
4.5·TCLCL-65
ns
2·TCLCL-30
ns
5·TCLCL-30
2.5·TCLCL-30
ns
0
0
ns
0
0
2·TCLCL-25
ns
TCLCL-25
ns
Table 24-16. External IDE 16-bit Bus Cycle - Data Write AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Variable Clock
Standard Mode
Symbol
Parameter
TCLCL
Clock Period
TLHLL
ALE Pulse Width
TAVLL
Min
Max
Variable Clock
X2 Mode
Min
Max
Unit
50
50
ns
2·TCLCL-15
TCLCL-15
ns
Address Valid to ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLAX
Address hold after ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLWL
ALE Low to WR Low
3·TCLCL-30
1.5·TCLCL-30
ns
TWLWH
WR Pulse Width
6·TCLCL-25
3·TCLCL-25
ns
TWHLH
WR High to ALE High
TAVWL
Address Valid to WR Low
4·TCLCL-30
2·TCLCL-30
ns
TQVWH
Data Valid to WR High
7·TCLCL-20
3.5·TCLCL-20
ns
TWHQX
Data Hold after WR High
TCLCL-15
0.5·TCLCL-15
ns
TCLCL-20
TCLCL+20
0.5·TCLCL-20
0.5·TCLCL+20
ns
223
4341H–MP3–10/07
24.3.3.3
Waveforms
Figure 24-17. External IDE 16-bit Bus Cycle - Data Read Waveforms
ALE
TLHLL
TLLRL
TRLRH
TRHLH
RD
TRLDV
TRHDZ
TRLAZ
TAVLL
P0
TLLAX
TRHDX
A7:0
D7:0
TAVRL
Data In
TAVDV
P2
D15:8(1)
A15:8
Data In
Note:
1. D15:8 is written in DAT16H SFR.
Figure 24-18. External IDE 16-bit Bus Cycle - Data Write Waveforms
ALE
TLHLL
TLLWL
TWLWH
TWHLH
WR
TAVWL
TAVLL
P0
TLLAX
TQVWH
A7:0
TWHQX
D7:0
Data Out
P2
D15:8(1)
A15:8
Data Out
Note:
24.4
1. D15:8 is the content of DAT16H SFR.
SPI Interface
24.4.0.4
Definition of Symbols
Table 24-17. SPI Interface Timing Symbol Definitions
Signals
224
Conditions
C
Clock
H
High
I
Data In
L
Low
O
Data Out
V
Valid
X
No Longer Valid
Z
Floating
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
24.4.0.5
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 24-18. SPI Interface Master AC Timing
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Parameter
Min
Max
Unit
Slave Mode
TCHCH
Clock Period
2
TPER
TCHCX
Clock High Time
0.8
TPER
TCLCX
Clock Low Time
0.8
TPER
TSLCH, TSLCL
SS Low to Clock edge
100
ns
TIVCL, TIVCH
Input Data Valid to Clock Edge
40
ns
TCLIX, TCHIX
Input Data Hold after Clock Edge
40
ns
TCLOV, TCHOV
Output Data Valid after Clock Edge
TCLOX, TCHOX
Output Data Hold Time after Clock Edge
0
ns
TCLSH, TCHSH
SS High after Clock Edge
0
ns
TSLOV
SS Low to Output Data Valid
50
ns
TSHOX
Output Data Hold after SS High
50
ns
TSHSL
SS High to SS Low
TILIH
Input Rise Time
2
µs
TIHIL
Input Fall Time
2
µs
TOLOH
Output Rise time
100
ns
TOHOL
Output Fall Time
100
ns
40
ns
(1)
Master Mode
TCHCH
Clock Period
2
TPER
TCHCX
Clock High Time
0.8
TPER
TCLCX
Clock Low Time
0.8
TPER
TIVCL, TIVCH
Input Data Valid to Clock Edge
20
ns
TCLIX, TCHIX
Input Data Hold after Clock Edge
20
ns
TCLOV, TCHOV
Output Data Valid after Clock Edge
TCLOX, TCHOX
Output Data Hold Time after Clock Edge
TILIH
Input Data Rise Time
2
µs
TIHIL
Input Data Fall Time
2
µs
TOLOH
Output Data Rise time
50
ns
TOHOL
Output Data Fall Time
50
ns
Note:
40
0
ns
ns
1. Value of this parameter depends on software.
225
4341H–MP3–10/07
24.4.0.6
Waveforms
Figure 24-19. SPI Slave Waveforms (SSCPHA= 0)
SS
(input)
TSLCH
TSLCL
TCHCH
SCK
(SSCPOL= 0)
(input)
TCHCX
TSHSL
TCLCX
TCHCL
SCK
(SSCPOL= 1)
(input)
TCLOX
TCHOX
TCLOV
TCHOV
TSLOV
MISO
(output)
TCLCH
TCLSH
TCHSH
SLAVE MSB OUT
BIT 6
TSHOX
SLAVE LSB OUT
(1)
TIVCH TCHIX
TIVCL TCLIX
MOSI
(input)
Note:
MSB IN
BIT 6
LSB IN
1. Not Defined but generally the MSB of the character which has just been received.
Figure 24-20. SPI Slave Waveforms (SSCPHA= 1)
SS
(input)
TSLCH
TSLCL
SCK
(SSCPOL= 0)
(input)
TCHCH
TCHCX
TSHSL
TCLCX
TCHCL
SCK
(SSCPOL= 1)
(input)
TCHOV
TCLOV
TSLOV
MISO
(output)
TCLCH
TCLSH
TCHSH
(1)
SLAVE MSB OUT
BIT 6
TCHOX
TCLOX
TSHOX
SLAVE LSB OUT
TIVCH TCHIX
TIVCL TCLIX
MOSI
(input)
Note:
226
MSB IN
BIT 6
LSB IN
1. Not Defined but generally the LSB of the character which has just been received.
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Figure 24-21. SPI Master Waveforms (SSCPHA= 0)
SS
(output)
TCHCH
SCK
(SSCPOL= 0)
(output)
TCHCX
TCLCH
TCLCX
TCHCL
SCK
(SSCPOL= 1)
(output)
TIVCH TCHIX
TIVCL TCLIX
MOSI
(input)
MSB IN
BIT 6
LSB IN
TCLOX
TCLOV
TCHOV
MISO
(output)
Note:
Port Data
MSB OUT
TCHOX
BIT 6
LSB OUT
Port Data
1. SS handled by software using general purpose port pin.
Figure 24-22. SPI Master Waveforms (SSCPHA= 1)
SS(1)
(output)
TCHCH
SCK
(SSCPOL= 0)
(output)
TCHCX
TCLCH
TCLCX
TCHCL
SCK
(SSCPOL= 1)
(output)
TIVCH TCHIX
TIVCL TCLIX
MOSI
(input)
MISO
(output)
Note:
MSB IN
BIT 6
TCLOV
TCLOX
TCHOX
TCHOV
Port Data
MSB OUT
BIT 6
LSB IN
LSB OUT
Port Data
1. SS handled by software using general purpose port pin.
227
4341H–MP3–10/07
24.4.1
24.4.1.1
Two-wire Interface
Timings
Table 24-19. TWI Interface AC Timing
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
INPUT
Min
Max
OUTPUT
Min
Max
Start condition hold time
14·TCLCL(4)
4.0 µs(1)
TLOW
SCL low time
16·TCLCL(4)
4.7 µs(1)
THIGH
SCL high time
14·TCLCL(4)
4.0 µs(1)
TRC
SCL rise time
1 µs
-(2)
TFC
SCL fall time
0.3 µs
0.3 µs(3)
TSU; DAT1
Data set-up time
250 ns
20·TCLCL(4)- TRD
TSU; DAT2
SDA set-up time (before repeated START condition)
250 ns
1 µs(1)
TSU; DAT3
SDA set-up time (before STOP condition)
250 ns
8·TCLCL(4)
THD; DAT
Data hold time
0 ns
8·TCLCL(4) - TFC
TSU; STA
Repeated START set-up time
14·TCLCL(4)
4.7 µs(1)
TSU; STO
STOP condition set-up time
14·TCLCL(4)
4.0 µs(1)
TBUF
Bus free time
14·TCLCL(4)
4.7 µs(1)
TRD
SDA rise time
1 µs
-(2)
TFD
SDA fall time
0.3 µs
0.3 µs(3)
Symbol
THD; STA
Notes:
228
Parameter
1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this
must be < 1 µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered out. Maximum capacitance on bus-lines SDA and
SCL= 400 pF.
4. TCLCL= TOSC= one oscillator clock period.
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
24.4.1.2
Waveforms
Figure 24-23. Two Wire Waveforms
Repeated START condition
START or Repeated START condition
START condition
Tsu;STA
STOP condition
Trd
0.7 VDD
0.3 VDD
SDA
(INPUT/OUTPUT)
Tsu;STO
Tfd
Trc
Tfc
0.7 VDD
0.3 VDD
SCL
(INPUT/OUTPUT)
Thd;STA
24.4.2
24.4.2.1
Tlow Thigh Tsu;DAT1
Tsu;DAT2
Thd;DAT
MMC Interface
Definition of symbols
Table 24-20. MMC Interface Timing Symbol Definitions
Signals
24.4.2.2
Tbuf
Tsu;DAT3
Conditions
C
Clock
H
High
D
Data In
L
Low
O
Data Out
V
Valid
X
No Longer Valid
Timings
Table 24-21. MMC Interface AC timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C, CL ≤ 100pF (10 cards)
Symbol
Parameter
Min
Max
Unit
TCHCH
Clock Period
50
ns
TCHCX
Clock High Time
10
ns
TCLCX
Clock Low Time
10
ns
TCLCH
Clock Rise Time
10
ns
TCHCL
Clock Fall Time
10
ns
TDVCH
Input Data Valid to Clock High
3
ns
TCHDX
Input Data Hold after Clock High
3
ns
TCHOX
Output Data Hold after Clock High
5
ns
TOVCH
Output Data Valid to Clock High
5
ns
229
4341H–MP3–10/07
24.4.2.3
Waveforms
Figure 24-24. MMC Input-Output Waveforms
TCHCH
TCHCX
TCLCX
MCLK
TCHCL
TCLCH
TCHIX
TIVCH
MCMD Input
MDAT Input
TCHOX
TOVCH
MCMD Output
MDAT Output
24.4.3
24.4.3.1
Audio Interface
Definition of symbols
Table 24-22. Audio Interface Timing Symbol Definitions
Signals
24.4.3.2
Conditions
C
Clock
H
High
O
Data Out
L
Low
S
Data Select
V
Valid
X
No Longer Valid
Timings
Table 24-23. Audio Interface AC timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C, CL≤ 30pF
Symbol
Min
Max
Unit
325.5(1)
ns
TCHCH
Clock Period
TCHCX
Clock High Time
30
ns
TCLCX
Clock Low Time
30
ns
TCLCH
Clock Rise Time
10
ns
TCHCL
Clock Fall Time
10
ns
TCLSV
Clock Low to Select Valid
10
ns
TCLOV
Clock Low to Data Valid
10
ns
Note:
230
Parameter
1. 32-bit format with Fs= 48 KHz.
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
24.4.3.3
Waveforms
Figure 24-25. Audio Interface Waveforms
TCHCH
TCHCX
TCLCX
DCLK
TCHCL
TCLCH
TCLSV
DSEL
Right
Left
TCLOV
DDAT
24.4.4
24.4.4.1
Flash Memory
Definition of symbols
Table 24-24. Flash Memory Timing Symbol Definitions
Signals
24.4.4.2
Conditions
S
ISP
L
Low
R
RST
V
Valid
B
FBUSY flag
X
No Longer Valid
Timings
Table 24-25. Flash Memory AC Timing
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Parameter
Min
Typ
Max
Unit
TSVRL
Input ISP Valid to RST Edge
50
ns
TRLSX
Input ISP Hold after RST Edge
50
ns
TBHBL
FLASH Internal Busy (Programming) Time
NFCY
Number of Flash Write Cycles
TFDR
Flash Data Retention Time
10
ms
100K
Cycle
10
Years
231
4341H–MP3–10/07
24.4.4.3
Waveforms
Figure 24-26. FLASH Memory - ISP Waveforms
RST
TSVRL
ISP
Note:
TRLSX
(1)
1. ISP must be driven through a pull-down resistor (see Section “In System Programming”,
page 218).
Figure 24-27. FLASH Memory - Internal Busy Waveforms
FBUSY bit
24.4.5
24.4.5.1
TBHBL
External Clock Drive and Logic Level References
Definition of symbols
Table 24-26. External Clock Timing Symbol Definitions
Signals
C
24.4.5.2
Conditions
Clock
H
High
L
Low
X
No Longer Valid
Timings
Table 24-27. External Clock AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Min
Max
Unit
TCLCL
Clock Period
50
ns
TCHCX
High Time
10
ns
TCLCX
Low Time
10
ns
TCLCH
Rise Time
3
ns
TCHCL
Fall Time
3
ns
Cyclic Ratio in X2 mode
40
TCR
232
Parameter
60
%
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
24.4.5.3
Waveforms
Figure 24-28. External Clock Waveform
TCLCH
VDD - 0.5
VIH1
TCHCX
TCLCX
VIL
0.45 V
TCHCL
TCLCL
Figure 24-29. AC Testing Input/Output Waveforms
INPUTS
VDD - 0.5
0.45 V
Note:
OUTPUTS
0.7 VDD
VIH min
0.3 VDD
VIL max
1. During AC testing, all inputs are driven at VDD -0.5 V for a logic 1 and 0.45 V for a logic 0.
2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0.
Figure 24-30. Float Waveforms
VLOAD
VLOAD + 0.1 V
VLOAD - 0.1 V
Note:
Timing Reference Points
VOH - 0.1 V
VOL + 0.1 V
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loading VOH/VOL level occurs with
IOL/IOH= ±20 mA.
233
4341H–MP3–10/07
25. Ordering Information
Part Number
Memory
Size
ADC
Supply
Voltage
Range
Max
Frequency
(MHz)
Package
Packing
Temp.
Product Marking
RoHS
Compliant
AT89C51SND2C-7FTIL
64K
Flash
No
3V
Industrial
40
BGA100
Tray
89C51SND2C-IL
No
AT89C51SND2C-7FRIL
64K
Flash
No
3V
Industrial
40
BGA100
Reel
89C51SND2C-IL
No
AT89C51SND2C-7FTJL
64K
Flash
No
3V
RoHS
40
BGA100
Tray
89C51SND2C-JL
Yes
AT89C51SND2C-7FRJL
64K
Flash
No
3V
RoHS
40
BGA100
Reel
89C51SND2C-JL
Yes
AT83SND2Cxxx-7FTJL
64K
ROM
No
3V
RoHS
40
BGA100
Tray
83C51SND2C-JL
Yes
AT83SND2Cxxx-7FRJL
64K
ROM
No
3V
RoHS
40
BGA100
Reel
83C51SND2C-JL
Yes
AT89C51SND2C-7FTUL
64K
Flash
No
3V
Green
40
BGA100
Reel
89C51SND2C-UL
Yes
AT89SND2CMP3B7FTUL
64K
Flash
Yes
3V
Green
40
BGA100
Tray
89SND2CMP3B-UL
Yes
AT83SND2CxxxB7FTUL
64K
ROM
Yes
3V
Green
40
BGA100
Tray
83SND2CxxxB-UL
Yes
AT80SND2CMP3B7FTUL
-
Yes
3V
Green
40
BGA100
Tray
80SND2CMP3B-UL
Yes
234
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
26. Package Information
26.1
CTBGA100
235
4341H–MP3–10/07
27. Datasheet Revision History
27.1
Changes from 4341A - 10/04 to 4341B - 01/05
1. Update Power Amplifier DC characteristics, Section “Electrical Characteristics”,
page 207.
2. Fix minor bugs.
3. Update power consumption measures, Table 24-2 on page 208.
27.2
Changes from 4341B - 01/05 to 4341C - 03/05
1. Change to hardware security system description. Section “Hardware Security System”,
page 20.
27.3
Changes from 4341C - 03/05 to 4341D - 04/05
1. Update to DAC gain information, Figure 15-2 on page 82.
2. Correction to BGA package pinout, Figure 4-1 on page 4.
3. Updated Ordering Information, Green product version changed to ROHS. (Green version
not yet available)
27.4
Changes from 4341D - 04/05 to 4341E - 06/05
1. Added Green Packaging Information. Page 228
2. Modified operating conditions, Page 1.
236
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
27.5
Changes from 4341E - 06/05 to 4341F - 03/06
1. Added 8xSND2CxxxMP3B description with A/D converter.
27.6
Changes from 4341F - 03/05 to 4341G - 07/07
1. Updated Package drawing for CTBGA100. “CTBGA100” on page 235.
27.7
Changes from 4341G - 07/07 to 4341H - 10/07
1. Added part number AT89C51SND2C-7FTUL to ordering information.
2. Modified address in the PSW register, Table 7-4 on page 29.
237
4341H–MP3–10/07
1.
Description ............................................................................................... 2
2.
Typical Applications ................................................................................ 2
3.
Block Diagram .......................................................................................... 3
4.
Pin Description ......................................................................................... 4
4.1 Pinouts ..................................................................................................................... 4
4.2 ................................................................................................................................. 5
4.3 Signals...................................................................................................................... 6
4.4 Internal Pin Structure.............................................................................................. 12
5.
Clock Controller ..................................................................................... 13
5.1 Oscillator ................................................................................................................ 13
5.2 X2 Feature.............................................................................................................. 14
5.3 PLL ......................................................................................................................... 14
5.4 Registers ................................................................................................................ 16
6.
Program/Code Memory ......................................................................... 18
6.1 ROM Memory Architecture ..................................................................................... 19
6.2 Flash Memory Architecture .................................................................................... 19
6.3 Hardware Security System ..................................................................................... 20
6.4 Boot Memory Execution ......................................................................................... 20
6.5 Preventing Flash Corruption................................................................................... 21
6.6 Registers ................................................................................................................ 22
6.7 Hardware Bytes ...................................................................................................... 22
7.
Data Memory .......................................................................................... 24
7.1 Internal Space ........................................................................................................ 24
7.2 External Space ....................................................................................................... 25
7.3 Dual Data Pointer ................................................................................................... 27
7.4 Registers ................................................................................................................ 29
8.
Special Function Registers ................................................................... 31
9.
Interrupt System .................................................................................... 37
9.1 Interrupt System Priorities ...................................................................................... 37
9.2 External Interrupts .................................................................................................. 40
9.3 Registers ................................................................................................................ 41
10. Power Management ............................................................................... 47
10.1 Reset .................................................................................................................... 47
238
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
10.2 Reset Recommendation to Prevent Flash Corruption .......................................... 48
10.3 Idle Mode.............................................................................................................. 49
10.4 Power-down Mode ............................................................................................... 49
10.5 Registers .............................................................................................................. 51
11. Timers/Counters .................................................................................... 52
11.1 Timer/Counter Operations .................................................................................... 52
11.2 Timer Clock Controller.......................................................................................... 52
11.3 Timer 0 ................................................................................................................. 53
11.4 Timer 1 ................................................................................................................. 55
11.5 Interrupt ................................................................................................................ 56
11.6 Registers .............................................................................................................. 57
12. Watchdog Timer ..................................................................................... 60
12.1 Description ........................................................................................................... 60
12.2 Watchdog Clock Controller................................................................................... 60
12.3 Watchdog Operation ............................................................................................ 61
12.4 Registers .............................................................................................................. 62
13. MP3 Decoder .......................................................................................... 63
13.1 Decoder ................................................................................................................ 63
13.2 Audio Controls ...................................................................................................... 65
13.3 Decoding Errors ................................................................................................... 65
13.4 Frame Information ................................................................................................ 66
13.5 Ancillary Data ....................................................................................................... 66
13.6 Interrupt ................................................................................................................ 66
13.7 Registers .............................................................................................................. 69
14. Audio Output Interface .......................................................................... 74
14.1 Description ........................................................................................................... 74
14.2 Clock Generator ................................................................................................... 75
14.3 Data Converter ..................................................................................................... 75
14.4 Audio Buffer.......................................................................................................... 76
14.5 MP3 Buffer ........................................................................................................... 77
14.6 Interrupt Request.................................................................................................. 77
14.7 MP3 Song Playing ................................................................................................ 77
14.8 Registers .............................................................................................................. 78
15. DAC and PA Interface ............................................................................ 81
239
4341H–MP3–10/07
15.1 DAC ...................................................................................................................... 81
15.2 Power Amplifier .................................................................................................... 98
15.3 Audio Supplies and Start-up................................................................................. 99
16. Universal Serial Bus ............................................................................ 103
16.1 USB Mass Storage Class Bulk-Only Transport .................................................. 103
16.2 USB Device Firmware Upgrade (DFU)............................................................... 103
16.3 Description ......................................................................................................... 103
16.4 Configuration ...................................................................................................... 107
16.5 Read/Write Data FIFO........................................................................................ 109
16.6 Bulk/Interrupt Transactions ................................................................................ 110
16.7 Control Transactions .......................................................................................... 114
16.8 Isochronous Transactions .................................................................................. 114
16.9 Miscellaneous..................................................................................................... 116
16.10 Suspend/Resume Management....................................................................... 117
16.11 USB Interrupt System....................................................................................... 119
16.12 Registers .......................................................................................................... 122
17. IDE/ATAPI Interface ............................................................................. 131
17.1 Description ......................................................................................................... 131
17.2 Registers ............................................................................................................ 133
18. MultiMedia Card Controller ................................................................. 134
18.1 Card Concept ..................................................................................................... 134
18.2 Bus Concept ....................................................................................................... 134
18.3 Description ......................................................................................................... 139
18.4 Clock Generator ................................................................................................. 140
18.5 Command Line Controller .................................................................................. 140
18.6 Data Line Controller ........................................................................................... 142
18.7 Interrupt .............................................................................................................. 148
18.8 Registers ............................................................................................................ 150
19. Synchronous Peripheral Interface ..................................................... 156
19.1 Description ......................................................................................................... 157
19.2 Interrupt .............................................................................................................. 160
19.3 Configuration ...................................................................................................... 160
19.4 Registers ............................................................................................................ 166
20. Serial I/O Port ....................................................................................... 168
240
AT8xC51SND2C/MP3B
4341H–MP3–10/07
AT8xC51SND2C/MP3B
20.1 Mode Selection................................................................................................... 168
20.2 Baud Rate Generator ......................................................................................... 168
20.3 Synchronous Mode (Mode 0) ............................................................................. 169
20.4 Asynchronous Modes (Modes 1, 2 and 3).......................................................... 171
20.5 Multiprocessor Communication (Modes 2 and 3) ............................................... 175
20.6 Automatic Address Recognition ......................................................................... 175
20.7 Interrupt .............................................................................................................. 177
20.8 Registers ............................................................................................................ 178
21. Two-wire Interface (TWI) Controller ................................................... 181
21.1 Description ......................................................................................................... 181
21.2 Registers ............................................................................................................ 195
22. Analog to Digital Converter ................................................................ 199
22.1 Description ......................................................................................................... 199
22.2 Registers ............................................................................................................ 202
23. Keyboard Interface .............................................................................. 204
23.1 Description ......................................................................................................... 204
23.2 Registers ............................................................................................................ 205
24. Electrical Characteristics .................................................................... 207
24.1 Absolute Maximum Rating ................................................................................. 207
24.2 DC Characteristics ............................................................................................. 207
24.3 AC Characteristics.............................................................................................. 219
24.4 SPI Interface....................................................................................................... 224
25. Ordering Information ........................................................................... 234
26. Package Information ............................................................................ 235
26.1 CTBGA100 ......................................................................................................... 235
27. Datasheet Revision History ................................................................ 236
27.1 Changes from 4341A - 10/04 to 4341B - 01/05.................................................. 236
27.2 Changes from 4341B - 01/05 to 4341C - 03/05 ................................................. 236
27.3 Changes from 4341C - 03/05 to 4341D - 04/05 ................................................. 236
27.4 Changes from 4341D - 04/05 to 4341E - 06/05 ................................................. 236
27.5 Changes from 4341E - 06/05 to 4341F - 03/06 .................................................. 237
27.6 Changes from 4341F - 03/05 to 4341G - 07/07 ................................................. 237
27.7 Changes from 4341G - 07/07 to 4341H - 10/07 ................................................. 237
241
4341H–MP3–10/07
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