ATmega48P/88P/168P - Summary

Features
• High Performance, Low Power Atmel® AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
•
•
•
•
•
•
•
•
•
– 131 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory Segments
– 4/8/16KBytes of In-System Self-Programmable Flash program memory
– 256/512/512Bytes EEPROM
– 512/1K/1KBytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
QTouch® library support
– Capacitive touch buttons, sliders and wheels
– QTouch and QMatrix acquisition
– Up to 64 sense channels
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel 10-bit ADC in TQFP and QFN/MLF package
Temperature Measurement
– 6-channel 10-bit ADC in PDIP Package
Temperature Measurement
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Byte-oriented 2-wire Serial Interface (Philips I2C compatible)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
and Extended Standby
I/O and Packages
– 23 Programmable I/O Lines
– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF
Operating Voltage:
– 1.8 - 5.5V for ATmega48P/88P/168PV
– 2.7 - 5.5V for ATmega48P/88P/168P
Temperature Range:
– -40C to 85C
Speed Grade:
– ATmega48P/88P/168PV: 0 - 4MHz @ 1.8 - 5.5V, 0 - 10MHz @ 2.7 - 5.5V
– ATmega48P/88P/168P: 0 - 10MHz @ 2.7 - 5.5V, 0 - 20MHz @ 4.5 - 5.5V
Low Power Consumption at 1MHz, 1.8V, 25C:
– Active Mode: 0.3mA
– Power-down Mode: 0.1µA
– Power-save Mode: 0.8µA (Including 32kHz RTC)
Note:
1. See “Data Retention” on page 8 for details.
8-bit Atmel
Microcontroller
with 4/8/16K
Bytes In-System
Programmable
Flash
ATmega48P/V
ATmega88P/V
ATmega168P/V
Summary
Rev. 8025NS–AVR–11/2015
ATmega48P/88P/168P
1.
Pin Configurations
Figure 1-1.
Pinout ATmega48P/88P/168P
PDIP
32
31
30
29
28
27
26
25
PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
TQFP Top View
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK/PCINT5)
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/OC2A/MOSI) PB3
(PCINT4/MISO) PB4
9
10
11
12
13
14
15
16
PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
AREF
AVCC
PB5 (SCK/PCINT5)
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
GND
VCC
GND
VCC
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK/PCINT5)
9
10
11
12
13
14
15
16
8
9
10
11
12
13
14
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/OC2A/MOSI) PB3
(PCINT4/MISO) PB4
NOTE: Bottom pad should be soldered to ground.
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
AREF
AVCC
PB5 (SCK/PCINT5)
PB4 (MISO/PCINT4)
PB3 (MOSI/OC2A/PCINT3)
PB2 (SS/OC1B/PCINT2)
PB1 (OC1A/PCINT1)
32
31
30
29
28
27
26
25
PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
28
27
26
25
24
23
22
21
20
19
18
17
16
15
32 MLF Top View
28 MLF Top View
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
VCC
GND
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
(PCINT21/OC0B/T1) PD5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NOTE: Bottom pad should be soldered to ground.
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/OC2A/MOSI) PB3
(PCINT4/MISO) PB4
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
GND
VCC
GND
VCC
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
(PCINT14/RESET) PC6
(PCINT16/RXD) PD0
(PCINT17/TXD) PD1
(PCINT18/INT0) PD2
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
VCC
GND
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
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8025NS–AVR–11/2015
ATmega48P/88P/168P
1.1
Pin Descriptions
1.1.1
VCC
Digital supply voltage.
1.1.2
GND
Ground.
1.1.3
Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting
Oscillator amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting
Oscillator amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7:6 is used as TOSC2:1
input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in “Alternate Functions of Port B” on page
84 and “System Clock and Clock Options” on page 27.
1.1.4
Port C (PC5:0)
Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
PC5:0 output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
1.1.5
PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical
characteristics of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
The minimum pulse length is given in Table 29-3 on page 322. Shorter pulses are not
guaranteed to generate a Reset.
The various special features of Port C are elaborated in “Alternate Functions of Port C” on page
87.
1.1.6
Port D (PD7:0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
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8025NS–AVR–11/2015
ATmega48P/88P/168P
The various special features of Port D are elaborated in “Alternate Functions of Port D” on page
90.
1.1.7
AVCC
AVCC is the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter. Note that PC6:4 use digital supply voltage, VCC.
1.1.8
AREF
AREF is the analog reference pin for the A/D Converter.
1.1.9
ADC7:6 (TQFP and QFN/MLF Package Only)
In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter.
These pins are powered from the analog supply and serve as 10-bit ADC channels.
2.
Overview
The ATmega48P/88P/168P is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega48P/88P/168P achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
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8025NS–AVR–11/2015
ATmega48P/88P/168P
Block Diagram
Block Diagram
GND
Figure 2-1.
VCC
2.1
Watchdog
Timer
Watchdog
Oscillator
Oscillator
Circuits /
Clock
Generation
Power
Supervision
POR / BOD &
RESET
debugWIRE
Flash
SRAM
PROGRAM
LOGIC
CPU
EEPROM
AVCC
AREF
DATABUS
GND
8bit T/C 0
16bit T/C 1
A/D Conv.
8bit T/C 2
Analog
Comp.
Internal
Bandgap
USART 0
SPI
TWI
PORT D (8)
PORT B (8)
PORT C (7)
2
6
RESET
XTAL[1..2]
PD[0..7]
PB[0..7]
PC[0..6]
ADC[6..7]
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8025NS–AVR–11/2015
ATmega48P/88P/168P
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than
conventional CISC microcontrollers.
The ATmega48P/88P/168P provides the following features: 4K/8K/16Kbytes of In-System
Programmable Flash with Read-While-Write capabilities, 256/512/512bytes EEPROM,
512/1K/1Kbytes SRAM, 23 general purpose I/O lines, 32 general purpose working registers,
three flexible Timer/Counters with compare modes, internal and external interrupts, a serial
programmable USART, a byte-oriented, 2-wire Serial Interface, an SPI serial port, a 6-channel
10-bit ADC (8 channels in TQFP and QFN/MLF packages), a programmable Watchdog Timer
with internal Oscillator, and five software selectable power saving modes. The Idle mode stops
the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port,
and interrupt system to continue functioning. The Power-down mode saves the register contents
but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware
reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to
maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode
stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching
noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running
while the rest of the device is sleeping. This allows very fast start-up combined with low power
consumption.
Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels
functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers
robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key
Suppression® (AKS™) technology for unambiguous detection of key events. The easy-to-use
QTouch Suite toolchain allows you to explore, develop and debug your own touch applications.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot
program running on the AVR core. The Boot program can use any interface to download the
application program in the Application Flash memory. Software in the Boot Flash section will
continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATmega48P/88P/168P is a powerful microcontroller that provides a
highly flexible and cost effective solution to many embedded control applications.
The ATmega48P/88P/168P AVR is supported with a full suite of program and system
development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators,
In-Circuit Emulators, and Evaluation kits.
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ATmega48P/88P/168P
2.2
Comparison Between ATmega48P, ATmega88P and ATmega168P
The ATmega48P, ATmega88P and ATmega168P differ only in memory sizes, boot loader
support, and interrupt vector sizes. Table 2-1 summarizes the different memory and interrupt
vector sizes for the three devices.
Table 2-1.
Memory Size Summary
Device
Flash
EEPROM
RAM
Interrupt Vector Size
ATmega48P
4KBytes
256Bytes
512Bytes
1 instruction word/vector
ATmega88P
8KBytes
512Bytes
1KBytes
1 instruction word/vector
ATmega168P
16KBytes
512Bytes
1KBytes
2 instruction words/vector
ATmega88P and ATmega168P support a real Read-While-Write Self-Programming mechanism.
There is a separate Boot Loader Section, and the SPM instruction can only execute from there.
In ATmega48P, there is no Read-While-Write support and no separate Boot Loader Section.
The SPM instruction can execute from the entire Flash.
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8025NS–AVR–11/2015
ATmega48P/88P/168P
3.
Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
Note:
4.
1.
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
5.
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler
documentation for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
6.
Capacitive touch sensing
The Atmel® QTouch® Library provides a simple to use solution to realize touch sensitive
interfaces on most Atmel AVR® microcontrollers. The QTouch Library includes support for the
QTouch and QMatrix® acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library
for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch
channels and sensors, and then calling the touch sensing API’s to retrieve the channel
information and determine the touch sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the
Atmel QTouch Library User Guide - also available for download from the Atmel website.
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ATmega48P/88P/168P
7.
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(0xFF)
Reserved
–
–
–
–
–
–
–
–
(0xFE)
Reserved
–
–
–
–
–
–
–
–
(0xFD)
Reserved
–
–
–
–
–
–
–
–
(0xFC)
Reserved
–
–
–
–
–
–
–
–
(0xFB)
Reserved
–
–
–
–
–
–
–
–
(0xFA)
Reserved
–
–
–
–
–
–
–
–
(0xF9)
Reserved
–
–
–
–
–
–
–
–
(0xF8)
Reserved
–
–
–
–
–
–
–
–
(0xF7)
Reserved
–
–
–
–
–
–
–
–
(0xF6)
Reserved
–
–
–
–
–
–
–
–
(0xF5)
Reserved
–
–
–
–
–
–
–
–
(0xF4)
Reserved
–
–
–
–
–
–
–
–
(0xF3)
Reserved
–
–
–
–
–
–
–
–
(0xF2)
Reserved
–
–
–
–
–
–
–
–
(0xF1)
Reserved
–
–
–
–
–
–
–
–
(0xF0)
Reserved
–
–
–
–
–
–
–
–
(0xEF)
Reserved
–
–
–
–
–
–
–
–
(0xEE)
Reserved
–
–
–
–
–
–
–
–
(0xED)
Reserved
–
–
–
–
–
–
–
–
(0xEC)
Reserved
–
–
–
–
–
–
–
–
(0xEB)
Reserved
–
–
–
–
–
–
–
–
(0xEA)
Reserved
–
–
–
–
–
–
–
–
(0xE9)
Reserved
–
–
–
–
–
–
–
–
(0xE8)
Reserved
–
–
–
–
–
–
–
–
(0xE7)
Reserved
–
–
–
–
–
–
–
–
(0xE6)
Reserved
–
–
–
–
–
–
–
–
(0xE5)
Reserved
–
–
–
–
–
–
–
–
(0xE4)
Reserved
–
–
–
–
–
–
–
–
(0xE3)
Reserved
–
–
–
–
–
–
–
–
(0xE2)
Reserved
–
–
–
–
–
–
–
–
(0xE1)
Reserved
–
–
–
–
–
–
–
–
(0xE0)
Reserved
–
–
–
–
–
–
–
–
(0xDF)
Reserved
–
–
–
–
–
–
–
–
(0xDE)
Reserved
–
–
–
–
–
–
–
–
(0xDD)
Reserved
–
–
–
–
–
–
–
–
(0xDC)
Reserved
–
–
–
–
–
–
–
–
(0xDB)
Reserved
–
–
–
–
–
–
–
–
(0xDA)
Reserved
–
–
–
–
–
–
–
–
(0xD9)
Reserved
–
–
–
–
–
–
–
–
(0xD8)
Reserved
–
–
–
–
–
–
–
–
(0xD7)
Reserved
–
–
–
–
–
–
–
–
(0xD6)
Reserved
–
–
–
–
–
–
–
–
(0xD5)
Reserved
–
–
–
–
–
–
–
–
(0xD4)
Reserved
–
–
–
–
–
–
–
–
(0xD3)
Reserved
–
–
–
–
–
–
–
–
(0xD2)
Reserved
–
–
–
–
–
–
–
–
(0xD1)
Reserved
–
–
–
–
–
–
–
–
(0xD0)
Reserved
–
–
–
–
–
–
–
–
(0xCF)
Reserved
–
–
–
–
–
–
–
–
(0xCE)
Reserved
–
–
–
–
–
–
–
–
(0xCD)
Reserved
–
–
–
–
–
–
–
–
(0xCC)
Reserved
–
–
–
–
–
–
–
–
(0xCB)
Reserved
–
–
–
–
–
–
–
–
(0xCA)
Reserved
–
–
–
–
–
–
–
–
(0xC9)
Reserved
–
–
–
–
–
–
–
–
(0xC8)
Reserved
–
–
–
–
–
–
–
–
(0xC7)
Reserved
–
–
–
–
–
–
–
–
(0xC6)
UDR0
(0xC5)
UBRR0H
USART I/O Data Register
Page
197
USART Baud Rate Register High
201
(0xC4)
UBRR0L
(0xC3)
Reserved
–
–
–
USART Baud Rate Register Low
–
–
–
–
–
201
(0xC2)
UCSR0C
UMSEL01
UMSEL00
UPM01
UPM00
USBS0
UCSZ01 /UDORD0
UCSZ00 / UCPHA0
UCPOL0
199/214
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ATmega48P/88P/168P
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xC1)
UCSR0B
RXCIE0
TXCIE0
UDRIE0
RXEN0
TXEN0
UCSZ02
RXB80
TXB80
198
(0xC0)
UCSR0A
RXC0
TXC0
UDRE0
FE0
DOR0
UPE0
U2X0
MPCM0
197
(0xBF)
Reserved
–
–
–
–
–
–
–
–
–
(0xBE)
Reserved
–
–
–
–
–
–
–
(0xBD)
TWAMR
TWAM6
TWAM5
TWAM4
TWAM3
TWAM2
TWAM1
TWAM0
–
248
(0xBC)
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
244
(0xBB)
TWDR
(0xBA)
TWAR
TWA6
TWA5
TWA4
TWS7
TWS6
TWS5
2-wire Serial Interface Data Register
(0xB9)
TWSR
(0xB8)
TWBR
(0xB7)
Reserved
–
(0xB6)
ASSR
–
(0xB5)
Reserved
–
247
TWA3
TWA2
TWA1
TWA0
TWGCE
248
TWS4
TWS3
–
TWPS1
TWPS0
247
2-wire Serial Interface Bit Rate Register
244
–
–
–
–
–
–
EXCLK
AS2
TCN2UB
OCR2AUB
OCR2BUB
TCR2AUB
TCR2BUB
–
–
–
–
–
–
–
167
(0xB4)
OCR2B
Timer/Counter2 Output Compare Register B
165
(0xB3)
OCR2A
Timer/Counter2 Output Compare Register A
165
(0xB2)
TCNT2
(0xB1)
TCCR2B
FOC2A
FOC2B
–
Timer/Counter2 (8-bit)
–
WGM22
CS22
CS21
CS20
165
164
(0xB0)
TCCR2A
COM2A1
COM2A0
COM2B1
COM2B0
–
–
WGM21
WGM20
161
(0xAF)
Reserved
–
–
–
–
–
–
–
–
(0xAE)
Reserved
–
–
–
–
–
–
–
–
(0xAD)
Reserved
–
–
–
–
–
–
–
–
(0xAC)
Reserved
–
–
–
–
–
–
–
–
(0xAB)
Reserved
–
–
–
–
–
–
–
–
(0xAA)
Reserved
–
–
–
–
–
–
–
–
(0xA9)
Reserved
–
–
–
–
–
–
–
–
(0xA8)
Reserved
–
–
–
–
–
–
–
–
(0xA7)
Reserved
–
–
–
–
–
–
–
–
(0xA6)
Reserved
–
–
–
–
–
–
–
–
(0xA5)
Reserved
–
–
–
–
–
–
–
–
(0xA4)
Reserved
–
–
–
–
–
–
–
–
(0xA3)
Reserved
–
–
–
–
–
–
–
–
(0xA2)
Reserved
–
–
–
–
–
–
–
–
(0xA1)
Reserved
–
–
–
–
–
–
–
–
(0xA0)
Reserved
–
–
–
–
–
–
–
–
(0x9F)
Reserved
–
–
–
–
–
–
–
–
(0x9E)
Reserved
–
–
–
–
–
–
–
–
(0x9D)
Reserved
–
–
–
–
–
–
–
–
(0x9C)
Reserved
–
–
–
–
–
–
–
–
(0x9B)
Reserved
–
–
–
–
–
–
–
–
(0x9A)
Reserved
–
–
–
–
–
–
–
–
(0x99)
Reserved
–
–
–
–
–
–
–
–
(0x98)
Reserved
–
–
–
–
–
–
–
–
(0x97)
Reserved
–
–
–
–
–
–
–
–
(0x96)
Reserved
–
–
–
–
–
–
–
–
(0x95)
Reserved
–
–
–
–
–
–
–
–
(0x94)
Reserved
–
–
–
–
–
–
–
–
(0x93)
Reserved
–
–
–
–
–
–
–
–
(0x92)
Reserved
–
–
–
–
–
–
–
–
(0x91)
Reserved
–
–
–
–
–
–
–
–
(0x90)
Reserved
–
–
–
–
–
–
–
–
(0x8F)
Reserved
–
–
–
–
–
–
–
–
(0x8E)
Reserved
–
–
–
–
–
–
–
–
(0x8D)
Reserved
–
–
–
–
–
–
–
–
(0x8C)
Reserved
–
–
–
–
–
–
–
–
(0x8B)
OCR1BH
Timer/Counter1 - Output Compare Register B High Byte
141
(0x8A)
OCR1BL
Timer/Counter1 - Output Compare Register B Low Byte
141
(0x89)
OCR1AH
Timer/Counter1 - Output Compare Register A High Byte
141
(0x88)
OCR1AL
Timer/Counter1 - Output Compare Register A Low Byte
141
(0x87)
ICR1H
Timer/Counter1 - Input Capture Register High Byte
142
(0x86)
ICR1L
Timer/Counter1 - Input Capture Register Low Byte
142
(0x85)
TCNT1H
Timer/Counter1 - Counter Register High Byte
141
(0x84)
TCNT1L
Timer/Counter1 - Counter Register Low Byte
141
(0x83)
Reserved
–
–
–
–
–
–
–
(0x82)
TCCR1C
FOC1A
FOC1B
–
–
–
–
–
–
140
(0x81)
TCCR1B
ICNC1
ICES1
–
WGM13
WGM12
CS12
CS11
CS10
139
(0x80)
TCCR1A
COM1A1
COM1A0
COM1B1
COM1B0
–
–
WGM11
WGM10
136
–
10
8025NS–AVR–11/2015
ATmega48P/88P/168P
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(0x7F)
DIDR1
–
–
–
–
–
–
AIN1D
AIN0D
253
(0x7E)
DIDR0
–
–
ADC5D
ADC4D
ADC3D
ADC2D
ADC1D
ADC0D
270
(0x7D)
Reserved
–
–
–
–
–
–
–
–
(0x7C)
ADMUX
REFS1
REFS0
ADLAR
–
MUX3
MUX2
MUX1
MUX0
266
(0x7B)
ADCSRB
–
ACME
–
–
–
ADTS2
ADTS1
ADTS0
269
(0x7A)
ADCSRA
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
267
(0x79)
ADCH
ADC Data Register High byte
269
(0x78)
ADCL
ADC Data Register Low byte
269
(0x77)
Reserved
–
–
–
–
–
–
–
–
(0x76)
Reserved
–
–
–
–
–
–
–
–
(0x75)
Reserved
–
–
–
–
–
–
–
–
(0x74)
Reserved
–
–
–
–
–
–
–
–
(0x73)
Reserved
–
–
–
–
–
–
–
–
(0x72)
Reserved
–
–
–
–
–
–
–
–
(0x71)
Reserved
–
–
–
–
–
–
–
–
(0x70)
TIMSK2
–
–
–
–
–
OCIE2B
OCIE2A
TOIE2
166
(0x6F)
TIMSK1
–
–
ICIE1
–
–
OCIE1B
OCIE1A
TOIE1
142
(0x6E)
TIMSK0
–
–
–
–
–
OCIE0B
OCIE0A
TOIE0
113
(0x6D)
PCMSK2
PCINT23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
PCINT17
PCINT16
76
(0x6C)
PCMSK1
–
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT9
PCINT8
76
(0x6B)
PCMSK0
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
76
(0x6A)
Reserved
–
–
–
–
–
–
–
–
(0x69)
EICRA
–
–
–
–
ISC11
ISC10
ISC01
ISC00
(0x68)
PCICR
–
–
–
–
–
PCIE2
PCIE1
PCIE0
(0x67)
Reserved
–
–
–
–
–
–
–
–
(0x66)
OSCCAL
(0x65)
Reserved
–
–
–
–
–
–
–
–
(0x64)
PRR
PRTWI
PRTIM2
PRTIM0
–
PRTIM1
PRSPI
PRUSART0
PRADC
(0x63)
Reserved
–
–
–
–
–
–
–
–
(0x62)
Reserved
–
–
–
–
–
–
–
–
(0x61)
CLKPR
CLKPCE
–
–
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
38
(0x60)
WDTCSR
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
55
0x3F (0x5F)
SREG
I
T
H
S
V
N
Z
C
10
0x3E (0x5E)
SPH
–
–
–
–
–
(SP10) 5.
SP9
SP8
13
0x3D (0x5D)
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
13
0x3C (0x5C)
Reserved
–
–
–
–
–
–
–
–
0x3B (0x5B)
Reserved
–
–
–
–
–
–
–
–
0x3A (0x5A)
Reserved
–
–
–
–
–
–
–
–
0x39 (0x59)
Reserved
–
–
–
–
–
–
–
–
0x38 (0x58)
Reserved
–
–
–
–
–
–
–
–
0x37 (0x57)
SPMCSR
SPMIE
(RWWSB)5.
–
(RWWSRE)5.
BLBSET
PGWRT
PGERS
SELFPRGEN
0x36 (0x56)
Reserved
–
–
–
–
–
–
–
–
0x35 (0x55)
MCUCR
–
BODS
BODSE
PUD
–
–
IVSEL
IVCE
0x34 (0x54)
MCUSR
–
–
–
–
WDRF
BORF
EXTRF
PORF
55
0x33 (0x53)
SMCR
–
–
–
–
SM2
SM1
SM0
SE
41
0x32 (0x52)
Reserved
–
–
–
–
–
–
–
–
0x31 (0x51)
Reserved
–
–
–
–
–
–
–
–
0x30 (0x50)
ACSR
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
0x2F (0x4F)
Reserved
–
–
–
–
–
–
–
–
0x2E (0x4E)
SPDR
0x2D (0x4D)
SPSR
SPIF
WCOL
–
–
–
–
–
SPI2X
177
0x2C (0x4C)
SPCR
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
176
0x2B (0x4B)
GPIOR2
General Purpose I/O Register 2
0x2A (0x4A)
GPIOR1
General Purpose I/O Register 1
0x29 (0x49)
Reserved
0x28 (0x48)
OCR0B
Timer/Counter0 Output Compare Register B
0x27 (0x47)
OCR0A
Timer/Counter0 Output Compare Register A
0x26 (0x46)
TCNT0
0x25 (0x45)
TCCR0B
FOC0A
FOC0B
–
–
WGM02
CS02
CS01
CS00
0x24 (0x44)
TCCR0A
COM0A1
COM0A0
COM0B1
COM0B0
–
–
WGM01
WGM00
0x23 (0x43)
GTCCR
TSM
–
–
–
–
–
PSRASY
PSRSYNC
0x22 (0x42)
EEARH
(EEPROM Address Register High Byte) 5.
0x21 (0x41)
EEARL
EEPROM Address Register Low Byte
22
0x20 (0x40)
EEDR
EEPROM Data Register
22
0x1F (0x3F)
EECR
0x1E (0x3E)
GPIOR0
Oscillator Calibration Register
–
–
–
72
38
SPI Data Register
–
Page
43
296
45/69/94
251
178
26
26
–
–
–
–
Timer/Counter0 (8-bit)
–
–
EEPM1
EEPM0
EERIE
General Purpose I/O Register 0
146/168
22
EEMPE
EEPE
EERE
22
26
11
8025NS–AVR–11/2015
ATmega48P/88P/168P
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x1D (0x3D)
EIMSK
–
–
–
–
–
–
INT1
INT0
74
0x1C (0x3C)
EIFR
–
–
–
–
–
–
INTF1
INTF0
74
0x1B (0x3B)
PCIFR
–
–
–
–
–
PCIF2
PCIF1
PCIF0
0x1A (0x3A)
Reserved
–
–
–
–
–
–
–
–
0x19 (0x39)
Reserved
–
–
–
–
–
–
–
–
0x18 (0x38)
Reserved
–
–
–
–
–
–
–
–
0x17 (0x37)
TIFR2
–
–
–
–
–
OCF2B
OCF2A
TOV2
166
0x16 (0x36)
TIFR1
–
–
ICF1
–
–
OCF1B
OCF1A
TOV1
143
0x15 (0x35)
TIFR0
–
–
–
–
–
OCF0B
OCF0A
TOV0
0x14 (0x34)
Reserved
–
–
–
–
–
–
–
–
0x13 (0x33)
Reserved
–
–
–
–
–
–
–
–
0x12 (0x32)
Reserved
–
–
–
–
–
–
–
–
0x11 (0x31)
Reserved
–
–
–
–
–
–
–
–
0x10 (0x30)
Reserved
–
–
–
–
–
–
–
–
0x0F (0x2F)
Reserved
–
–
–
–
–
–
–
–
0x0E (0x2E)
Reserved
–
–
–
–
–
–
–
–
0x0D (0x2D)
Reserved
–
–
–
–
–
–
–
–
0x0C (0x2C)
Reserved
–
–
–
–
–
–
–
–
0x0B (0x2B)
PORTD
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
95
0x0A (0x2A)
DDRD
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
95
0x09 (0x29)
PIND
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
95
0x08 (0x28)
PORTC
–
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
94
0x07 (0x27)
DDRC
–
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
94
94
0x06 (0x26)
PINC
–
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
0x05 (0x25)
PORTB
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
94
0x04 (0x24)
DDRB
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
94
0x03 (0x23)
PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
94
0x02 (0x22)
Reserved
–
–
–
–
–
–
–
–
0x01 (0x21)
Reserved
–
–
–
–
–
–
–
–
0x0 (0x20)
Reserved
–
–
–
–
–
–
–
–
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega48P/88P/168P
is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for
the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
5. Only valid for ATmega88P/168P.
12
8025NS–AVR–11/2015
ATmega48P/88P/168P
8.
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
Rd  Rd + Rr
Z,C,N,V,H
ADC
Rd, Rr
Add with Carry two Registers
Rd  Rd + Rr + C
Z,C,N,V,H
1
ADIW
Rdl,K
Add Immediate to Word
Rdh:Rdl  Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract two Registers
Rd  Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract Constant from Register
Rd  Rd - K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry two Registers
Rd  Rd - Rr - C
Z,C,N,V,H
1
1
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd  Rd - K - C
Z,C,N,V,H
1
SBIW
Rdl,K
Subtract Immediate from Word
Rdh:Rdl  Rdh:Rdl - K
Z,C,N,V,S
2
1
AND
Rd, Rr
Logical AND Registers
Rd Rd  Rr
Z,N,V
ANDI
Rd, K
Logical AND Register and Constant
Rd  Rd K
Z,N,V
1
OR
Rd, Rr
Logical OR Registers
Rd  Rd v Rr
Z,N,V
1
ORI
Rd, K
Logical OR Register and Constant
Rd Rd v K
Z,N,V
1
EOR
Rd, Rr
Exclusive OR Registers
Rd  Rd  Rr
Z,N,V
1
COM
Rd
One’s Complement
Rd  0xFF  Rd
Z,C,N,V
1
NEG
Rd
Two’s Complement
Rd  0x00  Rd
Z,C,N,V,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd  Rd v K
Z,N,V
1
CBR
Rd,K
Clear Bit(s) in Register
Rd  Rd  (0xFF - K)
Z,N,V
1
INC
Rd
Increment
Rd  Rd + 1
Z,N,V
1
DEC
Rd
Decrement
Rd  Rd  1
Z,N,V
1
TST
Rd
Test for Zero or Minus
Rd  Rd  Rd
Z,N,V
1
CLR
Rd
Clear Register
Rd  Rd  Rd
Z,N,V
1
SER
Rd
Set Register
Rd  0xFF
None
1
MUL
Rd, Rr
Multiply Unsigned
R1:R0  Rd x Rr
Z,C
2
MULS
Rd, Rr
Multiply Signed
R1:R0  Rd x Rr
Z,C
2
MULSU
Rd, Rr
Multiply Signed with Unsigned
R1:R0  Rd x Rr
Z,C
2
FMUL
Rd, Rr
Fractional Multiply Unsigned
R1:R0  (Rd x Rr) << 1
Z,C
2
FMULS
Rd, Rr
Fractional Multiply Signed
R1:R0  (Rd x Rr) << 1
Z,C
2
FMULSU
Rd, Rr
Fractional Multiply Signed with Unsigned
R1:R0  (Rd x Rr) << 1
Z,C
2
Relative Jump
PC PC + k + 1
None
2
Indirect Jump to (Z)
PC  Z
None
2
3
BRANCH INSTRUCTIONS
RJMP
k
IJMP
JMP(1)
k
Direct Jump
PC k
None
RCALL
k
Relative Subroutine Call
PC  PC + k + 1
None
3
Indirect Call to (Z)
PC  Z
None
3
ICALL
Direct Subroutine Call
PC  k
None
4
RET
Subroutine Return
PC  STACK
None
4
RETI
Interrupt Return
PC  STACK
I
if (Rd = Rr) PC PC + 2 or 3
None
CALL(1)
k
4
CPSE
Rd,Rr
Compare, Skip if Equal
1/2/3
CP
Rd,Rr
Compare
Rd  Rr
Z, N,V,C,H
1
CPC
Rd,Rr
Compare with Carry
Rd  Rr  C
Z, N,V,C,H
1
CPI
Rd,K
Compare Register with Immediate
Rd  K
Z, N,V,C,H
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC  PC + 2 or 3
None
1
1/2/3
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC  PC + 2 or 3
None
1/2/3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b)=0) PC  PC + 2 or 3
None
1/2/3
SBIS
P, b
Skip if Bit in I/O Register is Set
if (P(b)=1) PC  PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PCPC+k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PCPC+k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC  PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC  PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC  PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC  PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC  PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC  PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC  PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC  PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N  V= 0) then PC  PC + k + 1
None
1/2
BRLT
k
Branch if Less Than Zero, Signed
if (N  V= 1) then PC  PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC  PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC  PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC  PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC  PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC  PC + k + 1
None
1/2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC  PC + k + 1
None
1/2
13
8025NS–AVR–11/2015
ATmega48P/88P/168P
Mnemonics
Operands
Description
Operation
Flags
#Clocks
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC  PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC  PC + k + 1
None
1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
I/O(P,b)  1
None
2
CBI
P,b
Clear Bit in I/O Register
I/O(P,b)  0
None
2
LSL
Rd
Logical Shift Left
Rd(n+1)  Rd(n), Rd(0)  0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n)  Rd(n+1), Rd(7)  0
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0)C,Rd(n+1) Rd(n),CRd(7)
Z,C,N,V
1
ROR
Rd
Rotate Right Through Carry
Rd(7)C,Rd(n) Rd(n+1),CRd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n)  Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s)  1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s)  0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T  Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b)  T
None
1
1
SEC
Set Carry
C1
C
CLC
Clear Carry
C0
C
1
SEN
Set Negative Flag
N1
N
1
CLN
Clear Negative Flag
N0
N
1
SEZ
Set Zero Flag
Z1
Z
1
CLZ
Clear Zero Flag
Z0
Z
1
SEI
Global Interrupt Enable
I1
I
1
CLI
Global Interrupt Disable
I 0
I
1
1
SES
Set Signed Test Flag
S1
S
CLS
Clear Signed Test Flag
S0
S
1
SEV
Set Twos Complement Overflow.
V1
V
1
CLV
Clear Twos Complement Overflow
V0
V
1
SET
Set T in SREG
T1
T
1
CLT
Clear T in SREG
T0
T
1
SEH
CLH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H1
H0
H
H
1
1
None
1
None
1
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move Between Registers
MOVW
Rd, Rr
Copy Register Word
Rd  Rr
Rd+1:Rd  Rr+1:Rr
LDI
Rd, K
Load Immediate
Rd  K
None
1
LD
Rd, X
Load Indirect
Rd  (X)
None
2
LD
Rd, X+
Load Indirect and Post-Inc.
Rd  (X), X  X + 1
None
2
LD
Rd, - X
Load Indirect and Pre-Dec.
X  X - 1, Rd  (X)
None
2
2
LD
Rd, Y
Load Indirect
Rd  (Y)
None
LD
Rd, Y+
Load Indirect and Post-Inc.
Rd  (Y), Y  Y + 1
None
2
LD
Rd, - Y
Load Indirect and Pre-Dec.
Y  Y - 1, Rd  (Y)
None
2
LDD
Rd,Y+q
Load Indirect with Displacement
Rd  (Y + q)
None
2
LD
Rd, Z
Load Indirect
Rd  (Z)
None
2
LD
Rd, Z+
Load Indirect and Post-Inc.
Rd  (Z), Z  Z+1
None
2
LD
Rd, -Z
Load Indirect and Pre-Dec.
Z  Z - 1, Rd  (Z)
None
2
LDD
Rd, Z+q
Load Indirect with Displacement
Rd  (Z + q)
None
2
2
LDS
Rd, k
Load Direct from SRAM
Rd  (k)
None
ST
X, Rr
Store Indirect
(X) Rr
None
2
ST
X+, Rr
Store Indirect and Post-Inc.
(X) Rr, X  X + 1
None
2
ST
- X, Rr
Store Indirect and Pre-Dec.
X  X - 1, (X)  Rr
None
2
ST
Y, Rr
Store Indirect
(Y)  Rr
None
2
ST
Y+, Rr
Store Indirect and Post-Inc.
(Y)  Rr, Y  Y + 1
None
2
ST
- Y, Rr
Store Indirect and Pre-Dec.
Y  Y - 1, (Y)  Rr
None
2
STD
Y+q,Rr
Store Indirect with Displacement
(Y + q)  Rr
None
2
ST
Z, Rr
Store Indirect
(Z)  Rr
None
2
ST
Z+, Rr
Store Indirect and Post-Inc.
(Z)  Rr, Z  Z + 1
None
2
ST
-Z, Rr
Store Indirect and Pre-Dec.
Z  Z - 1, (Z)  Rr
None
2
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q)  Rr
None
2
STS
k, Rr
Store Direct to SRAM
(k)  Rr
None
2
Load Program Memory
R0  (Z)
None
3
LPM
LPM
Rd, Z
Load Program Memory
Rd  (Z)
None
3
LPM
Rd, Z+
Load Program Memory and Post-Inc
Rd  (Z), Z  Z+1
None
3
Store Program Memory
(Z)  R1:R0
None
-
In Port
Rd  P
None
1
SPM
IN
Rd, P
OUT
P, Rr
Out Port
P  Rr
None
1
PUSH
Rr
Push Register on Stack
STACK  Rr
None
2
14
8025NS–AVR–11/2015
ATmega48P/88P/168P
Mnemonics
POP
Operands
Rd
Description
Pop Register from Stack
Operation
Rd  STACK
Flags
#Clocks
None
2
MCU CONTROL INSTRUCTIONS
NOP
No Operation
None
1
SLEEP
Sleep
(see specific descr. for Sleep function)
None
1
WDR
BREAK
Watchdog Reset
Break
(see specific descr. for WDR/timer)
For On-chip Debug Only
None
None
1
N/A
Note:
1. These instructions are only available in ATmega168P.
15
8025NS–AVR–11/2015
ATmega48P/88P/168P
9.
Ordering Information
9.1
ATmega48P
Speed (MHz)
10(3)
20(3)
Note:
Ordering Code(2)
Package(1)
1.8 - 5.5
ATmega48PV-10AU
ATmega48PV-10AUR(4)
ATmega48PV-10MMU
ATmega48PV-10MMUR(4)
ATmega48PV-10MU
ATmega48PV-10MUR(4)
ATmega48PV-10PU
32A
32A
28M1
28M1
32M1-A
32M1-A
28P3
2.7 - 5.5
ATmega48P-20AU
ATmega48P-20AUR(4)
ATmega48P-20MMU
ATmega48P-20MMUR(4)
ATmega48P-20MU
ATmega48P-20MUR(4)
ATmega48P-20PU
32A
32A
28M1
28M1
32M1-A
32M1-A
28P3
Power Supply (V)
Operational Range
Industrial
(-40C to 85C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See Figure 29-1 on page 319 and Figure 29-2 on page 320.
4. Tape & Reel
Package Type
32A
32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
28M1
28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
32M1-A
32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
28P3
28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
16
8025NS–AVR–11/2015
ATmega48P/88P/168P
9.2
ATmega88P
Speed (MHz)
10(3)
20(3)
Note:
Ordering Code(2)
Package(1)
1.8 - 5.5
ATmega88PV-10AU
ATmega88PV-10AUR(4)
ATmega88PV-10MU
ATmega88PV-10MUR(4)
ATmega88PV-10PU
32A
32A
32M1-A
32M1-A
28P3
2.7 - 5.5
ATmega88P-20AU
ATmega88P-20AUR(4)
ATmega88P-20MU
ATmega88P-20MUR(4)
ATmega88P-20PU
32A
32A
32M1-A
32M1-A
28P3
Power Supply (V)
Operational Range
Industrial
(-40C to 85C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See Figure 29-1 on page 319 and Figure 29-2 on page 320.
4. Taper & Reel.
Package Type
32A
32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
28P3
28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
32M1-A
32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
17
8025NS–AVR–11/2015
ATmega48P/88P/168P
9.3
ATmega168P
Speed (MHz)(3)
10
20
Note:
Ordering Code(2)
Package(1)
1.8 - 5.5
ATmega168PV-10AU
ATmega168PV-10AUR(4)
ATmega168PV-10MU
ATmega168PV-10MUR(4)
ATmega168PV-10PU
32A
32A
32M1-A
32M1-A
28P3
2.7 - 5.5
ATmega168P-20AU
ATmega168P-20AUR(4)
ATmega168P-20MU
ATmega168P-20MUR(4)
ATmega168P-20PU
32A
32A
32M1-A
32M1-A
28P3
Power Supply (V)
Operational Range
Industrial
(-40C to 85C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See Figure 29-1 on page 319 and Figure 29-2 on page 320.
4. Taper & Reel.
Package Type
32A
32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
28P3
28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
32M1-A
32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
18
8025NS–AVR–11/2015
ATmega48P/88P/168P
10.
Packaging Information
10.1
32A
PIN 1 IDENTIFIER
PIN 1
e
B
E1
E
D1
D
C
0°~7°
A1
A2
A
L
COMMON DIMENSIONS
(Unit of measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ABA.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
8.75
9.00
9.25
D1
6.90
7.00
7.10
E
8.75
9.00
9.25
E1
6.90
7.00
7.10
B
0.30
–
0.45
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.80 TYP
2010-10-20
TITLE
32A, 32-lead, 7 x 7mm body size, 1.0mm body thickness,
0.8mm lead pitch, thin profile plastic quad flat package (TQFP)
DRAWING NO.
32A
REV.
C
19
8025NS–AVR–11/2015
ATmega48P/88P/168P
10.2
28M1
D
C
1
2
Pin 1 ID
3
E
SIDE VIEW
A1
TOP VIEW
A
y
D2
K
1
0.45
2
R 0.20
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
NOM
MAX
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
b
0.17
0.22
0.27
SYMBOL
3
E2
b
C
L
e
0.4 Ref
(4x)
The terminal #1 ID is a Laser-marked Feature.
Note:
0.20 REF
D
3.95
4.00
4.05
D2
2.35
2.40
2.45
E
3.95
4.00
4.05
E2
2.35
2.40
2.45
e
BOTTOM VIEW
NOT E
0.45
L
0.35
0.40
0.45
y
0.00
–
0.08
K
0.20
–
–
10/24/08
Package Drawing Contact:
[email protected]
TITLE
28M1, 28-pad, 4 x 4 x 1.0mm Body, Lead Pitch 0.45mm,
2.4 x 2.4mm Exposed Pad, Thermally Enhanced
Plastic Very Thin Quad Flat No Lead Package (VQFN)
GPC
ZBV
DRAWING NO.
28M1
REV.
B
20
8025NS–AVR–11/2015
ATmega48P/88P/168P
10.3
32M1-A
D
D1
1
2
3
0
Pin 1 ID
E1
SIDE VIEW
E
TOP VIEW
A3
A2
A1
A
K
0.08 C
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
A
P
D2
1
2
3
P
Pin #1 Notch
(0.20 R)
K
e
0.90
1.00
–
0.02
0.05
A2
–
0.65
1.00
A3
E2
b
0.80
A1
L
BOTTOM VIEW
0.20 REF
b
0.18
0.23
0.30
D
4.90
5.00
5.10
D1
4.70
4.75
4.80
D2
2.95
3.10
3.25
E
4.90
5.00
5.10
E1
4.70
4.75
4.80
E2
2.95
3.10
3.25
e
Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.
NOTE
0.50 BSC
L
0.30
0.40
0.50
P
–
–
0.60
12o
0
–
–
K
0.20
–
–
03/14/2014
32M1-A , 32-pad, 5 x 5 x 1.0mm Body, Lead Pitch 0.50mm,
3.10mm Exposed Pad, Micro Lead Frame Package (MLF)
32M1-A
F
21
8025NS–AVR–11/2015
ATmega48P/88P/168P
10.4
28P3
D
PIN
1
E1
A
SEATING PLANE
L
B2
B1
B
A1
(4 PLACES)
e
E
0º ~ 15º
C
COMMON DIMENSIONS
(Unit of Measure = mm)
REF
MIN
NOM
MAX
A
–
–
4.5724
A1
0.508
–
–
D
34.544
–
E
7.620
–
8.255
E1
7.112
–
7.493
B
0.381
–
0.533
B1
1.143
–
1.397
SYMBOL
eB
Note:
1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25mm (0.010").
34.798 Note 1
B2
0.762
–
1.143
L
3.175
–
3.429
C
0.203
–
0.356
eB
–
–
10.160
e
NOTE
Note 1
2.540 TYP
09/28/01
2325 Orchard Parkway
San Jose, CA 95131
TITLE
28P3, 28-lead (0.300"/7.62mm Wide) Plastic Dual
Inline Package (PDIP)
DRAWING NO.
28P3
REV.
B
22
8025NS–AVR–11/2015
ATmega48P/88P/168P
11.
Errata
11.1
Errata ATmega48P
The revision letter in this section refers to the revision of the ATmega48P device.
11.1.1 Rev. K
•
•
•
•
Full swing crystal oscillator not supported
Power save mode current consumption increased
Parallel programming timing modified
Write wait delay for NVM is increased
1. Full swing crystal oscillator not supported
The full swing crystal oscillator functionality is not available in revision K.
Problem fix/Workaround:
Use alternative clock sources available in the device.
2. Power save mode current consumption increased
Current consumption in power save mode has increased as follow:
Previous die revision –
ATmega48P only
Symbol
Parameter
Condition
Icc
Power-save
mode(1)(2)
32 kHz
TOSC
enable,
Vcc = 1.8V
Notes:
1.
2.
Min
Typ.
Max
Units
0.75
1.6
µA
New die revision –
ATmega48P only
Min
Typ.
Max
Units
1.4
1.9
µA
The current consumption values include input leakage current.
Maximum values are characterized values and not test limits in production.
3. Parallel programming timing modified
The parallel programming timing is modified as follows:
Previous die revision
Symbol
Parameter
Min
tWLRH_CE
/WR Low to
RDY/BSY
High for Chip
Erase
tBVDV
/BS1 Valid to
DATA valid
tOLDV
/OE Low to
DATA Valid
Typ.
Revision K
Max
Units
Min
7.5
9
ms
0
250
ns
250
ns
Typ.
Max
Units
9.8
10.5
ms
0
335
ns
335
ns
4. Write wait delay for NVM is increased
23
8025NS–AVR–11/2015
ATmega48P/88P/168P
The write delay for non-volatile memory (NWM) is increased as follows:
Other revisions
Revision K
Symbol
Minimum Wait Delay
Minimum Wait Delay
tWD_ERASE
9ms
10.5ms
11.1.2 Rev. D to J
Not sampled.
11.1.3 Rev. C
No known errata.
11.1.4 Rev. B
No known errata.
11.1.5 Rev. A
Not Sampled.
11.2
Errata ATmega88P
11.2.1 The revision letter in this section refers to the revision of the ATmega88P device.Rev. K
•
•
•
•
Full swing crystal oscillator not supported
Power save mode current consumption increased
Parallel programming timing modified
Write wait delay for NVM is increased
1. Full swing crystal oscillator not supported
The full swing crystal oscillator functionality is not available in revision K.
Problem fix/Workaround:
Use alternative clock sources available in the device.
2. Power save mode current consumption increased
Current consumption in power save mode has increased as follow:
Previous die revision
Symbol
Parameter
Condition
Icc
Power-save
mode(1)(2)
32 kHz
TOSC
enable,
Vcc = 1.8V
Notes:
1.
2.
Min
Typ.
Max
Units
0.72
1.6
µA
Revision K
Min
Typ.
Max
Units
1.4
1.9
µA
The current consumption values include input leakage current.
Maximum values are characterized values and not test limits in production.
3. Parallel programming timing modified
24
8025NS–AVR–11/2015
ATmega48P/88P/168P
The parallel programming timing is modified as follows:
Previous die revision
Symbol
Parameter
Min
tWLRH_CE
/WR Low to
RDY/BSY
High for Chip
Erase
tBVDV
/BS1 Valid to
DATA valid
tOLDV
/OE Low to
DATA Valid
Typ.
Revision K
Max
Units
Min
7.5
9
ms
0
250
ns
250
ns
Typ.
Max
Units
9.8
10.5
ms
0
335
ns
335
ns
4. Write wait delay for NVM is increased
The write delay for non-volatile memory (NWM) is increased as follows:
Other revisions
Revision K
Symbol
Minimum Wait Delay
Minimum Wait Delay
tWD_ERASE
9ms
10.5ms
11.2.2 Rev. D to J
Not sampled.
11.2.3 Rev. C
Not sampled.
11.2.4 Rev. B
No known errata.
11.2.5 Rev. A
No known errata.
25
8025NS–AVR–11/2015
ATmega48P/88P/168P
11.3
Errata ATmega168P
The revision letter in this section refers to the revision of the ATmega168P device.
11.3.1 Rev. K
•
•
•
•
Full swing crystal oscillator not supported
Power save mode current consumption increased
Parallel programming timing modified
Write wait delay for NVM is increased
1. Full swing crystal oscillator not supported
The full swing crystal oscillator functionality is not available in revision K.
Problem fix/Workaround:
Use alternative clock sources available in the device.
2. Power save mode current consumption increased
Current consumption in power save mode has increased as follow:
Symbol
Parameter
Condition
Icc
Power-save
mode(1)(2)
32 kHz TOSC
enable, Vcc =
1.8V
Notes:
1.
2.
Previous die revision
Min Typ.
Max
Units
0.8
1.6
Min
µA
Revision K
Typ.
Max
1.4
1.9
Units
µA
The current consumption values include input leakage current.
Maximum values are characterized values and not test limits in production.
3. Parallel programming timing modified
The parallel programming timing is modified as follows:
Previous die revision
Symbol
Parameter
Min
tWLRH_CE
/WR Low to
RDY/BSY
High for Chip
Erase
tBVDV
/BS1 Valid to
DATA valid
tOLDV
/OE Low to
DATA Valid
Typ.
Revision K
Max
Units
Min
7.5
9
ms
0
250
ns
250
ns
Typ.
Max
Units
9.8
10.5
ms
0
335
ns
335
ns
4. Write wait delay for NVM is increased
The write delay for non-volatile memory (NWM) is increased as follows:
26
8025NS–AVR–11/2015
ATmega48P/88P/168P
Other revisions
Revision K
Symbol
Minimum Wait Delay
Minimum Wait Delay
tWD_ERASE
9ms
10.5ms
11.3.2 Rev. D to J
Not sampled.
11.3.3 Rev. C
No known errata.
11.3.4 Rev B
No known errata.
11.3.5 Rev A
No known errata.
27
8025NS–AVR–11/2015
ATmega48P/88P/168P
12.
Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
12.1
Rev. 8025N-11/15
Updated errata section:
1.
12.2
12.3
“Errata ATmega88P” on page 24
l
“Errata ATmega168P” on page 26
Added Atmel QTouch Library Support and QTouch Sensing Capability Features.
Updated “Ordering Information” to include Tape and Reel devices.
3.
Updated the datasheet with Atmel new style guide.
Rev. 8025L-07/10
Removed from the front page, the note “Not recommended for new design”.
Editorial updates.
Rev. 8025K-10/09
Updated “Low Frequency Crystal Oscillator” with the Table 9-8 on page 33.
Editorial updates.
Rev. 8025J-05/09
1.
2.
3.
12.6
l
1.
2.
1.
2.
12.5
“Errata ATmega48P” on page 23
Rev. 8025M-06/11
1.
2.
12.4
l
Removed the “About” section.
Removed ATmega328P device and its reference from the data sheet.
Editorial updates.
Rev. 8025I-02/09
1.
Removed “preliminary” from ATmega48P/88P/168P.
28
8025NS–AVR–11/2015
ATmega48P/88P/168P
12.7
Rev. 8025H-02/09
1.
2.
3.
4.
5.
12.8
Rev. 8025G-01/09
1
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
12.9
Added Power-save Maximum values and footnote to “ATmega48P DC
Characteristics” on page 317.
Added Power-save Maximum values and footnote to “ATmega88P DC
Characteristics” on page 318.
Added Power-save Maximum values and footnote to “ATmega168P DC
Characteristics” on page 319.
Added Power-save Maximum values and footnote to “” on page 319.
Added errata for revision A, “” on page 27.
ATmega48P/88P not recommended for new designs.
Updated the footnote Note1 of the Table 9-3 on page 30.
Updated the Table 9-5 on page 31 by removing a footnote Note1.
Updated the Table 9-11 on page 34 by removing a footnote Note1.
Updated the footnote Note1 of the Table 9-13 on page 35.
Updated the footnote Note2 of the “ATmega48P DC Characteristics” on page 317
and removed TBD from the table.
Updated the footnote Note2 of the “ATmega88P DC Characteristics” on page 318
and removed TBD from the table.
Updated the footnote Note2 of the “ATmega168P DC Characteristics” on page 319
and removed TBD from the table.
Updated the footnote Note2 of the “” on page 319 and removed TBD from the table.
Updated the footnote Note1 of the Table 29-4 on page 322.
Replaced the Figure 30-69 on page 366 by a correct one.
Replaced the Figure 29-173 on page 419 by a correct one.
Updated “Errata” on page 23.
Updated ”MCUCR – MCU Control Register” on page 44.
Updated “TCCR2B – Timer/Counter Control Register B” on page 164.
Rev. 8025F-08/08
1.
2.
Updated “Register Summary” on page 9 with Power-save numbers.
Added ATmega328P ”Standby Supply Current” on page 408.
12.10 Rev. 8025E-08/08
1.
2.
3.
4.
Updated description of “Stack Pointer” on page 13.
Updated description of use of external capacitors in “Low Frequency Crystal
Oscillator” on page 33.
Updated Table 9-10 in “Low Frequency Crystal Oscillator” on page 33.
Added note to “Address Match Unit” on page 224.
29
8025NS–AVR–11/2015
ATmega48P/88P/168P
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Added section “Reading the Signature Row from Software” on page 290.
Updated “Program And Data Memory Lock Bits” on page 298 to include
ATmega328P in the description.
Added “” on page 319.
Updated “Speed Grades” on page 319 for ATmega328P.
Removed note 6 and 7 from the table “2-wire Serial Interface Characteristics” on
page 325.
Added figure “Minimum Reset Pulse width vs. VCC.” on page 354 for ATmega48P.
Added figure “Minimum Reset Pulse width vs. VCC.” on page 378 for ATmega88P.
Added figure “Minimum Reset Pulse width vs. VCC.” on page 402 for ATmega168P.
Added “Register Summary” on page 9.
Updated Ordering Information for “Packaging Information” on page 19.
12.11 Rev. 8025D-03/08
1.
2.
3.
4.
Updated figures in “Speed Grades” on page 319.
Updated note in Table 29-4 in “System and Reset Characteristics” on page 322.
Ordering codes for “Packaging Information” on page 19 updated.
- ATmega328P is offered in 20 MHz option only.
Added Errata for ATmega328P rev. B, “” on page 27.
12.12 Rev. 8025C-01/08
1.
Power-save Maximum values removed form “ATmega48P DC Characteristics” on
page 317, “ATmega88P DC Characteristics” on page 318, and “ATmega168P DC
Characteristics” on page 319.
12.13 Rev. 8025B-01/08
1.
Updated “Features” on page 1.
2.
Added “Data Retention” on page 8.
3.
Updated Table 9-2 on page 29.
4.
Removed “Low-frequency Crystal Oscillator Internal Load Capacitance“ table
from“Low Frequency Crystal Oscillator” on page 33.
5.
Removed JTD bit from “MCUCR – MCU Control Register” on page 45.
6.
7.
Updated typical and general program setup for Reset and Interrupt Vector Addresses
in “Interrupt Vectors in ATmega168P” on page 64 and ”Interrupt Vectors in
ATmega328P” on page 65.
Updated Interrupt Vectors Start Address in Table 12-5 on page 65 and Table 11-7 on
page 66.
8.
Updated “Temperature Measurement” on page 265.
9.
Updated ATmega328P “Fuse Bits” on page 299.
10.
Removed VOL3/VOH3 rows from “DC Characteristics” on page 316.
30
8025NS–AVR–11/2015
ATmega48P/88P/168P
11.
Updated condition for VOL in “DC Characteristics” on page 316.
Updated max value for VIL2 in “DC Characteristics” on page 316.
12.
Added “ATmega48P DC Characteristics” on page 317, “ATmega88P DC
Characteristics” on page 318, and “ATmega168P DC Characteristics” on page 319.
13.
Updated “System and Reset Characteristics” on page 322.
14.
Added “ATmega48P Typical Characteristics” on page 330, “ATmega88P Typical
Characteristics” on page 354, and “ATmega168P Typical Characteristics” on page
378.
15.
Updated note in “Instruction Set Summary” on page 13.
12.14 Rev. 8025A-07/07
1.
Initial revision.
31
8025NS–AVR–11/2015
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Rev. 8025NS-AVR-11/2015
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8025NS–AVR–11/2015
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