ATA663203/ATA663231/ATA663254 LIN Bus Device Family including Voltage Regulator and LIN SBC(1) with Compatible Footprint DATASHEET Features ● Supply voltage up to 40V ● Operating voltage VS = 5V to 28V ● Supply current ● Sleep mode: typically 9µA ● Silent mode: typically 47µA ● Very low current consumption at low supply voltages (2V < VS < 5.5V): typically 130µA ● Linear low-drop voltage regulator, 85mA current capability: ● MLC (multi-layer ceramic) capacitor with 0 ESR ● Normal, fail-safe, and silent mode ● Atmel® ATA663254: VCC = 5.0V ±2% ● Atmel ATA663231: VCC = 3.3V ±2% ● Sleep mode: VCC is switched off ● Active mode ● Atmel ATA663203: VCC = 5.0V ±2% ● VCC undervoltage detection with open drain reset output (NRES, 4ms reset time) ● Voltage regulator is short-circuit and over-temperature protected ● LIN physical layer according to LIN 2.0, 2.1, 2.2, 2.2A and SAEJ2602-2 ● Wake-up capability via LIN bus (100µs dominant) ● Wake-up source recognition ● TXD time-out timer ● Bus pin is over-temperature and short-circuit protected versus GND and battery ● Advanced EMC and ESD performance ● Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications Rev.1.3” ● Interference and damage protection according to ISO7637 ● Qualified according to AEC-Q100 ● Packages: ● DFN8 (all types) with wettable flanks (Moisture Sensitivity Level 1) ● SO8 (only Atmel ATA663254) Note: 1. LIN SBC: LIN system basis chip including LIN transceiver and voltage regulator. 9337F-AUTO-02/16 1. Description The Atmel® ATA6632xx device family includes two basic products; a LIN system basis chip (SBC) and a low-drop voltage regulator with compatible footprints. The Atmel ATA663231/54 (system basis chip) is a fully integrated LIN transceiver, designed according to the LIN specification 2.0, 2.1, 2.2, 2.2A and SAEJ2602-2, with a low-drop voltage regulator (3.3V/5V/85mA). The combination of voltage regulator and bus transceiver makes it possible to develop simple but powerful slave nodes in LIN bus systems. Atmel ATA663231/54 is designed to handle the low-speed data communication in vehicles (for example, in convenience electronics). Improved slope control at the LIN driver ensures secure data communication up to 20Kbaud. The bus output is designed to withstand high voltage. Sleep mode and silent mode guarantee minimized current consumption even in the case of a floating or a short-circuited LIN bus. The Atmel ATA663203 (voltage regulator) is a fully integrated low-drop voltage regulator, with 5V output voltage and 85mA current capability. It is especially designed for the automotive environment. A key feature is that the current consumption is always below 170µA (without load), even if the supply voltage is below the regulator’s nominal output voltage. Table 1-1. ATA6632xx Device Family Description Atmel ATA6632xx LIN-SBC with 3.3V regulator 31 LIN-SBC with 5V regulator 54 Voltage regulator 5V 03 Figure 1-1. Block Diagram LIN Transceiver with Integrated Voltage Regulator (SBC) Atmel ATA663231/54 VCC - 1 VS 6 LIN 8 VCC 3 NRES Normal and Fail-safe Mode Receiver RXD 7 + RF-filter VCC Wake-up bus timer TXD EN GND 4 2 5 TXD Time-out timer Short-circuit and overtemperature protection Slew rate control Sleep mode Control VCC unit switched off Voltage regulator Normal/Silent/ Fail-safe Mode 3.3V/5V Undervoltage reset 2 ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 VCC Figure 1-2. Block Diagram Voltage Regulator VS 7 PMOS Voltage Reference + 8 VCC 3 NRES Undervoltage Reset Atmel ATA663203 5 GND ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 3 2. Pin Configuration Figure 2-1. Pinning DFN8 RXD EN NRES TXD ATA663231 ATA663254 DFN8 3x3 NC NC NRES NC VCC VS LIN GND SBC ATA663203 DFN8 3x3 Voltage regulator Figure 2-2. Pinning SO8 ATA663254 RXD EN NRES TXD 1 8 2 7 SO8 3 6 4 5 Table 2-1. Pin Description Pin Symbol 1 RXD 2 EN 3 NRES 4 TXD Transmit data input 5 GND Ground, heat slug 6 LIN LIN bus line input/output 7 VS Supply voltage 8 VCC VCC VS LIN GND Function Receive data output Enables normal mode if the input is high VCC undervoltage output, open drain, low at reset Output voltage regulator 3.3V/5V/85mA (1) Backside Heat slug, internally connected to the GND pin Note: 1. Only for the DFN8 package. 4 ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 VCC VS NC GND 3. Pin Description 3.1 Supply Pin (VS) LIN operating voltage is VS = 5V to 28V. Undervoltage detection is implemented to disable transmission if VS falls below typ. 4.5V, thereby avoiding false bus messages. After switching on VS, the IC starts in fail-safe mode and the voltage regulator is switched on. The supply current in sleep mode is typically 9µA and 47µA in silent mode. 3.2 Ground Pin (GND) The IC does not affect the LIN bus in the event of GND disconnection. It is able to handle a ground shift of up to 11.5% of VS. 3.3 Voltage Regulator Output Pin (VCC) The internal 3.3V/5V voltage regulator is capable of driving loads up to 85mA, supplying the microcontroller and other ICs on the PCB and is protected against overload by means of current limitation and overtemperature shutdown. Furthermore, the output voltage is monitored and causes a reset signal at the NRES output pin if it drops below a defined threshold VVCC_th_uv_down. 3.4 Undervoltage Reset Output (NRES) If the VCC voltage falls below the undervoltage detection threshold VCC_th_uv_down, NRES switches to low after tres_f. The NRES stays low even if VCC = 0V because NRES is internally driven from the VS voltage. If VS voltage ramps down, NRES stays low until VS < 1.5V and then becomes highly impedant. The implemented undervoltage delay keeps NRES low for tReset = 4ms after VCC reaches its nominal value. 3.5 Bus Pin (LIN) (SBC only) A low-side driver with internal current limitation and thermal shutdown as well as an internal pull-up resistor according to LIN specification 2.x is implemented. The voltage range is from –27V to +40V. This pin exhibits no reverse current from the LIN bus to VS, even in the event of a GND shift or VBat disconnection. The LIN receiver thresholds comply with the LIN protocol specification. The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope-controlled. During a short circuit at LIN to VBat, the output limits the output current to IBUS_LIM. Due to the power dissipation, the chip temperature exceeds TLINoff and the LIN output is switched off. The chip cools down and after a hysteresis of Thys, switches the output on again. RXD stays on high because LIN is high. The VCC regulator works independently during LIN overtemperature switch-off. During a short circuit from LIN to GND the IC can be switched into sleep or silent mode and even in this case the current consumption is lower than 100µA in sleep mode and lower than 120µA in silent mode. If the short-circuit disappears, the IC starts with a remote wake-up. The reverse current is < 2µA at pin LIN during loss of VBat. This is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition. ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 5 3.6 Input/Output (TXD) (SBC only) In normal mode the TXD pin is the microcontroller interface for controlling the state of the LIN output. TXD must be pulled to ground in order to drive the LIN bus low. If TXD is high or unconnected (internal pull-up resistor), the LIN output transistor is turned off and the bus is in the recessive state. If the TXD pin stays at GND level while switching into normal mode, it must be pulled to high level longer than 10µs before the LIN driver can be activated. This feature prevents the bus line from being accidentally driven to dominant state after normal mode has been activated (also in case of a short circuit at TXD to GND). During fail-safe mode, this pin is used as output and signals the fail-safe source. The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in the dominant state. If TXD is forced to low longer than tdom > 20ms, the LIN bus driver is switched to the recessive state. Nevertheless, when switching to sleep mode, the actual level at the TXD pin is relevant. To reactivate the LIN bus driver, switch TXD to high (> 10µs). 3.7 Output Pin (RXD) (SBC only) In normal mode this pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is indicated by a high level at RXD; LIN low (dominant state) is indicated by a low level at RXD. The output is a push-pull stage switching between VCC and GND. The AC characteristics are measured by an external load capacitor of 20pF. In silent mode the RXD output switches to high. 3.8 Enable Input Pin (EN) (SBC only) The enable input pin controls the operating mode of the device. If EN is high, the circuit is in normal mode, with transmission paths from TXD to LIN and from LIN to RXD both active. The VCC voltage regulator operates with 3.3V/5V/85mA output capability. If EN is switched to low while TXD is still high, the device is forced to silent mode. No data transmission is then possible, and current consumption is reduced to IVSsilent typ. 47µA. The VCC regulator retains its full functionality. If EN is switched to low while TXD is low, the device is forced to sleep mode. No data transmission is possible, and the voltage regulator is switched off. The EN pin provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected. 6 ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 4. Functional Description 4.1 Physical Layer Compatibility Because the LIN physical layer is independent of higher LIN layers (e.g., LIN protocol layer), all nodes with a LIN physical layer according to revision 2.x can be mixed with LIN physical layer nodes based on earlier versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3) without any restrictions. 4.2 Operating Modes Figure 4-1. SBC Operating Modes a: VS > VVS_th_U_F_up (2.4V) b: VS < VVS_th_U_down (1.9V) c: Bus wake-up event (LIN) d: VCC < VVCC_th_uv_down (2.4V/4.2V) e: VS < VVS_th_N_F_down (3.9V) f: VS > VVS_th_F_N_up (4.9V) Unpowered Mode All circuitry OFF a b Fail-safe Mode EN = 0 TXD = 0 &f (1) VCC: ON 5V/3.3V VCC monitor active Communication: OFF Wake-up Signalling Undervoltage Signalling EN = 0 TXD = 1 &d&f (1) EN = 1 &f b Sleep Mode VCC: OFF Communication: OFF EN = 1 1. Table 4-1. EN = 1 Normal Mode &f Go to sleep command EN = 0 TXD = 0 Note: c & f, d b d, e c&f VCC: 5V/3.3V VCC monitor active Communication: ON &f Go to silent EN = 0 command TXD = 1 Silent Mode VCC: 5V/3.3V VCC monitor active Communication: OFF Condition f is valid for VS ramp up; at VS ramp down condition e is valid instead of f. SBC (ATA663254, ATA663231) Operating Modes Operating Mode Transceiver VCC (SBC only) LIN Fail-safe OFF 3.3V/5V Recessive Signaling fail-safe sources (see Table 4-2) Follows data transmission TXD RXD Normal ON 3.3V/5V TXD-dependent Silent (SBC only) OFF 3.3V/5V Recessive High High Sleep/Unpowered OFF 0V Recessive Low Low ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 7 Figure 4-2. Voltage Regulator Operating Modes a: VS > VVS_th_U_F_up (2.4V) b: VS < VVS_th_U_down (1.9V) Unpowered Mode All circuitry OFF a b Active Mode VCC: ON 5V VCC monitor active 4.2.1 Normal Mode (SBC only) This is the normal transmitting and receiving mode of the LIN Interface, in accordance with LIN specification 2.x. The VCC voltage regulator operates with 3.3V/5V output voltage, with a low tolerance of ±2% and a maximum output current of 85mA. If an undervoltage condition occurs, NRES is switched to low and the IC changes its state to fail-safe mode. 4.2.2 Silent Mode (SBC only) A falling edge at EN while TXD is high switches the IC into silent mode. The TXD signal has to be logic high during the mode select window. The transmission path is disabled in silent mode. The voltage regulator is active. The overall supply current from VBat is a combination of the IVSsilent = 47µA plus the VCC regulator output current IVCC. Figure 4-3. Switching to Silent Mode Normal Mode Silent Mode EN TXD Mode select window td = 3.2µs NRES VCC Delay time silent mode td_silent = maximum 20µs LIN LIN switches directly to recessive mode 8 ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 In silent mode the internal slave termination between the LIN pin and VS pin is disabled to minimize the current consumption in case the pin LIN is short-circuited to GND. Only a weak pull-up current (typically 10µA) between the LIN pin and VS pin is present. Silent mode can be activated independently from the current level on pin LIN. If an undervoltage condition occurs, NRES is switched to low and the Atmel® SBC changes its state to fail-safe mode. 4.2.3 Sleep Mode (SBC only) A falling edge at EN while TXD is low switches the IC into sleep mode. The TXD signal has to be logic low during the mode select window (Figure 4-6). Figure 4-4. Switching to Sleep Mode Sleep Mode Normal Mode EN Mode select window TXD td = 3.2µs NRES VCC Delay time sleep mode td_sleep = maximum 20µs LIN LIN switches directly to recessive mode In order to avoid any influence to the LIN pin when switching into sleep mode it is possible to switch the EN up to 3.2µs earlier to low than the TXD. The easiest and best way to do this is by having two falling edges at TXD and EN at the same time. In sleep mode the transmission path is disabled. Supply current from VBat is typically IVSsleep = 9µA. The VCC regulator is switched off; NRES and RXD are low. The internal slave termination between the LIN pin and VS pin is disabled to minimize the current consumption in case the LIN pin is short-circuited to GND. Only a weak pull-up current (typically 10µA) between the LIN pin and the VS pin is present. The sleep mode can be activated independently from the current level on the LIN pin. Voltage below the LIN pre-wake detection VLINL at the LIN pin activates the internal LIN receiver and starts the wake-up detection timer. If the TXD pin is short-circuited to GND, it is possible to switch to sleep mode via EN after t > tdom. ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 9 4.2.4 Fail-Safe Mode (SBC only) The device automatically switches to fail-safe mode at system power-up. The voltage regulator is switched on. The NRES output remains low for tres = 4ms and causes the microcontroller to be reseted. LIN communication is switched off. The IC stays in this mode until EN is switched to high. The IC then changes to normal mode. A low at NRES switches the IC into failsafe mode directly. During fail-safe mode the TXD pin is an output and, together with the RXD output pin, signals the failsafe source. If the device enters fail-safe mode coming from the normal mode (EN=1) due to an VS undervoltage condition (VS < VVS_th_N_F_down), it is possible to switch into sleep or silent mode by a falling edge at the EN input. With this feature the current consumption can be further reduced. A wake-up event from either silent or sleep mode is signalled to the microcontroller using the RXD pin and the TXD pin. A VS undervoltage condition is also signalled at these two pins. The coding is shown in the table below. A wake-up event switches the IC to fail-safe mode. Table 4-2. 4.2.5 Signaling in Fail-safe Mode Fail-Safe Sources TXD RXD LIN wake-up (LIN pin) Low Low VSth (battery) undervoltage detection (VS < 3.9V) High Low Active Mode (Voltage Regulator only) The device automatically switches to active mode at system power-up. The VCC voltage regulator operates with 5V output voltage, with a low tolerance of ±2% and a maximum output current of 85mA. The NRES output remains low for tres = 4ms and causes the microcontroller to be reseted. The current consumption is typically 47µA. If an undervoltage condition occurs, NRES switches to low. 10 ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 4.3 Wake-up Scenarios from Silent Mode or Sleep Mode 4.3.1 Remote Wake-up via LIN Bus 4.3.1.1 Remote Wake-up from Silent Mode (SBC only) A remote wake-up from silent mode is only possible if TXD is high. A voltage less than the LIN pre-wake detection VLINL at the LIN pin activates the internal LIN receiver and starts the wake-up detection timer. A falling edge at the LIN pin followed by a dominant bus level maintained for a certain period of time (> tbus) and the following rising edge at pin LIN (see Figure 45) result in a remote wake-up request. The device switches from silent mode to fail-safe mode, the VCC voltage regulator remains activated and the internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at the RXD pin and TXD pin (strong pull-down at TXD). EN high can be used to switch directly to normal mode. Figure 4-5. LIN Wake-up from Silent Mode Bus wake-up filtering time tbus Fail-safe Mode Normal Mode LIN bus RXD High TXD High VCC Low Low (strong pull-down) Silent mode 3.3V/5V Fail-safe mode 3.3V/5V High Normal mode EN High EN NRES Undervoltage detection active ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 11 4.3.1.2 Remote Wake-up from Sleep Mode (SBC only) A falling edge at the LIN pin followed by a dominant bus level maintained for a certain period of time (> tbus) and a following rising edge at the LIN pin result in a remote wake-up request, causing the device to switch from sleep mode to fail-safe mode. The VCC regulator is activated, and the internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at RXD and TXD (strong pull-down at TXD) (see Figure 4-6). EN high can be used to switch directly from sleep/silent mode to fail-safe mode. If EN is still high after VCC ramp-up and undervoltage reset time, the IC switches to normal mode. Figure 4-6. LIN Wake-up from Sleep Mode Bus wake-up filtering time tbus Fail-safe Mode LIN bus RXD High Low High Low (strong pull-down) High Low TXD VCC Normal Mode On state Off state tVCC EN High EN Reset time NRES 4.3.2 Low Microcontroller start-up time delay Wake-up Source Recognition (SBC only) The device can distinguish between different wake-up sources. The wake-up source can be read on the TXD and RXD pin in fail-safe mode. These flags are immediately reset if the microcontroller sets the EN pin to high and the IC is in normal mode. Table 4-3. Signaling in Fail-safe Mode Fail-Safe Sources 12 TXD RXD LIN wake-up (LIN pin) Low Low VSth (battery) undervoltage detection (VS < 3.9V) High Low ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 Behavior under Low Supply Voltage Condition After the battery voltage has been connected to the application circuit, the voltage at the VS pin increases according to the block capacitor used in the application (see Figure 9-1 on page 25). If VVS is higher than the minimum VS operation threshold VVS_th_U_F_up, the IC mode changes from unpowered mode to fail-safe mode. As soon as VVS exceeds the undervoltage threshold VVS_th_F_N_up, the LIN transceiver can be activated. The VCC output voltage reaches its nominal value after tVCC. This parameter depends on the externally applied VCC capacitor and the load. The NRES output is low for the reset time delay treset. No mode change is possible during this time treset. The behavior of VCC, NRES and VS is shown in the following diagrams (ramp-up and ramp-down): V (V) Figure 4-7. VCC and NRES versus VS (Ramp-up) for 3.3V (SBC only) 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 VS NRES VCC 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 1.0 0.5 0.0 VS (V) Figure 4-8. VCC and NRES versus VS (Ramp-down) for 3.3V (SBC only) V (V) 4.4 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 VS NRES 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 VCC 2.5 2.0 1.5 VS (V) ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 13 V (V) Figure 4-9. VCC and NRES versus VS (Ramp-up) for 5V (SBC and Voltage Regulator) 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 VS NRES VCC 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VS (V) V (V) Figure 4-10. VCC and NRES versus VS (Ramp-down) for 5V (SBC and Voltage Regulator) 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 VS NRES VCC 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 VS (V) Please note that the upper graphs are only valid if the VS ramp-up and ramp-down times are much slower than the VCC ramp-up time tVcc and the NRES delay time treset. If during sleep mode the voltage level of VVS drops below the undervoltage detection threshold VVS_th_N_F_down (typ. 4.3V), the operation mode is not changed and no wake-up is possible. Only if the supply voltage on pin VS drops below the VS operation threshold VVS_th_U_down (typ. 2.05V), does the IC switch to unpowered mode. If during silent mode the VCC voltage drops below the VCC undervoltage threshold VVCC_th_uv_down the IC switches into failsafe mode. If the supply voltage on pin VS drops below the VS operation threshold VVS_th_U_down (typ. 2.05V), does the IC switch to unpowered mode. If during normal mode the voltage level on the VS pin drops below the VS undervoltage detection threshold VVS_th_N_F_down (typ. 4.3V), the IC switches to fail-safe mode. This means the LIN transceiver is disabled in order to avoid malfunctions or false bus messages. The voltage regulator remains active. For 3.3V SBC: In this undervoltage situation it is possible to switch the device into sleep mode or silent mode by a falling edge at the EN input. For this feature, switching into these two current saving modes is always guaranteed, allowing current consumption to be reduced even further. When the VCC voltage drops below the VCC undervoltage threshold VVCC_th_uv_down (typ. 2.6V) the IC switches into fail-safe mode. For 5V SBC: Because of the VCC undervoltage condition in this situation, the IC is in fail-safe mode and can be switched into sleep mode only. Only when the supply voltage VVS drops below the operation threshold VVS_th_U_down (typ. 2.05V) does the IC switch into unpowered mode. The current consumption of the SBC in silent mode or in fail-safe mode and the voltage regulator is always below 170µA, even when the supply voltage VS is lower than the regulator’s nominal output voltage VCC. 14 ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 Voltage Regulator Figure 4-11. Voltage Regulator: Supply Voltage Ramp-up and Ramp-down V VS 12V VCC 3.3V/5.0V VVCC_th_uv_up VVCC_th_uv_down 2.4V t tVCC tReset tres_f NRES 3.3V/5.0V t The voltage regulator needs an external capacitor for compensation and to smooth the disturbances from the microcontroller. It is recommended to use a MLC capacitor with a minimum capacitance of 1.8µF together with a 100nF ceramic capacitor. Depending on the application, the values of these capacitors can be modified by the customer. During a short circuit at VCC, the output limits the output current to IVCClim. Because of undervoltage, NRES switches to low and sends a reset to the microcontroller. If the chip temperature exceeds the value TVCCoff, the VCC output switches off. The chip cools down and, after a hysteresis of Thys, switches the output on again. When the Atmel ATA6632xx is being soldered onto the PCB it is mandatory to connect the heat slug with a wide GND plate on the printed board to get a good heat sink. The main power dissipation of the IC is created from the VCC output current IVCC, which is needed for the application. “Power Dissipation: Safe Operating Area: Regulator’s Output Current IVcc versus Supply Voltage VS” is shown in Figure 4-12. Figure 4-12. DFN8 Package Power Dissipation: Safe Operating Area: Regulator’s Output Current IVcc versus Supply Voltage VS at Different Ambient Temperatures (Rthja = 50K/W assumed) 90 I_Vcc [mA] 4.5 80 Tamb = 85°C 70 Tamb = 95°C 60 Tamb = 105°C 50 Tamb = 115°C 40 30 Tamb = 125°C 20 10 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 VS [V] ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 15 Figure 4-13. SO8 Package Power Dissipation: Safe Operating Area: VCC Output Current versus Supply Voltage VS at Different Ambient Temperatures Due to Rthja = 80K/W 90 80 IVCC (mA) 70 60 Tamb = 85°C 50 40 Tamb = 95°C 30 Tamb = 105°C Tamb = 115°C 20 10 0 5 6 7 8 9 10 11 12 VS (V) 16 ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 13 14 15 16 17 18 5. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Supply voltage VS VS –0.3 Pulse time ≤ 500ms Ta = 25°C Output current IVCC ≤ 85mA Pulse time ≤ 2min Ta = 25°C Output current IVCC ≤ 85mA Typ. Max. Unit +40 V VS +43.5 V VS 28 V Logic pins voltage levels (RxD, TxD, EN, NRES) VLogic –0.3 +5.5 V Logic pins output DC currents ILogic –5 +5 mA LIN - DC voltage - Pulse time < 500ms VLIN –27 +40 +43.5 V V VVCC IVCC –0.3 +5.5 +200 V mA VCC - DC voltage - DC input current ESD according to IBEE LIN EMC Test specification 1.0 following IEC 61000-4-2 - Pin VS, LIN to GND (with external circuitry acc. applications diagram) ±6 kV ESD HBM following STM5.1 with 1.5k/100pF - Pin VS, LIN to GND ±6 kV ±3 kV CDM ESD STM 5.3.1 ±750 V Machine Model ESD AEC-Q100-RevF(003) ±200 V HBM ESD ANSI/ESD-STM5.1 JESD22-A114 AEC-Q100 (002) Junction temperature Tj –40 +150 °C Storage temperature Ts –55 +150 °C ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 17 6. Thermal Characteristics DFN8 Parameters Symbol Min. Typ. Max. Unit Thermal resistance junction to heat slug RthjC 10 K/W Thermal resistance junction to ambient, where heat slug is soldered to PCB according to JEDEC Rthja 50 K/W Thermal shutdown of VCC regulator TVCCoff 150 165 180 °C Thermal shutdown of LIN output TLINoff 150 165 180 °C Thermal shutdown hysteresis 7. Thys 10 °C Thermal Characteristics SO8 Parameters Heat sink at GND (pin 5) on PCB (fused lead frame to pin 5) Symbol Min. RthJA Typ. Max. 80 Unit K/W Thermal shutdown Toff 150 165 180 °C Thermal shutdown hysteresis Thys 5 10 20 °C 18 ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 8. Electrical Characteristics 5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins. No. Parameters 1 Test Conditions Pin Symbol Min. Typ. Max. Unit Type* VS VS 5 13.5 28 V A Sleep mode VLIN > VS – 0.5V VS < 14V, T = 27°C VS IVSsleep 6 9 12 µA B Sleep mode VLIN > VS – 0.5V VS < 14V VS IVSsleep 3 10 15 µA A Sleep mode, VLIN = 0V bus shorted to GND VS < 14V VS IVSsleep_short 20 50 100 µA A Bus recessive 5.5V< VS < 14V without load at VCC T = 27°C VS IVSsilent 30 47 58 µA B Bus recessive 5.5V< VS < 14V without load at VCC VS IVSsilent 30 50 64 µA A Bus recessive 2.0V< VS < 5,5V without load at VCC VS IVSsilent 50 130 170 µA A Silent mode 5.5V< VS < 14V bus shorted to GND without load at VCC VS IVSsilent_short 50 80 120 µA A Bus recessive VS < 14V without load at VCC VS IVSrec 150 230 290 µA A Bus dominant (internal LIN pull-up resistor active) VS < 14V without load at VCC VS IVSdom 200 700 950 µA A VS IVSfail 40 55 80 µA A VS IVSfail 50 130 170 µA A VS VVS_th_N_F_down 3.9 4.3 4.7 V A VS VVS_th_F_N_up 4.1 4.6 4.9 V A VS VVS_hys_F_N 0.1 0.25 0.4 V A Switch to unpowered mode VS VVS_th_U_down 1.9 2.05 2.3 V A Switch from unpowered to fail-safe mode VS VVS_th_U_F_up 2.0 2.25 2.4 V A VS pin 1.1 Nominal DC voltage range 1.2 Supply current in sleep mode Supply current in silent mode (SBC) / 1.3 Active mode (voltage regulator) 1.4 Supply current in normal mode Supply current in normal 1.5 mode Bus recessive 5.5V < VS < 14V Supply current in fail-safe without load at VCC 1.6 mode Bus recessive 2.0V < VS < 5.5V without load at VCC VS undervoltage threshold Decreasing supply voltage 1.7 (switching from normal to Increasing supply voltage fail-safe mode) 1.8 VS undervoltage hysteresis VS operation threshold 1.9 (switching to unpowered mode) *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 19 8. Electrical Characteristics (Continued) 5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins. No. Parameters 1.10 2 Test Conditions VS undervoltage hysteresis Pin Symbol Min. Typ. Max. Unit Type* VS VVS_hys_U 0.1 0.2 0.3 V A 0.2 0.4 V A V A RXD output pin (only SBC) 2.1 Low-level output sink capability Normal mode, VLIN = 0V, IRXD = 2mA RXD VRXDL 2.2 High-level output source capability Normal mode VLIN = VS, IRXD = –2mA RXD VRXDH VCC – 0.4V 3.1 Low-level voltage input TXD VTXDL –0.3 +0.8 V A 3.2 High-level voltage input TXD VTXDH 2 VCC + 0.3V V A TXD RTXD 40 100 k A 3.4 High-level leakage current VTXD = VCC TXD ITXD –3 +3 µA A Low-level output sink 3.7 current at LIN wake-up request TXD ITXD 2 8 mA A EN VENL –0.3 +0.8 V A VCC + 0.3V V A 200 k A +3 µA A 0.2 0.4 V A 4 6 ms A 3 TXD input/output pin (only SBC) 3.3 Pull-up resistor 4 VTXD = 0V Fail-safe Mode VLIN = VS VTXD = 0.4V 70 2.5 EN input pin (only SBC) 4.1 Low-level voltage input 4.2 High-level voltage input EN VENH 2 4.3 Pull-down resistor VEN = VCC EN REN 50 4.4 Low-level input current VEN = 0V EN IEN –3 5 VCC – 0.2V 125 NRES open drain output pin 5.1 Low-level output voltage VS ≥ 5.5V INRES = 2mA NRES VNRESL 5.2 Undervoltage reset time VVS ≥ 5.5V CNRES = 20pF NRES tReset 2 Reset debounce time for falling edge VVS ≥ 5.5V CNRES = 20pF NRES tres_f 0.5 10 µs A 5.4 Switch off leakage current VNRES = 5.5V NRES INRES_L –3 +3 µA A 4V < VS < 18V (0mA to 50mA) VCC VCCnor 3.234 3.366 V A 4.5V < VS < 18V (0mA to 85mA) VCC VCCnor 3.234 3.366 V C VCC VCClow VVS – VD 3.366 V A 5.3 8 VCC voltage regulator (3.3V) 8.1 Output voltage VCC 8.2 Output voltage VCC at low 3V < VS < 4V VS 8.3 Regulator drop voltage VS > 3V, IVCC = –15mA VCC VD1 100 150 mV A 8.4 Regulator drop voltage VS > 3V, IVCC = –50mA VCC VD2 300 500 mV A 8.5 Line regulation maximum 4V < VS < 18V VCC VCCline 0.1 0.2 % A 8.6 Load regulation maximum 5mA < IVCC < 50mA VCC VCCload 0.1 0.5 % A 8.7 Output current limitation VS > 4V VCC IVCClim –180 –120 mA A 8.8 Load capacity MLC capacitor VCC Cload µF D 1.8 2.2 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 20 ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 8. Electrical Characteristics (Continued) 5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins. No. Parameters Test Conditions Pin VCC undervoltage threshold (NRES ON) Referred to VCC VS > 4V VCC undervoltage threshold (NRES OFF) 8.10 Hysteresis of VCC undervoltage threshold 8.11 Ramp-up time VS > 4V to CVCC = 2.2µF VCC = 3.3V Iload = –5mA at VCC 8.9 9 Min. Typ. Max. Unit Type* VCC VVCC_th_uv_down 2.3 2.5 2.8 V A Referred to VCC VS > 4V VCC VVCC_th_uv_up 2.5 2.6 2.9 V A Referred to VCC VS > 4V VCC VVCC_hys_uv 100 200 300 mV A VCC tVCC 1 1.5 ms A 5.5V < VS < 18V (0mA to 50mA) VCC VCCnor 4.9 5.1 V A 6V < VS < 18V (0mA to 85mA) VCC VCCnor 4.9 5.1 V C Output voltage VCC at low 4V < VS < 5.5V VS VCC VCClow VVS – VD 5.1 V A VCC voltage regulator (5V) 9.1 Output voltage VCC 9.2 Symbol 9.3 Regulator drop voltage VS > 4V, IVCC = –20mA VCC VD1 100 200 mV A 9.4 Regulator drop voltage VS > 4V, IVCC = –50mA VCC VD2 300 500 mV A 9.5 Regulator drop voltage VS > 3.3V, IVCC = –15mA VCC VD3 150 mV A 9.6 Line regulation maximum 5.5V < VS < 18V VCC VCCline 0.1 0.2 % A 9.7 Load regulation maximum 5mA < IVCC < 50mA VCC VCCload 0.1 0.5 % A 9.8 Output current limitation VS > 5.5V VCC IVCClim –180 –120 mA A 9.9 Load capacity Cload µF D 1.8 2.2 VCC VVCC_th_uv_down 4.2 4.4 4.6 V A Referred to VCC VS > 4V VCC VVCC_th_uv_up 4.3 4.6 4.8 V A 9.11 Hysteresis of undervoltage Referred to VCC threshold VS > 5.5V VCC VVCC_hys_uv 100 200 300 mV A 9.12 Ramp-up time VS > 5.5V CVCC = 2.2µF to VCC = 5V Iload = –5mA at VCC VCC tVCC 1 1.5 ms A 9.10 10 10.1 MLC capacitor VCC VCC undervoltage threshold (NRES ON) Referred to VCC VS > 4V VCC undervoltage threshold (NRES OFF) LIN bus driver (only SBC): bus load conditions: Load 1 (small): 1nF, 1k; Load 2 (large): 10nF, 500; CRXD = 20pF, Load 3 (medium): 6.8nF, 660 characterized on samples 12.7 and 12.8 specifies the timing parameters for proper operation at 20kb/s and 12.9 and 12.10 at 10.4kb/s Driver recessive output voltage Load1/Load2 LIN VBUSrec 10.2 Driver dominant voltage VVS = 7V Rload = 500 LIN 10.3 Driver dominant voltage VVS = 18V Rload = 500 10.4 Driver dominant voltage 10.5 Driver dominant voltage 0.9 VS VS V A V_LoSUP 1.2 V A LIN V_HiSUP 2 V A VVS = 7V Rload = 1000 LIN V_LoSUP_1k 0.6 V A VVS = 18V Rload = 1000 LIN V_HiSUP_1k 0.8 V A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 21 8. Electrical Characteristics (Continued) 5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 10.6 Pull-up resistor to VS The serial diode is mandatory LIN RLIN 20 30 47 k A 1.0 V D 200 mA A mA A 10.7 Voltage drop at the serial In pull-up path with Rslave diodes ISerDiode = 10mA LIN VSerDiode 0.4 10.8 LIN current limitation VBUS = VBat_max LIN IBUS_LIM 40 120 LIN IBUS_PAS_dom –1 –0.35 Driver off 8V < VBat < 18V 8V < VBUS < 18V VBUS ≥ VBat LIN IBUS_PAS_rec Leakage current when control unit disconnected GNDDevice = VS from ground. 10.11 V = 12V Loss of local ground must Bat 0V < VBUS < 18V not affect communication in the residual network LIN IBUS_NO_gnd Leakage current at disconnected battery. Node has to sustain the VBat disconnected 10.12 current that can flow under VSUP_Device = GND this condition. Bus must 0V < VBUS < 18V remain operational under this condition. LIN IBUS_NO_bat LIN CLIN VBUS_CNT = (Vth_dom + Vth_rec)/2 LIN VBUS_CNT 0.475 VS 11.2 Receiver dominant state VEN = 5V/3.3V LIN VBUSdom 11.3 Receiver recessive state VEN = 5V/3.3V LIN Input leakage current Input leakage current at driver off 10.9 the receiver including pullVBUS = 0V up resistor as specified VBat = 12V Leakage current LIN 10.10 recessive 10.13 11 11.1 10 20 µA A +0.5 +10 µA A 0.1 2 µA A 20 pF D 0.525 VS V A –27 0.4 VS V A VBUSrec 0.6 VS 40 V A LIN VBUShys 0.028 0.175 0.1 x VS VS VS V A LIN VLINH VS – 2V VS + 0.3V V A Activates the LIN receiver LIN VLINL –27 VS – 3.3V V A VLIN = 0V LIN tbus 50 100 150 µs A EN tnorm 5 15 20 µs A Capacitance on pin LIN to GND LIN bus receiver (only SBC) Center of receiver threshold 11.4 Receiver input hysteresis Vhys = Vth_rec – Vth_dom 11.5 Pre-wake detection LIN high-level input voltage 11.6 Pre-wake detection LIN low-level input voltage 12 12.1 –10 0.5 VS Internal timers (only SBC) Dominant time for wake-up via LIN bus Time delay for mode 12.2 change from fail-safe into VEN = 5V/3.3V normal mode via EN pin *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 22 ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 8. Electrical Characteristics (Continued) 5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* EN tsleep 5 15 20 µs A VTXD = 0V TXD tdom 20 40 60 ms A Time delay for mode change from silent mode 12.6 into normal mode via EN pin VEN = 5V/3.3V EN ts_n 5 15 40 µs A 12.7 Duty cycle 1 THRec(max) = 0.744 VS THDom(max) = 0.581 VS VS = 7.0V to 18V tBit = 50µs D1 = tbus_rec(min)/(2 tBit) LIN D1 0.396 12.8 Duty cycle 2 THRec(min) = 0.422 VS THDom(min) = 0.284 VS VS = 7.6V to 18V tBit = 50µs D2 = tbus_rec(max)/(2 tBit) LIN D2 12.9 Duty cycle 3 THRec(max) = 0.778 VS THDom(max) = 0.616 VS VS = 7.0V to 18V tBit = 96µs D3 = tbus_rec(min)/(2 tBit) LIN D3 12.10 Duty cycle 4 THRec(min) = 0.389 VS THDom(min) = 0.251 VS VS = 7.6V to 18V tBit = 96µs D4 = tbus_rec(max)/(2 tBit) LIN D4 VS = 7.0V to 18V LIN tSLOPE_fall tSLOPE_rise Time delay for mode 12.3 change from normal mode VEN = 0V to sleep mode via EN pin 12.5 12.11 13 13.1 TXD dominant time-out time Slope time falling and rising edge at LIN A 0.581 A 0.417 A 0.590 3.5 A 22.5 µs A 6 µs A +2 µs A Receiver electrical AC parameters of the LIN physical layer LIN receiver, RXD load conditions: CRXD = 20pF Propagation delay of receiver Symmetry of receiver 13.2 propagation delay rising edge minus falling edge VS = 7.0V to 18V trx_pd = max(trx_pdr , trx_pdf) RXD trx_pd VS = 7.0V to 18V trx_sym = trx_pdr – trx_pdf RXD trx_sym –2 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 23 Figure 8-1. Definition of Bus Timing Characteristics tBit tBit tBit TXD (Input to transmitting node) tBus_dom(max) tBus_rec(min) Thresholds of receiving node1 THRec(max) VS (Transceiver supply of transmitting node) THDom(max) LIN Bus Signal Thresholds of receiving node2 THRec(min) THDom(min) tBus_dom(min) tBus_rec(max) RXD (Output of receiving node1) trx_pdf(1) trx_pdr(1) RXD (Output of receiving node2) trx_pdr(2) 24 ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 trx_pdf(2) 9. Application Circuits Figure 9-1. Typical Application Circuit SBC D1 VCC C5 R1 10kΩ C4 100nF VCC EN Microcontroller D2 VCC R2 1kΩ VS Master node pull up C2 DFN8/SO8 NRES 100nF LIN LIN C3 TXD VBAT 10µF/50V 2.2µF Atmel ATA663254 ATA663231 RXD + C1 220pF GND GND GND Note: Heat slug must always be connected to GND (for DFN8 package). Figure 9-2. Typical Application Circuit Voltage Regulator VCC D1 C5 C4 100nF VCC R1 10kΩ + 10µF/50V 2.2µF Atmel ATA663203 VBAT C1 VCC VS Microcontroller C2 DFN8 3x3 NRES 100nF GND GND GND Note: 10. Heat slug must always be connected to GND. Ordering Information Extended Type Number Package Remarks ATA663231-GBQW DFN8 3.3V LIN system basis chip, Pb-free, 6k, taped and reeled ATA663254-GBQW DFN8 5V LIN system basis chip, Pb-free, 6k, taped and reeled ATA663203-GBQW DFN8 5V voltage regulator, Pb-free, 6k, taped and reeled ATA663254-GAQW SO8 5V LIN system basis chip, Pb-free, 4k, taped and reeled ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 25 11. Package Information Figure 11-1. DFN8 Top View D 8 E PIN 1 ID technical drawings according to DIN specifications 1 A A3 A1 Dimensions in mm Side View Partially Plated Surface Bottom View 4 COMMON DIMENSIONS E2 1 Z 8 (Unit of Measure = mm) 5 e D2 L Z 10:1 Symbol MIN NOM MAX A 0.8 0.85 0.9 A1 0 0.035 0.05 A3 0.16 0.21 0.26 D 2.9 3 3.1 D2 2.3 2.4 2.5 E 2.9 3 3.1 E2 1.5 1.6 1.7 L 0.35 0.4 0.45 b e 0.25 0.3 0.65 0.35 NOTE b 10/11/13 TITLE Package Drawing Contact: [email protected] 26 Package: VDFN_3x3_8L Exposed pad 2.4x1.6 ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 GPC DRAWING NO. REV. 6.543-5165.03-4 1 Figure 11-2. SO8 E1 L A b A2 A1 C D e 8 E 5 technical drawings according to DIN specifications Dimensions in mm 1 4 COMMON DIMENSIONS Pin 1 identity (Unit of Measure = mm) Symbol MIN NOM MAX A 1.5 1.65 1.8 A1 0.1 0.15 0.25 A2 1.4 1.47 1.55 D 4.8 4.9 5 E 5.8 6 6.2 E1 3.8 3.9 4 L 0.4 0.65 0.9 C 0.15 0.2 0.25 b 0.3 0.4 0.5 e NOTE 1.27 BSC 05/08/14 TITLE Package Drawing Contact: [email protected] Package: SO8 GPC DRAWING NO. REV. 6.543-5185.01-4 1 ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 27 12. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History Features on page 1 updated Section 2 “Pin Configuration” on page 4 updated Section 4.5 “Voltage Regulator” on pages 15 to 16 updated 9337F-AUTO-02/16 Section 7 “Thermal Characteristics SO8” on page 18 added Section 9 “Application Circuits” on page 25 updated Section 10 “Ordering Information” on page 25 updated Figure 11-2 “SO8” on page 27 added Section 4.2 “Operating Modes” on page 7: Note 1 added below Figure 4-1 9337E-AUTO-12/15 Figure 4-11 “Voltage Regulator: Supply Voltage Ramp-up and Ramp-down” on page 15: Parameter names updated Figure 1- 2 “Block Diagram Voltage Regulator” on page 3 added ATA663203 pin configuration on page 4 added 9337D-AUTO-07/14 Figure 4-3 “Voltage Regulator Operating Modes” on page 8 added Section 4.2.5 “Active Mode (Voltage Regulator only)” on page 10 added Figure 8-2 “Typical Application Circuit Voltage Regulator” on page 23 added Section 9 “Ordering Information” on page 24 updated 28 ATA663203/ATA663231/ATA663254 [DATASHEET] 9337F–AUTO–02/16 XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2016 Atmel Corporation. / Rev.: 9337F–AUTO–02/16 Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. 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