AT25128A/256A Automotive - Mature

Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
– Data Sheet Describes Mode 0 Operation
• Standard-voltage Operation
•
•
•
•
•
•
•
•
– 2.7 (VCC = 2.7V to 5.5V)
Automotive Temperature Range 40°C to +125°C
5 MHz Clock Rate
64-byte Page Mode and Byte Write Operation
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software
Data Protection
Self-timed Write Cycle (5 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: >100 Years
8-lead JEDEC SOIC and 8-lead TSSOP Packages
Description
The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable programmable read-only memory (EEPROM) organized as 16,384/32,768 words of 8 bits
each. The device is optimized for use in many industrial and automotive applications
where low-power and low-voltage operation are essential. The devices are available in
space-saving 8-lead JEDEC SOIC and 8-lead TSSOP packages.
The AT25128A/256A is enabled through the Chip Select pin (CS) and accessed via a
three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no separate erase cycle is required before write.
SPI
Automotive
Temperature
Serial
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
AT25128A
AT25256A
Table 1. Pin Configurations
Pin Name
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
NC
No Connect
DC
Don't Connect
Not Recommended
for New Design.
8-lead SOIC
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
Replaced by
AT25128B/256B
Automotive.
8-lead TSSOP
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
5088F–SEEPR–2/07
1
Block write protection is enabled by programming the status register with top one-forth,
top one-half, or entire array of write protection. Separate program enable and program
disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status
register. The HOLD pin may be used to suspend any serial communication without
resetting the serial sequence
.
Absolute Maximum Ratings*
Operating Temperature  40C to +125C
Storage Temperature 65C to +150C
Voltage on Any Pin
with Respect to Ground  1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
*NOTICE:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
16384/32768 x 8
2
AT25128A/256A
5088F–SEEPR–2/07
AT25128A/256A
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol
Test Conditions
COUT
CIN
Note:
Max
Units
Conditions
Output Capacitance (SO)
8
pF
VOUT = 0V
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
VIN = 0V
1. This parameter is characterized and is not 100% tested.
Table 3. DC Characteristics
Applicable over recommended operating range from TA = 40°C to +125°C, VCC = +2.7V to +5.5V
Symbol
Parameter
Max
Units
VCC1
Supply Voltage
2.7
5.5
V
VCC2
Supply Voltage
4.5
5.5
V
ICC1
Supply Current
VCC = 5.0V at 1 MHz, SO = Open, Read
2.0
3.0
mA
ICC2
Supply Current
VCC = 5.0V at 2 MHz,
SO = Open, Read, Write
3.0
5.0
mA
ICC3
Supply Current
VCC = 5.0V at 5 MHz,
SO = Open, Read, Write
3.5
6.0
mA
ISB1
Standby Current
VCC = 2.7V, CS = VCC
0.5
12.0(1)
µA
ISB2
Standby Current
VCC = 5.0V, CS = VCC
2.0
15.0(1)
µA
IIL
Input Leakage
VIN = 0V to VCC
3.0
3.0
µA
Output Leakage
VIN = 0V to VCC
3.0
3.0
µA
Input Low-voltage
1.0
VCC x 0.3
V
VIH(2)
Input High-voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low-voltage
3.6  VCC  5.5V
IOL = 3.0 mA
0.4
V
VOL2
Output Low-voltage
2.7 VCC  3.6V
IOL = 0.15mA
0.2
V
VOH1
Output High-voltage
3.6  VCC  5.5V
IOH = 1.6 mA
VCC 0.8
V
Output High-voltage
2.7 VCC  3.6V
IOH = 100 µA
VCC 0.2
V
IOL
VIL
(2)
VOH2
Note:
Test Condition
Min
Typ
1. Maximum value at +125°C
2. VIL and VIH max are reference only and are not tested.
3
5088F–SEEPR–2/07
Table 4. AC Characteristics
Applicable over recommended operating range from TA = 40C to +125C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min
Max
Units
fSCK
SCK Clock Frequency
2.7–5.5
0
5.0
MHz
tRI
Input Rise Time
2.7–5.5
2
µs
tFI
Input Fall Time
2.7–5.5
2
µs
tWH
SCK High Time
2.7–5.5
40
ns
tWL
SCK Low Time
2.7–5.5
40
ns
tCS
CS High Time
2.7–5.5
80
ns
tCSS
CS Setup Time
2.7–5.5
80
ns
tCSH
CS Hold Time
2.7–5.5
80
ns
tSU
Data In Setup Time
2.7–5.5
5
ns
tH
Data In Hold Time
2.7–5.5
20
ns
tHD
Hold Setup Time
2.7–5.5
40
ns
tCD
Hold Hold Time
2.7–5.5
40
ns
tV
Output Valid
2.7–5.5
0
tHO
Output Hold Time
2.7–5.5
0
tLZ
Hold to Output Low Z
2.7–5.5
0
tHZ
Hold to Output High Z
tDIS
tWC
(1)
Endurance
Note:
4
40
ns
ns
40
ns
2.7–5.5
80
ns
Output Disable Time
2.7–5.5
80
ns
Write Cycle Time
2.7–5.5
5
ms
5.0V, 25C, Page Mode
1M
Write Cycles
1. This parameter is ensured by characterization only.
AT25128A/256A
5088F–SEEPR–2/07
AT25128A/256A
Serial Interface
Description
MASTER: The device that generates the serial clock.
SLAVE: Because the serial clock pin (SCK) is always an input, the AT25128A/256A
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25128A/256A has separate pins designated for
data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25128A/256A, and the serial output pin (SO) will remain in a high impedance state
until the falling edge of CS is detected again. This will reinitialize the serial
communication.
CHIP SELECT: The AT25128A/256A is selected when the CS pin is low. When the
device is not selected, data will not be accepted via the SI pin, and the SO pin will
remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the
AT25128A/256A. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without
resetting the serial sequence. To pause, the HOLD pin must be brought low while the
SCK pin is low. To resume serial communication, the HOLD pin is brought high while the
SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored
while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations
when held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a
write to the status register. If the internal write cycle has already been initiated, WP
going low will have no effect on any write operation to the status register. The WP pin
function is blocked when the WPEN bit in the status register is “0”. This will allow the
user to install the AT25128A/256A in a system with the WP pin tied to ground and still be
able to write to the status register. All WP pin functions are enabled when the WPEN bit
is set to “1”.
5
5088F–SEEPR–2/07
Figure 2. SPI Serial Interface
AT25128A/256A
6
AT25128A/256A
5088F–SEEPR–2/07
AT25128A/256A
Functional
Description
The AT25128A/256A is designed to interface directly with the synchronous serial
peripheral interface (SPI) of the 6800 type series of microcontrollers.
The AT25128A/256A utilizes an 8-bit instruction register. The list of instructions and
their operation codes are contained in Table 5. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low CS transition.
Table 5. Instruction Set for the AT25128A/256A
Instruction Name
Instruction Format
Operation
WREN
0000 X110
Set Write Enable Latch
WRDI
0000 X100
Reset Write Enable Latch
RDSR
0000 X101
Read Status Register
WRSR
0000 X001
Write Status Register
READ
0000 X011
Read Data from Memory Array
WRITE
0000 X010
Write Data to Memory Array
WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC
is applied. All programming instructions must therefore be preceded by a Write Enable
instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write
Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides
access to the status register. The Ready/Busy and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the block write protection
bits indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 6. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
Table 7. Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = “0” (RDY) indicates the device is ready.
Bit 0 = “1” indicates the write cycle is in progress.
Bit 1 (WEN)
Bit 1 = “0” indicates the device is not WRITE ENABLED. Bit 1 = “1”
indicates the device is write enabled.
Bit 2 (BP0)
See Table 8.
Bit 3 (BP1)
See Table 8.
Bits 4–6 are “0”s when device is not in an internal write cycle.
Bit 7 (WPEN)
See Table 9.
Bits 0–7 are “1”s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select
one of four levels of protection. The AT25128A/256A is divided into four array segments.
7
5088F–SEEPR–2/07
Top quarter, top half, or all of the memory segments can be protected. Any of the data
within any selected segment will therefore be read only. The block write protection levels
and corresponding status register control bits are shown in Table 8.
Bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g., WREN, tWC, RDSR).
Table 8. Block Write Protect Bits
Status Register Bits
Array Addresses Protected
Level
BP1
BP0
AT25128A
AT25256A
0
0
0
None
None
1 (1/4)
0
1
3000–3FFF
6000–7FFF
2 (1/2)
1
0
2000–3FFF
4000–7FFF
3 (All)
1
1
0000–3FFF
0000–7FFF
The WRSR instruction also allows the user to enable or disable the write protect (WP)
pin through the use of the write protect enable (WPEN) bit. Hardware write protection is
enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is
disabled when either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected, writes to the status register, including the block protect bits and the
WPEN bit, and the block-protected sections in the memory array are disabled. Writes
are only allowed to sections of the memory that are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to
“0” as long as the WP pin is held low.
Table 9. WPEN Operation
WPEN
WP
WEN
Protected
Blocks
Unprotected
Blocks
Status
Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writeable
Writeable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writeable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writeable
Writeable
READ SEQUENCE (READ): Reading the AT25128A/256A via the SO pin requires the
following sequence. After the CS line is pulled low to select a device, the read op-code
is transmitted via the SI line followed by the byte address to be read (see Table 10).
Upon completion, any data on the SI line will be ignored. The data (D7–D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS
line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be
shifted out. When the highest address is reached, the address counter will roll over to
the lowest address, allowing the entire memory to be read in one continuous read cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25128A/256A, two separate
instructions must be executed. First, the device must be write enabled via the WREN
instruction. Then a Write instruction may be executed. Also, the address of the memory
location(s) to be programmed must be outside the protected address field location
8
AT25128A/256A
5088F–SEEPR–2/07
AT25128A/256A
selected by the block write protection level. During an internal write cycle, all commands
will be ignored except the RDSR instruction.
A Write instruction requires the following sequence. After the CS line is pulled low to
select the device, the WRITE op-code is transmitted via the SI line followed by the byte
address and the data (D7–D0) to be programmed (see Table 10). Programming will start
after the CS pin is brought high. The low-to-high transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a Read Status
Register (RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”,
the write cycle has ended. Only the RDSR instruction is enabled during the write programming cycle.
The AT25128A/256A is capable of a 64-byte page write operation. After each byte of
data is received, the six low-order address bits are internally incremented by one; the
high order bits of the address will remain constant. If more than 64 bytes of data are
transmitted, the address counter will roll over and the previously written data will be
overwritten. The AT25128A/256A is automatically returned to the write disable state at
the completion of a write cycle.
NOTE: If the device is not write enabled (WREN), the device will ignore the Write
instruction and will return to the standby state when CS is brought high. A new CS falling
edge is required to reinitiate the serial communication.
Table 10. Address Key
Address
AT25128A
AT25256A
AN
A13 – A0
A14 – A0
Don’t Care Bits
A15 – A14
A15
9
5088F–SEEPR–2/07
Timing Diagrams (for SPI Mode 0 [0, 0])
Figure 3. Synchronous Data Timing
t CS
VIH
CS
VIL
t CSH
t CSS
VIH
t WH
SCK
t WL
VIL
tH
t SU
VIH
SI
VALID IN
VIL
tV
VOH
SO
HI-Z
t HO
t DIS
HI-Z
VOL
Figure 4. WREN Timing
Figure 5. WRDI Timing
10
AT25128A/256A
5088F–SEEPR–2/07
AT25128A/256A
Figure 6. RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
1
0
SCK
INSTRUCTION
SI
SO
HIGH IMPEDANCE
DATA OUT
7
6
5
4
3
MSB
Figure 7. WRSR Timing
11
5088F–SEEPR–2/07
Figure 8. READ Timing
Figure 9. WRITE Timing
Figure 10. HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
SO
tLZ
12
AT25128A/256A
5088F–SEEPR–2/07
AT25128A/256A
AT25128A Ordering Information
Ordering Code
Package
Operation Range
8S1
8A2
Lead-free/Halogen-free
Automotive Temperature
(40C to 125C)
AT25128AN-10SQ-2.7
AT25128A-10TQ-2.7
Package Type
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8A2
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
2.7
Low-voltage (2.7V to 5.5V)
13
5088F–SEEPR–2/07
AT25256A Ordering Information
Ordering Code
Package
Operation Range
8S1
8A2
Lead-free/Halogen-free
Automotive Temperature
(40C to 125C)
AT25256AN-10SQ-2.7
AT25256A-10TQ-2.7
Package Type
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8A2
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
2.7
14
Low-voltage (2.7V to 5.5V)
AT25128A/256A
5088F–SEEPR–2/07
AT25128A/256A
Packaging Information
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
Side View
SYMBOL
MIN
NOM
MAX
A
1.35
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.00
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
∅
0˚
–
8˚
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
R
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
8S1
REV.
B
15
5088F–SEEPR–2/07
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
b
D
MIN
NOM
MAX
NOTE
2.90
3.00
3.10
2, 5
4.50
3, 5
E
E1
e
A2
D
6.40 BSC
4.30
A
–
–
1.20
A2
0.80
1.00
1.05
b
0.19
–
0.30
e
Side View
L
0.60
0.75
1.00 REF
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
R
16
4
0.65 BSC
0.45
L1
Notes:
4.40
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
8A2
REV.
B
AT25128A/256A
5088F–SEEPR–2/07
AT25128A/256A
Revision History
Doc. Rev.
Date
Comments
5088F
8/2012
Not Recommended for New Design.
Replaced by AT25128B/256B Automotive.
5088F
2/2007
Revision history implemented
Removed PDIP package offering
Removed Pb’d parts
17
5088F–SEEPR–2/07
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
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Switzerland
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Room 1219
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East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
Japan
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1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Atmel Operations
Memory
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
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Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
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