AT73C211 - Mature

Features
•
•
•
•
•
•
•
DC to DC Converter 1.9V / 2.5V (DCDC1)
LDO Regulator 2.7V / 2.8V (LDO1)
LDO Regulator 2.8V (LDO2)
LDO Regulator 2.8V (LDO3)
LDO Regulator 2.47V / 2.66 (LDO4) - Backup Battery Supply
LDO Regulator 1.72V / 2.66 (LDO5) - RTC Supply
Reset Generator
1. Description
The AT73C211 is a power management device for digital, analog, interface, and, in
some cases, RF and backup sections of add-on modules used as accessories in popular handheld devices like mobile phones, digital still cameras, PDAs and a wide
range of multimedia devices. The AT73C211 can also be used to supply the CPU with
a high-efficiency DC-DC Converter, a radio frequency transceiver with high power
supply rejection ratio (PSRR) and noise performance low-dropout (LDO) regulators, or
memories and analog sections with independent LDO channels.
Power
Management
AT73C211
In addition, the AT73C211 integrates LDO regulators to recharge backup elements
and convert its voltage to microcontroller RTC supply.
LDO regulators and DC-DC converters output voltage can be programmed by a mask
change.
6199A–PMGMT–20-Sep-05
2. Functional Block Diagram
Figure 2-1.
AT73C211 Block Diagram
VPAD
VBATT
VBATT
POR
UP-ON/OFF
UP-ON/OFF
VPAD
RESET
GENERATOR
35ms
EN
ON/OFF
10KHz
OSC
ON/OFF
PMC
State
Machine
LS
SPI
VBATT>3.2V
CORE DC/ DC
en_vpad
CREF
GND
Vref
FB
DCDC
EN
Over-Temp
DGND
LX
LX
VIN
LP
CREF
RESET-B
en_vcore
reset
EN
RESET-B
State Machine Reset
GND
EN
VCORE
VCORE
1.9/2.5V / 300 mA
GND1
GND
ECO-MODE
ECO-MODE
ANALOG LDO
VIN
VBATT
LDO1
en_vcore
GND
AGND
EN
AVCC
2.7/ 2.8V / 130 mA
AGND
AGND
BB1
VIN-REG1
VBATT
PAD LDO
VIN-REG2
VBATT
VIN
LP
RTC SUPPLY BLOCK
VCC-RTC
1.72 /2.66V
0.5mA
GND
2.8V
AVCC
EN-ANALOG-B
EN-ANALOG-B
BAT-RTC
2.47 /2.66V
5 mA
VOUT
GND
BAT-RTC
VBACK
VCC-RTC
GND
VIN
GND
LDO4
LDO5
AGND1
V-PAD
2.8V / 80 mA
LDO2
EN
GND
V-PAD
VOUT
GND
2.7V
BB1
DEEP
DISCHARGED
EN
2.6V
BB1
VVIB
EN
GND
GND GND
VBATT
VIBRATOR LDO
VIN
en_vcore
EN-VIB
VOUT
VIB -OUT
V-VIB
2.8V /130 mA
LDO3
EN
GND
DGND
GND
GND
BB1
GND
TEST
GND
2
AT73C211
6199A–PMGMT–20-Sep-05
AT73C211
3. Pin Description
Table 3-1.
Pin Description
Signal
Pin
Type
A/D
Description
VBATT
E1
VBATT1
ON/OFF
D5
IPD
D
Key ON/OFF input, 1.5M Ohm pull-down
UP-ON/OFF
C6
I
D
Hold the Power ON from MCU
RESET-B
F6
OD
D
Reset open collector output. Need external pull-up to VBATT
VIN-REG1
G6
VBATT2
LX
F7
O
A
DC/DC converter output inductor
ECO-MODE
G5
IPD
D
Eco Mode, from MCU - sets VCORE, V-PAD in low power mode,
1.5M Ohm pull-down
VCORE
G4
O
A
DC/DC converter output (MCU core supply)
GND1
G7
Ground
Ground of DC/DC converter
VIN-REG2
A5
VBATT3
Input supply
EN-ANALOG-B
B5
IPD
D
Enable the analog LDO, active at logic 0, 1.5M Ohm pull-down
AVCC
B4
O
A
Analog LDO output (MCU chip analog supply)
AGND
A7
Ground
V-PAD
B6
O
A
Digital LDO output (MCU chip digital PAD supply)
VCC-RTC
B7
O
A
MCU RTC supply output
BAT-RTC
A6
I/O
A
RTC backup battery charger - must be connected through a 2.2K
Ohm resistor to the backup battery
VIN-RF
A3
VBATT4
Input supply
AGND2
A2
Ground
Ground
VIN-VIB
D7
VBATT5
Input supply for vibrator LDO
EN-VIB
E6
IPD
D
Vibrator driver input (from baseband chip), 1.5M Ohm pull-down
VVIB
E7
O
A
Vibrator LDO output (Voltage regulator)
GND
D1
Ground
CREF
C7
O
A
Bandgap decoupling - 100 nF capacitor must be connected from
this pin to ground
BB1
D4
I
D
BB1 = 1 => VCORE = 2.5V, BB1= 0 => VCORE = 1.9V
TEST
E5
IPD
A
Connect to AGND
Input supply
Input supply for DC/DC converter
Ground of AVCC, V-PAD and RTC LDO
Ground
3
6199A–PMGMT–20-Sep-05
4. Functional Description
4.1
DC to DC Converter 1.9V/2.5V - 300 mA for Coprocessor Core
The DC-to-DC converter is a synchronous mode DC-to-DC “buck”-switched regulator using
fixed-frequency architecture (PWM) and capable of providing 300 mA of continuous current. It
has two levels of voltage programming for the co-processor core (1.9V or 2.5V). The operating
supply range is from 3.1V to 5.5V, making it suitable for Li-Ion, Li-polymer or Ni-MH battery
applications. The DC-to-DC converter is based on pulse width modulation architecture to control the noise perturbation for switching noise sensitive applications (Wireless). The operating
frequency is set to 900 kHz using an internal clock, allowing the use of a small surface inductor and moderate output voltage ripple. The controller consists of a reference ramp generator,
a feedback comparator, the logic driver used to drive the internal switches, the feedback circuits used to manage the different modes of operation and the over-current protection circuits.
An economic mode has been defined to reduce quiescent current. A low-dropout voltage regulator in parallel to the DC-to-DC converter minimizes standby current consumption during
standby mode.
Figure 4-1.
Dual-power DC-to-DC Converter
VBATT
ECO-MODE
DC-to-DC Buck
1.9V or 2.5V
300 mA
Internal FET
L
VCORE
C
LDO
1.9V or 2.5V
10 mA
Low Power
Low undershoot voltage is expected when going from PWM to LDO mode and vice-versa. The
circuit is designed in order to avoid any spikes when transition between two modes is enabled.
Figure 4-2.
Low-power/Full-power DC-to-DC Converter Transition
VCORE
VCORE
High Power
ECO-MODE
4
Low Power
High Power
Low Power
ECO-MODE
AT73C211
6199A–PMGMT–20-Sep-05
AT73C211
Figure 4-3 shows typical efficiency levels of the DC-to-DC converter for several input voltages.
Figure 4-3.
DC-to-DC Converter with 1.9V Target Typical Case(1)
100
Efficiency (%)
95
90
85
VIN=3.1V
80
VIN=3.6V
75
VIN=4.2V
70
0
50
100
150
200
250
300
350
400
Load Current (m A)
Note:
4.2
1. L = 10 µH, ESR = 0.2 Ohm, c = 22 µF, @ESR = 0.1 Ohm
LDO1, LDO3 Regulators
The PSRR measures the degree of immunity against voltage fluctuations achieved by a regulator. An example of its importance is in the case of a GSM phone when the antenna switch
activates the RF power amplifier (PA). This causes a current peak of up to 2A on the battery,
with an important spike on the battery voltage. The voltage regulator must filter or attenuate
this spike.
5
6199A–PMGMT–20-Sep-05
Figure 4-4.
Functional Diagram of LDO Single Mode
VBATT
VINT
ON
ON
IBIAS
VBG
ON
Pass
Device
GND
VOUT
VOUT1
VOUT2
VOUTS
GND
Current Sensing
and Limiter
ON
R1
GND
R2
ON
GND
Figure 4-5 shows the Power Supply Rejection Ratio as functions of frequency and battery voltage. If a noise signal occurs at 1 kHz when the battery voltage is at 3V, the noise will be
attenuated by 70 dB (divided by more than 3000) at the output of the regulator. Consequently,
a 2V spike on the battery is attenuated to less than 1 mV, which is low enough to avoid any
risk of malfunction by a device supplied by the regulator.
Figure 4-5.
Power Supply Rejection Ratio in Function of Frequency and Battery Voltage
P o w e r S u p p ly Re je ctio n Ra tio a t F u ll Lo a d
P o w e r S u p p ly Re je ctio n Ra tio a t F u ll L o a d
ve rsu s Ba tte ry V o lta g e
10
100
1000
10000
100000
3.0
-30
-35
4.5
5.0
5.5
-50
-45
-60
-50
-55
V BAT = 4.25V
-60
V BAT = 5.5V
P S RR [d B]
PSRR [d B]
4.0
-40
V BAT = 3V
-40
-65
3.5
-30
-70
-80
-90
Freq = 1 kHz
Freq = 20 kHz
Freq = 100 kHz
-100
-70
-110
-75
Freq = 100 Hz
-120
-80
Ba tte ry V o lta g e [V ]
Fr e q [Hz ]
6
AT73C211
6199A–PMGMT–20-Sep-05
AT73C211
4.3
LDO2 Regulator
The first approach to reducing standby current is to decrease the standby current inside the
regulators themselves. Atmel achieves this by implementing a dual mode architecture where
two output transistors are used in parallel as switches in the regulation loop. Figure 4-6 illustrates this architecture.
Figure 4-6.
Functional Diagram of LDO Dual Mode
VBATT
ON
LP
V BG
ON
LP
V BG
ON
ON
GND
VOUT
GND
VVOUT1
VVOUT2
ON
LP
Current Sensing
and Limiting
GND
VOUT
R1
VCORE
R2
ON
BIAS
ON, LP
GND
GND
In Figure 4-6, the left-hand output transistor is sized large enough for the required output current under full load, for example, 100 mA. In order to achieve a sufficient margin of stability,
the current sensing block uses a bias cell where the current consumption is linked to the
required output current. The higher the output current, the higher the bias current needed to
stabilize the loop.
The right-hand output transistor delivers a very small output current, typically less than 1 mA,
sufficient only to maintain the output voltage with enough current to cover the leakage current
of the supplied device. This requires a much smaller bias current and, consequently, a smaller
standby current inside the regulator.
7
6199A–PMGMT–20-Sep-05
5. Electrical Characteristics
5.1
Absolute Maximum Ratings
Operating Temperature (Industrial).............. -40° C to +85° C
*NOTICE:
Storage Temperature .................................. -55°C to +150°C
Power Supply Input Pads............................... -0.3V to +5.5V
I/O Input (all except to power supply) ........... -0.3V to +3.3V
5.2
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or other
conditions beyond those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
DC to DC Converter
Table 5-1.
DC to DC Converter Electrical Characteristics (tAMB = -20° C to 85° C, VIN = 3.2V to 4.2V unless otherwise
specified)
Symbol
Parameter
VOUT
Output Voltage
IOUT
Output Current
IOFF
Standby Current
EFF
Efficiency
IOUT = 10 mA to 200 mA @1.9V
90
%
∆VDCLD
Static Load Regulation
10% to 90% of IOUT(MAX)
7
mV
∆VTRLD
Transient Load Regulation
10% to 90% of IOUT(MAX),
TR = TF = 5µs
30
mV
∆VDCLE
Static Line Regulation
10% to 90% of IOUT(MAX),
VIN = 3.2V to 4.2V
20
mV
∆VTRLE
Transient Line Regulation
10% to 90% of IOUT(MAX),
VIN = 3.2V to 4.2V
35
mV
PSRR
Ripple Rejection
LDO Mode up to 1 KHz
45
dB
∆VLPFP
Overshoot Voltage
Voltage drop from LDO (ECOMODE = 1) to PWM (ECOMODE = 0)
∆VFPLP
Undershoot Voltage
Voltage drop from PWM (ECOMODE = 0) to LDO (ECO-MODE
= 1)
Min
Typ
Max
Unit
BB1 = 0
1.9
V
BB1 = 1
2.5
V
PWM Mode (ECO-MODE = 0)
150
LDO Mode (ECO-MODE = 1)
Table 5-2.
0.1
40
0
300
mA
5
mA
1
µA
10
mV
-15
0
mV
Min
Typ
Max
Unit
17
22
26
µF
100
mOhm
12
µH
1.1
Ohm
DC to DC Converter External Components
Symbol
Parameter
COUT
Output Capacitor Value
CESR
Output Capacitor ESR
LOUT
Output Inductor Value
LESR
Output Inductor ESR
8
Conditions
Conditions
8
At 100 kHz
10
AT73C211
6199A–PMGMT–20-Sep-05
AT73C211
5.3
LDO1 Regulator Electrical Characteristics
Table 5-3.
LDO1 Electrical Characteristics (tAMB = -20°C to 85°C, VIN = 3.2V to 4.2V unless otherwise specified)
Symbol
Parameter
VOUT
Output Voltage
IOUT
Output Current
80
IQC
Quiescent Current
195
∆VOUT
Line Regulation
VIN: 3V to 3.4V, IOUT = 130 mA
1
2
mV
∆VPEAK
Line Regulation Transient
Same as above, TR = TF = 5 µs
1.5
2.85
mV
∆VOUT
Load Regulation
10% - 90% IOUT
3
mV
∆VPEAK
Load Regulation Transient
Same as above, TR = TF = 5 µs
2.4
mV
PSRR
Ripple rejection
F = 217 Hz; VIN = 3.6V
VN
Output Noise
BW: 10 Hz to 100 kHz
TR
Rise Time
100% IOUT, 10% - 90% VOUT
ISD
Shut Down Current
Table 5-4.
Conditions
Min
Typ
Max
Unit
BB1 = 0
2.7
V
BB1 = 1
2.8
V
1.2
70
130
µA
73
29
mA
dB
37
µVRMS
50
µs
1
µA
LDO1 External Components
Symbol
Parameter
COUT
Output Capacitor Value
CESR
Output Capacitor ESR
Conditions
100 kHz
Min
Typ
Max
Unit
1.98
2.2
2.42
µF
50
mOhm
9
6199A–PMGMT–20-Sep-05
5.4
LDO2 Regulator Electrical Characteristics
Table 5-5.
LDO2 Electrical Characteristics (tAMB = -20°C to 85°C, VIN = 3.2V to 4.2V unless otherwise specified)
Symbol
Parameter
Conditions
VOUT
Output Voltage
IOUT
Output Current
IQC
Quiescent Current
∆VOUT
Line Regulation
VIN: 3V to 3.4V, IOUT = 80 mA
∆VPEAK
Line Regulation Transient
Same as above, TR = TF = 5 µs
∆VOUT
Load Regulation
10% - 90% IOUT, VIN = 3V
∆VPEAK
Load Regulation Transient
Same as above, TR = TF = 5 µs
PSRR
Ripple rejection
F = 217 Hz; VIN = 3.6V
VN
Output Noise
BW: 10 Hz to 100 kHz
TR
Rise Time
100% IOUT, 10% - 90% VOUT
ISD
Shut Down Current
Min
Unit
V
PWM Mode (ECO-MODE = 0)
80
mA
LDO Mode (ECO-MODE = 1)
5
mA
100
LDO Mode (ECO-MODE = 1)
Table 5-6.
Max
2.8
PWM Mode (ECO-MODE = 0)
10
µA
1
2
mV
1.5
2.85
mV
3
mV
2.4
mV
1.2
70
µA
73
29
dB
37
µVRMS
50
µs
1
µA
LDO2 External Components
Symbol
Parameter
COUT
Output Capacitor Value
CESR
Output Capacitor ESR
10
Typ
Conditions
100 kHz
Min
Typ
Max
Unit
1.98
2.2
2.42
µF
50
mOhm
AT73C211
6199A–PMGMT–20-Sep-05
AT73C211
5.5
LDO3 Regulator Electrical Characteristics
Table 5-7.
LDO3 Electrical Characteristics (tAMB = -20°C to 85°C, VIN = 3.2V to 4.2V unless otherwise specified)
Symbol
Parameter
VOUT
Output Voltage
2.8
IOUT
Output Current
80
IQC
Quiescent Current
195
∆VOUT
Line Regulation
VIN: 3V to 3.4V, IOUT = 130 mA
1
2
mV
∆VPEAK
Line Regulation Transient
Same as above, TR = TF = 5 µs
1.5
2.85
mV
∆VOUT
Load Regulation
10% - 90% IOUT, VIN = 3V
3
mV
∆VPEAK
Load Regulation Transient
Same as above, TR = TF = 5 µs
2.4
mV
PSRR
Ripple rejection
F = 217 Hz; VIN = 3.6V
VN
Output Noise
BW: 10 Hz to 100 kHz
TR
Rise Time
100% IOUT, 10% - 90% VOUT
ISD
Shut Down Current
Table 5-8.
Conditions
Min
Typ
1.2
70
Max
V
130
mA
µA
73
29
Unit
dB
37
µVRMS
50
µs
1
µA
LDO3 External Components
Symbol
Parameter
COUT
Output Capacitor Value
CESR
Output Capacitor ESR
Conditions
100 kHz
Min
Typ
Max
Unit
1.98
2.2
2.42
µF
50
mOhm
11
6199A–PMGMT–20-Sep-05
5.6
LDO4 Regulator Electrical Characteristics
Table 5-9.
LDO4 Electrical Characteristics (tAMB = -20°C to 85°C, VIN = 3.2V to 4.2V unless otherwise specified)
Symbol
Parameter
VOUT
Output Voltage
IOUT
Output Current
2
mA
IQC
Quiescent Current
10
µA
∆VOUT
Line Regulation
VIN: 3V to 3.4V, IOUT = 2 mA
15
mV
∆VPEAK
Line Regulation Transient
Same as above, TR = TF = 5 µs
30
mV
∆VOUT
Load Regulation
10% - 90% IOUT, VIN = 3V
15
mV
∆VPEAK
Load Regulation Transient
Same as above, TR = TF = 5 µs
20
mV
PSRR
Ripple rejection
F = 217 Hz; VIN = 3.6V
ISD
Shut Down Current
Table 5-10.
Min
Typ
Max
Unit
BB1 = 0
2.47
V
BB1 = 1
2.66
V
50
dB
1
µA
LDO4 External Components
Symbol
Parameter
COUT
Output Capacitor Value
CESR
Output Capacitor ESR
12
Conditions
Conditions
100 kHz
Min
Typ
Max
Unit
1.98
2.2
2.42
µF
100
mOhm
AT73C211
6199A–PMGMT–20-Sep-05
AT73C211
5.7
LDO5 Regulator Electrical Characteristics
Table 5-11.
LDO5 Electrical Characteristics (tAMB = -20°C to 85°C, VIN = 3.2V to 4.2V unless otherwise specified)
Symbol
Parameter
VOUT
Output Voltage
IOUT
Output Current
IQC
Quiescent Current
∆VOUT
Line Regulation
∆VPEAK
Conditions
Min
Typ
Max
Unit
BB1 = 0
1.72
V
BB1 = 1
2.66
V
0.5
mA
5
µA
VIN: 3V to 3.4V, IOUT = 0.5 mA
15
mV
Line Regulation Transient
Same as above, TR = TF = 5 µs
30
mV
∆VOUT
Load Regulation
10% - 90% IOUT, VIN = 3V
15
mV
∆VPEAK
Load Regulation Transient
Same as above, TR = TF = 5 µs
20
mV
PSRR
Ripple rejection
F = 217 Hz; VIN = 3.6V
ISD
Shut Down Current
Table 5-12.
50
dB
1
µA
LDO4 External Components
Symbol
Parameter
COUT
Output Capacitor Value
CESR
Output Capacitor ESR
Conditions
100 kHz
Min
Typ
Max
Unit
65
100
135
nF
100
mOhm
20
13
6199A–PMGMT–20-Sep-05
5.8
Package Outline (Top view)
Figure 5-1.
Forty-nine Ball FBGA Package (Top View)
1
2
NC
3
AGND2
4
VIN-RF
5
6
GND
VIN-REG2
AVCC
EN-ANALOG-B
7
BAT-RTC
AGND
A
1
2
3
NC
NC
4
NC
5
6
7
V-PAD
VCC-RTC
B
1
2
NC
3
NC
4
NC
5
NC
6
NC
7
UP-ON/OFF
CREF
C
1
2
GND
3
NC
4
NC
5
BB1
6
ON/OFF
7
NC
VIN-VIB
D
1
2
VBATT
3
NC
4
NC
5
GND
6
TEST
7
VVIB
EN-VIB
E
1
2
NC
3
NC
4
GND
5
NC
6
NC
7
RESET-B
LX
F
1
2
NC
3
GND
4
NC
5
V-CORE
ECO-MODE
6
7
VIN-REG1
GND1
G
14
AT73C211
6199A–PMGMT–20-Sep-05
AT73C211
6. Revision History
Table 6-1.
Revision History
Doc. Rev.
Comments
6199A
First issue.
Change
Request Ref.
15
6199A–PMGMT–20-Sep-05
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