ATF1500ABV - Mature

Features
• Operates between 3.0V to 5.25V
• High-density, High-performance Electrically-erasable Complex
•
•
•
•
•
•
•
Programmable Logic Device
– 44-pin, 32 I/O CPLD
– 100% connected
– 12 ns Maximum Pin-to-pin Delay
– Registered Operation up to 90.9 MHz
– Fully Connected Input and Feedback Logic Array
Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
Advanced Power Management Features
– Pin-controlled 5 µA Standby Mode (Typical)
– Programmable Pin-keeper Inputs and I/Os
Available in Commercial and Industrial Temperature Ranges
Available in 44-lead PLCC and TQFP Packages
Advanced EEPROM Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latchup Immunity
Supported by Popular Third-party Tools
Security Fuse Feature
Highperformance
EE PLD
ATF1500ABV
1. Description
The ATF1500ABV is a high-performance, high-density complex PLD. Built on an
advanced EEPROM technology, it has maximum pin-to-pin delays of 12 ns and supports sequential logic operation at speeds up to 90.9 MHz. With 32 logic macrocells
and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI and classic
PLDs.
TQFP Top View
44
43
42
41
40
39
38
37
36
35
34
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
12
13
14
15
16
17
18
19
20
21
22
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
7
8
9
10
11
12
13
14
15
16
17
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
6
5
4
3
2
1
44
43
42
41
40
I/O
I/O
I/O/PD
VCC
OE2/I
GCLR/I
OE1/I
CLK/I
GND
I/O
I/O
I/O
I/O
I/O/PD
VCC
OE2/I
GCLR/I
OE1/I
CLK/I
GND
I/O
I/O
PLCC Top View
0723K–PLD–6/05
2. Pin Configurations
2
Pin Name
Function
CLK
Clock
I
Logic Inputs
I/O
Bi-directional Buffers
GCLR
Register Reset (active low)
OE1, OE2
Output Enable (active low)
VCC
(+3V to 5.25V) Supply
PD
Power-down (active high)
ATF1500ABV
0723K–PLD–6/05
ATF1500ABV
3. Functional Logic Diagram(1)
Note:
1. Arrows connecting macrocells indicate direction and groupings of CASIN/CASOUT data flow.
3
0723K–PLD–6/05
The ATF1500ABV’s 100% connected global input and feedback architecture simplifies logic
placement and eliminates pinout changes due to design changes. Any Macrocell may be connected to any I/O pin.
The ATF1500ABV has 32 bi-directional I/O pins and four dedicated input pins. Each dedicated
input pin can also serve as a global control signal: register clock, register reset or output enable.
Each of these control signals can be selected for use individually within each macrocell.
Each of the 32 logic macrocells generates a buried feedback, which goes to the global bus.
Each input and I/O pin also feeds into the global bus. Because of this global busing, each of
these signals is always available to all 32 macrocells in the device.
Each macrocell also generates a foldback logic term, which goes to a regional bus. All signals
within a regional bus are connected to all 16 macrocells within the region.
Cascade logic between macrocells in the ATF1500ABV allows fast, efficient generation of complex logic functions. The ATF1500ABV contains four such logic chains, each capable of creating
sum term logic with a fan-in of up to 40 product terms.
4. Bus-friendly Pin-keeper Input and I/Os
All input and I/O pins on the ATF1500ABV have programmable “data-keeper” circuits. If activated, when any pin is driven high or low and then subsequently left floating, it will stay at that
previous high or low level.
This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels that
cause unnecessary power consumption and system noise. The keeper circuits eliminate the
need for external pull-up resistors and eliminate their DC power consumption.
Pin-keeper circuits can be disabled. Programming is controlled in the logic design file. Once the
pin-keeper circuits are disabled, normal termination procedures are required for unused inputs
and I/Os.
5. Speed/Power Management
The ATF1500ABV has several built-in speed and power management features. The
ATF1500ABV contains circuitry that automatically puts the device into a low-power standby
mode when no logic transitions are occurring. This not only reduces power consumption during
inactive periods, but also provides proportional power savings for most applications running at
system speeds below 10 MHz.
All ATF1500ABVs also have an optional pin-controlled power-down mode. In this mode, current
drops to typically 2 mA. When the power-down option is selected, the PD pin is used to powerdown the part. The power-down option is selected in the design source file. When enabled, the
device goes into power-down when the PD pin is high. In the power-down mode, all internal logic
signals are latched and held, as are any enabled outputs. All pin transitions are ignored until the
PD is brought low. When the power-down feature is enabled, the PD cannot be used as a logic
input or output. However, the PD pin’s macrocell may still be used to generate buried foldback
and cascade logic signals.
Each output also has individual slew rate control. This may be used to reduce system noise by
slowing down outputs that do not need to operate at maximum speed. Outputs default to slow
switching, and may be specified as fast switching in the design file.
4
ATF1500ABV
0723K–PLD–6/05
ATF1500ABV
6. Input Diagram
VCC
INPUT
100K
ESD
PROTECTION
CIRCUIT
PROGRAMMABLE
OPTION
7. I/O Diagram
VCC
OE
DATA
I/O
VCC
100K
PROGRAMMABLE
OPTION
8. Design Software Support
ATF1500ABV designs are supported by several third-party tools. Automated fitters allow logic
synthesis using a variety of high level description languages and formats.
5
0723K–PLD–6/05
9. ATF1500ABV Macrocell
10. ATF1500ABV Macrocell
The ATF1500ABV macrocell is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select
multiplexer; OR/XOR/CASCADE logic; a flip-flop; output select and enable; and logic array
inputs.
10.1
Product Terms and Select Mux
Each ATF1500ABV macrocell has five product terms. Each product term receives as its inputs
all signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as needed to the
macrocell logic gates and control signals. The PTMUX programming is determined by the design
compiler, which selects the optimum macrocell configuration.
10.2
OR/XOR/CASCADE Logic
The ATF1500ABV macrocell’s OR/XOR/CASCADE logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR
gate, creating a five-input AND/OR sum term. With the addition of the CASIN from neighboring
6
ATF1500ABV
0723K–PLD–6/05
ATF1500ABV
macrocells, this can be expanded to as many as 40 product terms with little small additional
delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions.
One input to the XOR comes from the OR sum term. The other XOR input can be a product term
or a fixed high or low level. For combinatorial outputs, the fixed-level input allows output polarity
selection. For registered functions, the fixed levels allow De Morgan minimization of the product
terms. The XOR gate is also used to emulate JK-type flip-flops.
10.3
Flip-flop
The ATF1500ABV’s flip-flop has very flexible data and control functions. The data input can
come from either the XOR gate or from a separate product term. Selecting the separate product
term allows creation of a buried registered feedback within a combinatorial output macrocell.
In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-through
latch. In this mode, data passes through when the clock is high and is latched when the clock is
low.
The clock itself can be either the global CLK pin or an individual product term. The flip-flop
changes state on the clock’s rising edge. When the CLK pin is used as the clock, one of the
macrocell product terms can be selected as a clock enable. When the clock enable function is
active and the enable signal (product term) is low, all clock edges are ignored.
The flip-flop’s asynchronous reset signal (AR) can be either the pin global clear (GCLR), a product term, or always off. AR can also be a logic OR of GCLR with a product term. The
asynchronous preset (AP) can be a product term or always off.
10.4
Output Select and Enable
The ATF1500ABV macrocell output can be selected as registered or combinatorial. When the
output is registered, the same registered signal is fed back internally to the global bus. When the
output is combinatorial, the buried feedback can be either the same combinatorial signal or it
can be the register output if the separate product term is chosen as the flip-flop input.
The output enable multiplexer (MOE) controls the output enable signals. Any buffer can be permanently enabled for simple output operation. Buffers can also be permanently disabled to allow
use of the pin as an input. In this configuration all the macrocell resources are still available,
including the buried feedback, expander and CASCADE logic.
The output enable for each macrocell can also be selected as either of the two OE pins or as an
individual product term.
10.5
Global/Regional Buses
The global bus contains all input and I/O pin signals as well as the buried feedback signal from
all 32 macrocells. Together with the complement of each signal, this provides a 68-bit bus as
input to every product term. Having the entire global bus available to each macrocell eliminates
any potential routing problems. With this architecture designs can be modified without requiring
pinout changes.
Each macrocell also generates a foldback product term. This signal goes to the regional bus,
and is available to 16 macrocells. The foldback is an inverse polarity of one of the macrocell’s
product terms. The 16 foldback terms in each region allow generation of high fan-in sum terms
(up to 21 product terms) with little additional delay.
7
0723K–PLD–6/05
11. Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
*NOTICE:
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +6.5V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns.
Maximum out put pin voltage is VCC + 0.75V DC,
which may overshoot to 6.5V for pulses of less
than 20 ns.
12. DC and AC Operating Conditions
Commercial
Industrial
0°C - 70°C
-40°C - 85°C
3.0V - 5.25V
3.0V - 5.25V
Operating Temperature (Ambient)
VCC Power Supply
13. DC Characteristics
Symbol
Parameter
Condition
IIL
Input or I/O
Low Leakage Current
IIH
Input or I/O
High Leakage Current
Min
Typ
Max
Units
0 ≤ VIN ≤ VIL(max)
-10
µA
VIH,min < VIN ≤ VCC
10
µA
Com.
35
mA
Ind.
40
mA
ATF1500ABV
ICC1(1)
Power Supply Current,
Standby
VCC = MAX,
VIN = 0, VCC
Com.
3
mA
Ind.
5
mA
ATF1500ABVL
ICC2
Power Supply Current,
Power Down Mode
VCC = MAX,
VIN = 0, VCC
IOS
Output Short Circuit
Current
VOUT = 0.5V
VIL
Input Low Voltage
VCC, min < VCC
< VCC, max
VIH
Input High Voltage
VOL
Output Low Voltage
VCC = MIN
IOL = 4 mA
Output High Voltage
VCC = MIN
IOH = -0.1 mA
VOH
Note:
8
2
mA
-130
mA
-0.5
0.8
V
2.0
VCC + 1
V
0.45
V
VCC - .2
V
1. All ICC parameters measured with outputs open, and a 16-bit loadable, up/down counter programmed into each region.
ATF1500ABV
0723K–PLD–6/05
ATF1500ABV
14. AC Waveforms
15. Register AC Characteristics, Input Pin Clock
-12
Symbol
Parameter
-15
Min
Max
Min
Max
Units
2
7
2
8
ns
3
3
ns
I, I/O Setup Time
10
11
ns
tSFS
Feedback Setup Time
10
11
ns
tHS
Input, I/O, Feedback Hold Time
0
0
ns
tPS
Clock Period
13
14
ns
tWS
Clock Width
6.5
7
ns
tCOS(1)
Clock to Output
tCFS
Clock to Feedback
tSIS
fMAXS
External Feedback 1/(tSIS + tCOS)
58.8
52.6
MHz
Internal Feedback 1/(tSFS + tCFS)
76.9
71.4
MHz
No Feedback 1/(tPS)
76.9
71.4
MHz
tRPRS
Reset Pin Recovery Time
3
4
ns
tRTRS
Reset Term Recovery Time
10
12
ns
Notes:
1. For slow slew outputs, add tSSO.
9
0723K–PLD–6/05
16. Register AC Characteristics, Product Term Clock
-12
Symbol
tCOA
(1)
Parameter
Min
-15
Max
Min
Max
Units
Clock to Output
12
15
ns
tCFA
Clock to Feedback
8
10
ns
tSIA
I, I/O Setup Time
4
4
ns
tSFA
Feedback Setup Time
4
4
ns
tHA
Input, I/O, Feedback Hold Time
4
4
ns
tPA
Clock Period
12
14
ns
tWA
Clock Width
6
7
ns
fMAXA
tRPRA
tRTRA
Notes:
External Feedback 1/(tSIA + tCOA)
62.5
52.6
MHz
Internal Feedback 1/(tSFA + tCFA)
83.3
71.4
MHz
No Feedback 1/(tPA)
83.3
71.4
MHz
Reset Pin Recovery Time
0
0
ns
Reset/Preset Term Recovery Time
6
6
ns
1. For slow slew outputs, add tSSO.
17. AC Characteristics
-12
-15
Symbol
Parameter
Min
Max
Min
Max
Units
tPD(1)
I, I/O or FB to Non-Registered Output
3
12
3
15
ns
tPD2
I, I/O to Feedback
tPD3(1)
9
ns
Feedback to Non-Registered Output
15
ns
tPD4
Feedback to Feedback
9
ns
tEA(1)
OE Term to Output Enable
3
12
3
15
ns
tER
OE Term to Output Disable
2
tPZX(1)
12
2
15
ns
OE Pin to Output Enable
2
8
2
9
ns
tPXZ
OE Pin to Output Disable
1.5
8
1.5
9
ns
tPF
Preset To Feedback
9
12
ns
Preset to Registered Output
14
20
ns
Reset Pin to Feedback
3
5
ns
Reset Pin to Registered Output
8
11
ns
tRTF
Reset Term to Feedback
9
12
ns
tRTO(1)
Reset Term to Registered Output
14
20
ns
tCAS
Cascade Logic Delay
1
1
ns
tSSO
Slow Slew Output Adder
3
4
ns
tFLD
Foldback Term Delay
7
8
ns
tPO
(1)
tRPF
tRPO
(1)
Notes:
10
8
3
12
3
8
1. For slow slew outputs, add tSSO.
ATF1500ABV
0723K–PLD–6/05
ATF1500ABV
18. Power-down AC Characteristics
-12
-15
Symbol
Parameter
Min
tIVDH
Valid I, I/O before PD High
12
15
ns
12
15
ns
(2)
before PD High
Max
Min
Max
Units
tGVDH
Valid OE
tCVDH
Valid Clock(2) before PD High
12
15
ns
tDHIX
Input Don't Care after PD High
22
25
ns
tDHGX
OE Don't Care after PD High
22
25
ns
tDHCX
Clock Don't Care after PD High
22
25
ns
tDLIV
PD Low to Valid I, I/O
(2)
PD Low to Valid OE
tDLGV
(2)
1
1
µs
1
1
µs
tDLCV
PD Low to Valid Clock
1
1
µs
tDLOV(1)
PD Low to Valid Output
1
1
µs
Notes:
1. For slow slew outputs, add tSSO.
2. Pin or Product Term
19. Input Test Waveforms and Measurement Levels
20. Output Test Load
21. Pin Capacitance
(f = 1 MHz, T = 25°C)(1)
Typ
Max
Units
Conditions
CIN
4.5
5.5
pF
VIN = 0V
COUT
3.5
4.5
pF
VOUT = 0V
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
11
0723K–PLD–6/05
22. Power-up Reset
The ATF1500ABV’s registers are designed to reset during power-up. At a point delayed slightly
from VCC crossing VRST, all registers will be reset to the low state. As a result, the registered output state will always be low on power-up.
This feature is critical for state machine initialization. However, due to the asynchronous nature
of reset and the uncertainty of how VCC actually rises in the system, the following conditions are
required:
1. The VCC rise must be monotonic.
2. Signals from which clocks are derived must remain stable during TPR.
3. After TPR occurs, all input and feedback setup times must be met before driving the
clock signal high.
23. Power-down Mode
The ATF1500ABV includes an optional pin-controlled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply current is reduced to less than 10 µA. During power-down, all output data and internal logic states
are latched and held. Therefore, all registered and combinatorial output data remain valid. Any
outputs that were in a High-Z state at the onset of power-down will remain at High-Z. During
power-down, all input signals except the power-down pin are blocked. Input and I/O hold latches
remain active to ensure that pins do not float to indeterminate levels, further reducing system
power. The power-down pin feature is enabled in the logic design file. Designs using the powerdown pin may not use the PD pin logic array input. However, all other PD pin macrocell
resources may still be used, including the buried feedback and foldback product term array
inputs.
24. Register Preload
The ATF1500ABV’s registers are provided with circuitry to allow loading of each register with
either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with
preload vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done
automatically when vectors are run by any approved programmers. The preload mode is
enabled by raising an input pin to a high voltage level. Contact Atmel PLD Applications for PRELOAD pin assignments, timing and voltage requirements.
12
ATF1500ABV
0723K–PLD–6/05
ATF1500ABV
Parameter
Description
Typ
Max
Units
TPR
Power-up
Reset Time
2
10
µs
VRST
Power-up
Reset
Voltage
2.2
2.7
V
25. Output Slew Rate Control
Each ATF1500ABV macrocell contains a configuration bit for each I/O to control its output slew
rate. This allows selected data paths to operate at maximum throughput while reducing system
noise from outputs that are not speed-critical. Outputs default to slow edges, and may be individually set to fast in the design file. Output transition times for outputs configured as “slow” have a
tSSO delay adder.
26. Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF1500ABV fuse patterns.
Once programmed, fuse verify and preload are prohibited. However, the 160-bit User Signature
remains accessible.
The security fuse should be programmed last, as its effect is immediate.
13
0723K–PLD–6/05
27. Ordering Information
tPD
(ns)
tCOS
(ns)
FMAXS
(MHz)
12
6
15
8
Note:
Ordering Code
Package
Operation Range
62.5
ATF1500ABV-12AC
ATF1500ABV-12JC
44A
44J
Commercial
(0°C to 70°C)
52.6
ATF1500ABV-15AC
ATF1500ABV-15JC
44A
44J
Commercial
(0°C to 70°C)
The last time buy date is Sept. 30, 2005 for shaded parts. The suggested replacements are ATF1502ASV-15JU44 or
ATF1502ASV-15AU44 which are Green packages.
Package Type
44A
44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44J
44-lead, Plastic J-leaded Chip Carrier (PLCC)
14
ATF1500ABV
0723K–PLD–6/05
ATF1500ABV
28. Packaging Information
28.1
44A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
e
E
D1
D
C
0˚~7˚
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
11.75
12.00
12.25
D1
9.90
10.00
10.10
E
11.75
12.00
12.25
E1
9.90
10.00
10.10
B
0.30
–
0.45
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.80 TYP
10/5/2001
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
REV.
44A
B
15
0723K–PLD–6/05
28.2
44J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
D2/E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
17.399
–
17.653
D1
16.510
–
16.662
E
17.399
–
17.653
E1
16.510
–
16.662
D2/E2
14.986
–
16.002
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
16
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
44J
B
ATF1500ABV
0723K–PLD–6/05
ATF1500ABV
29. Revision History
Revision
Comments
0723K
Industrial grade parts were removed from the datasheet
17
0723K–PLD–6/05
Atmel Corporation
2325 Orchard Parkway
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