ATxmega64B1/128B1 - Complete

Atmel AVR XMEGA B1 8- and 16-bit Microcontroller
ATxmega128B1 / ATxmega64B1
Features
 High-performance, low-power Atmel® AVR® XMEGA® 8- and16-bit Microcontroller
 Nonvolatile program and data memories




64K - 128KBytes of in-system self-programmable flash
4K - 8KBytes boot section
2KBytes EEPROM
4K - 8KBytes internal SRAM
 Peripheral features
 Two-channel DMA controller
 Four-channel event system
 Three 16-bit timer/counters
 Two timer/counters with four output compare or input capture channels
 One timer/counter with two output compare or input capture channels
 High resolution extensions one timer/counter
 Advanced waveform extension (AWeX) on one timer/counter
 Split mode on two timer/counters
 One USB device interface
 USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
 32 endpoints with full configuration flexibility
 Two USARTs with IrDA support for one USART
 AES and DES crypto engine
 CRC-16 (CRC-CCITT) and CRC-32 (IEEE® 802.3) generator
 One two-wire interface with dual address match (I2C and SMBus compatible)
 One serial peripheral interface (SPI)
 16-bit Real Time Counter (RTC) with separate oscillator
 Liquid Crystal Display (LCD)
 Up to 4x40 segment driver
 Built in contrast control
 ASCII character mapping
 Flexible SWAP of segment and common terminals buses
 Two eight-channel, 12-bit, three hundred thousand SPS Analog to Digital Converters
 Four Analog Comparators with window compare function, and current source feature
 External interrupts on all general purpose I/O pins
 Programmable watchdog timer with separate on-chip ultra low power oscillator
 QTouch® library support
 Capacitive touch buttons, sliders and wheels
 Special microcontroller features
 Power-on reset and programmable brown-out detection
 Internal and external clock options with PLL
 Programmable multilevel interrupt controller
 Five sleep modes
 Programming and debug interfaces
 JTAG (IEEE 1149.1 Compliant) interface, including boundary scan
 PDI (Program and Debug Interface)
 I/O and packages
 53 Programmable I/O pins
 100-lead TQFP, 100-ball VFBGA
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
 Operating voltage
 1.6 – 3.6V
 Operating frequency
 0 – 12MHz from 1.6V
 0 – 32MHz from 2.7V
1.
Ordering Information
Flash
[Bytes]
Ordering Code
EEPROM
[Bytes]
SRAM
[Bytes]
Speed
[MHz]
Power
supply
Package(1)(2)(3)
Temp.
ATxmega128B1-AU
100A
ATxmega128B1-AUR(4)
-40C - 85C
ATxmega128B1-CU
128K + 8K
2K
8K
32
1.6 - 3.6V
7A1
ATxmega128B1-CUR(4)
ATxmega128B1-AN
100A
-40C - 105C
ATxmega128B1-ANR(4)
ATxmega64B1-AU
100A
ATxmega64B1-AUR(4)
-40C - 85C
ATxmega64B1-CU
64K + 4K
2K
4K
32
1.6 - 3.6V
7A1
ATxmega64B1-CUR(4)
ATxmega64B1-AN
100A
-40C - 105C
ATxmega64B1-ANR(4)
Notes:
1.
2.
3.
4.
This device can also be supplied in wafer form. Contact your local Atmel sales office for detailed ordering information.
Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
For packaging information, see “Errata” on page 136.
Tape and Reel.
Package Type
100A
100-lead, 14 x 14mm body size, 1.0mm body thickness, 0.5mm lead pitch, thin profile plastic quad flat package (TQFP)
7A1
100-ball (10x10 array), 7 x 7 x 1.0mm body, ball pitch 0.65mm, very thin fine-pitch ball grid array (VFBGA)
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
2
Typical Applications
Industrial control
Climate control
Low power battery applications
Factory automation
RF and ZigBee®
Power tools
Building control
USB connectivity
HVAC
Board control
Sensor control
Utility metering
White goods
Optical
Medical applications
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
3
2.
Pinout/Block Diagram
Figure 2-1. Block Diagram and Pinout
PB6
PB5
PB4
PB3
PB2
PB1
PB0
AVCC
AGND
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PR1
PR0
COM3
COM2
COM1
COM0
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
General Purpose I/O
GND
External clock / Crystal pins
PB7
Programming, debug, test
Analog function / Oscillators
99
LCD
100
Power
Ground
Digital function
VCC
1
75
CAPH
PC0
2
74
CAPL
PC1
3
73
VLCD
72
BIAS2
71
BIAS1
70
VCC
69
GND
68
SEG0
67
SEG1
66
SEG2
65
SEG3
64
SEG4
63
SEG5
62
SEG6
61
SEG7
60
SEG8
59
SEG9
58
SEG10
57
SEG11
56
SEG12
55
SEG13
54
SEG14
11
PD0
12
PD1
13
PD2
14
PDI / RESET
15
PDI
16
GND
17
VCC
18
TC0:1
19
PE1
20
PE2
Note:
TEMPREF
Watchdog
Oscillator
Power
Supervision
Real Time
Counter
VREF
Sleep
Controller
Reset
Controller
Event System
Controller
Interrupt
Controller
OCD
Prog/Debug
Interface
USART0
SPI
TWI
USB
TC0
Watchdog
Timer
DMA
Controller
Crypto / CRC
BUS
Controller
CPU
USART0
EEPROM
IRCOM
PE0
OSC/CLK
Control
COM
VCC
DATA BUS
LCD PWR
9
10
EVENT ROUTING NETWORK
SEG
PC7
GND
Port R
AREF
8
ADC
PC6
AC0:1
7
Port A
AREF
6
PC5
ADC
PC4
JTAG
5
Port C
PC3
Port D
4
Port E
PC2
AC0:1
Port B
FLASH
SRAM
DATA BUS
SEG
21
Port G
LCD Controller
Port M
1.
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PG3 / SEG36
PG4 / SEG35
PG5 / SEG34
PG6 / SEG33
PG7 / SEG32
PM0 / SEG31
PM1 / SEG30
PM2 / SEG29
PM3 / SEG28
PM4 / SEG27
PM5 / SEG26
PM6 / SEG25
PM7 / SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
PG2 / SEG37
51
PG1 / SEG38
25
29
PE6
PG0 / SEG39
SEG16
28
SEG15
52
VCC
53
24
27
23
PE5
26
PE4
PE7
22
GND
PE3
For full details on pinout and alternate pin functions refer to “Pinout and Pin Functions” on page 54.
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
4
Figure 2-2. VFBGA Pinout
Top view
1
2
3
4
5
6
Bottom view
7
8
9
10
10
9
8
7
6
5
4
3
2
1
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
Table 2-1.
VFBGA Pinout
1
2
3
4
5
6
7
8
9
10
A
PC0
VCC
PB6
PB2
AVCC
PA5
PA1
PR1
COM2
CAPH
B
PC3
GND
PB7
PB4
AGND
PA4
PA0
PR0
COM1
CAPL
C
PC5
PC4
PC1
PB5
PA7
PA3
COM3
COM0
BIAS2
BIAS1
D
VCC
GND
PD0
PC2
PB0
PA6
SEG0
VLCD
GND
VCC
E
PD2
PDI/
RESET
PD1
PC6
PB1
PA2
SEG1
SEG4
SEG3
SEG2
F
VCC
GND
PDI
PC7
PB3
PM2/
SEG29
SEG10
SEG7
SEG6
SEG5
G
PE2
PE1
PE3
PE0
PE4
SEG23
SEG15
SEG13
SEG9
SEG8
H
PE5
PE6
PG1/
SEG38
PG4/
SEG35
PG7/
SEG32
PM5/
SEG26
SEG21
SEG18
SEG12
SEG11
J
PE7
PG0/
SEG39
PG3/
SEG36
PG6/
SEG33
PM1/
SEG30
PM4/
SEG27
PM7/
SEG24
SEG20
SEG16
SEG14
K
GND
VCC
PG2/
SEG37
PG5/
SEG34
PM0/
SEG31
PM3/
SEG28
PM6/
SEG25
SEG22
SEG19
SEG17
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
5
3.
Overview
The Atmel® AVR® XMEGA® is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers
based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the Atmel AVR XMEGA
devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the
system designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times
faster than conventional single-accumulator or CISC based microcontrollers.
The Atmel AVR XMEGA B1 devices provide the following features: in-system programmable flash with read-while-write
capabilities; internal EEPROM and SRAM; two-channel DMA controller, four-channel event system and programmable
multilevel interrupt controller, 53 general purpose I/O lines, real-time counter (RTC); Liquid Crystal Display supporting up
to 4x40 segment driver, ASCII character mapping and built-in contrast control (LCD); three flexible, 16-bit timer/counters
with compare and PWM channels; two USARTs; one two-wire serial interface (TWI); one full speed USB 2.0 interface;
one serial peripheral interface (SPI); AES and DES cryptographic engine; two 8-channel, 12-bit ADCs with
programmable gain; four analog comparators (ACs) with window mode; programmable watchdog timer with separate
internal oscillator; accurate internal oscillators with PLL and prescaler; and programmable brown-out detection.
The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. The
devices also have an IEEE std. 1149.1 compliant JTAG interface, and this can also be used for on-chip debug and
programming.
The ATx devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the
SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The power-down
mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI,
USB resume, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to
run, allowing the application to maintain a timer base while the rest of the device is sleeping. In power-save mode, the
LCD controller is allowed to refresh data to the panel. In standby mode, the external crystal oscillator keeps running while
the rest of the device is sleeping. This allows very fast startup from the external crystal, combined with low power
consumption. In extended standby mode, both the main oscillator and the asynchronous timer continue to run, and the
LCD controller is allowed to refresh data to the panel. To further reduce power consumption, the peripheral clock to each
individual peripheral can optionally be stopped in active mode and idle sleep mode.
Atmel offers a free QTouch® library for embedding capacitive touch buttons, sliders and wheels functionality into AVR
microcontrollers.
The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can
be reprogrammed in-system through the PDI or JTAG interfaces. A boot loader running in the device can use any
interface to download the application program to the flash memory. The boot loader software in the boot flash section will
continue to run while the application flash section is updated, providing true read-while-write operation. By combining an
8/16-bit RISC CPU with in-system, self-programmable flash, the Atmel XMEGA B1 is a powerful microcontroller family
that provides a highly flexible and cost effective solution for many embedded applications.
The atmel AVR ATx devices are supported with a full suite of program and system development tools, including C
compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
6
3.1
Block Diagram
Figure 3-1. XMEGA B1 Block Diagram
PR[0..1]
XTAL1 /
TOSC1
Power
LCD
Ground
Programming, debug, test
Digital function
External clock / Crystal pins
Analog function / Oscillators
General Purpose I/O
XTAL2 /
TOSC2
Oscillator
Circuits/
Clock
Generation
PORT R (2)
Real Time
Counter
Watchdog
Oscillator
EVENT ROUTING NETWORK
DATA BUS
PA[0..7]
Watchdog
Timer
Event System
Controller
PORT A (8)
Oscillator
Control
Power
Supervision
POR/BOD &
RESET
SRAM
DMA
Controller
ACA
Sleep
Controller
ADCA
BUS Matrix
AREFA
GND
RESET /
PDI_CLK
PDI
Prog/Debug
Controller
VCC
PDI_DATA
VCC/10
JTAG
Int. Refs.
PORT B
AES
Tempref
OCD
AREFB
DES
Interrupt
Controller
CPU
ADCB
LCD
LCD POWER[0..4]
COM[0..3]
SEG[0..23]
CRC
ACB
NVM Controller
PORT M (8)
SEG[31..24] /
PM[0..7]
PORT G (8)
SEG[39..32] /
PG[0..7]
PORT B (8)
Flash
EEPROM
DATA BUS
PORT D (3)
TCE0
USARTE0
USB
SPIC
PORT C (8)
TWIC
TCC0:1
USARTC0
EVENT ROUTING NETWORK
IRCOM
PB[0..7]/
JTAG
To Clock
Generator
PORT E (8)
TOSC1
(Alternate)
TOSC2
PC[0..7]
PD[0..2]
PE[0..7]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
7
4.
Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
4.1
Recommended Reading

XMEGA B Manual

XMEGA Application Notes
This device data sheet only contains part specific information with a short description of each peripheral and module. The
XMEGA B Manual describes the modules and peripherals in depth. The XMEGA application notes contain example code
and show applied use of the modules and peripherals.
All documentations are available from www.atmel.com/avr.
5.
Capacitive Touch Sensing
The Atmel QTouch® library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR
microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced
reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for unambiguous detection of key
events. The QTouch library includes support for the QTouch and QMatrix acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR
Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the
touch sensing API’s to retrieve the channel information and determine the touch sensor states.
The QTouch library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User
Guide - also available for download from the Atmel website.
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
8
6.
AVR CPU
6.1
Features
 8/16-bit, high-performance Atmel AVR RISC CPU


142 instructions
Hardware multiplier
 32x8-bit registers directly connected to the ALU
 Stack in RAM
 Stack pointer accessible in I/O memory space
 Direct addressing of up to 16MB of program memory and 16MB of data memory
 True 16/24-bit access to 16/24-bit I/O registers
 Efficient support for 8-, 16-, and 32-bit arithmetic
 Configuration change protection of system-critical features
6.2
Overview
All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and
perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the
program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable
Multilevel Interrupt Controller” on page 28.
6.3
Architectural Overview
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories
and buses for program and data. Instructions in the program memory are executed with single-level pipe lining. While
one instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions
to be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr.
Figure 6-1. Block Diagram of the AVR CPU Architecture
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
9
The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is
updated to reflect information about the result of the operation.
The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have
single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a
register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data
space addressing, enabling efficient address calculations.
The memory spaces are linear. The data memory space and the program memory space are two different memory
spaces.
The data memory space is divided into I/O registers and SRAM. In addition, the EEPROM can be memory mapped in the
data memory.
All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O
memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F.
The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as
data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.
The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different
addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.
Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM.
The program memory is divided in two sections, the application program section and the boot program section. Both
sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for selfprogramming of the application flash memory must reside in the boot program section. The application section contains
an application table section with separate lock bits for write and read/write protection. The application table section can
be used for save storing of nonvolatile data in the program memory.
6.4
ALU - Arithmetic Logic Unit
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general
purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register
and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the
status register is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit
arithmetic are supported, and the instruction set allows for efficient implementation of 32-bit arithmetic. The hardware
multiplier supports signed and unsigned multiplication and fractional format.
6.4.1
Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different
variations of signed and unsigned integer and fractional numbers:

Multiplication of unsigned integers

Multiplication of signed integers

Multiplication of a signed integer with an unsigned integer

Multiplication of unsigned fractional numbers

Multiplication of signed fractional numbers

Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
10
6.5
Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash program memory ‘0.’ The program
counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole
address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general
data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After
reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the
I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be
accessed through the five different addressing modes supported in the AVR CPU.
6.6
Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. This information can be used for altering program flow in order to perform conditional operations. Note that
the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many
cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine nor restored when returning from an
interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
6.7
Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing
temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit
registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and
POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing
data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded
after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point
above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.
During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be
two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program
memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices
with more than 128KB of program memory, the return address is three bytes, and hence the SP is decremented/
incremented by three. The return address is popped off the stack when returning from interrupts using the RETI
instruction, and from subroutine calls using the RET instruction.
The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one
when data is popped off the stack using the POP instruction.
To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts
for up to four instructions or until the next I/O memory write.
6.8
Register File
The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register
file supports the following input/output schemes:

One 8-bit output operand and one 8-bit result input

Two 8-bit output operands and one 8-bit result input

Two 8-bit output operands and one 16-bit result input

One 16-bit output operand and one 16-bit result input
Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient
address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash
program memory.
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
11
7.
Memories
7.1
Features
 Flash program memory








One linear address space
In-system programmable
Self-programming and boot loader support
Application section for application code
Application table section for application code or data storage
Boot section for application code or bootloader code
Separate read/write protection lock bits for all sections
Built in fast CRC check of a selectable flash program memory section
 Data memory







One linear address space
Single-cycle access from CPU
SRAM
EEPROM
 Byte and page accessible
 Optional memory mapping for direct load and store
I/O memory
 Configuration and status registers for all peripherals and modules
 Four bit-accessible general purpose registers for global variables or flags
Bus arbitration
 Safe and deterministic handling of priority between CPU, DMA controller, and other bus masters
Separate buses for SRAM, EEPROM and I/O memory
 Simultaneous bus access for CPU and DMA controller
 Production signature row memory for factory programmed data

ID for each microcontroller device type
Serial number for each device
 Calibration bytes for factory calibrated peripherals

 User signature row

One flash page in size
Can be read and written from software
 Content is kept after chip erase

7.2
Overview
The Atmel AVR architecture has two main memory spaces; the program memory and the data memory. Executable code
can reside only in the program memory, while data can be stored in the program memory and the data memory. The data
memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and
require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write
operations. This prevents unrestricted access to the application software.
A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can
only be written by an external programmer.
The available memory size configurations are shown in “Ordering Information” on page 2. In addition, each device has a
Flash memory signature row for calibration data, device identification, serial number etc.
XMEGA B1 [DATASHEET]
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7.3
Flash Program Memory
The Atmel AVR XMEGA devices contain on-chip, in-system re-programmable flash memory for program storage. The
flash memory can be accessed for read and write from an external programmer through the PDI or from application
software running in the device.
All AVR CPU instructions are 16- or 32-bits wide, and each flash location is 16 bits wide. The flash memory is organized
in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but
device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store
program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate
when executed from the boot loader section.
The application section contains an application table section with separate lock settings. This enables safe storage of
nonvolatile data in the program memory.
Figure 7-1. Flash Program Memory (hexadecimal address)
Word Address
ATxmega128B1
ATxmega64B1
0
0
Application section (bytes)
(128K/64K)
...
7.3.1
EFFF
/
77FF
F000
/
7800
FFFF
/
7FFF
Application table section (bytes)
(8K/4K)
10000
/
8000
Boot section (bytes)
10FFF
/
87FF
(8K/4K)
Application Section
The application section is the section of the flash that is used for storing the executable application code. The protection
level for the application section can be selected by the boot lock bits for this section. The application section can not store
any boot loader code since the SPM instruction cannot be executed from the application section.
7.3.2
Application Table Section
The application table section is a part of the application section of the flash memory that can be used for storing data.
The size is identical to the boot loader section. The protection level for the application table section can be selected by
the boot lock bits for this section. The possibilities for different protection levels on the application section and the
application table section enable safe parameter storage in the program memory. If this section is not used for data,
application code can reside here.
7.3.3
Boot Loader Section
While the application section is used for storing the application code, the boot loader software must be located in the boot
loader section because the SPM instruction can only initiate programming when executing from this section. The SPM
instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader
section can be selected by the boot loader lock bits. If this section is not used for boot loader software, application code
can be stored here.
XMEGA B1 [DATASHEET]
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7.3.4
Production Signature Row
The production signature row is a separate memory section for factory programmed data. It contains calibration data for
functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the
corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to
the corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical
Characteristics” on page 69.
The production signature row also contains an ID that identifies each microcontroller device type and a serial number for
each manufactured device. The serial number consists of the production lot number, wafer number, and wafer
coordinates for the device. The device ID for the available devices is shown in Table 7-1 on page 14.
The production signature row cannot be written or erased, but it can be read from application software and external
programmers.
Table 7-1.
Device ID Bytes for XMEGA B1 Devices
Device
7.3.5
Device ID bytes
Byte 2
Byte 1
Byte 0
ATxmega64B1
52
96
1E
ATxmega128B1
4D
97
1E
User Signature Row
The user signature row is a separate memory section that is fully accessible (read and write) from application software
and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration
data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase
commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during
multiple program/erase operations and on-chip debug sessions.
7.4
Fuses and Lock bits
The fuses are used to configure important system functions, and can only be written from an external programmer. The
application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and
watchdog, startup configuration, JTAG enable, and JTAG user ID.
The lock bits are used to set protection levels for the different flash sections (i.e., if read and/or write access should be
blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels.
Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the
lock bits are erased after the rest of the flash memory has been erased.
An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero.
Both fuses and lock bits are re-programmable like the flash program memory.
7.5
Data Memory
The data memory contains the I/O memory, internal SRAM and optionally memory mapped EEPROM. The data memory
is organized as one continuous memory section, see Figure 7-2 on page 15. To simplify development, I/O Memory,
EEPROM, and SRAM will always have the same start addresses for all XMEGA devices.
XMEGA B1 [DATASHEET]
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Figure 7-2. Data Memory Map (hexadecimal address)
Byte Address
ATxmega128B1
0
Byte Address
ATxmega64B1
0
I/O Registers (4K)
FFF
I/O Registers (4KB)
FFF
1000
1000
EEPROM (2K)
17FF
EEPROM (2K)
17FF
RESERVED
2000
RESERVED
2000
Internal SRAM (8K)
3FFF
7.6
Internal SRAM (4K)
2FFF
EEPROM
Atmel AVR XMEGA B1 devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data
space (default) or memory mapped and accessed in normal data space. The EEPROM supports both byte and page
access. Memory mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing
this, EEPROM is accessible using load and store instructions. Memory mapped EEPROM will always start at
hexadecimal address 0x1000.
7.7
I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O
memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions,
which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT
instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F,
single-cycle instructions for manipulation and checking of individual bits are available.
The I/O memory address for all peripherals and modules in XMEGA B1 is shown in the “Peripheral Module Address Map”
on page 60.
7.7.1
General Purpose I/O Registers
The lowest four I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for
storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
7.8
Data Memory and Bus Arbitration
Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA controller
read, and DMA controller write, etc.) can access different memory sections at the same time.
7.9
Memory Timing
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from
SRAM takes two cycles. For burst read (DMA), new data are available every cycle. EEPROM page load (write) takes one
cycle, and three cycles are required for read. For burst read, new data are available every second cycle. Refer to the
instruction summary for more details on instructions and instruction timing.
7.10
Device ID and Revision
Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A
separate register contains the revision number of the device.
XMEGA B1 [DATASHEET]
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7.11
JTAG Disable
It is possible to disable the JTAG interface from the application software. This will prevent all external JTAG access to the
device until the next device reset or until JTAG is enabled again from the application software. As long as JTAG is
disabled, the I/O pins required for JTAG can be used as normal I/O pins.
7.12
I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the
I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is
enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers
themselves are protected by the configuration change protection mechanism.
7.13
Flash and EEPROM Page Size
The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the
flash and byte accessible for the EEPROM.
Table 7-2 on page 16 shows the Flash Program Memory organization. Flash write and erase operations are performed
on one page at a time, while reading the Flash is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used
for addressing. The most significant bits in the address (FPAGE) give the page number and the least significant address
bits (FWORD) give the word in the page.
Table 7-2.
Devices
Number of Words and Pages in the Flash
PC size
Flash
Page size
FWORD
bits
bytes
words
ATxmega64B1
16
64K + 4K
128
Z[7:1]
ATxmega128B1
17
128K + 8K
128
Z[8:1]
FPAGE
Application
Boot
Size
No. of
pages
Size
No. of
pages
Z[16:8]
64K
256
4K
16
Z[17:9]
128K
512
8K
32
Table 7-3 on page 16 shows EEPROM memory organization for the XMEGA B1 devices. EEEPROM write and erase
operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For
EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The most significant bits in the address
(E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page.
Table 7-3.
Devices
Number of Bytes and Pages in the EEPROM
EEPROM
Page size
E2BYTE
E2PAGE
No. of pages
Size
Bytes
ATxmega64B1
2K
32
ADDR[4:0]
ADDR[10:5]
64
ATxmega128B1
2K
32
ADDR[4:0]
ADDR[10:5]
64
XMEGA B1 [DATASHEET]
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8.
DMAC – Direct Memory Access Controller
8.1
Features
 Allows high speed data transfers with minimal CPU intervention

from data memory to data memory
from data memory to peripheral
 from peripheral to data memory
 from peripheral to peripheral

 Two DMA channels with separate

transfer triggers
interrupt vectors
 addressing modes

 Programmable channel priority
 From 1 byte to 16MB of data in a single transaction


Up to 64KB block transfers with repeat
1, 2, 4, or 8 byte burst transfers
 Multiple addressing modes

Static
Incremental
 Decremental

 Optional reload of source and destination addresses at the end of each

Burst
Block
 Transaction

 Optional interrupt on end of transaction
 Optional connection to CRC generator for CRC on DMA data
8.2
Overview
The two-channel direct memory access (DMA) controller can transfer data between memories and peripherals, and thus
off-load these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU
time. The four DMA channels enable up to four independent and parallel transfers.
The DMA controller can move data between SRAM and peripherals, between SRAM locations and directly between
peripheral registers. With access to all peripherals, the DMA controller can handle automatic transfer of data to/from
communication modules. The DMA controller can also read from memory mapped EEPROM.
Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of configurable size from 1
byte to 64KB. A repeat counter can be used to repeat each block transfer for single transactions up to 16MB. Source and
destination addressing can be static, incremental or decremental. Automatic reload of source and/or destination
addresses can be done after each burst or block transfer, or when a transaction is complete. Application software,
peripherals, and events can trigger DMA transfers.
The two DMA channels have individual configuration and control settings. This include source, destination, transfer
triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a
transaction is complete or when the DMA controller detects an error on a DMA channel.
To allow for continuous transfers, the channels can be interlinked so that the second takes over the transfer when the
first is finished, and vice versa.
XMEGA B1 [DATASHEET]
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9.
Event System
9.1
Features
 System for direct peripheral-to-peripheral communication and signaling
 Peripherals can directly send, receive, and react to peripheral events

CPU and DMA controller independent operation
100% predictable signal timing
 Short and guaranteed response time

 Four event channels for up to four different and parallel signal routings and configurations
 Events can be sent and/or used by most peripherals, clock system, and software
 Additional functions include


Quadrature decoders
Digital filtering of I/O pin state
 Works in active mode and idle sleep mode
9.2
Overview
The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one
peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for
short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction
without the use of interrupts, CPU, or DMA controller resources, and is thus a powerful tool for reducing the complexity,
size and execution time of application code. It also allows for synchronized timing of actions in several peripheral
modules.
A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt
conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing
network. How events are routed and used by the peripherals is configured in software.
Figure 9-1 on page 19 shows a basic diagram of all connected peripherals. The event system can directly connect
together analog and digital converters, analog comparators, I/O port pins, the real-time counter, timer/counters, IR
communication module (IRCOM), and USB interface. It can also be used to trigger DMA transactions (DMA controller).
Events can also be generated from software and the peripheral clock.
XMEGA B1 [DATASHEET]
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Figure 9-1. Event System Overview and Connected Peripherals
CPU /
Software
DMA
Controller
Event Routing Network
ADC
AC
clkPER
Prescaler
Real Time
Counter
Event
System
Controller
Timer /
Counters
USB
Port pins
IRCOM
The event routing network consists of four software-configurable multiplexers that control how events are routed and
used. These are called event channels, and allow for up to four parallel event configurations and routings. The maximum
routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode.
XMEGA B1 [DATASHEET]
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10.
System Clock and Clock Options
10.1
Features
 Fast start-up time
 Safe run-time clock switching
 Internal oscillators:

32MHz run-time calibrated oscillator
2MHz run-time calibrated oscillator
 32.768kHz calibrated oscillator
 32kHz Ultra Low Power (ULP) oscillator with 1kHz output

 External clock options

0.4MHz - 16MHz crystal oscillator
32.768kHz crystal oscillator
 External clock

 PLL with 20MHz - 128MHz output frequency


Internal and external clock options and 1x to 31x multiplication
Lock detector
 Clock prescalers with 1x to 2048x division
 Fast peripheral clocks running at two and four times the CPU clock
 Automatic run-time calibration of internal oscillators
 External oscillator and PLL lock failure detection with optional non-maskable interrupt
10.2
Overview
Atmel AVR XMEGA devices have a flexible clock system supporting a large number of clock sources. It incorporates
both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked
loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL)
is available, and can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over
voltage and temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the
internal oscillator if the external oscillator or PLL fails.
When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device
will always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and
prescalers can be changed from software at any time.
Figure 10-1 on page 21 presents the principal clock system in the XMEGA B1 family of devices. Not all of the clocks need
to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power
reduction registers, as described in “Power Management and Sleep Modes” on page 23.
XMEGA B1 [DATASHEET]
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Figure 10-1. The Clock System, Clock Sources, and Clock Distribution
Real Time
Counter
LCD
Peripherals
RAM
Non-Volatile
Memory
AVR CPU
clkPER
clkCPU
clkPER2
clkPER4
clkRTC
clkLCD
USB
clkUSB
System Clock Prescalers
Watchdog
Timer
Prescaler
clkSYS
Brown-out
Detector
System Clock Multiplexer
(SCLKSEL)
DIV32
DIV32
DIV32
RTCSRC
USBSRC
PLL
DIV4
PLLSRC
10.3
XTAL2
0.4 – 16 MHz
XTAL
XTAL1
32.768 kHz
TOSC
TOSC2
32.768 kHz
Int. OSC
TOSC1
32 kHz
Int. ULP
32 MHz
Int. Osc
2 MHz
Int. Osc
PC[7:0]
XOSCSEL
Clock Sources
The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock
sources can be directly enabled and disabled from software, while others are automatically enabled or disabled,
depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other
clock sources, DFLLs, and PLL, are turned off by default.
The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the
internal oscillators, refer to the device datasheet.
10.3.1 32kHz Ultra Low Power Internal Oscillator
This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low
power clock source, and it is not designed for high accuracy.The oscillator employs a built-in prescaler that provides a
1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device.
This oscillator can be selected as the clock source for the RTC and for LCD.
XMEGA B1 [DATASHEET]
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10.3.2 32.768kHz Calibrated Internal Oscillator
This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency
close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the
oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz
output. This oscillator can be used as a clock source for the system clock, RTC and LCD, and as the DFLL reference
clock.
10.3.3 32.768kHz Crystal Oscillator
A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low
frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator
can be used as a clock source for the system clock, RTC and LCD, and as the DFLL reference clock.
10.3.4 0.4 - 16MHz Crystal Oscillator
This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4MHz - 16MHz.
10.3.5 2MHz Run-time Calibrated Internal Oscillator
The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated during
production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for automatic run-time
calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy.
10.3.6 32MHz Run-time Calibrated Internal Oscillator
The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to
provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for
automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator
accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz. The
production signature row contains 48MHz calibration values intended used when the oscillator is used a full-speed USB
clock source.
10.3.7 External Clock Sources
The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator.
XTAL1 or each pin of port C can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated
to driving a 32.768kHz crystal oscillator.
10.3.8 PLL with 1x-31x Multiplication Factor
The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a userselectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output
frequencies from all clock sources.
XMEGA B1 [DATASHEET]
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11.
Power Management and Sleep Modes
11.1
Features
 Power management for adjusting power consumption and functions
 Five sleep modes

Idle
Power down
 Power save
 Standby
 Extended standby

 Power reduction register to disable clock and turn off unused peripherals in active and idle modes
11.2
Overview
Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
This enables the Atmel AVR XMEGA Microcontroller to stop unused modules to save power.
All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application
code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the
device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals
and all enabled reset sources can restore the microcontroller from sleep to active mode.
In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When
this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This
reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power
management than sleep modes alone.
11.3
Sleep Modes
Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA
microcontrollers have five different sleep modes tuned to match the typical functional stages during application
execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the
device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an
enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal
program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending
when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt
service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution
starts.
The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will
reset, start up, and execute from the reset vector.
11.3.1 Idle Mode
In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but
all peripherals, including the interrupt controller, event system and DMA controller are kept running. Any enabled
interrupt will wake the device.
11.3.2 Power-down Mode
In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of
asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the twowire interface address match interrupt, asynchronous port interrupts, and the USB resume interrupt.
XMEGA B1 [DATASHEET]
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11.3.3 Power-save Mode
Power-save mode is identical to power down, with two exceptions:
1.
If the real-time counter (RTC) is enabled, it will keep running during sleep, and the device can also wake up from
either an RTC overflow or compare match interrupt.
2.
If the liquid crystal display controller (LCD) is enabled, it will keep running during sleep, and the device can wake
up from LCD frame completed interrupt.
11.3.4 Standby Mode
Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running
while the CPU, peripheral, RTC, and LCD clocks are stopped. This reduces the wake-up time.
11.3.5 Extended Standby Mode
Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are
kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.
XMEGA B1 [DATASHEET]
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12.
System Control and Reset
12.1
Features
 Reset the microcontroller and set it to initial state when a reset source goes active
 Multiple reset sources that cover different situations






Power-on reset
External reset
Watchdog reset
Brownout reset
PDI reset
Software reset
 Asynchronous operation

No running system clock in the device is required for reset
 Reset status register for reading the reset source from the application code
12.2
Overview
The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where
operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset
source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins
are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their
initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of
the accessed location can not be guaranteed.
After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts
running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to
move the reset vector to the lowest address in the boot section.
The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software
reset feature makes it possible to issue a controlled system reset from the user software.
The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows
which sources have issued a reset since the last power-on.
12.3
Reset Sequence
A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is
active. When all reset requests are released, the device will go through three stages before the device starts running
again:

Reset counter delay

Oscillator startup

Oscillator calibration
If another reset requests occurs during this process, the reset sequence will start over again.
12.4
Reset Sources
12.4.1 Power-on Reset
A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and
reaches the POR threshold voltage (VPOT), and this will start the reset sequence.
The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level.
The VPOT level is higher for falling VCCthan for rising VCC. Consult the datasheet for POR characteristics data.
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12.4.2 Brownout Detection
The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed,
programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip
erase and when the PDI is enabled.
12.4.3 External Reset
The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is
driven below the RESET pin threshold voltage, VRST, for longer than the minimum pulse period, tEXT. The reset will be
held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.
12.4.4 Watchdog Reset
The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from
the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for one
to two clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog Timer” on page 27.
12.4.5 Software Reset
The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset
control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any
instruction from when a software reset is requested until it is issued.
12.4.6 Program and Debug Interface Reset
The program and debug interface reset contains a separate reset source that is used to reset the device during external
programming and debugging. This reset source is accessible only from external debuggers and programmers.
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13.
WDT – Watchdog Timer
13.1
Features
 Issues a device reset if the timer is not reset before its timeout period
 Asynchronous operation from dedicated oscillator
 1kHz output of the 32kHz ultra low power oscillator
 11 selectable timeout periods, from 8ms to 8s
 Two operation modes:


Normal mode
Window mode
 Configuration lock to prevent unwanted changes
13.2
Overview
The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover
from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout
period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a
microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application
code.
The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT
must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued.
Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution.
The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock
source, and will continue to operate to issue a system reset even if the main clocks fail.
The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For
increased safety, a fuse for locking the WDT settings is also available.
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14.
Interrupts and Programmable Multilevel Interrupt Controller
14.1
Features
 Short and predictable interrupt response time
 Separate interrupt configuration and vector address for each interrupt
 Programmable multilevel interrupt controller

Interrupt prioritizing according to level and vector address
Three selectable interrupt levels for all interrupts: low, medium, and high
 Selectable, round-robin priority scheme within low-level interrupts
 Non-maskable interrupts for critical functions

 Interrupt vectors optionally placed in the application section or the boot loader section
14.2
Overview
Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have
one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it
will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt
controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged
by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are
prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level
interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the
interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest
interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are
serviced within a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.
14.3
Interrupt Vectors
The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in
each peripheral. The base addresses for the Atmel AVR XMEGA B1 devices are shown in Table 14-1. Offset addresses
for each interrupt available in the peripheral are described for each peripheral in the XMEGA B manual. For peripherals
or modules that have only one interrupt, the interrupt vector is shown in Table 14-1. The program address is the word
address.
Table 14-1. Reset and Interrupt Vectors
Program address
(Base address)
Source
0x000
RESET
0x002
OSCF_INT_vect
Crystal Oscillator Failure Interrupt vector (NMI)
0x004
PORTC_INT_base
Port C Interrupt base
0x008
PORTR_INT_base
Port R Interrupt base
0x00C
DMA_INT_base
DMA Controller Interrupt base
0x014
RTC_INT_base
Real Time Counter Interrupt base
0x018
TWIC_INT_base
Two-Wire Interface on Port C Interrupt base
0x01C
TCC0_INT_base
Timer/Counter 0 on port C Interrupt base
Interrupt description
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Program address
(Base address)
Source
Interrupt description
0x028
TCC1_INT_base
Timer/Counter 1 on port C Interrupt base
0x030
SPIC_INT_vect
SPI on port C Interrupt vector
0x032
USARTC0_INT_base
USART 0 on port C Interrupt base
0x03E
USB_INT_base
USB on port D Interrupt base
0x046
LCD_INT_base
LCD Interrupt base
0x048
AES_INT_vect
AES Interrupt vector
0x04A
NVM_INT_base
Non-Volatile Memory Interrupt base
0x04E
PORTB_INT_base
Port B Interrupt base
0x052
ACB_INT_base
Analog Comparator on Port B Interrupt base
0x058
ADCB_INT_base
Analog to Digital Converter on Port B Interrupt base
0x060
PORTD_INT_base
Port D Interrupt base
0x064
PORTG_INT_base
Port G Interrupt base
0x068
PORTM_INT_base
Port M Interrupt base
0x06C
PORTE_INT_base
Port E Interrupt base
0x074
TCE0_INT_base
Timer/Counter 0 on port E Interrupt base
0x08A
USARTE0_INT_base
USART 0 on port E Interrupt base
0x096
PORTA_INT_base
Port A Interrupt base
0x09A
ACA_INT_base
Analog Comparator on Port A Interrupt base
0x0A0
ADCA_INT_base
Analog to Digital Converter on Port A Interrupt base
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15.
I/O Ports
15.1
Features
 53 general purpose input and output pins with individual configuration
 Output driver with configurable driver and pull settings:

Totem-pole
Wired-AND
 Wired-OR
 Bus-keeper
 Inverted I/O

 Input with synchronous and/or asynchronous sensing with interrupts and events

Sense both edges
Sense rising edges
 Sense falling edges
 Sense low level

 Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations
 Optional slew rate control
 Asynchronous pin change sensing that can wake the device from all sleep modes
 Two port interrupts with pin masking per I/O port
 Efficient and safe access to port pins

Hardware read-modify-write through dedicated toggle/clear/set registers
Configuration of multiple pins in a single operation
 Mapping of port registers into bit-accessible I/O memory space

 Peripheral clocks output on port pin
 Real-time counter clock output to port pin
 Event channels can be output on port pin
 Remapping of digital peripheral pin functions

15.2
Selectable USART, SPI, and timer/counter input/output pin locations
Overview
One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with configurable
driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for
selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from
all sleep modes, included the modes where no clocks are running.
All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins
have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor
configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other
pin.
The port pin configuration also controls input and output selection of other device functions. It is possible to have both the
peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events
from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as
USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus
application needs.
The notation of the ports are PORTA, PORTB, PORTC, PORTD, PORTE, PORTG, PORTM, and PORTR.
15.3
Output Driver
All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to
reduce electromagnetic emission.
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15.3.1 Push-pull
Figure 15-1. I/O Configuration - Totem-pole
DIRn
OUTn
Pn
INn
15.3.2 Pull-down
Figure 15-2. I/O Configuration - Totem-pole with Pull-down (on Input)
DIRn
OUTn
Pn
INn
15.3.3 Pull-up
Figure 15-3. I/O Configuration - Totem-pole with Pull-up (on Input)
DIRn
OUTn
Pn
INn
15.3.4 Bus-keeper
The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level
was ‘1’, and pull-down if the last level was ‘0’.
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Figure 15-4. I/O Configuration - Totem-pole with Bus-keeper
DIRn
OUTn
Pn
INn
15.3.5 Others
Figure 15-5. Output Configuration - Wired-OR with Optional Pull-down
OUTn
Pn
INn
Figure 15-6. I/O Configuration - Wired-AND with Optional Pull-up
INn
Pn
OUTn
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15.4
Input Sensing
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is
shown in Figure 15-7 on page 33.
Figure 15-7. Input Sensing System Overview
Asynchronous sensing
EDGE
DETECT
Interrupt
Control
IREQ
Synchronous sensing
Pn
Synchronizer
INn
D Q D Q
INVERTED I/O
R
EDGE
DETECT
Event
R
When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.
15.5
Alternate Port Functions
Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is
enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins
are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for
that peripheral. “Pinout and Pin Functions” on page 54 shows which modules on peripherals that enable alternate
functions on a pin, and which alternate functions that are available on a pin.
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16.
T/C – 16-bit Timer/Counter Type 0 and 1
16.1
Features
 Three 16-bit timer/counters


Two timer/counters of type 0
One timer/counters of type 1
 32-bit Timer/Counter support by cascading two timer/counters
 Up to four compare or capture (CC) channels


Four CC channels for timer/counters of type 0
Two CC channels for timer/counters of type 1
 Double buffered timer period setting
 Double buffered capture or compare channels
 Waveform generation:

Frequency generation
Single-slope pulse width modulation
 Dual-slope pulse width modulation

 Input capture:

Input capture with noise cancelling
Frequency capture
 Pulse width capture
 32-bit input capture

 Timer overflow and error interrupts/events
 One compare match or input capture interrupt/event per CC channel
 Can be used with event system for:

Quadrature decoding
Count and direction control
 Capture

 Can be used with DMA and to trigger DMA transactions
 High-resolution extension

Increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit)
 Advanced waveform extension:

Low- and high-side output with programmable dead-time insertion (DTI)
 Event controlled fault protection for safe disabling of drivers
16.2
Overview
Atmel AVR XMEGA devices have a set of three flexible 16-bit Timer/Counters (TC). Their capabilities include accurate
program execution timing, frequency, and waveform generation, and input capture with time and frequency
measurement of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit
capture.
A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be
used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC
channels can be used together with the base counter to do compare match control, frequency generation, and pulse
width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either
capture or compare functions, but cannot perform both at the same time.
A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system.
The event system can also be used for direction control and capture trigger or to synchronize operations.
There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and
timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0.
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Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with four compare channels
each.
Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced
waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and highside output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can
also generate a synchronized bit pattern across the port pins.
The Advanced Waveform Extension can be enabled to provide extra and more advanced features for the Timer/Counter.
This are only available for Timer/Counter 0. See “TC2 –16-bit Timer/Counter Type 2” on page 36 for more details.
The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by
using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res – High Resolution
Extension” on page 38 for more details.
Figure 16-1. Overview of a Timer/Counter and closely Related Peripherals
Timer/Counter
Base Counter
Prescaler
clkPER
Timer Period
Control Logic
Counter
Event
System
clkPER4
Buffer
Capture
Control
Waveform
Generation
Dead-Time
Insertion
Pattern
Generation
Fault
Protection
PORT
Comparator
AWeX
Hi-Res
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
PORTC has one Timer/Counter 0 and one Timer/Counter1. PORTE has one Timer/Counter 0. Notation of these are
TCC0 (Time/Counter C0), TCC1, and TCE0, respectively.
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17.
TC2 –16-bit Timer/Counter Type 2
17.1
Features
 A system of two 8-bit timer/counters


Low-byte timer/counter
High-byte timer/counter
 Eight compare channels


Four compare channels for the low-byte timer/counter
Four compare channels for the high-byte timer/counter
 Waveform generation

Single slope pulse width modulation
 Timer underflow interrupts/events
 One compare match interrupt/event per compare channel for the low-byte timer/counter
 Can be used with the event system for count control
 Can be used to trigger DMA transactions
 High-resolution extension increases frequency and waveform resolution by 4x or 8x
17.2
Overview
A timer/counter 2 is realized when a timer/counter 0 is set in split mode. It is a system of two 8-bit timer/counters, each
with four compare channels. This results in eight configurable pulse width modulation (PWM) channels with individually
controlled duty cycles, and is intended for applications that require a high number of PWM channels.
The two 8-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter,
respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare
match interrupts, events and DMA triggers.
The two 8-bit timer/counters have a shared clock source and separate period and compare settings. They can be clocked
and timed from the peripheral clock, with optional prescaling, or from the event system. The counters are always
counting down.
The timer/counter 2 is set back to timer/counter 0 by setting it in normal mode; hence, one timer/counter can exist only as
either type 0 or type 2.
PORTC and PORTE each has one Timer/Counter 2. Notation of these are TCC2 (Time/Counter C2) and TCE2
respectively.
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18.
AWeX – Advanced Waveform Extension
18.1
Features
 Waveform output with complementary output from each compare channel
 Four dead-time insertion (DTI) units

8-bit resolution
Separate high and low side dead-time setting
 Double buffered dead time
 Optionally halts timer during dead-time insertion

 Pattern generation unit creating synchronised bit pattern across the port pins


Double buffered pattern generation
Optional distribution of one compare channel output across the port pins
 Event controlled fault protection for instant and predictable fault triggering
18.2
Overview
The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation (WG)
modes. It is primarily intended for use with different types of motor control and other power control applications. It
enables low and high side output with dead-time insertion and fault protection for disabling and shutting down external
drivers. It can also generate a synchronized bit pattern across the port pins.
Each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs when any
AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the noninverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS
switching. The DTI output will override the normal port value according to the port override setting.
The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition,
the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator
unit is enabled, the DTI unit is bypassed.
The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable
the AWeX output. The event system ensures predictable and instant fault reaction, and gives flexibility in the selection of
fault triggers.
The AWEX is available for TCC0. The notation of this is AWEXC.
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19.
Hi-Res – High Resolution Extension
19.1
Features
 Increases waveform generator resolution up to 8x (three bits)
 Supports frequency, single-slope PWM, and dual-slope PWM generation
 Supports the AWeX when this is used for the same timer/counter
19.2
Overview
The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a
timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM
generation. It can also be used with the AWeX if this is used for the same timer/counter.
The hi-res extension uses the peripheral 4x clock (ClkPER4). The system clock prescalers must be configured so the
peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension
is enabled.
Atmel AVR XMEGA B1 devices have one Hi-Res Extension that can be enabled for the timer/counters pair on PORTC.
The notation of this is HIRESC.
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20.
RTC – 16-bit Real-Time Counter
20.1
Features
 16-bit resolution
 Selectable clock source

32.768kHz external crystal
External clock
 32.768kHz internal oscillator
 32kHz internal ULP oscillator

 Programmable 10-bit clock prescaling
 One compare register
 One period register
 Clear counter on period overflow
 Optional interrupt/event on overflow and compare match
20.2
Overview
The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to
keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals.
The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the
configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs
a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal
oscillator or the 32kHz internal ULP oscillator.
The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the
counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the
maximum resolution is 30.5µs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the
maximum timeout period is more than 18 hours (65536 seconds). The RTC can give a compare interrupt and/or event
when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period
register value.
Figure 20-1. Real-time Counter Overview
External Clock
TOSC1
TOSC2
32.768kHz Crystal Osc
32.768kHz Int. Osc
DIV32
DIV32
32kHz int ULP (DIV32)
PER
RTCSRC
clkRTC
10-bit
prescaler
=
TOP/
Overflow
=
”match”/
Compare
CNT
COMP
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21.
USB – Universal Serial Bus Interface
21.1
Features
 One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface
 Integrated on-chip USB transceiver, no external components needed
 16 endpoint addresses with full endpoint flexibility for up to 31 endpoints


One input endpoint per endpoint address
One output endpoint per endpoint address
 Endpoint address transfer type selectable to:

Control transfers
Interrupt transfers
 Bulk transfers
 Isochronous transfers

 Configurable data payload size per endpoint, up to 1023 bytes
 Endpoint configuration and data buffers located in internal SRAM


Configurable location for endpoint configuration data
Configurable location for each endpoint's data buffer
 Built-in direct memory access (DMA) to internal SRAM for:


Endpoint configurations
Reading and writing endpoint data
 Ping-pong operation for higher throughput and double buffered operation


Input and output endpoint data buffers used in a single direction
CPU/DMA controller can update data buffer during transfer
 Multi-packet transfer for reduced interrupt load and software intervention


Data payload exceeding maximum packet size is transferred in one continuous transfer
No interrupts or software interaction on packet transaction level
 Transaction complete FIFO for workflow management when using multiple endpoints

Tracks all completed transactions in a first-come, first-served work queue
 Clock selection independent of system clock source and selection
 Minimum 1.5MHz CPU clock required for low speed USB operation
 Minimum 12MHz CPU clock required for full speed operation
 Connection to event system
 On chip debug possibilities during USB transactions
21.2
Overview
The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface.
The USB supports 16 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total of
31 configurable endpoints and one control endpoint. Each endpoint address is fully configurable and can be configured
for any of the four transfer types: control, interrupt, bulk, or isochronous. The data payload size is also selectable, and it
supports data payloads up to 1023 bytes.
No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to keep the configuration for
each endpoint address and the data buffer for each endpoint. The memory locations used for endpoint configurations
and data buffers are fully configurable. The amount of memory allocated is fully dynamic, according to the number of
endpoints in use and the configuration of these. The USB module has built-in direct memory access (DMA), and will
read/write data from/to the SRAM when a USB transaction takes place.
To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and
output endpoints are both used in the same direction. The CPU or DMA controller can then read/write one data buffer
while the USB module writes/reads the others, and vice versa. This gives double buffered communication.
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Multi-packet transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as
multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB
transfers.
For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle and
a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any sleep
mode.
PORTD has one USB. Notation of this is USB.
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22.
TWI – Two-wire Interface
22.1
Features
 One two-wire interface peripheral
 Bidirectional, two-wire communication interface
Phillips I2C compatible
 System Management Bus (SMBus) compatible

 Bus master and slave operation supported

Slave operation
Single bus master operation
 Bus master in multi-master bus environment
 Multi-master arbitration

 Flexible slave address match functions

7-bit and general call address recognition in hardware
10-bit addressing supported
 Address mask register for dual address match or address range masking
 Optional software address recognition for unlimited number of addresses

 Slave can operate in all sleep modes, including power-down
 Slave address match can wake device from all sleep modes
 100kHz and 400kHz bus frequency support
 Slew-rate limited output drivers
 Input filter for bus noise and spike suppression
 Support arbitration between start/repeated start and data bit (SMBus)
 Slave arbitration allows support for address resolve protocol (ARP) (SMBus)
22.2
Overview
The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus
(SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line.
A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a
slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or
several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to
transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol.
The TWI module supports master and slave functionality. The master and slave functionality are separated from each
other, and can be enabled and configured separately. The master module supports multi-master bus operation and
arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick command
and smart mode can be enabled to auto-trigger operations and reduce software complexity.
The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is
also supported. A dedicated address mask register can act as a second address match register or as a register for
address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables
the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address
matching to let this be handled in software instead.
The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision,
and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave
modes.
It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external
TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by
the TWI bus.
PORTC has one TWI. Notation of this peripheral is TWIC.
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23.
SPI – Serial Peripheral Interface
23.1
Features
 One SPI peripheral
 Full-duplex, three-wire synchronous data transfer
 Master or slave operation
 LSB first or MSB first data transfer
 Eight programmable bit rates
 Interrupt flag at the end of transmission
 Write collision flag to indicate data collision
 Wake up from idle sleep mode
 Double speed master mode
23.2
Overview
The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It
allows fast communication between an Atmel AVR XMEGA device and peripheral devices or between several
microcontrollers. The SPI supports full-duplex communication.
A device connected to the bus must act as a master or slave.The master initiates and controls all data transactions.
PORTC has one SPI. Notation of this peripheral is SPIC.
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24.
USART
24.1
Features
 Two Identical USART peripherals
 Full-duplex operation
 Asynchronous or synchronous operation


Synchronous clock rates up to 1/2 of the device clock frequency
Asynchronous clock rates up to 1/8 of the device clock frequency
 Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits
 Fractional baud rate generator


Can generate desired baud rate from any system clock frequency
No need for external oscillator with certain frequencies
 Built-in error detection and correction schemes

Odd or even parity generation and parity check
Data overrun and framing error detection
 Noise filtering includes false start bit detection and digital low-pass filter

 Separate interrupts for

Transmit complete
Transmit data register empty
 Receive complete

 Multiprocessor communication mode


Addressing scheme to address a specific devices on a multi-device bus
Enable unaddressed devices to automatically ignore all frames
 Master SPI mode

Double buffered operation
Configurable data order
 Operation up to 1/2 of the peripheral clock frequency

 IRCOM module for IrDA compliant pulse modulation/demodulation
24.2
Overview
The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial
communication module. The USART supports full-duplex communication and asynchronous and synchronous operation.
The USART can be configured to operate in SPI master mode and used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide range of standards. The
USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate
interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow
are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can
also be enabled.
The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates
from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency
to achieve a required baud rate. It also supports external clock input in synchronous slave operation.
When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive
buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes.
The registers are used in both modes, but their functionality differs for some control settings.
An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and
demodulation for baud rates up to 115.2kbps.
PORTC and PORTE each has one USART. Notation of these peripherals are USARTC0 and USARTE0 respectively.
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25.
IRCOM – IR Communication Module
25.1
Features
 Pulse modulation/demodulation for infrared communication
 IrDA compatible for baud rates up to 115.2kbps
 Selectable pulse modulation scheme

3/16 of the baud rate period
Fixed pulse period, 8-bit programmable
 Pulse modulation disabled

 Built-in filtering
 Can be connected to and used by any USART
25.2
Overview
XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to
115.2kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART.
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26.
AES and DES Crypto Engine
26.1
Features
 Data Encryption Standard (DES) CPU instruction
 Advanced Encryption Standard (AES) crypto module
 DES Instruction

Encryption and decryption
DES supported
 Encryption/decryption in 16 CPU clock cycles per 8-byte block

 AES crypto module

Encryption and decryption
Supports 128-bit keys
 Supports XOR data load mode to the state memory
 Encryption/decryption in 375 clock cycles per 16-byte block

26.2
Overview
The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used standards for
cryptography. These are supported through an AES peripheral module and a DES CPU instruction, and the
communication interfaces and the CPU can use these for fast, encrypted communication and secure data storage.
DES is supported by an instruction in the AVR CPU. The 8-byte key and 8-byte data blocks must be loaded into the
register file, and then the DES instruction must be executed 16 times to encrypt/decrypt the data block.
The AES crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data must
be loaded into the key and state memory in the module before encryption/decryption is started. It takes 375 peripheral
clock cycles before the encryption/decryption is done. The encrypted/encrypted data can then be read out, and an
optional interrupt can be generated. The AES crypto module also has DMA support with transfer triggers when
encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded.
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27.
CRC – Cyclic Redundancy Check Generator
27.1
Features
 Cyclic redundancy check (CRC) generation and checking for

Communication data
Program or data in flash memory
 Data in SRAM and I/O memory space

 Integrated with flash memory, DMA controller and CPU

Continuous CRC on data going through a DMA channel
Automatic CRC of the complete or a selectable range of the flash memory
 CPU can load data to the CRC generator through the I/O interface

 CRC polynomial software selectable to


CRC-16 (CRC-CCITT)
CRC-32 (IEEE 802.3)
 Zero remainder detection
27.2
Overview
A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data, and
it is commonly used to determine the correctness of a data transmission, and data present in the data and program
memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be
appended to the data and used as a checksum. When the same data are later received or read, the device or application
repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error.
The application will then detect this and may take a corrective action, such as requesting the data to be sent again or
simply not using the incorrect data.
Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n bits
(any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer error
bursts. The CRC module in XMEGA devices supports two commonly used CRC polynomials; CRC-16 (CRC-CCITT) and
CRC-32 (IEEE 802.3).


CRC-16:
Polynomial:
x16+x12+x5+1
Hex value:
0x1021
CRC-32:
Polynomial:
x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
Hex value:
0x04C11DB7
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28.
LCD - Liquid Crystal Display Controller
28.1
Features
 Display capacity up to 40 segment and up to four common terminals
 Supports up to 16 GPIOs
 Shadow display memory gives full freedom in segment update
 ASCII character mapping
 Swap capability option on segment and/or common terminal buses
 Supports from static up to 1/4 duty
 Supports static and 1/3 bias
 LCD driver active in power save mode for low power operation
 Software selectable low power waveform
 Flexible selection of frame frequency
 Programmable blink mode and frequency on two segment terminals
 Uses Only 32kHz RTC clock source
 On-chip LCD power supply
 Software contrast adjustment control
 Equal source and sink capability to Increase glass life time
 Extended interrupt mode for display update or wake-up from sleep mode
28.2
Overview
The LCD controller is intended for monochrome passive liquid crystal display (LCD) with up to four common terminals
and up to 40 Segments terminals. If the application does not need all the LCD segments available on the XMEGA, up to
16 of the unused LCD pins can be used as general purpose I/O pins.
The LCD controller can be clocked by an internal or an external asynchronous 32kHz clock source. This 32kHz oscillator
source selection is the same as for the real time counter (RTC).
Dedicated Low Power Waveform, Contrast Control, Extended Interrupt Mode, Selectable Frame Frequency and Blink
functionality are supported to off-load the CPU, reduce interrupts and reduce power consumption.
To reduce hardware design complexity, the LCD includes integrated LCD buffers, an integrated power supply voltage
and an innovative SWAP mode. Using SWAP mode, the hardware designers have more flexibility during board layout as
they can rearrange the pin sequence on Segment and/or Common Terminal Buses.
Figure 28-1. LCD Overview
Character
Mapping
Timing
Control & Swap
SEG[39:0]
Display
Memory
Shadow
Display
Memory
Analog
Switch
Array
COM[3:0]
LCD Power
Supply
CAPH
VLCD
BIAS1
BIAS2
CAPL
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29.
ADC – 12-bit Analog to Digital Converter
29.1
Features
 Two Analog to Digital Converters (ADCs)
 12-bit resolution
 Up to three hundred thousand samples per second


Down to 2.3µs conversion time with 8-bit resolution
Down to 3.35µs conversion time with 12-bit resolution
 Differential and single-ended input

Up to 16 single-ended inputs
16x4 differential inputs without gain
 16x4 differential input with gain

 Built-in differential gain stage

1/2x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options
 Single, continuous and scan conversion options
 Three internal inputs

Internal temperature sensor
AVCC voltage divided by 10
 1.1V bandgap voltage

 Internal and external reference options
 Compare function for accurate monitoring of user defined thresholds
 Optional event triggered conversion for accurate timing
 Optional DMA transfer of conversion results
 Optional interrupt/event on compare result
29.2
Overview
The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to
three hundred thousand samples per second (KSPS). The input selection is flexible, and both single-ended and
differential measurements can be done. For differential measurements, an optional gain stage is available to increase the
dynamic range. In addition, several internal signal inputs are available. The ADC can provide both signed and unsigned
results.
The ADC measurements can either be started by application software or an incoming event from another peripheral in
the device. The ADC measurements can be started with predictable timing, and without software intervention. It is
possible to use DMA to move ADC results directly to memory or peripherals when conversions are done.
Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the
ADC. The output from the AVCC/10 and the bandgap voltage can also be measured by the ADC.
The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention
required.
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Figure 29-1. ADC Overview
ADC0
•
•
•
ADC15
Compare
Register
ADC
Internal
signals
ADC0
•
•
•
ADC7
<
>
VINP
Threshold
(Int Req)
CH0 Result
VINN
Internal 1.00V
Internal AVCC/1.6V
Internal AVCC/2
AREFA
AREFB
Reference
Voltage
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from
3.35µs for 12-bit to 2.3µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when
the result is represented as a signed integer (signed 16-bit number).
PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB, respectively.
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30.
AC – Analog Comparator
30.1
Features
 Four Analog Comparators (AC)
 Selectable hysteresis

No
Small
 Large

 Analog comparator output available on pin
 Flexible input selection

All pins on the port
Bandgap reference voltage
 A 64-level programmable voltage scaler of the internal AVCC voltage

 Interrupt and event generation on:

Rising edge
Falling edge
 Toggle

 Window function interrupt and event generation on:

Signal above window
Signal inside window
 Signal below window

 Constant current source with configurable output pin selection
30.2
Overview
The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this
comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several
different combinations of input change.
One important property of the analog comparator’s dynamic behavior is the hysteresis. This parameter may be adjusted
in order to achieve the optimal operation for each application.
The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler. The
analog comparator output state can also be output on a pin for use by external devices.
A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example,
external resistors used to charge capacitors in capacitive touch sensing applications.
The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and
analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in
window mode to compare a signal to a voltage range instead of a voltage level.
PORTA and PORTB each has one AC pair. Notations are ACA and ACB, respectively.
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Figure 30-1. Analog Comparator Overview
Pin Input
+
AC0
-
Pin Input
AC0OUT
Hysteresis
Enable
Voltage
Scaler
ACnMUXCTRL
ACnCTRL
Interrupt
Mode
WINCTRL
Enable
Bandgap
Interrupt
Sensititivity
Control
&
Window
Function
Interrupts
Events
Hysteresis
+
AC1
-
Pin Input
AC1OUT
Pin Input
The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in
Figure 30-2.
Figure 30-2. Analog Comparator Window Function
+
AC0
Upper limit of window
Interrupt
sensitivity
control
Input signal
Interrupts
Events
+
AC1
Lower limit of window
-
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31.
Programming and Debugging
31.1
Features
 Programming

External programming through PDI or JTAG interfaces
 Minimal protocol overhead for fast operation
 Built-in error detection and handling for reliable operation
 Boot loader support for programming through any communication interface
 Debugging






Non-intrusive, real-time, on-chip debug system
No software or hardware resources required from device except pin connection
Program flow control
 Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor
Unlimited number of user program breakpoints
Unlimited number of user data breakpoints, break on:
 Data location read, write, or both read and write
 Data location content equal or not equal to a value
 Data location content is greater or smaller than a value
 Data location content is within or outside a range
No limitation on device clock frequency
 Program and Debug Interface (PDI)

Two-pin interface for external programming and debugging
Uses the Reset pin and a dedicated pin
 No I/O pins required during programming or debugging

 JTAG interface


31.2
Four-pin, IEEE Std. 1149.1 compliant interface for programming and debugging
Boundary scan capabilities according to IEEE Std. 1149.1 (JTAG)
Overview
The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip
debugging of a device.
The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user
signature row.
Debug is supported through an on-chip debug system that offers non-intrusive, real-time debug. It does not require any
software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete
program flow control and support for an unlimited number of program and complex data breakpoints. Application debug
can be done from a C or other high-level language source code level, as well as from an assembler and disassembler
level.
Programming and debugging can be done through two physical interfaces. The primary one is the PDI physical layer,
which is available on all devices. This is a two-pin interface that uses the Reset pin for the clock input (PDI_CLK) and one
other dedicated pin for data input and output (PDI_DATA). A JTAG interface is also available on most devices, and this
can be used for programming and debugging through the four-pin JTAG interface. The JTAG interface is IEEE Std.
1149.1 compliant, and supports boundary scan. Any external programmer or on-chip debugger/emulator can be directly
connected to either of these interfaces. Unless otherwise stated, all references to the PDI assume access through the
PDI physical layer.
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32.
Pinout and Pin Functions
The device pinout is shown in “Pinout/Block Diagram” on page 4. In addition to general purpose I/O functionality, each
pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin.
Only one of the pin functions can be used at time.
32.1
Alternate Pin Function Description
The tables below show the notation for all pin functions available and describe its function.
32.1.1 Operation/Power Supply
VCC
Digital supply voltage
AVCC
Analog supply voltage
GND
Ground
AGND
Analog Ground
32.1.2 Port Interrupt Functions
SYNC
Port pin with full synchronous and limited asynchronous interrupt function
ASYNC
Port pin with full synchronous and full asynchronous interrupt function
32.1.3 Analog Functions
ACn
Analog Comparator input pin n
ACnOUT
Analog Comparator n Output
ADCn
Analog to Digital Converter input pin n
AREF
Analog Reference input pin
32.1.4 LCD Functions
SEGn
LCD Segment Drive Output n
COMn
LCD Common Drive Output n
VLCD
LCD Voltage Multiplier Output
BIAS2
LCD Intermediate Voltage 2 Output (VLCD * 2/3)
BIAS1
LCD Intermediate Voltage 1 Output (VLCD * 1/3)
CAPH
LCD High End Of Flying Capacitor
CAPL
LCD Low End Of Flying Capacitor
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32.1.5 Timer/Counter and AWEX Functions
OCnxLS
Output Compare Channel x Low Side for Timer/Counter n
OCnxHS
Output Compare Channel x High Side for Timer/Counter n
32.1.6 Communication Functions
SCL
Serial Clock for TWI
SDA
Serial Data for TWI
SCLIN
Serial Clock In for TWI when external driver interface is enabled
SCLOUT
Serial Clock Out for TWI when external driver interface is enabled
SDAIN
Serial Data In for TWI when external driver interface is enabled
SDAOUT
Serial Data Out for TWI when external driver interface is enabled
XCKn
Transfer Clock for USART n
RXDn
Receiver Data for USART n
TXDn
Transmitter Data for USART n
SS
Slave Select for SPI
MOSI
Master Out Slave In for SPI
MISO
Master In Slave Out for SPI
SCK
Serial Clock for SPI
D-
Data- for USB
D+
Data+ for USB
32.1.7 Oscillators, Clock, and Event
TOSCn
Timer Oscillator pin n
XTALn
Input/Output for Oscillator pin n
CLKOUT
Peripheral Clock Output
EVOUT
Event Channel 0 Output
RTCOUT
RTC Clock Source Output
32.1.8 Debug/System Functions
RESET
Reset pin
PDI_CLK
Program and Debug Interface Clock pin
PDI_DATA
Program and Debug Interface Data pin
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32.2
TCK
JTAG Test Clock
TDI
JTAG Test Data In
TDO
JTAG Test Data Out
TMS
JTAG Test Mode Select
Alternate Pin Functions
The tables below show the primary/default function for each pin on a port in the first column, the pin number in the
second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that
enable and use the alternate pin functions.
For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the
first table where this apply.
Table 32-1. Port A - Alternate Functions
PIN #
INTERRUPT
ADCA POS/
GAINPOS
ADCB POS/
GAINPOS
ADCA
NEG
ACA
POS
ACA
NEG
PA0
82
SYNC
ADC0
ADC8
ADC0
AC0
AC0
PA1
83
SYNC
ADC1
ADC9
ADC1
AC1
AC1
PA2
84
SYNC/ASYNC
ADC2
ADC10
ADC2
AC2
PA3
85
SYNC
ADC3
ADC11
ADC3
AC3
PA4
86
SYNC
ADC4
ADC12
ADC4
AC4
PA5
87
SYNC
ADC5
ADC13
ADC5
AC5
PA6
88
SYNC
ADC6
ADC14
ADC6
AC6
PA7
89
SYNC
ADC7
ADC15
ADC7
PORT A
ADCA
GAINNEG
ACA
OUT
REFA
AREF
AC3
AC5
AC1OUT
AC7
AC0OUT
ACB
POS
ACB
NEG
ACB
OUT
Table 32-2. Port B - Alternate Functions
PORT B
PIN #
INTERRUPT
ADCA POS/
GAINPOS
ADCB POS/
GAINPOS
ADCB
NEG
ADCB
GAINNEG
AGND
90
AVCC
91
PB0
92
SYNC
ADC8
ADC0
ADC0
AC0
AC0
PB1
93
SYNC
ADC9
ADC1
ADC1
AC1
AC1
PB2
94
SYNC/ASYNC
ADC10
ADC2
ADC2
AC2
PB3
95
SYNC
ADC11
ADC3
ADC3
AC3
PB4
96
SYNC
ADC12
ADC4
ADC4
AC4
PB5
97
SYNC
ADC13
ADC5
ADC5
AC5
PB6
98
SYNC
ADC14
ADC6
ADC6
AC6
PB7
99
SYNC
ADC15
ADC7
ADC7
REFB
JTAG
AREF
AC3
TMS
AC5
AC7
TDI
AC1OUT
TCK
AC0OUT
TDO
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
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Table 32-3. Port C - Alternate Functions
PORT C
PIN #
INTERRUPT
TCC0(1)
AWEXC
TCC1
USARTC0(2)
SPIC(3)
TWIC
EXTCLK
SDA
EXTCLKC0
SCL
EXTCLKC1
CLOCKOUT
EVENTOUT
(4)
(5)
GND
100
VCC
1
PC0
2
SYNC
OC0A
OC0ALS
PC1
3
SYNC
OC0B
OC0AHS
XCK0
PC2
4
SYNC/ASYNC
OC0C
OC0BLS
RXD0
EXTCLKC2
PC3
5
SYNC
OC0D
OC0BHS
TXD0
EXTCLKC3
PC4
6
SYNC
OC0CLS
OC1A
SS
EXTCLKC4
PC5
7
SYNC
OC0CHS
OC1B
MOSI
EXTCLKC5
PC6
8
SYNC
OC0DLS
MISO
EXTCLKC6
RTCOUT
PC7
9
SYNC
OC0DHS
SCK
EXTCLKC7
clkPER
Notes:
1.
2.
3.
4.
5.
EVOUT
Pin mapping of all TC0 can optionally be moved to high nibble of port.
Pin mapping of all USART0 can optionally be moved to high nibble of port.
Pins MOSI and SCK for all SPI can optionally be swapped.
CLKOUT can optionally be moved between port C and E and between pin 4 and 7.
EVOUT can optionally be moved between port C and E and between pin 4 and 7.
Table 32-4. Port D - Alternate Functions
PORT D
PIN #
INTERRUPT
USBD
GND
10
VCC
11
PD0
12
SYNC
D-
PD1
13
SYNC
D+
PD2
14
SYNC/ASYNC
Table 32-5. Program and Debug Functions
PROG
PIN #
INTERRUPT
PROG
RESET
15
PDI_CLK
PDI
16
PDI_DATA
GND
17
VCC
18
XMEGA B1 [DATASHEET]
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Table 32-6. Port E - Alternate Functions
PIN #
INTERRUPT
TCE0(1)
PE0
19
SYNC
OC0A
PE1
20
SYNC
OC0B
XCK0
PE2
21
SYNC/ASYNC
OC0C
RXD0
PE3
22
SYNC
OC0D
TXD0
PE4
23
SYNC
PE5
24
SYNC
PE6
25
SYNC
PE7
26
SYNC
PORT E
USARTE0(2)
CLOCKOUT(4)
EVENTOUT(5)
Alternate TOSC
TOSC2
clkPER
EVOUT
TOSC1
Table 32-7. LCD
LCD(1)(2)
PIN #
INTERRUPT(1)
GPIO(1)
GND
27
VCC
28
SEG39
29
SYNC
PG0
SEG38
30
SYNC
PG1
SEG37
31
SYNC/ASYNC
PG2
SEG36
32
SYNC
PG3
SEG35
33
SYNC
PG4
SEG34
34
SYNC
PG5
SEG33
35
SYNC
PG6
SEG32
36
SYNC
PG7
SEG31
37
SYNC
PM0
SEG30
38
SYNC
PM1
SEG29
39
SYNC/ASYNC
PM2
SEG28
40
SYNC
PM3
SEG27
41
SYNC
PM4
SEG26
42
SYNC
PM5
SEG25
43
SYNC
PM6
SEG24
44
SYNC
PM7
SEG23
45
SEG22
46
SEG21
47
SEG20
48
SEG19
49
BLINK(1)
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
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LCD(1)(2)
PIN #
INTERRUPT(1)
GPIO(1)
BLINK(1)
SEG18
50
SEG17
51
SEG16
52
SEG15
53
SEG14
54
SEG13
55
SEG12
56
SEG11
57
SEG10
58
SEG9
59
SEG8
60
SEG7
61
SEG6
62
SEG5
63
SEG4
64
SEG3
65
SEG2
66
SEG1
67
BLINK
SEG0
68
BLINK
GND
69
VCC
70
BIAS1
71
BIAS2
72
VLCD
73
CAPL
74
CAPH
75
COM0
76
COM1
77
COM2
78
COM3
79
Notes:
1.
2.
Pin mapping of all Segment terminals (SEGn) can be optionally swapped. Interrupt, GPIO and Blink functions will be automatically swapped.
Pin mapping of all Common terminals (COMn) can be optionally swapped.
Table 32-8. Port R- Alternate Functions
PORT R
PIN #
INTERRUPT
XTAL
TOSC
PR0
80
SYNC
XTAL2
TOSC2
PR1
81
SYNC
XTAL1
TOSC1
XMEGA B1 [DATASHEET]
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33.
Peripheral Module Address Map
The address maps show the base address for each peripheral and module in XMEGA B1. For complete register
description and summary for each peripheral module, refer to the XMEGA B Manual.
Table 33-1. Peripheral Module Address Map
Base address
Name
Description
0x0000
GPIO
General Purpose I/O Registers
0x0010
VPORT0
Virtual Port 0
0x0014
VPORT1
Virtual Port 1
0x0018
VPORT2
Virtual Port 2
0x001C
VPORT3
Virtual Port 3
0x0030
CPU
CPU
0x0040
CLK
Clock Control
0x0048
SLEEP
Sleep Controller
0x0050
OSC
Oscillator Control
0x0060
DFLLRC32M
DFLL for the 32MHz Internal Oscillator
0x0068
DFLLRC2M
DFLL for the 2MHz Internal Oscillator
0x0070
PR
Power Reduction
0x0078
RST
Reset Controller
0x0080
WDT
Watch-Dog Timer
0x0090
MCU
MCU Control
0x00A0
PMIC
Programmable Multilevel Interrupt Controller
0x00B0
PORTCFG
Port Configuration
0x00C0
AES
AES Module
0x00D0
CRC
CRC Module
0x0100
DMA
DMA Controller
0x0180
EVSYS
0x01C0
NVM
Non Volatile Memory (NVM) Controller
0x0200
ADCA
Analog to Digital Converter on port A
0x0240
ADCB
Analog to Digital Converter on port B
0x0380
ACA
Analog Comparator pair on port A
0x0390
ACB
Analog Comparator pair on port B
0x0400
RTC
Real Time Counter
0x0480
TWIC
Two-wire Interface on port C
0x04C0
USB
USB Device
0x0600
PORTA
Port A
0x0620
PORTB
Port B
0x0640
PORTC
Port C
0x0660
PORTD
Port D
0x0680
PORTE
Port E
0x06C0
PORTG
Port G
0x0760
PORTM
Port M
0x07E0
PORTR
Port R
Event System
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
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Base address
Name
Description
0x0800
TCC0
Timer/Counter 0 on port C
0x0840
TCC1
Timer/Counter 1 on port C
0x0880
AWEXC
Advanced Waveform Extension on port C
0x0890
HIRESC
High Resolution Extension on port C
0x08A0
USARTC0
0x08C0
SPIC
0x08F8
IRCOM
0x0A00
TCE0
0x0AA0
USARTE0
0x0D00
LCD
USART 0 on port C
Serial Peripheral Interface on port C
Infrared Communication Module
Timer/Counter 0 on port E
USART 0 on port E
Liquid Crystal Display
XMEGA B1 [DATASHEET]
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61
34.
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
Arithmetic and Logic Instructions
ADD
Rd, Rr
Add without Carry
Rd

Rd + Rr
Z,C,N,V,S,H
1
ADC
Rd, Rr
Add with Carry
Rd

Rd + Rr + C
Z,C,N,V,S,H
1
ADIW
Rd, K
Add Immediate to Word
Rd

Rd + 1:Rd + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract without Carry
Rd

Rd - Rr
Z,C,N,V,S,H
1
SUBI
Rd, K
Subtract Immediate
Rd

Rd - K
Z,C,N,V,S,H
1
SBC
Rd, Rr
Subtract with Carry
Rd

Rd - Rr - C
Z,C,N,V,S,H
1
SBCI
Rd, K
Subtract Immediate with Carry
Rd

Rd - K - C
Z,C,N,V,S,H
1
SBIW
Rd, K
Subtract Immediate from Word
Rd + 1:Rd

Rd + 1:Rd - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND
Rd

Rd  Rr
Z,N,V,S
1
ANDI
Rd, K
Logical AND with Immediate
Rd

Rd  K
Z,N,V,S
1
OR
Rd, Rr
Logical OR
Rd

Rd v Rr
Z,N,V,S
1
ORI
Rd, K
Logical OR with Immediate
Rd

Rd v K
Z,N,V,S
1
EOR
Rd, Rr
Exclusive OR
Rd

Rd  Rr
Z,N,V,S
1
COM
Rd
One’s Complement
Rd

$FF - Rd
Z,C,N,V,S
1
NEG
Rd
Two’s Complement
Rd

$00 - Rd
Z,C,N,V,S,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd

Rd v K
Z,N,V,S
1
CBR
Rd,K
Clear Bit(s) in Register
Rd

Rd  ($FFh - K)
Z,N,V,S
1
INC
Rd
Increment
Rd

Rd + 1
Z,N,V,S
1
DEC
Rd
Decrement
Rd

Rd - 1
Z,N,V,S
1
TST
Rd
Test for Zero or Minus
Rd

Rd  Rd
Z,N,V,S
1
CLR
Rd
Clear Register
Rd

Rd  Rd
Z,N,V,S
1
SER
Rd
Set Register
Rd

$FF
None
1
MUL
Rd,Rr
Multiply Unsigned
R1:R0

Rd x Rr (UU)
Z,C
2
MULS
Rd,Rr
Multiply Signed
R1:R0

Rd x Rr (SS)
Z,C
2
MULSU
Rd,Rr
Multiply Signed with Unsigned
R1:R0

Rd x Rr (SU)
Z,C
2
FMUL
Rd,Rr
Fractional Multiply Unsigned
R1:R0

Rd x Rr<<1 (UU)
Z,C
2
FMULS
Rd,Rr
Fractional Multiply Signed
R1:R0

Rd x Rr<<1 (SS)
Z,C
2
FMULSU
Rd,Rr
Fractional Multiply Signed with Unsigned
R1:R0

Rd x Rr<<1 (SU)
Z,C
2
DES
K
Data Encryption
if (H = 0) then R15:R0
else if (H = 1) then R15:R0


Encrypt(R15:R0, K)
Decrypt(R15:R0, K)
PC

PC + k + 1
None
2
1/2
Branch instructions
RJMP
k
Relative Jump
IJMP
Indirect Jump to (Z)
PC(15:0)
PC(21:16)


Z,
0
None
2
EIJMP
Extended Indirect Jump to (Z)
PC(15:0)
PC(21:16)


Z,
EIND
None
2
PC

k
None
3
JMP
k
Jump
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
62
Mnemonics
Operands
Description
RCALL
k
Relative Call Subroutine
Operation
Flags
#Clocks
PC

PC + k + 1
None
2 / 3 (1)
ICALL
Indirect Call to (Z)
PC(15:0)
PC(21:16)


Z,
0
None
2 / 3 (1)
EICALL
Extended Indirect Call to (Z)
PC(15:0)
PC(21:16)


Z,
EIND
None
3 (1)
call Subroutine
PC

k
None
3 / 4 (1)
RET
Subroutine Return
PC

STACK
None
4 / 5 (1)
RETI
Interrupt Return
PC

STACK
I
4 / 5 (1)
if (Rd = Rr) PC

PC + 2 or 3
None
1/2/3
CALL
k
CPSE
Rd,Rr
Compare, Skip if Equal
CP
Rd,Rr
Compare
CPC
Rd,Rr
Compare with Carry
CPI
Rd,K
Compare with Immediate
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b) = 0) PC

PC + 2 or 3
None
1/2/3
SBRS
Rr, b
Skip if Bit in Register Set
if (Rr(b) = 1) PC

PC + 2 or 3
None
1/2/3
SBIC
A, b
Skip if Bit in I/O Register Cleared
if (I/O(A,b) = 0) PC

PC + 2 or 3
None
2/3/4
SBIS
A, b
Skip if Bit in I/O Register Set
If (I/O(A,b) =1) PC

PC + 2 or 3
None
2/3/4
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC

PC + k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC

PC + k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC

PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC

PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC

PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC

PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC

PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC

PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC

PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC

PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N  V= 0) then PC

PC + k + 1
None
1/2
BRLT
k
Branch if Less Than, Signed
if (N  V= 1) then PC

PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC

PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC

PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC

PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC

PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC

PC + k + 1
None
1/2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC

PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if (I = 1) then PC

PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if (I = 0) then PC

PC + k + 1
None
1/2

Rr
None
1
Rd - Rr
Z,C,N,V,S,H
1
Rd - Rr - C
Z,C,N,V,S,H
1
Rd - K
Z,C,N,V,S,H
1
Data transfer instructions
MOV
Rd, Rr
Copy Register
Rd
XMEGA B1 [DATASHEET]
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Mnemonics
Operands
Description
MOVW
Rd, Rr
Copy Register Pair
LDI
Rd, K
Load Immediate
Operation
Flags
#Clocks
1
Rd+1:Rd

Rr+1:Rr
None
Rd

K
None
1
(1)(2)
LDS
Rd, k
Load Direct from data space
Rd

(k)
None
2
LD
Rd, X
Load Indirect
Rd

(X)
None
1 (1)(2)
LD
Rd, X+
Load Indirect and Post-Increment
Rd
X


(X)
X+1
None
1 (1)(2)
LD
Rd, -X
Load Indirect and Pre-Decrement
X  X - 1,
Rd  (X)


X-1
(X)
None
2 (1)(2)
LD
Rd, Y
Load Indirect
Rd  (Y)

(Y)
None
1 (1)(2)
LD
Rd, Y+
Load Indirect and Post-Increment
Rd
Y


(Y)
Y+1
None
1 (1)(2)
LD
Rd, -Y
Load Indirect and Pre-Decrement
Y
Rd


Y-1
(Y)
None
2 (1)(2)
LDD
Rd, Y+q
Load Indirect with Displacement
Rd

(Y + q)
None
2 (1)(2)
LD
Rd, Z
Load Indirect
Rd

(Z)
None
1 (1)(2)
LD
Rd, Z+
Load Indirect and Post-Increment
Rd
Z


(Z),
Z+1
None
1 (1)(2)
LD
Rd, -Z
Load Indirect and Pre-Decrement
Z
Rd


Z - 1,
(Z)
None
2 (1)(2)
LDD
Rd, Z+q
Load Indirect with Displacement
Rd

(Z + q)
None
2 (1)(2)
STS
k, Rr
Store Direct to Data Space
(k)

Rd
None
2 (1)
ST
X, Rr
Store Indirect
(X)

Rr
None
1 (1)
ST
X+, Rr
Store Indirect and Post-Increment
(X)
X


Rr,
X+1
None
1 (1)
ST
-X, Rr
Store Indirect and Pre-Decrement
X
(X)


X - 1,
Rr
None
2 (1)
ST
Y, Rr
Store Indirect
(Y)

Rr
None
1 (1)
ST
Y+, Rr
Store Indirect and Post-Increment
(Y)
Y


Rr,
Y+1
None
1 (1)
ST
-Y, Rr
Store Indirect and Pre-Decrement
Y
(Y)


Y - 1,
Rr
None
2 (1)
STD
Y+q, Rr
Store Indirect with Displacement
(Y + q)

Rr
None
2 (1)
ST
Z, Rr
Store Indirect
(Z)

Rr
None
1 (1)
ST
Z+, Rr
Store Indirect and Post-Increment
(Z)
Z


Rr
Z+1
None
1 (1)
ST
-Z, Rr
Store Indirect and Pre-Decrement
Z

Z-1
None
2 (1)
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q)

Rr
None
2 (1)
Load Program Memory
R0

(Z)
None
3
LPM
LPM
Rd, Z
Load Program Memory
Rd

(Z)
None
3
LPM
Rd, Z+
Load Program Memory and Post-Increment
Rd
Z


(Z),
Z+1
None
3
Extended Load Program Memory
R0

(RAMPZ:Z)
None
3
ELPM
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
64
Mnemonics
Operands
Description
ELPM
Rd, Z
Extended Load Program Memory
Rd

ELPM
Rd, Z+
Extended Load Program Memory and PostIncrement
Rd
Z
Store Program Memory
SPM
Operation
Flags
#Clocks
(RAMPZ:Z)
None
3


(RAMPZ:Z),
Z+1
None
3
(RAMPZ:Z)

R1:R0
None
-
(RAMPZ:Z)
Z


R1:R0,
Z+2
None
-
Rd

I/O(A)
None
1
I/O(A)

Rr
None
1
STACK

Rr
None
1 (1)
SPM
Z+
Store Program Memory and Post-Increment
by 2
IN
Rd, A
In From I/O Location
OUT
A, Rr
Out To I/O Location
PUSH
Rr
Push Register on Stack
POP
Rd
Pop Register from Stack
Rd

STACK
None
2 (1)
XCH
Z, Rd
Exchange RAM location
Temp
Rd
(Z)



Rd,
(Z),
Temp
None
2
LAS
Z, Rd
Load and Set RAM location
Temp
Rd
(Z)



Rd,
(Z),
Temp v (Z)
None
2
LAC
Z, Rd
Load and Clear RAM location
Temp
Rd
(Z)



Rd,
(Z),
($FFh – Rd)  (Z)
None
2
LAT
Z, Rd
Load and Toggle RAM location
Temp
Rd
(Z)



Rd,
(Z),
Temp  (Z)
None
2
Rd(n+1)
Rd(0)
C



Rd(n),
0,
Rd(7)
Z,C,N,V,H
1
Rd(n)
Rd(7)
C



Rd(n+1),
0,
Rd(0)
Z,C,N,V
1
Rd(0)
Rd(n+1)
C



C,
Rd(n),
Rd(7)
Z,C,N,V,H
1
Bit and bit-test instructions
LSL
Rd
Logical Shift Left
LSR
Rd
Logical Shift Right
ROL
Rd
Rotate Left Through Carry
ROR
Rd
Rotate Right Through Carry
Rd(7)
Rd(n)
C



C,
Rd(n+1),
Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n)

Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)

Rd(7..4)
None
1
BSET
s
Flag Set
SREG(s)

1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s)

0
SREG(s)
1
SBI
A, b
Set Bit in I/O Register
I/O(A, b)

1
None
1
CBI
A, b
Clear Bit in I/O Register
I/O(A, b)

0
None
1
BST
Rr, b
Bit Store from Register to T
T

Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b)

T
None
1
SEC
Set Carry
C

1
C
1
CLC
Clear Carry
C

0
C
1
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
65
Mnemonics
Operands
Description
Operation
Flags
#Clocks
SEN
Set Negative Flag
N

1
N
1
CLN
Clear Negative Flag
N

0
N
1
SEZ
Set Zero Flag
Z

1
Z
1
CLZ
Clear Zero Flag
Z

0
Z
1
SEI
Global Interrupt Enable
I

1
I
1
CLI
Global Interrupt Disable
I

0
I
1
SES
Set Signed Test Flag
S

1
S
1
CLS
Clear Signed Test Flag
S

0
S
1
SEV
Set Two’s Complement Overflow
V

1
V
1
CLV
Clear Two’s Complement Overflow
V

0
V
1
SET
Set T in SREG
T

1
T
1
CLT
Clear T in SREG
T

0
T
1
SEH
Set Half Carry Flag in SREG
H

1
H
1
CLH
Clear Half Carry Flag in SREG
H

0
H
1
None
1
None
1
MCU control instructions
BREAK
Break
NOP
No Operation
SLEEP
Sleep
(see specific descr. for Sleep)
None
1
Watchdog Reset
(see specific descr. for WDR)
None
1
WDR
Notes:
1.
2.
(See specific descr. for BREAK)
Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.
One extra cycle must be added when accessing Internal SRAM.
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
66
35.
Packaging Information
35.1
100A
PIN 1
B
PIN 1 IDENTIFIER
E1
e
E
D1
D
C
0°~7°
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
15.75
16.00
16.25
D1
13.90
14.00
14.10
SYMBOL
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AED.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.08mm maximum.
E
15.75
16.00
16.25
E1
13.90
14.00
14.10
B
0.17
–
0.27
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.50 TYP
2014-02-05
100A, 100-lead, 14 x 14mm Body Size, 1.0mm Body Thickness,
0.5mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
100A
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
E
67
35.2
7A1
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
68
36.
Electrical Characteristics
All typical values are measured at T = 25°C unless other temperature condition is given. All minimum and maximum
values are valid across operating temperature and voltage unless other conditions are given.
36.1
Absolute Maximum Ratings
Stresses beyond those listed in Table 36-1 on page 69 under may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or other conditions beyond those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Table 36-1. Absolute Maximum Ratings
Symbol
36.2
Parameter
Min.
Typ.
Max.
Units
VCC
Power supply voltage
-0.3
4
V
IVCC
Current into a VCC pin
200
IGND
Current out of a GND pin
200
VPIN
Pin voltage with respect to GND and VCC
-0.5
VCC+0.5
V
IPIN
I/O pin sink/source current
-25
25
mA
TA
Storage temperature
-65
150
Tj
Junction temperature
mA
°C
150
General Operating Ratings
The device must operate within the ratings listed in Table 36-2 on page 69 in order for all other electrical characteristics
and typical characteristics of the device to be guaranteed and valid.
Table 36-2. General Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
VCC
Power supply voltage
1.60
3.6
AVCC
Analog supply voltage
1.60
3.6
TA
Temperature range
-40
85
Tj
Junction temperature
-40
105
Units
V
°C
Table 36-3. Operating Voltage and Frequency
Symbol
ClkCPU
Parameter
CPU clock frequency
Condition
Min.
Typ.
Max.
VCC = 1.6V
0
12
VCC = 1.8V
0
12
VCC = 2.7V
0
32
VCC = 3.6V
0
32
Units
MHz
The maximum System clock frequency of the Atmel AVR XMEGA B1 devices is depending on VCC. As shown in Figure
36-1 on page 70 the frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V.
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
69
Figure 36-1. Maximum Frequency vs. VCC
MHz
32
Safe Operating Area
12
1.6 1.8
2.7
3.6
V
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
70
36.3
DC Characteristics
Table 36-4. Current Consumption for Active and Sleep Modes
Symbol
Parameter
Condition
32kHz, Ext. Clk
Active Power
consumption(1)
1MHz, Ext. Clk
2MHz, Ext. Clk
32MHz, Ext. Clk
32kHz, Ext. Clk
Idle Power
consumption(1)
1MHz, Ext. Clk
2MHz, Ext. Clk
ICC
32MHz, Ext. Clk
Min.
T = 85°C
WDT and Sampled BOD enabled, T = 25°C
150
VCC = 3.0V
320
VCC = 1.8V
350
VCC = 3.0V
700
VCC = 1.8V
650
800
1.0
1.6
10
15
VCC = 3.0V
Power-save
power
consumption(2)
mA
4.0
VCC = 3.0V
8.0
VCC = 1.8V
80
VCC = 3.0V
150
VCC = 1.8V
160
250
300
600
4.7
7
0.1
1.0
2.1
5
1.2
2.5
1.3
3
3.1
7
VCC = 3.0V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
Units
µA
VCC = 1.8V
WDT and Sampled BOD enabled, T = 25°C
WDT and Sampled BOD enabled, T=85°C
Max.
VCC = 1.8V
T = 25°C
Power-down
power
consumption
Typ.
µA
RTC on ULP clock, WDT and sampled BOD
enabled, T = 25°C
VCC = 1.8V
1.2
VCC = 3.0V
1.3
RTC on 1.024kHz low power 32.768kHz
TOSC, T = 25°C
VCC = 1.8V
0.8
VCC = 3.0V
0.9
RTC from low power 32.768kHz TOSC,
T = 25°C
VCC = 1.8V
1.3
VCC = 3.0V
1.6
mA
µA
µA
XMEGA B1 [DATASHEET]
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71
Symbol
Parameter
Power-save
power
consumption(2)
ICC
Reset power
consumption
Notes:
1.
2.
Condition
Min.
Typ.
RTC on ULP clock, WDT, sampled BOD and
LCD enabled, and all pixels ON, T = 25°C
VCC = 1.8V
4.6
VCC = 3.0V
5.2
RTC on 1.024kHz low power 32.768kHz
TOSC, LCD enabled and all pixels ON
T = 25°C
VCC = 1.8V
3.9
VCC = 3.0V
4.3
RTC from low power 32.768kHz TOSC, LCD
enabled and all pixels ON, T = 25°C
VCC = 1.8V
4.0
VCC = 3.0V
4.5
Current through RESET pin substracted
VCC = 3.0V
420
Max.
Units
µA
All Power Reduction Registers set.
Maximum limits are based on characterization and not tested in production.
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
72
Table 36-5. Current Consumption for Modules and Peripherals
Symbol
Parameter
Condition(1)
Min.
Typ.
ULP oscillator
1.0
32.768kHz int.
oscillator
26
2MHz int.
oscillator
Max.
Units
80
DFLL enabled with 32.768kHz int. osc. as reference
112
255
32MHz int.
oscillator
DFLL enabled with 32.768kHz int. osc. as reference
444
PLL
Multiplication factor = 20x
316
Watchdog Timer
1
Continuous mode
126
Sampled mode, include ULP oscillator
1.3
BOD
Contrast min
No pixel load
ICC
Contrast typ
LCD(2)
Contrast max
22pF pixel load
All pixels OFF
3.0
100 pixels ON
3.0
All pixels ON
3.0
All pixels OFF
3.3
100 pixels ON
3.4
All pixels ON
3.4
All pixels OFF
3.8
100 pixels ON
3.9
All pixels ON
3.9
All pixels OFF
3.7
All pixels ON
4.3
µA
Contrast typ
Internal 1.0V
reference
100
Temperature
sensor
100
1.3
16ksps
VREF = Ext ref
ADC
CURRLIMIT = LOW
1.1
CURRLIMIT = MEDIUM
1.0
CURRLIMIT = HIGH
0.9
75ksps
VREF = Ext ref
1.7
300ksps
VREF = Ext ref
3.1
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
mA
73
Symbol
Parameter
Condition(1)
Min.
AC
ICC
1.
2.
36.4
Max.
Units
440
DMA
615Kbps between I/O registers and SRAM
USART
Rx and Tx enabled, 9600 BAUD
115
µA
9
Flash memory and EEPROM programming
Notes:
Typ.
4.4
mA
All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz External clock
without prescaling, T = 25°C unless other conditions are given.
LCD configuration: internal voltage generation, 32Hz low power frame rate, 1/3 bias, clocked by low power 32.768kHz TOSC.
Wake-up Time from Sleep Modes
Table 36-6. Device Wake-up Time from Sleep Modes with Various System Clock Sources
Symbol
Parameter
Condition
External 2MHz clock
Wake-up time from Idle,
Standby, and Extend Standby
twakeup
Typ.
Max.
Units
2
120
2MHz internal oscillator
2
32MHz internal oscillator
0.2
External 2MHz clock
4.5
32.768kHz internal oscillator
320
µs
Wake-up time from Power-save
and Power-down mode
Note:
32.768kHz internal oscillator
Min.
1.
2MHz internal oscillator
9
32MHz internal oscillator
5
The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 36-2 on page 74. All peripherals and
modules start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 36-2. Wake-up Time Definition
Wake-up time
Wake-up request
Clock output
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
74
36.5
I/O Pin Characteristics
The I/O pins complies with the JEDEC LVTTL and LVCSMOS specification and the high- and low-level input and output
voltage limits reflect or exceed this specification.
Table 36-7. I/O Pin Characteristics
Symbol
(1)
IOH/
IOL
Parameter
Condition
Min.
Max.
Units
-20
20
mA
VCC = 3.0 - 3.6V
0.6*VCC
VCC+0.3
VCC = 2.3 - 2.7V
0.6*VCC
VCC+0.3
VCC = 1.6 - 2.3V
0.6*VCC
VCC+0.3
VCC = 3.0 - 3.6V
-0.3
0.4*VCC
VCC = 2.3 - 2.7V
-0.3
0.4*VCC
VCC = 1.6 - 2.3V
-0.3
0.4*VCC
I/O pin source/sink current
(2)
VIH
High level input voltage
VIL
Low level input voltage
VOL
Output low voltage GPIO
VOH
Output high voltage GPIO
Typ.
VCC = 3.3V
IOL = 15mA
0.4
0.76
VCC = 3.0V
IOL = 10mA
0.26
0.64
VCC = 1.8V
IOL = 5mA
0.17
0.46
VCC = 3.3V
IOH = -8mA
2.6
2.8
VCC = 3.0V
IOH = -6mA
2.1
2.6
VCC = 1.8V
IOH = -2mA
1.4
1.6
IIN
Input leakage current I/O pin
RP
Pull/Buss keeper resistor
25
RRST
Reset pin pull-up resistor
25
1
µA
k
4
(3)
tr
Notes:
<0.01
V
Rise time
No load
ns
slew rate limitation
1.
2.
3.
7
The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC, PORTD, PORTE, and PDI must for each port not exceed 200mA.
The sum of all IOH for PORTG and PORTM must not exceed 100mA.
The sum of all IOH for PORTR must not exceed 100mA.
The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC, PORTD, and PORTE must for each port not exceed 200mA.
The sum of all IOL for PORTG and PORTM must not exceed 100mA.
The sum of all IOL PORTR must not exceed 100mA.
From design simulations.
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
75
36.6
Liquid Crystal Display Characteristics
Table 36-8.
Symbol
Liquid Crystal Display Characteristics
Parameter
Condition
Min.
Typ.
Max.
SEG
Segment terminal pins
0
40
COM
Common terminal pins
0
4
fFrame
LCD frame frequency
31.25
512
CFlying
Flying capacitor
Contrast
100
Contrast adjustment
VLCD
BIAS2
F(clkLCD)=32.768kHz
LCD regulated voltages
BIAS1
-0.5
COM0 to COM3
RSEG
Segment output impedance
SEG0 to SEG39(1)
Notes:
1.
36.7
ADC Characteristics
nF
0.5
2*VLCD/3
V
V
VLCD/3
(1)
Common output impedance
Hz
3
CFlying = 0.1µF
0.1µF on VLCD, BIAS2 and
BIAS1 pins
RCOM
0
Units
0.25
0.5
1
2
4
8
Typ.
Max.
k
Applies to Static and 1/3 bias.
Table 36-9. Power Supply, Reference, and Input Range
Symbol
Parameter
AVCC
Analog supply voltage
VREF
Reference voltage
Condition
Min.
VCC- 0.3
VCC+ 0.3
1
AVCC- 0.6
Units
V
Rin
Input resistance
Switched
4.5
k
Cin
Input capacitance
Switched
5
pF
RAREF
Reference input resistance
(leakage only)
CAREF
Reference input capacitance
Static load
Vin
Input range
Vin
Conversion range
Vin
Conversion range
>10
M
7
pF
0
VREF
Differential mode, Vinp - Vinn
0.95*VREF
0.95*VREF
Single ended unsigned mode, Vinp
0.05*VREF
0.95*VREF
V
Table 36-10. Clock and Timing
Symbol
ClkADC
Parameter
ADC clock frequency
Condition
Min.
Maximum is 1/4 of peripheral clock
frequency
100
Sample rate
Max.
Units
1800
kHz
Measuring internal signals
fClkADC
Typ.
125
16
300
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
ksps
76
Symbol
Parameter
Condition
Min.
Current limitation (CURRLIMIT) off
fADC
Typ.
16
Max.
Units
300
CURRLIMIT = LOW
250
CURRLIMIT = MEDIUM
150
CURRLIMIT = HIGH
50
Sample rate
ksps
Sampling time
1/2 ClkADC cycle
0.25
5
Conversion time (latency)
(RES+2)/2+(GAIN !=0)
RES (Resolution) = 8 or 12
6
10
Start-up time
ADC clock cycles
12
24
ADC settling time
After changing reference or input
mode
7
7
Min.
Typ.
Max.
Differential
8
12
12
Single ended signed
7
11
11
Single ended unsigned
8
12
12
µs
ClkADC
cycles
Table 36-11. Accuracy Characteristics
Symbol
RES
Condition(2)
Parameter
Resolution
12-bit resolution
Differential
mode
INL(1)
Integral non-linearity
Single ended
unsigned mode
Differential
mode
DNL(1)
Differential non-linearity
Single ended
unsigned mode
Offset error
Differential
mode
16kSPS, VREF = 3V
1
16kSPS, VREF = 1V
2
300kSPS, VREF = 3V
1
300kSPS, VREF = 1V
2
16kSPS, VREF = 3.0V
1
1.5
16kSPS, VREF = 1.0V
2
3
16kSPS, VREF = 3V
1
16kSPS, VREF = 1V
2
300kSPS, VREF = 3V
1
300kSPS, VREF = 1V
2
16kSPS, VREF = 3.0V
1
1.5
16kSPS, VREF = 1.0V
2
3
Bits
LSB
LSB
Temperature drift
Operating voltage drift
Units
8
mV
0.01
mV/K
0.25
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
mV/V
77
Symbol
Condition(2)
Parameter
Gain error
Min.
1.
2.
Units
-5
AVCC/1.6
-5
AVCC/2.0
-6
Bandgap
±10
Temperature drift
0.02
mV/K
2
mV/V
Differential
mode
mV
External reference
-8
AVCC/1.6
-8
AVCC/2.0
-8
Bandgap
±10
Temperature drift
0.03
mV/K
2
mV/V
Single ended
unsigned mode
mV
Operating voltage drift
Notes:
Max.
External reference
Operating voltage drift
Gain error
Typ.
Maximum numbers are based on characterisation and not tested in production, and valid for 10% to 90% input voltage range.
Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
Table 36-12. Gain Stage Characteristics
Symbol
Parameter
Condition
Min.
Typ.
Rin
Input resistance
Switched in normal mode
4.0
k
Csample
Input capacitance
Switched in normal mode
4.4
pF
Signal range
Gain stage output
Propagation delay
ADC conversion rate
Clock rate
Same as ADC
0
Max.
AVCC- 0.3
1800
0.5x gain, normal mode
-1
1x gain, normal mode
-1
8x gain, normal mode
-1
64x gain, normal mode
10
0.5x gain, normal mode
10
Offset error,
1x gain, normal mode
10
input referred
8x gain, normal mode
-20
64x gain, normal mode
-150
V
ClkADC
cycles
1
100
Units
Gain error
kHz
%
mV
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
78
36.8
Analog Comparator Characteristics
Table 36-13. Analog Comparator Characteristics
Symbol
Voff
Ilk
Parameter
Condition
Min.
Typ.
Input offset voltage
10
Input leakage current
<10
Input voltage range
0.1
AC startup time
Max.
Units
mV
50
nA
AVCC- 0.1
V
50
µs
Vhys1
Hysteresis, none
VCC = 1.6V - 3.6V
0
Vhys2
Hysteresis, small
VCC = 1.6V - 3.6V
12
Vhys3
Hysteresis, large
VCC = 1.6V - 3.6V
28
30
Propagation delay
VCC = 3.0V, T= 85°C
22
tdelay
VCC = 1.6V - 3.6V
21
40
0.3
0.5
mV
ns
64-Level Voltage Scaler Integral nonlinearity (INL)
Current source accuracy after calibration
5
LSB
%
Current source calibration range
Single mode
4
6
Current source calibration range
Double mode
8
12
µA
36.9
Bandgap and Internal 1.0V Reference Characteristics
Table 36-14. Bandgap and Internal 1.0V Reference Characteristics
Symbol
Parameter
Condition
Min.
As reference for ADC
Typ.
Max.
1 ClkPER + 2.5µs
Startup time
As input voltage to ADC and AC
Units
µs
1.5
Bandgap voltage
1.1
V
INT1V
Internal 1.00V reference for ADC
T= 85°C, after calibration
Variation over voltage and temperature
Calibrated at T= 85°C
0.99
1
1.01
2.25
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
%
79
36.10 Brownout Detection Characteristics
Table 36-15. Brownout Detection Characteristics(1)
Symbol
Parameter
Condition
BOD level 0 falling VCC
T = 85C, calibrated
Min.
Typ.
Max.
1.5
1.6
1.72
BOD level 1 falling VCC
1.8
BOD level 2 falling VCC
2.0
BOD level 3 falling VCC
2.2
BOD level 4 falling VCC
2.4
BOD level 5 falling VCC
2.6
BOD level 6 falling VCC
2.8
BOD level 7 falling VCC
3.0
V
Continuous mode
tBOD
Note:
0.4
Detection time
µs
Sampled mode
VHYST
1000
Hysteresis
1.
Units
1.6
%
BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level.
36.11 External Reset Characteristics
Table 36-16. External Reset Characteristics
Symbol
Parameter
tEXT
Minimum reset pulse width
VRST
Reset threshold voltage
Condition
Min.
Typ.
Max.
Units
90
1000
ns
VCC = 2.7 - 3.6V
0.50*VCC
VCC = 1.6 - 2.7V
0.40*VCC
V
36.12 Power-on Reset Characteristics
Table 36-17. Power-on Reset Characteristics
Symbol
Parameter
VPOT-(1)
POR threshold voltage falling VCC
VPOT+
POR threshold voltage rising VCC
Note:
1.
Condition
Min.
Typ.
VCC falls faster than 1V/ms
0.4
1.0
VCC falls at 1V/ms or slower
0.8
1.3
Max.
Units
V
1.3
1.59
V
Both VPOT- values are only valid when BOD is disabled. When BOD is enabled the µBOD is enabled, and VPOT- =VPOT+.
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
80
36.13 Flash and EEPROM Memory Characteristics
Table 36-18. Endurance and Data Retention
Symbol
Parameter
Condition
Min.
25°C
10K
85°C
10K
25°C
100
55°C
25
25°C
100K
85°C
100K
25°C
100
55°C
25
Typ.
Max.
Write/erase cycles
Units
Cycle
Flash
Data retention
Year
Write/erase cycles
Cycle
EEPROM
Data retention
Year
Table 36-19. Programming Time
Symbol
Parameter
Chip Erase
Flash
EEPROM
Notes:
1.
2.
Condition
Min.
Typ.(1)
128KB flash, EEPROM(2)
75
64KB flash, EEPROM(2)
55
Page Erase
4
Page Write
4
Page Write Automatic Page Erase and Write
8
Page Erase
4
Page Write
4
Page Write Automatic Page Erase and Write
8
Max.
Units
ms
ms
ms
Programming is timed from the 2MHz internal oscillator.
EEPROM is not erased if the EESAVE fuse is programmed.
36.14 Clock and Oscillator Characteristics
36.14.1 Calibrated 32.768kHz Internal Oscillator Characteristics
Table 36-20. Calibrated 32.768kHz Internal Oscillator Characteristics
Symbol
Parameter
Condition
Min.
Frequency
Factory calibrated accuracy
User calibration accuracy
Typ.
Max.
32.768
T = 85C, VCC = 3.0V
Units
kHz
-0.5
0.5
%
-0.5
0.5
%
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
81
36.14.2 Calibrated 2MHz RC Internal Oscillator Characteristics
Table 36-21. Calibrated 2MHz Internal Oscillator Characteristics
Symbol
Parameter
Frequency range
Condition
Min.
DFLL can tune to this frequency over
voltage and temperature
1.8
Factory calibrated frequency
Factory calibration accuracy
Typ.
Max.
Units
2.2
MHz
2.0
T = 85C, VCC= 3.0V
User calibration accuracy
MHz
-1.5
1.5
%
-0.2
0.2
%
DFLL calibration step size
0.22
%
36.14.3 Calibrated and tunable 32MHz Internal Oscillator Characteristics
Table 36-22. Calibrated 32MHz Internal Oscillator Characteristics
Symbol
Parameter
Frequency range
Condition
Min.
DFLL can tune to this frequency over
voltage and temperature
30
Factory calibrated frequency
Factory calibration accuracy
Typ.
Max.
Units
35
MHz
32
T = 85C, VCC= 3.0V
User calibration accuracy
MHz
-1.5
1.5
%
-0.2
0.2
%
DFLL calibration step size
0.23
%
36.14.4 32kHz Internal ULP Oscillator Characteristics
Table 36-23. 32kHz Internal ULP Oscillator Characteristics
Symbol
Parameter
Condition
Min.
Factory calibrated frequency
Factory calibration accuracy
Typ.
Max.
32
T = 85C, VCC= 3.0V
-12
Units
kHz
12
%
Max.
Units
MHz
36.14.5 Phase Locked Loop (PLL) Characteristics
Table 36-24. Internal PLL Characteristics
Symbol
fIN
Input Frequency
Output frequency(1)
fOUT
Note:
Parameter
1.
Condition
Min.
Typ.
Output frequency must be within fOUT
0.4
64
VCC= 1.6 - 1.8V
20
48
VCC= 2.7 - 3.6V
20
128
MHz
Start-up time
23
100
µs
re-lock time
20
50
µs
The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
82
36.14.6 External Clock Characteristics
Figure 36-3. External Clock Drive Waveform
tCH
tCH
tCF
tCR
VIH1
VIL1
tCL
tCK
Table 36-25. External Clock used as System Clock without Prescaling
Symbol
Clock frequency(1)
1/tCK
tCK
Clock period
tCH
Clock high time
tCL
Clock low time
tCR
Rise time (for maximum frequency)
tCF
Fall time (for maximum frequency)
tCK
Note:
Parameter
Change in period from one clock cycle to the next
1.
Condition
Min.
Typ.
Max.
VCC = 1.6 - 1.8V
0
12
VCC = 2.7 - 3.6V
0
32
VCC = 1.6 - 1.8V
83.3
VCC = 2.7 - 3.6V
31.5
VCC = 1.6 - 1.8V
30.0
VCC = 2.7 - 3.6V
12.5
VCC = 1.6 - 1.8V
30.0
VCC = 2.7 - 3.6V
12.5
Units
MHz
ns
VCC = 1.6 - 1.8V
10
VCC = 2.7 - 3.6V
3
VCC = 1.6 - 1.8V
10
VCC = 2.7 - 3.6V
3
10
%
The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
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Table 36-26. External Clock with Prescaler(1) for System Clock
Symbol
Parameter
Condition
Clock frequency(2)
1/tCK
tCK
Clock period
tCH
Clock high time
tCL
Clock low time
tCR
Rise time (for maximum frequency)
tCF
Fall time (for maximum frequency)
tCK
Notes:
Min.
Typ.
VCC = 1.6 - 1.8V
0
90
VCC = 2.7 - 3.6V
0
142
VCC = 1.6 - 1.8V
11
VCC = 2.7 - 3.6V
7
VCC = 1.6 - 1.8V
4.5
VCC = 2.7 - 3.6V
2.4
VCC = 1.6 - 1.8V
4.5
VCC = 2.7 - 3.6V
2.4
Units
MHz
ns
VCC = 1.6 - 1.8V
1.5
VCC = 2.7 - 3.6V
1.0
VCC = 1.6 - 1.8V
1.5
VCC = 2.7 - 3.6V
1.0
Change in period from one clock cycle to the next
1.
2.
Max.
10
%
System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
36.14.7 External 16MHz Crystal Oscillator and XOSC Characteristics
Table 36-27. External 16MHz Crystal Oscillator and XOSC Characteristics
Symbol
Parameter
Cycle to cycle jitter
Condition
Min.
Typ.
XOSCPWR=0, FRQRANGE=0
0
XOSCPWR=0, FRQRANGE=1, 2, or 3
0
XOSCPWR=1
0
XOSCPWR=0, FRQRANGE=0
0
XOSCPWR=0, FRQRANGE=1, 2, or 3
0
XOSCPWR=1
0
Max.
Units
ns
Long term jitter
XOSCPWR=0, FRQRANGE=0
0.03
XOSCPWR=0, FRQRANGE=1
0.03
XOSCPWR=0, FRQRANGE=2 or 3
0.03
XOSCPWR=1
0.03
Frequency error
%
XOSCPWR=0, FRQRANGE=0
50
XOSCPWR=0, FRQRANGE=1
50
XOSCPWR=0, FRQRANGE=2 or 3
50
XOSCPWR=1
50
Duty cycle
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
84
Symbol
Parameter
Condition
44k
1MHz crystal, CL=20pF
67k
2MHz crystal, CL=20pF
67k
2MHz crystal
82k
8MHz crystal
1500
9MHz crystal
1500
8MHz crystal
2700
9MHz crystal
2700
12MHz crystal
1000
9MHz crystal
3600
12MHz crystal
1300
16MHz crystal
590
9MHz crystal
390
12MHz crystal
50
16MHz crystal
10
9MHz crystal
1500
12MHz crystal
650
16MHz crystal
270
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
12MHz crystal
1000
16MHz crystal
440
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
12MHz crystal
1300
16MHz crystal
590
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator, CL=100pF
1.0
XOSCPWR=0,
FRQRANGE=1
2MHz crystal, CL=20pF
2.6
XOSCPWR=0,
FRQRANGE=2
8MHz crystal, CL=20pF
0.8
XOSCPWR=0,
FRQRANGE=3
12MHz crystal, CL=20pF
1.0
XOSCPWR=1,
FRQRANGE=3
16MHz crystal, CL=20pF
1.4
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
Negative impedance (1)
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
Start-up time
ESR
Typ.
0.4MHz resonator, CL=100pF
XOSCPWR=0,
FRQRANGE=0
RQ
Min.
SF = Safety factor
Max.
Units

ms
min(RQ)/
SF
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
k
85
Symbol
Parameter
Condition
Min.
Typ.
CXTAL1
Parasitic capacitance
5.9
CXTAL2
Parasitic capacitance
8.3
Parasitic capacitance load
3.5
CLOAD
Note:
1.
Max.
Units
pF
Numbers for negative impedance are not tested but guaranteed from design and characterization.
36.14.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics
Table 36-28. External 32.768kHz Crystal Oscillator and TOSC Characteristics
Symbol
Parameter
ESR/R1
Recommended crystal equivalent
series resistance (ESR)
CIN_TOSC
Condition
Min.
Crystal load capacitance 6.5pF
60
Crystal load capacitance 9.0pF
35
Crystal load capacitance 12.0pF
28
Normal mode
3.5
Low power mode
3.5
Units
k
pF
capacitance load matched to
crystal specification
3
Long term Jitter (SIT)
1.
Max.
Input capacitance between TOSC pins
Recommended safety factor
Note:
Typ.
0
%
See Figure 36-4 for definition.
Figure 36-4. TOSC Input Capacitance
CL1
TOSC1
CL2
Device internal
External
TOSC2
32.768 kHz crystal
The input capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without
external capacitors.
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
86
36.15 SPI Characteristics
Figure 36-5. SPI Timing Requirements in Master Mode
SS
tSCKR
tMOS
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
MISO
(Data Input)
tMIH
tSCK
MSB
LSB
tMOH
tMOH
MOSI
(Data Output)
MSB
LSB
Figure 36-6. SPI Timing Requirements in Slave Mode
SS
tSSS
tSCKR
tSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
MOSI
(Data Input)
tSIH
MSB
tSOSSS
MISO
(Data Output)
tSSCK
LSB
tSOS
MSB
tSOSSH
LSB
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
87
Table 36-29. SPI Timing Characteristics and Requirements
Symbol
Parameter
Condition
Min.
Typ.
Max.
tSCK
SCK period
Master
(See Table 21-4 in
XMEGA B Manual)
tSCKW
SCK high/low width
Master
0.5*SCK
tSCKR
SCK rise time
Master
2.7
tSCKF
SCK fall time
Master
2.7
tMIS
MISO setup to SCK
Master
11
tMIH
MISO hold after SCK
Master
0
tMOS
MOSI setup SCK
Master
0.5*SCK
tMOH
MOSI hold after SCK
Master
1
tSSCK
Slave SCK period
Slave
4*t ClkPER
tSSCKW
SCK high/low width
Slave
2*t ClkPER
tSSCKR
SCK rise time
Slave
1600
tSSCKF
SCK fall time
Slave
1600
tSIS
MOSI setup to SCK
Slave
3
tSIH
MOSI hold after SCK
Slave
t ClkPER
tSSS
SS setup to SCK
Slave
21
tSSH
SS hold after SCK
Slave
20
tSOS
MISO setup SCK
Slave
8
tSOH
MISO hold after SCK
Slave
13
tSOSS
MISO setup after SS low
Slave
11
tSOSH
MISO hold after SS high
Slave
8
Units
ns
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
88
36.16 Two-wire Interface Characteristics
Table 36-30 describes the requirements for devices connected to the Two-wire Serial Bus. The Atmel AVR XMEGA Twowire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 36-7.
Figure 36-7. Two-wire Interface Bus Timing
tof
tHIGH
tLOW
tr
SCL
tSU;STA
tHD;DAT
tSU;STO
tSU;DAT
tHD;STA
SDA
tBUF
Table 36-30. Two-wire Serial Bus Characteristics
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VIH
Input high voltage
0.7*VCC
VCC+0.5
VIL
Input low voltage
-0.5
0.3*VCC
Vhys
Hysteresis of Schmitt trigger inputs
0.05VCC(1)
0
VOL
Output low voltage
0
0.4
20+0.1Cb(1)(2)
300
20+0.1Cb(1)(2)
250
0
50
-10
10
µA
10
pF
400
kHz
300ns
--------------Cb

tr
Rise time for both SDA and SCL
tof
Output fall time from VIHmin to VILmax
tSP
Spikes suppressed by input filter
II
Input current for each I/O pin
CI
Capacitance for each I/O pin
fSCL
SCL clock frequency
RP
Value of pull-up resistor
tHD;STA
3mA, sink current
10pF < Cb < 400pF(2)
0.1VCC < VI < 0.9VCC
fPER(3)>max(10fSCL, 250kHz)
fSCL  100kHz
fSCL > 100kHz
Hold time (repeated) START condition
tLOW
Low period of SCL clock
tHIGH
High period of SCL clock
tSU;STA
Set-up time for a repeated START condition
tHD;DAT
Data hold time
0
V CC – 0.4V
---------------------------3mA
100ns
--------------Cb
fSCL  100kHz
4.0
fSCL > 100kHz
0.6
fSCL  100kHz
4.7
fSCL > 100kHz
1.3
fSCL  100kHz
4.0
fSCL > 100kHz
0.6
fSCL  100kHz
4.7
fSCL > 100kHz
0.6
fSCL  100kHz
0
3.5
fSCL > 100kHz
0
0.9
V
ns
µs
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
89
Symbol
Parameter
tSU;DAT
Data setup time
tSU;STO
Setup time for STOP condition
Bus free time between a STOP and START
condition
tBUF
Notes:
1.
2.
3.
Condition
Min.
fSCL  100kHz
250
fSCL > 100kHz
100
fSCL  100kHz
4.0
fSCL > 100kHz
0.6
fSCL  100kHz
4.7
fSCL > 100kHz
1.3
Typ.
Max.
Units
ns
µs
Required only for fSCL > 100kHz.
Cb = Capacitance of one bus line in pF.
fPER = Peripheral clock frequency.
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
90
37.
Typical Characteristics
37.1
Current Consumption
37.1.1 Active Mode Supply Current
Figure 37-1. Active Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C.
1000
3.6V
900
800
3.0V
ICC [μA]
700
2.7V
600
500
2.2V
400
1.8V
1.6V
300
200
100
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Frequency [MHz]
Figure 37-2. Active Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C.
14
3.6V
12
Icc[mA]
10
3.0V
2.7V
8
6
2.2V
4
1.8V
2
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
91
Figure 37-3. Active Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator.
Data
6000sheet plot checklist
5500 apply the following checklist to all data sheet plots:
Please
ICC [µA]
5000
[ ] Is the most recent revision of PlotTool.xlt and the PlotTool database being used?
[4500
] Is the plotted data reasonable?
[4000
] Has data outside of device specification been removed from the data set?
Temp [°C]
[ ] Has data outside of the plot region been removed from the data set?
3500
105
[ ] Has "Analysis mode" been unchecked?
85
[3000
] Has the Y axis been adjusted to best fit the data? Is the unit correct?
25
[2500
] Has the X axis been adjusted according to data sheet requirement?
- 40
[ ] Has the Z axis legend been positioned correctly (correct order, no overlap)
2000
[ ] Are there at least eight grid lines for both X and Y axis?
1500
1.6
1.8
2
2.2
2.4
2.6
VCC [V]
2.8
3
3.2
3.4
3.6
Figure 37-4. Active Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator.
2120
-40°C
25°C
85°C
105°C
1940
1760
Icc [µA]
1580
1400
1220
1040
860
680
500
1.6
1.8
2.0
2.2
2.4
2.6
VCC [V]
2.8
3.0
3.2
3.4
3.6
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
92
Figure 37-5. Active Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz.
Data
53 sheet plot checklist
Please
apply the following checklist to all data sheet plots:
50
ICC [µA]
[47]
[ ]
[44]
[ ]
[41]
[ ]
[38]
[ ]
[35]
Is the most recent revision of PlotTool.xlt and the PlotTool database being used?
Is the plotted data reasonable?
Has data outside of device specification been removed from the data set?
Temp [°C]
Has data outside of the plot region been removed from the data set?
105
Has "Analysis mode" been unchecked?
85
Has the Y axis been adjusted to best fit the data? Is the unit correct?
25
Has the X axis been adjusted according to data sheet requirement?
-40
Has the Z axis legend been positioned correctly (correct order, no overlap)
Are there at least eight grid lines for both X and Y axis?
32
1.6
1.8
2
2.2
2.4
2.6
VCC [V]
2.8
3
3.2
3.4
3.6
Figure 37-6. Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator.
14000
-40°C
13000
25°C
85°C
105°C
Icc [µA]
12000
11000
10000
9000
8000
2.7
2.8
2.9
3.0
3.1
3.2
VCC [V]
3.3
3.4
3.5
3.6
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
93
37.1.2 Idle Mode Supply Current
Figure 37-7. Idle Mode Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C.
180
3.6V
160
Icc[μA]
140
3.0V
120
2.7V
100
2.2V
80
1.8V
1.6V
60
40
20
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Frequency [MHz]
Figure 37-8. Idle Mode Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C.
6
3.6V
5
3.0V
Icc[mA]
4
2.7V
3
2
2.2V
1
1.8V
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
94
Figure 37-9. Idle Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator.
38.8
105°C
37.6
36.4
Icc [µA]
35.2
-40°C
85°C
34.0
32.8
25°C
31.6
30.4
29.2
28.0
1.6
1.8
2.0
2.2
2.4
2.6
VCC [V]
2.8
3.0
3.2
3.4
3.6
Figure 37-10.Idle Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator.
455
-40°C
25°C
85°C
427
399
105°C
Icc [µA]
371
343
315
287
259
231
203
175
1.6
1.8
2.0
2.2
2.4
2.6
VCC [V]
2.8
3.0
3.2
3.4
3.6
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
95
Figure 37-11.Idle Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz.
Data
2100sheet plot checklist
Please
1900 apply the following checklist to all data sheet plots:
ICC [µA]
[1700
] Is the most recent revision of PlotTool.xlt and the PlotTool database being used?
[ ] Is the plotted data reasonable?
[1500
] Has data outside of device specification been removed from the data set?
Temp [°C]
[ ] Has data outside of the plot region been removed from the data set?
105
1300
[ ] Has "Analysis mode" been unchecked?
85
[ ] Has the Y axis been adjusted to best fit the data? Is the unit correct?
1100
25
[ ] Has the X axis been adjusted according to data sheet requirement?
-40
[ 900
] Has the Z axis legend been positioned correctly (correct order, no overlap)
[ ] Are there at least eight grid lines for both X and Y axis?
700
1.6
1.8
2
2.2
2.4
2.6
VCC [V]
2.8
3
3.2
3.4
3.6
Figure 37-12.Idle Mode Current vs. VCC
fSYS = 32MHz internal oscillator.
- 40°C
25°C
85°C
105°C
5800
5300
4800
Icc [µA]
4300
3800
3300
2800
2300
1800
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
96
37.1.3 Power-down Mode Supply Current
Figure 37-13. Power-down Mode Supply Current vs. Temperature
All functions disabled.
8
3.0V
2.7V
2.2V
1.8V
7
6
Icc [µA]
5
4
3
2
1
0
-40
-25
-10
5
20
35
50
Temperature [°C]
65
80
95
110
Figure 37-14. Power-down Mode Supply Current vs. Temperature
Watchdog and sampled BOD enabled.
9
3.0V
2.7V
2.2V
1.8V
8
7
Icc [µA]
6
5
4
3
2
1
0
-40
-25
-10
5
20
35
50
Temperature [°C]
65
80
95
110
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
97
Figure 37-15. Power-down Mode Supply Current vs. VCC
All functions disabled.
9
8
105°C
7
Icc [µA]
6
5
4
3
85°C
2
1
25°C
-40°C
0
1.6
1.8
2.0
2.2
2.4
2.6
VCC [V]
2.8
3.0
3.2
3.4
3.6
Figure 37-16. Power-down Mode Supply Current vs. VCC
Watchdog and sampled BOD enabled and running from internal ULP oscillator.
10
9
105°C
8
ICC [µA]
7
6
5
4
85°C
3
2
25°C
-40°C
1
0
1.6
1.8
2.0
2.2
2.4
2.6
VCC [V]
2.8
3.0
3.2
3.4
3.6
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
98
37.2
I/O Pin Characteristics
37.2.1 Pull-up
Figure 37-17. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 1.8V.
70
-40°C
63
56
25°C
85°C
49
105 °C
I [µA]
42
35
28
21
14
7
0
0
0.2
0.4
0.6
0.8
1.0
VPIN [V]
1.2
1.4
1.6
1.8
2.7
3.0
Figure 37-18. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.0V.
135
-40°C
120
25°C
105
85°C
I [µA]
90
105 °C
75
60
45
30
15
0
0
0.3
0.6
0.9
1.2
1.5
VPIN [V]
1.8
2.1
2.4
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
99
Figure 37-19. I/O Pin Pull-up Resistor Current vs. Pin Voltage
VCC = 3.3V.
160
-40°C
140
25°C
85°C
100
105 °C
I [µA]
120
80
60
40
20
0
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
VPIN [V]
2.4
2.7
3.0
3.3
3.6
37.2.2 Output Voltage vs. Sink/Source Current
Figure 37-20. I/O Pin Output Voltage vs. Source Current
VCC = 1.8V.
1.9
1.8
1.7
VPIN [V]
1.6
1.5
-40°C
1.4
25°C
1.3
85°C
1.2
1.1
105°C
1.0
-6
-5
-4
-3
IPIN [mA]
-2
-1
0
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
100
Figure 37-21. I/O Pin Output Voltage vs. Source Current
VCC = 3.0V.
3.0
2.8
2.6
VPIN [V]
2.4
2.2
-40°C
2.0
25°C
1.8
85°C
1.6
105°C
1.4
-20
-18
-16
-14
-12
-10
IPIN [mA]
-8
-6
-4
-2
0
-8
-6
-4
-2
0
Figure 37-22. I/O Pin Output Voltage vs. Source Current
VCC = 3.3V.
3.35
3.15
2.95
VPIN [V]
2.75
2.55
-40°C
2.35
25°C
2.15
85°C
1.95
105°C
1.75
-20
-18
-16
-14
-12
-10
IPIN [mA]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
101
Figure 37-23. I/O Pin Output Voltage vs. Sink Current
VCC = 1.8V.
2.7
105°C
85°C
2.4
2.1
VPIN [V]
1.8
1.5
1.2
25°C
0.9
-40°C
0.6
0.3
0
0
2
4
6
8
10
IPIN [mA]
12
14
16
18
20
Figure 37-24. I/O Pin Output Voltage vs. Sink Current
VCC = 3.0V.
0.64
105°C
85°C
0.56
25°C
-40°C
0.48
VPIN [V]
0.40
0.32
0.24
0.16
0.08
0.00
0
2
4
6
8
10
IPIN [mA]
12
14
16
18
20
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
102
Figure 37-25. I/O Pin Output Voltage vs. Sink Current
VCC = 3.3V.
0.64
105°C
0.56
85°C
0.48
25°C
-40°C
VPIN [V]
0.40
0.32
0.24
0.16
0.08
0.00
0
2
4
6
8
10
IPIN [mA]
12
14
16
18
20
37.2.3 Thresholds and Hysteresis
Figure 37-26. I/O Pin Input Threshold Voltage vs. VCC
VIH I/O pin read as “1”.
1.8
-40°C
25°C
85°C
105°C
1.6
VTHRESHOLD [V]
1.4
1.2
1.0
0.8
0.6
0.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
103
Figure 37-27. I/O Pin Input Threshold Voltage vs. VCC
VIL I/O pin read as “0”.
1.8
-40°C
25°C
85°C
105°C
1.6
VTHRESHOLD [V]
1.4
1.2
1.0
0.8
0.6
0.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 37-28. I/O Pin Input Hysteresis vs. VCC.
350
VHYSTERESIS [mV]
300
250
200
150
-40°C
25°C
85°C
100
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
104
ADC Characteristics
Figure 37-29. INL Error vs. External VREF
T = 25°C, VCC = 3.6V, external reference.
2.5
2.3
2.1
INL [LS B
1.9
1.7
1.5
1.3
105ºC
1.1
- 40ºC
85ºC
25ºC
0.9
0.7
0.5
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
V REF[V]
Figure 37-30. ADC INL vs. VREF
SE Unsigned mode, VCC = 3.6V external reference.
INL [LS B]
37.3
3.5
3.3
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
105°C
85°C
25°C
- 40°C
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
V REF [V]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
105
Figure 37-31. ADC DNL vs. VREF
DNL [LS B ]
Differential signed mode, VCC = 3.6V external reference.
2.1
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
- 40ºC
105ºC
85ºC
25ºC
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
V REF [V
Figure 37-32. ADC DNL vs. VREF
SE unsigned mode, VCC = 3.6V, external reference.
3.0
2.8
2.6
DNL [LS B ]
2.4
2.2
2.0
1.8
1.6
1.4
- 40ºC
1.2
1.0
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
25ºC
85ºC
105ºC
V REF [V]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
106
Figure 37-33. ADC Offset vs. VCC.
SE Unsigned mode, VREF = 1.0V, external reference.
14
105ºC
85ºC
25ºC
- 40ºC
12
O ffs et [mV]
10
8
6
4
2
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V cc [V]
Figure 37-34. ADC Offset vs. VREF.
SE Unsigned mode, VCC = 3.6V, external reference.
O ffs et [mV]
23.0
21.0
105ºC
19.0
85ºC
17.0
25ºC
15.0
- 40ºC
13.0
11.0
9.0
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
V REF [V]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
107
Figure 37-35. ADC Offset vs. VREF.
Differential signed mode, VCC = 3.6V, external reference.
10.0
9.0
105ºC
85ºC
25ºC
O ffs et [mV]
8.0
7.0
- 40ºC
6.0
5.0
4.0
3.0
2.0
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3
3.2
3.4
3.6
V REF [V]
Figure 37-36. ADC Offset vs. VCC.
Differential signed mode, VREF = 1.0V, external reference.
1.6
1.8
2
2.2
2.4
2.6
2.8
-3.0
-3.5
-4.0
O ffs et [mV]
-4.5
-5.0
105ºC
-5.5
-6.0
85ºC
-6.5
25ºC
-7.0
-7.5
- 40ºC
-8.0
V cc [V]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
108
Figure 37-37. ADC Gain Error vs. VREF.
Differential signed mode, external reference.
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
-1.0 1
G ain E rror [mV]
-3.0
-5.0
-7.0
-9.0
- 40ºC
25ºC
85ºC
105°C
-11.0
-13.0
-15.0
V REF[V]
Figure 37-38. ADC Gain Error vs. VREF.
SE Unsigned mode, external reference.
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
0.0
-1.0
-2.0
G ain E rror [mV]
-3.0
- 40ºC
-4.0
-5.0
-6.0
25ºC
-7.0
-8.0
85ºC
-9.0
105ºC
-10.0
V REF [V]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
109
Figure 37-39. ADC Gain Error vs. VCC.
Differential signed mode, external reference.
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
-3.0
-3.5
G ain E rro r [mV]
-4.0
-4.5
-5.0
-5.5
25ºC
-6.0
- 40ºC
-6.5
-7.0
85ºC
105°C
-7.5
V cc [V]
Figure 37-40. ADC Gain Error vs. VCC.
SE Unsigned mode, external reference.
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
0
-1
G ain E rro r [mV]
-2
-3
-4
-5
- 40ºC
-6
25ºC
85ºC
105°C
-7
-8
V cc [V]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
110
Figure 37-41. ADC Gain Error vs. Temperature
Differential signed mode, external reference.
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
-1.0
G ain E rror [mV]
-3.0
-5.0
1.0V Vref
-.,0
1.5V Vref
-9.0
2.0V Vref
2.5V Vref
3.0V Vref
-11.0
-13.0
-15.0
T emperature [ºC ]
Figure 37-42. ADC Gain Error vs. Temperature
SE Unsigned mode, VCC = 3.6V, external reference.
-40
-3.0
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
G ain E rro r [mV]
-4.0
-5.0
-6.0
1.0V Vref
-7.0
1.5V Vref
2.0V Vref
-8.0
2.5V Vref
3.0V Vref
-9.0
-10.0
T emperature [ºC ]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
111
Analog Comparator Characteristics
Figure 37-43. Analog Comparator Hysteresis vs. VCC
High-speed mode, small hysteresis.
18
16
105°C
VHYST [mV]
14
85°C
12
25°C
10
- 40°C
8
6
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-44. Analog Comparator Hysteresis vs. VCC
High-speed mode, large hysteresis.
34
105°C
32
VHYST [mV]
37.4
85°C
30
28
25°C
26
24
-40°C
22
20
18
16
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V CC [V]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
112
Figure 37-45. Analog Comparator Propagation Delay vs. VCC
High speed mode.
34
32
t PD [ns]
30
28
26
24
22
105°C
85°C
20
18
16
1.6
25°C
- 40°C
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vcc [V]
Figure 37-46. Analog Comparator Current Consumption vs. VCC
High-speed mode.
270
105°C
Module Consumption [µA]
260
85°C
250
240
25°C
230
-40°C
220
210
200
190
180
1.8
2.0
2.2
2.4
2.6
2.8
VCC [V]
3.0
3.2
3.4
3.6
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
113
Figure 37-47. Analog Comparator Voltage Scaler vs. SCALEFAC
T = 25°C.
4.0
3.6V
3.3V
3.0V
2.7V
3.5
VSCALE [V]
3.0
2.5
2.0
1.8V
1.6V
1.5
1.0
0.5
0
0
7
14
21
28
35
42
49
56
63
SCALEFAC
Figure 37-48. Analog Comparator Offset Voltage vs. Common Mode Voltage
High-speed mode.
18
V HYST [mV]
16
105°C
14
85°C
12
25°C
10
- 40°C
8
6
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
V CC [V]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
114
Figure 37-49. Analog Comparator Current Source vs. Calibration
VCC = 3.0V, double mode.
12.0
ICURRENTSOURCE [µA]
11.5
11.0
10.5
10.0
9.5
9.0
-40°C
25°C
85°C
105°C
8.5
8.0
0
2
3
4
5
6
7
8
9
10
CURRCALIBA[3..0]
11
12
13
14
15
Internal 1.0V Reference Characteristics
Figure 37-50. ADC/DAC Internal 1.0V Reference vs. Temperature
1.012
1.010
Bandgap Voltage [V]
37.5
1
1.008
1.006
1.004
1.8V
1.002
2.7V
3.0V
1.000
0.998
- 40
-25
-10
5
20
35
50
Temperature [°C]
65
80
95
110
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
115
BOD Characteristics
Figure 37-51. BOD Thresholds vs. Temperature
BOD level = 1.6V.
1.624
1.622
1.620
VBOT [V]
1.618
1.616
Rising VCC
1.614
1.612
1.610
1.608
1.606
Falling VCC
1.604
-40
-25
-10
5
20
35
50
Temperature [°C]
65
80
95
110
Figure 37-52. BOD Thresholds vs. Temperature
BOD level = 2.2V.
2.350
2.345
2.340
VBOT [V]
37.6
Rising VCC
2.335
2.330
2.325
2.320
2.315
2.310
Falling VCC
2.305
-40
-25
-10
5
20
35
50
Temperature [°C]
65
80
95
110
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
116
Figure 37-53. BOD Thresholds vs. Temperature
BOD level = 3.0V.
3.072
3.064
3.056
Rising VCC
VBOT [V]
3.048
3.040
3.032
3.024
3.016
3.008
Falling VCC
3.000
-40
-25
-10
5
20
35
50
Temperature [°C]
65
80
95
110
Figure 37-54. BOD Current Consumption vs. VCC
Continuous mode, BOD level = 1.6V.
159
105°C
151
85°C
143
ICC [µA]
135
25°C
127
-40°C
119
111
103
95
1.8
2.0
2.2
2.4
2.6
2.8
VCC [V]
3.0
3.2
3.4
3.6
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
117
Figure 37-55. BOD Current Consumption vs. VCC
Sampled mode, BOD level = 1.6V.
10
105°C
9
8
ICC [µA]
7
6
5
85°C
4
3
2
25°C
1
-40°C
0
1.6
2.0
2.2
2.4
2.6
VCC [V]
2.8
3.0
3.2
3.4
3.6
External Reset Characteristics
Figure 37-56. Minimum Reset Pin Pulse Width vs. VCC
136
129
122
t RST [ns]
37.7
1.8
115
108
101
105°C
85°C
94
25°C
-40°C
87
80
1.6
1.8
2.0
2.2
2.4
2.6
VCC [V]
2.8
3.0
3.2
3.4
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
118
Figure 37-57. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V.
70
-40°C
60
25°C
85°C
IRESET [µA]
50
105°C
40
30
20
10
0
0
0.2
0.4
0.6
0.8
1.0
VRESET [V]
1.2
1.4
1.6
1.8
2.7
3.0
Figure 37-58. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.0V.
140
120
-40°C
25°C
IRESET [µA]
100
85°C
105°C
80
60
40
20
0
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
VRESET [V]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
119
Figure 37-59. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.3V.
140
-40°C
25°C
120
85°C
100
IRESET [µA]
105°C
80
60
40
20
0
0
0.3
0.6
0.9
1.2
1.5
1.8
VRESET [V]
2.1
2.4
2.7
3.0
3.3
Figure 37-60. Reset Pin Input Threshold Voltage vs. VCC
VIH - Reset pin read as “1”.
1.8
-40°C
25°C
85°C
105°C
1.6
VTHRESHOLD [V]
1.4
1.2
1.0
0.8
0.6
0.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
120
Figure 37-61. Reset Pin Input Threshold Voltage vs. VCC
VIL - Reset pin read as “0”.
1.8
-40°C
25°C
85°C
105°C
1.6
VTHRESHOLD [V]
1.4
1.2
1.0
0.8
0.6
0.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA B1 [DATASHEET]
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121
37.8
Oscillator Characteristics
37.8.1 Ultra Low-power Internal Oscillator
Figure 37-62. Ultra Low-power Internal Oscillator Frequency vs. Temperature.
Data
sheet plot checklist
35.0
34.5 apply the following checklist to all data sheet plots:
Please
F requency [kHz]
34.0
[ ] Is the most recent revision of PlotTool.xlt and the PlotTool database being used?
[ 33.5
] Is the plotted data reasonable?
[ ] Has data outside of device specification been removed from the data set?
33.0
[ ] Has data outside of the plot region been removed from the data set?
[ 32.5
] Has "Analysis mode" been unchecked?
[ ] Has the Y axis been adjusted to best fit the data? Is the unit correct?
[ 32.0
] Has the X axis been adjusted according to data sheet requirement?
[ ] Has the Z axis legend been positioned correctly (correct order, no overlap)
31.5
[ ] Are there at least eight grid lines for both X and Y axis?
3.3V
3.0V
2.7V
1.8V
1.6V
31.0
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [ °C ]
37.8.2 32.768kHz Internal Oscillator
Figure 37-63. 32.768kHz Internal Oscillator Frequency vs. Temperature.
32.875
1.8V
1.6V
2.2V
3.6V
2.7V
3.0V
32.860
Frequency [MHz]
32.845
32.830
32.815
32.800
32.785
32.770
32.755
32.740
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
122
Figure 37-64. 32.768kHz Internal Oscillator Calibration Step Size
T = -40°C to 85°C, VCC = 3V.
1.00%
105°C
85°C
25°C
-40°C
0.50%
Frequency StepSize
0.00%
-0.50%
-1.00%
-1.50%
-2.00%
-2.50%
-3.00%
-3.50%
-4.00%
0
32
64
96
128
160
RC32KCAL[7..0]
192
224
256
Figure 37-65. 32.768kHz Internal Oscillator Frequency vs. Calibration Value
VCC = 3.0V, T = 25°C.
55
Frequency [kHz]
50
3.0V
45
40
35
30
25
20
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
256
RC32KCAL[7..0]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
123
37.8.3 2MHz Internal Oscillator
Figure 37-66. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled.
2.15
2.13
Frequency [MHz]
2.11
2.09
2.07
2.05
2.03
3.6V
3.0V
2.7V
2.2V
1.8V
1.6V
2.01
1.99
1.97
1.95
-40
-25
-10
5
20
35
50
Temperature [°C]
65
80
95
110
Figure 37-67. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled.
2.009
1.8V
1.6V
3.6V
2.2V
3.0V
2.7V
2.008
Frequency [MHz]
2.007
2.006
2.005
2.004
2.003
2.002
2.001
2.000
1.999
-40
-25
-10
5
20
35
50
Temperature [°C]
65
80
95
110
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
124
Step Error [%]
Figure 37-68. 2MHz Internal Oscillator CALA Calibration Step Size
VCC = 3V.
-0.146
85°C
105°C
-0.161
25°C
-0.176
-40°C
-0.191
-0.206
-0.221
-0.236
-0.251
-0.266
0
16
32
48
64
80
DFLLRC2MCALA
96
112
128
Figure 37-69. 2MHz Internal Oscillator CALB Calibration Step Size
VCC = 3V, DFLL enabled.
-0.15
-0.16
-0.18
85°C
105°C
25°C
-0.19
-40°C
Step Error [%]
-0.17
-0.20
-0.21
-0.22
-0.23
-0.24
-0.25
-0.26
0
8
16
24
32
40
DFLLRC2MCALB
48
56
64
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
125
37.8.4 32MHz Internal Oscillator
Figure 37-70. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled.
DFLL Disabled
35.5
35.0
Frequency [MHz]
34.5
34.0
33.5
33.0
32.5
3.6V
3.0V
2.7V
2.2V
1.8V
1.6V
32.0
31.5
31.0
-40
-25
10
5
20
35
50
Temperature [°C]
65
80
95
110
Figure 37-71. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled,
from
the32.768kHz
32.768kHz internal
DFLL
with
internal oscillator
oscillator. as reference
32.11
1.8V
2.2V
1.6V
3.0V
2.7V
32.09
Frequency [MHz]
32.08
32.06
3.3V
32.05
32.03
32.02
32.00
31.99
-40
-25
-10
5
20
35
50
Temperature [°C]
65
80
95
110
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
126
Figure 37-72. 32MHz Internal Oscillator CALA Calibration Step Size
VCC = 3.0V.
Frequency Step Error [%]
-0.12
25°C
-0.14
85°C
-0.16
105°C
-0.18
-40°C
-0.20
-0.22
-0.24
-0.26
-0.28
-0.30
0
16
32
48
64
80
DFLLRC32MCALA
96
112
128
Figure 37-73. 32MHz Internal Oscillator CALB Calibration Step Size
VCC = 3.0V, CALA = mid value.
0.60
Frequency Step size [%]
0.50
0.40
0.30
0.20
-40°C
0.10
0.00
-0.10
105°C
25°C
-0.20
85°C
-0.30
-0.40
0
8
16
24
32
40
48
56
64
DFLLRC32MCALB
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
127
Figure 37-74. 32MHz Internal Oscillator Frequency vs. CALA Calibration Value
VCC = 3.0V.
56
-40°C
54
25°C
52
f [MHz]
50
85°C
105°C
48
46
44
42
40
38
0
20
40
60
80
DFLLRC32MCALA
100
120
140
Figure 37-75. 32MHz Internal Oscillator Frequency vs. CALB Calibration Value
VCC = 3.0V, DFLL enabled.
80
70
-40°C
25°C
85°C
105°C
f [MHz]
60
50
40
30
20
0
10
20
30
40
DFLLRC32MCALB
50
60
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
128
37.8.5 32MHz Internal Oscillator Calibrated to 48MHz
Figure 37-76. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled.
53
Frequency [MHz]
52
51
50
49
3.6V
3.0V
2.7V
2.2V
1.8V
1.6V
48
47
46
-40
-25
-10
5
20
35
50
Temperature [°C]
65
80
95
110
Figure 37-77. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator.
48.18
1.6V
1.8V
2.2V
3.6V
2.7V
3.0V
48.15
Frequency (MHz)
48.12
48.09
48.06
48.03
48.00
47.97
47.94
47.91
-40
-25
-10
5
20
35
50
Temperature [°C]
65
80
95
110
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–12/2014
129
Figure 37-78. 32MHz Internal Oscillator CALA Calibration Step Size
Using 48MHz calibration value from signature row, VCC = 3.0V.
0.80
Frequency Step sizer [%]
0.60
0.40
0.20
-40°C
0.00
105°C
85°C
-0.20
25°C
-0.40
-0.60
0
16
32
48
64
CALA
80
96
112
128
Figure 37-79. 48MHz Internal Oscillator Frequency vs. CALA Calibration Value
VCC = 3.0V.
60
-40°C
58
Frequency [MHz]
56
25°C
54
85°C
105°C
52
50
48
46
44
42
0
16
32
48
64
CALA
80
96
112
128
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
130
PDI Characteristics
Figure 37-80. Maximum PDI Frequency vs. VCC
21
20
25°C
19
f min [kHz]
37.9
-40°C
18
85°C
17
105°C
16
15
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA B1 [DATASHEET]
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37.10 LCD Characteristics
Figure 37-81. ICC vs. Frame Rate
32Hz Low Power Frame Rate from 32.768kHz TOSC, w/ and w/o pixel load, VCC = 1.8V, T = 25°C.
11
22pF All Pixels ON
10
ICC [µA]
9
8
22pF All Pixels OFF
7
6
5
0pF All Pixels ON
4
0pF All Pixels OFF
3
32
64
96
128
160
192
224
256
Frame Rate[Hz]
Figure 37-82. ICC vs. Frame Rate
32Hz Low Power Frame Rate from 32.768kHz TOSC, w/ and w/o pixel load, VCC = 3.0V, T = 25°C.
13
12
22pF All Pixels ON
11
ICC [µA]
10
9
22pF 100 Pixels ON
8
7
22pF All Pixels OFF
6
0pF All Pixels ON
5
0pF 100 Pixels ON
4
0pF All Pixels OFF
3
32
64
96
128
160
192
224
256
Frame Rate[Hz]
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
132
Figure 37-83. ICC vs. Frame Rate
0pF load.
15
85 °C
13
ICC [µA]
25 °C
11
-40 °C
9
7
5
3
32
64
96
128
160
192
224
256
Frame Rate[Hz]
Figure 37-84. ICC vs. Contrast
32Hz Low Power Frame Rate from 32.768kHz TOSC, w/o pixel load, VCC = 1.8V.
7.5
7
6.5
ICC [µA]
85°C
6
5.5
5
25°C
-40°C
4.5
4
3.5
3
-32
-23
-14
-5
4
13
22
31
Contrast
XMEGA B1 [DATASHEET]
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Figure 37-85. ICC vs. Contrast
32Hz Low Power Frame Rate from 32.768kHz TOSC, w/o pixel load, VCC = 3.0V.
7.5
7
85°C
ICC [µA]
6.5
6
5.5
5
25°C
4.5
-40°C
4
3.5
3
-32
-23
-14
-5
4
13
22
31
Contrast
Figure 37-86. PSAVE LCD LP 32Hz vs. Temperature
3.20
ModuleConsumption [µA]
3.05
2.90
2.75
3.6
2.60
2.45
3.0
2.30
1.6
2.2
1.8
2.15
2.00
-40
-25
-10
5
20
35
50
Temperature [°C]
65
80
95
110
XMEGA B1 [DATASHEET]
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134
Figure 37-87. PSAVE LCD LP 32Hz vs. Temperature
RTC, WDT, BOD sampled.
3.6
IccModuleConsumption [µA]
3.4
3.2
1.6
3.0
3.6
2.8
2.6
3.0
1.8
2.2
2.4
2.2
2.0
-40
-25
-10
5
20
35
50
Temperature [°C]
65
80
95
110
Figure 37-88. PSAVE vs. Temperature
RTC, WDT, BOD sampled.
0.32
ModuleConsumption [µA]
0.29
0.26
0.23
3.6
0.20
2.2
0.17
0.14
1.8
3.0
0.11
0.08
-40
1.6
-25
-10
5
20
35
50
Temperature [°C]
65
80
95
110
XMEGA B1 [DATASHEET]
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135
38.
Errata
38.1
ATxmega64B1, ATxmega128B1
38.1.1 Rev. C
• Device revision number
• AWeX fault protection restore is not done correct in Pattern Generation Mode
1. Device revision number is unchanged between rev. B and rev. C
2. AWeX fault protection restore is not done correctly in Pattern Generation Mode
When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN is
restored according to the corresponding enabled DTI channels. For Common Waveform Channel Mode (CWCM),
this has no effect as the OUTOVEN is correct after restoring from fault. For Pattern Generation Mode (PGM),
OUTOVEN should instead have been restored according to the DTILSBUF register.
Problem fix/Workaround
For CWCM no workaround is required.
For PGM in latched mode, disable the DTI channels before returning from the fault condition. Then, set correct
OUTOVEN value and enable the DTI channels, before the direction (DIR) register is written to enable the correct
outputs again.
For PGM in cycle-by-cycle mode there is no workaround.
38.1.2 Rev. B
Not sampled.
38.1.3 Rev. A
• Power down consumption
• ADC conversion error when x0.5 gain is used
• Disabling of USART transmitter does not automatically set the TxD pin direction to input
1. Power Down consumption
After reset, when system enters in power down or when ADC is disabled, extra power consumption is drawn.
Problem fix/Workaround
Set ADC to a configuration different from differential mode.
2. ADC conversion error when x0.5 gain is used
When the gain is set to x0.5, the conversion result is similar to the gain setting x1.
Problem fix/Workaround
There is no workaround.
3. Disabling of USART transmitter does not automatically set the TxD pin direction to input
If the USART transmitter is idle with no frames to transmit, setting TXEN to zero will not automatically set the TxD
pin direction to input.
XMEGA B1 [DATASHEET]
Atmel-8330H-AVR-ATxmega64B1-128B1_datasheet–AVR–12/2014
136
Problem fix/Workaround
The TxD pin direction can be set to input using the Port DIR register. Be advised that setting the Port DIR register
to input will be immediate. Ongoing transmissions will be truncated.
XMEGA B1 [DATASHEET]
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137
39.
Datasheet Revision History
Note that the referring page numbers in this section are referred to this document. The referring revision in this section
are referring to the document revision.
39.1
8330H – 12/2014
1.
39.2
39.3
Corrected description for VFBGA pinout in Table 2-1 on page 5.
8330G – 11/2014
1.
Information for 105°C are added.
2.
Several small changes are made to set up the document according to the new template.
3.
AVDD in Table 32-2 on page 56 has been corrected to AVCC.
4.
Changed Vcc to AVcc in Section 29. “ADC – 12-bit Analog to Digital Converter” on page 49 and
Section 30. “AC – Analog Comparator” on page 51.
5.
Added error information on USART transmitter to Section 38. “Errata” on page 136.
6.
Changed pin names in Table 2-1 on page 5
from VCC1, LVCC1 and LVCC01 to VCC
from GND1, LGND1 and LGND01 to GND
from D2W_D to PDI_DATA
7.
Changed unit value for parameter tSU;DAT to ns in Table 36-30 on page 89.
8.
Corrected description for VFBGA pinout. Pin F2 changed from VCC to GND in Table 2-1 on
page 5.
8330F – 02/2014
Added the correct VFBGA package drawing:
1.
2.
39.4

Replaced the package 100C1 (CBGA) by the package 7A1 (VFBGA)

Updated the package type in “Ordering Information” on page 2

Updated the title in Figure 2-2 on page 5 and in the Table 2-1 on page 5

Updated the package type in “Typical Characteristics” on page 91
Updated the title name of the Table 36-24 on page 82.
8330E – 06/2013
1.
Added pinout for CBGA package option: Figure 2-2 and Table 2-1 on page 5.
XMEGA B1 [DATASHEET]
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138
39.5
39.6
39.7
39.8
8330D – 01/2013
1.
Updated “Ordering Information” on page 2: Added -AUR, -CU and -CUR options.
2.
Updated “Packaging Information” : Added package drawing for “7A1” on page 68.
3.
Updated Table 32-5 on page 57: PDI and RESET pins updated.
4.
Updated pin number for PR1 to pin 81 in Table 32-8 on page 59.
5.
Updated “External clock with prescaler for system clock” Table 36-26 on page 84.
6.
Added ESR parameter to the “External 16MHz crystal oscillator and XOSC characteristics.”
Table 36-27 on page 84.
8330C – 07/2012
1.
Updated the Table 32-4 on page 57. PDI_CLOCK is on pin 16 and PDI_DATA on pin 15.
2.
Updated the datasheet using the Atmel new template.
3.
Updated “Errata” , “Rev. C” on page 136: “JTAG revision” replaced by “Device revision number”.
8330B – 02/2012
1.
Updated the Table 7-2 on page 16. The page size (words) for ATxmega128B1 changed from
256 to 128.
2.
Updated all “Electrical Characteristics” on page 69.
3.
Updated all “Typical Characteristics” on page 91.
4.
Updated “Errata” on page 136.
8330A – 10/2011
1.
Initial revision.
XMEGA B1 [DATASHEET]
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XMEGA B1 [DATASHEET]
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Table Of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2.
Pinout/Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.1
4.
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
Recommended Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.
Capacitive Touch Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
6.
AVR CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7.
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
8.
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fuses and Lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Memory and Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device ID and Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash and EEPROM Page Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
13
14
14
15
15
15
15
15
16
16
16
DMAC – Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
8.1
8.2
9.
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ALU - Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Stack and Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
9.1
9.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10. System Clock and Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
10.1
10.2
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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11. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
11.1
11.2
11.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
12.1
12.2
12.3
12.4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
25
25
13. WDT – Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
13.1
13.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
14. Interrupts and Programmable Multilevel Interrupt Controller . . . . . . . . . . . . . . . . .28
14.1
14.2
14.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
15. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
15.1
15.2
15.3
15.4
15.5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alternate Port Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
30
30
33
33
16. T/C – 16-bit Timer/Counter Type 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
16.1
16.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
17. TC2 –16-bit Timer/Counter Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
17.1
17.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
18. AWeX – Advanced Waveform Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
18.1
18.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
19. Hi-Res – High Resolution Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
19.1
19.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
20. RTC – 16-bit Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
20.1
20.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
21. USB – Universal Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
21.1
21.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
22. TWI – Two-wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
22.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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22.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
23. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
23.1
23.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
24. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
24.1
24.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
25. IRCOM – IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
25.1
25.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
26. AES and DES Crypto Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
26.1
26.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
27. CRC – Cyclic Redundancy Check Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
27.1
27.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
28. LCD - Liquid Crystal Display Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
28.1
28.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
29. ADC – 12-bit Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
29.1
29.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
30. AC – Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
30.1
30.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
31. Programming and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
31.1
31.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
32. Pinout and Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
32.1
32.2
Alternate Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Alternate Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
33. Peripheral Module Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
34. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
35. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
35.1
35.2
100A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7A1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
36. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
36.1
36.2
36.3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
General Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
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36.4
36.5
36.6
36.7
36.8
36.9
36.10
36.11
36.12
36.13
36.14
36.15
36.16
Wake-up Time from Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Liquid Crystal Display Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bandgap and Internal 1.0V Reference Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Brownout Detection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-on Reset Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash and EEPROM Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock and Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two-wire Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
75
76
76
79
79
80
80
80
81
81
87
89
37. Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
37.1
37.2
37.3
37.4
37.5
37.6
37.7
37.8
37.9
37.10
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
I/O Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Internal 1.0V Reference Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
BOD Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
External Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
PDI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
LCD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
38. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
38.1
ATxmega64B1, ATxmega128B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
39. Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
39.1
39.2
39.3
39.4
39.5
39.6
39.7
39.8
8330H – 12/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8330G – 11/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8330F – 02/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8330E – 06/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8330D – 01/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8330C – 07/2012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8330B – 02/2012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8330A – 10/2011 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
138
138
138
138
139
139
139
139
Table Of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
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XXXXXX
Atmel Corporation
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© 2014 Atmel Corporation. / Rev.: Atmel-8330H-AVR-ATxmega64B1-128B1-Datasheet_12/2014.
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