ATF750C(L) - Complete

Features
• Advanced, High-speed, Electrically-erasable Programmable Logic Device
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– Superset of 22V10
– Enhanced Logic Flexibility
– Backward Compatible with ATV750B/BL and ATV750/L
Low-power Edge-sensing “L” Option with 1 mA Standby Current
D- or T-type Flip-flop
Product Term or Direct Input Pin Clocking for Flip-flop
7.5 ns Maximum Pin-to-pin Delay with 5V Operation
Highest Density Programmable Logic Available in 24-pin and 28-pin Packages
– Advanced Electrically-erasable Technology
– Reprogrammable
– 100% Tested
Increased Logic Flexibility
– 42 Array Inputs, 20 Sum Terms and 20 Flip-flops
Enhanced Output Logic Flexibility
– All 20 Flip-flops Feed Back Internally
– 10 Flip-flops are also Available as Outputs
Programmable Pin-keeper Circuits
Dual-in-line and Surface Mount Package in Standard Pinouts
Full Military, Commercial and Industrial Temperature Ranges
20-year Data Retention
2000V ESD Protection
1000 Erase/Write Cycles
Green Package Options (Pb/Halide-free/RoHS Compliant) Available
High-speed
Complex
Programmable
Logic Device
ATF750C
ATF750CL
1. Block Diagram
(OE PRODUCT TERMS)
12
INPUT
PINS
PROGRAMMABLE
INTERCONNECT
AND
COMBINATORIAL
LOGIC ARRAY
4 TO 8
PRODUCT
TERMS
LOGIC
OPTION
(UP T0 20
FLIP-FLOPS)
OUTPUT
OPTION
10
I/O
PINS
(CLOCK PIN)
0776L–PLD–11/08
2. Pin Configurations
Pin
Function
CLK
Clock
IN
Logic Inputs
I/O
Bi-directional Buffers
GND
Ground
VCC
+5V Supply
24
23
22
21
20
19
18
17
16
15
14
13
IN
IN
CLK/IN
VCC(1)
VCC
I/O
I/O
1
2
3
4
5
6
7
8
9
10
11
12
PLCC/LCC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
IN
IN
IN
GND(1)
IN
IN
IN
4
3
2
1
28
27
26
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
2.2
5
6
7
8
9
10
11
25
24
23
22
21
20
19
12
13
14
15
16
17
18
DIP/SOIC/TSSOP
I/O
I/O
I/O
GND(1)
I/O
I/O
I/O
IN
IN
GND
GND(1)
IN
I/O
I/O
2.1
Note:
For PLCC, pins 1, 8, 15, and 22 can be left unconnected. For superior performance, connect VCC to pin 1
and GND to pins 8, 15, and 22.
3. Description
The ATF750C(L)s are twice as powerful as most other 24-pin programmable logic devices.
Increased product terms, sum terms, flip-flops and output logic configurations
translate into more usable gates. High-speed logic and uniform predictable delays guarantee
fast in-system performance. The ATF750C(L) is a high-performance CMOS (electrically-erasable) complex programmable logic device (CPLD) that utilizes Atmel’s proven electricallyerasable technology.
Each of the ATF750C(L)’s 22 logic pins can be used as an input. Ten of these can be used as
inputs, outputs or bi-directional I/O pins. Each flip-flop is individually configurable as either D- or
T-type. Each flip-flop output is fed back into the array independently. This allows burying of all
the sum terms and flip-flops.
There are 171 total product terms available. There are two sum terms per output, providing
added flexibility. A variable format is used to assign between four to eight product terms per sum
term. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20
sum terms and flip-flops, complex state machines are easily implemented with logic to spare.
Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flip-flop
may also be individually configured to have direct input pin controlled clocking. Each output has
its own enable product term. One product term provides a common synchronous preset for all
flip-flops. Register preload functions are provided to simplify testing. All registers automatically
reset upon power-up.
The ATF750CL is a low-power device with speeds as fast as 15 ns. The ATF750CL provides the
optimum low-power CPLD solution. This device significantly reduces total system power,
thereby allowing battery-powered operations.
2
ATF750C(L)
0776L–PLD–11/08
ATF750C(L)
4. Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
*NOTICE:
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
5. DC and AC Operating Conditions
All members of the family are specified to operate in either one of two voltage ranges. Parameters are specified as noted to
be either 2.7V to 3.6V, 5V ±5% or 5V ±10%.
5V Operation
Operating Temperature (Ambient)
VCC Power Supply
Commercial
-7.5, -10, -15
Industrial
-10, -15
0°C - 70°C
-40°C - +85°C
-55°C - +125°C
(case)
5V ± 5%
5V ± 10%
5V ± 10%
Military
3
0776L–PLD–11/08
6. Logic Options
Combinatorial Output
Combined Terms
Registered Output
Combined Terms
Separate Terms
Separate Terms
7. Clock Mux
CKMUX
CKi
CLOCK
PRODUCT
TERM
CLK
PIN
TO
LOGIC
CELL
SELECT
8. Output Options
4
ATF750C(L)
0776L–PLD–11/08
ATF750C(L)
9. Bus-friendly Pin-keeper Input and I/Os
All input and I/O pins on the ATF750C(L) have programmable “pin-keeper” circuits. If activated,
when any pin is driven high or low and then subsequently left floating, it will stay at that previous
high or low level.
This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels,
which causes unnecessary power consumption and system noise. The keeper circuits eliminate
the need for external pull-up resistors and eliminate their DC power consumption.
Enabling or disabling of the pin-keeper circuits is controlled by the device type chosen in the
logic compiler device selection menu. Please refer to the software compiler table for more
details. Once the pin-keeper circuits are disabled, normal termination procedures are required
for unused inputs and I/Os.
10. Input Diagram
VCC
INPUT
100K
ESD
PROTECTION
CIRCUIT
PROGRAMMABLE
OPTION
11. I/O Diagram
VCC
OE
DATA
I/O
VCC
100K
PROGRAMMABLE
OPTION
5
0776L–PLD–11/08
12. DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Output Leakage
Current
Min
Typ
Max
Units
VIN = -0.1V to VCC + 1V
10
µA
VOUT = -0.1V to VCC + 0.1V
10
µA
Com.
125
180
mA
Ind., Mil.
135
190
mA
Com.
125
180
mA
Ind., Mil.
135
190
mA
Com.
0.12
1
mA
Ind.
0.15
2
mA
-120
mA
-0.6
0.8
V
2.0
VCC + 0.75
V
C-7, -10
ICC
Power Supply
Current, Standby
VCC = Max,
VIN = Max,
Outputs Open
C-15
CL-15
IOS(1)
Output Short
Circuit Current
VOUT = 0.5V
VIL
Input Low Voltage
4.5 ≤VCC ≤5.5V
VIH
Input High Voltage
VOL
Output Low
Voltage
VOH
Note:
Output High
Voltage
VIN = VIH or VIL,
VCC = Min
VIN = VIH or VIL,
VCC = Min
IOL = 16 mA
Com., Ind.
0.5
V
IOL = 12 mA
Mil.
0.5
V
IOL = 24 mA
Com.
0.8
V
IOH = -4.0 mA
2.4
V
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
13. Input Test Waveforms and Measurement Levels
tR, tF < 3 ns (10% to 90%)
14. Output Test Load
VCC
300
(390 MIL.)
390
(750 MIL.)
6
ATF750C(L)
0776L–PLD–11/08
ATF750C(L)
15. AC Waveforms, Product Term Clock(1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
16. AC Characteristics, Product Term Clock(1)
-7
Min
-10
Max
Min
C/CL-15
Max
Min
Max
Units
10
15
ns
7.5
10
15
ns
7.5
10
15
ns
5
12
ns
5
9
ns
Symbol
Parameter
tPD
Input or Feedback to Non-registered Output
7.5
tEA
Input to Output Enable
tER
Input to Output Disable
tCO
Clock to Output
3
7.5
4
10
tCF
Clock to Feedback
1
5
4
7.5
tS
Input Setup Time
3
4
8/12
ns
tSF
Feedback Setup Time
3
4
7
ns
tH
Hold Time
1
2
5
ns
tP
Clock Period
7
11
14
ns
tW
Clock Width
3.5
5.5
7
ns
fMAX
External Feedback 1/(tS + tCO)
95
71
50/41
MHz
Internal Feedback 1/(tSF + tCF)
125
86
62
MHz
No Feedback 1/(tP)
142
90
71
MHz
tAW
Asynchronous Reset Width
5
10
15
ns
tAR
Asynchronous Reset Recovery Time
3
10
15
ns
tAP
Asynchronous Reset to Registered Output Reset
tSP
Note:
Setup Time, Synchronous Preset
8
4
12
7
15
8
ns
ns
1. See ordering information for valid part numbers.
7
0776L–PLD–11/08
17. AC Waveforms, Input Pin Clock(1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
18. AC Characteristics, Input Pin Clock
-7
Max
Min
C/CL-15
Symbol
Parameter
tPD
Input or Feedback to Non-registered Output
7.5
tEA
Input to Output Enable
tER
Input to Output Disable
tCOS
Clock to Output
0
6.5
0
7
tCFS
Clock to Feedback
0
3.5
0
5
tSS
Input Setup Time
4
5
8/12.5
ns
tSFS
Feedback Setup Time
4
5
7
ns
tHS
Hold Time
0
0
0
ns
tPS
Clock Period
7
10
12
ns
tWS
Clock Width
3.5
5
6
ns
fMAXS
Min
-10
Max
Min
Max
Units
10
15
ns
7.5
10
15
ns
7.5
10
15
ns
0
10
ns
0
5.5
ns
External Feedback 1/(tSS + tCOS)
95
83
55/44
MHz
Internal Feedback 1/(tSFS + tCFS)
133
100
80
MHz
No Feedback 1/(tPS)
142
100
83
MHz
tAW
Asynchronous Reset Width
5
10
15
ns
tARS
Asynchronous Reset Recovery Time
5
10
15
ns
tAP
Asynchronous Reset to Registered Output Reset
tSPS
Setup Time, Synchronous Preset
8
8
5
10
5/9
15
11
ns
ns
ATF750C(L)
0776L–PLD–11/08
ATF750C(L)
19. Functional Logic Diagram ATF750C, Upper Half
9
0776L–PLD–11/08
20. Functional Logic Diagram ATF750C, Lower Half
10
ATF750C(L)
0776L–PLD–11/08
ATF750C(L)
21. Power-up Reset
The registers in the ATF750C(L)s are designed to reset during power-up. At a point delayed
slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will
depend on the polarity of the output buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature
of reset and the uncertainty of how VCC actually rises in the system, the following conditions are
required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving the
clock terms or pin high, and
3. The clock pin, or signals from which clock terms are derived, must remain stable
during tPR.
Parameter
Description
Typ
Max
Units
tPR
Power-up Reset Time
600
1000
ns
VRST
Power-up Reset Voltage
2.0
4.5
V
22. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
Max
Units
CIN
5
8
pF
VIN = 0V
COUT
6
8
pF
VOUT = 0V
Note:
Conditions
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100%
tested.
11
0776L–PLD–11/08
23. Using the ATF750C’s Many Advanced Features
The ATF750C(L)’s advanced flexibility packs more usable gates into 24 pins than any other logic
device. The ATF750C(L)s start with the popular 22V10 architecture, and add several enhanced
features:
• Selectable D- and T-type Registers
Each ATF750C(L) flip-flop can be individually configured as either D- or T-type. Using the Ttype configuration, JK and SR flip-flops are also easily created. These options allow more
efficient product term usage.
• Selectable Asynchronous Clocks
Each of the ATF750C(L)’s flip-flops may be clocked by its own clock product term or directly
from Pin 1 (SMD Lead 2). This removes the constraint that all registers must use the same
clock. Buried state machines, counters and registers can all coexist in one device while
running on separate clocks. Individual flip-flop clock source selection further allows mixing
higher performance pin clocking and flexible product term clocking within one design.
• A Full Bank of Ten More Registers
The ATF750C(L) provides two flip-flops per output logic cell for a total of 20. Each register
has its own sum term, its own reset term and its own clock term.
• Independent I/O Pin and Feedback Paths
Each I/O pin on the ATF750C(L) has a dedicated input path. Each of the 20 registers has its
own feedback terms into the array as well. This feature, combined with individual product
terms for each I/O’s output enable, facilitates true bi-directional I/O design.
24. Synchronous Preset and Asynchronous Reset
One synchronous preset line is provided for all 20 registers in the ATF750C(L). The appropriate
input signals to cause the internal clocks to go to a high state must be received during a synchronous preset. Appropriate setup and hold times must be met, as shown in the switching
waveform diagram.
An individual asynchronous reset line is provided for each of the 20 flip-flops. Both master and
slave halves of the flip-flops are reset when the input signals received force the internal resets
high.
25. Software Support
All family members of the ATF750C(L) can be designed with Atmel®-WinCUPL.
Additionally, the ATF750C may be programmed to perform the ATV750(L) functional subset (no
T-type flip-flops, pin clocking or D/T2 feedback) using the ATV750 JEDEC file. In this case, the
ATF750C becomes a direct replacement or speed upgrade for the ATV750. The ATF750C is a
direct replacement for the ATV750(L) and the ATV750B(L).
12
ATF750C(L)
0776L–PLD–11/08
ATF750C(L)
26. Software Compiler Mode Selection
Table 26-1.
Software Compiler Mode Selection
Device
Atmel - WinCupL Device Mnemonic
Pin-keeper
ATF750C-DIP
V750C
V750CPPK
Disabled
Enabled
ATF750C-PLCC
V750LCC
V750CPPKLCC
Disabled
Enabled
27. Third Party Programmer Support
Table 27-1.
Third Party Programmer Support
Device
Description
ATF750C (V750)
V750 Cross-programming. JEDEC file compatible with standard V750 JEDEC
file (total fuses in JEDEC file = 14394). The Programmer will automatically
program “0”s into the User Rrow (UES), and disable the Pin-keeper features. The
Fuse Checksum will be the same as the old ATV750/L file. This device type is
recommended for customers that are directly migrating from an ATV750/L device
to an ATF750C/CL device.
ATF750C (V750B)
V750B Cross-programming. JEDEC file compatible with standard V750B
JEDEC file (total fuses in JEDEC file = 14435). The Programmer will
automatically program “0”s into the User Row (UES), and disable the Pin-keeper
feature. The Fuse Checksum will be the same as the old ATV750B/BL file. This
device type is recommended for customers that are directly migrating from an
ATV750B/BL device to an ATF750C/CL device.
ATF750C
Programming of User Row (UES) bits supported and Pin-keeper bit is userprogrammable. (Total fuses in JEDEC file = 14504). This is the default device
type and is recommended for users that have re-compiled their source design
files to specifically target the ATF750C device.
Note:
1. The ATF750C has 14,504 JEDEC fuses.
28. Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF750C(L) fuse patterns.
Once the security fuse is programmed, all fuses will appear programmed during verify.
The security fuse should be programmed last, as its effect is immediate.
13
0776L–PLD–11/08
29. Preload of Registered Outputs
The ATF750C(L)’s registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A VIH level on the I/O pin will force the register high; a VIL will force it low, independent of the output polarity. The PRELOAD state is entered
by placing a 10.25V to 10.75V signal on pin 8 on DIPs, and lead 10 on SMDs. When the clock
term is pulsed high, the data on the I/O pins is placed into the register chosen by the select pin
.
14
Level Forced on Registered
Output Pin during Preload Cycle
Select Pin
State
Register #0 State
after Cycle
Register #1 State
after Cycle
VIH
Low
High
X
VIL
Low
Low
X
VIH
High
X
High
VIL
High
X
Low
ATF750C(L)
0776L–PLD–11/08
ATF750C(L)
ATF750CL SUPPLY CURRENT
VS. SUPPLY VOLTAGE (TA = 25°C)
ATF750C
ATF750CSUPPLY
SUPPLYCURRENT
CURRENTVS.
VS.
SUPPLY
SUPPLYVOLTAGE
VOLTAGE(T
(TAA==25°C)
25°C)
120
120
140
100
100
120
80
80
100
ICC (µA)
160
IICC
(mA)
CC (mA)
140
140
60
60
80
40
40
60
20
20
40
20
00
4.50
4.50
4.75
4.75
5.00
5.00
5.25
5.25
5.50
5.50
0
4.50
SUPPLY
SUPPLYVOLTAGE
VOLTAGE(V)
(V)
4.75
5.25
5.50
SUPPLY CURRENT VS. FREQUENCY
LOW-POWER ("L") VERSION (TA = 25°C)
SUPPLY CURRENT VS. FREQUENCY
STANDARD POWER (TA = 25°C)
160
5.00
SUPPLY VOLTAGE (V)
140
120
100
ICC (mA)
ICC (mA)
120
80
80
60
40
40
20
0
0
0
5
10
25
50
75
0
100
5
10
ATF750C/CL OUTPUT SOURCE CURRENT
VS. SUPPLY VOLTAGE (VOH = 2.4V)
50
75
100
ATF750C/CL OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25°C)
0
0.00
-5
-10.00
-10
-20.00
-15
-30.00
-20
IOH (mA)
IOH (mA)
25
FREQUENCY (MHz)
FREQUENCY (MHz)
-25
-30
-40.00
-50.00
-60.00
-35
-40
-70.00
-45
-80.00
-50
4
4.5
5
SUPPLY VOLTAGE (V)
5.5
6
-90.00
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
VOH (V)
15
0776L–PLD–11/08
ATF750C/CL OUTPUT SINK CURRENT
VS. SUPPLY VOLTAGE (VOL = 0.5V)
ATF750C/CL OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25°C)
140
44
43
120
42
100
40
IOL (mA)
IOL (mA)
41
39
38
37
80
60
40
36
20
35
34
0
4
4.5
5
5.5
6
0
0.5
1
1.5
2
90
30
80
25
INPUT CURRENT (uA)
60
IOL (mA)
3.5
4
4.5
5
20
70
50
40
30
20
15
10
5
0
-5
-10
-15
10
-20
0
-25
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0
0.5
1
1.5
VOL (V)
ATF750C/CL INPUT CURRENT VS. INPUT VOLTAGE
(VCC = 5V,TA = 25°C)
WITHOUT PIN-KEEPER
2
2.5
3
3.5
4
INPUT VOLTAGE (V)
4.5
5
5.5
6
ATF750C/CL INPUT CLAMP CURRENT
VS. INPUT VOLTAGE (VCC = 5V,TA = 35°C)
1.8
0
1.6
-10
-20
INPUT CURRENT (mA)
INPUT CURRENT (uA)
3
ATF750C/CL INPUT CURRENT VS. INPUT VOLTAGE
(VCC = 5V,TA = 25°C)
ATF750C/CL OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25°C)
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-30
-40
-50
-60
-70
-80
-90
-100
-0.2
0
0
0.5
1
1.5
2
2.5
3
3.5
INPUT VOLTAGE (V)
16
2.5
VOL (V)
SUPPLY VOLTAGE (V)
4
4.5
5
5.5
-0.2
-0.4
-0.6
-0.8
-1
6
INPUT VOLTAGE (V)
ATF750C(L)
0776L–PLD–11/08
ATF750C(L)
30. ATF750C(L) Military Ordering Information
tPD
(ns)
10
15
Note:
tCOS
(ns)
7
10
Ext.
fMAXS
(MHz)
83
55
Ordering Code
Package
ATF750C-10GM/883
ATF750C-10NM/883
5962-0720101MLA
5962-0720101M3A
24D3
28L
24D3
28L
ATF750C-15GM/883
ATF750C-15NM/883
5962-0720102MLA
5962-0720102M3A
24D3
28L
24D3
28L
Operation Range
Military/883
(-55° C to 125° C)
Class B, Fully Compliant
1. Special order only: TSSOP package requires special thermal management.
31. ATF750C(L) Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD
(ns)
7.5
10
15
tCOS
(ns)
6.5
7
10
Ext.
fMAXS
(MHz)
Ordering Code
Package
Operation Range
95
ATF750C-7JX
ATF750C-7PX
ATF750C-7SX
28J
24P3
24S
Commercial
(0° C to 70° C)
83
ATF750C-10JU
ATF750C-10PU
ATF750C-10SU
ATF750C-10XU
28J
24P3
24S
24X
Industrial
(-40° C to 85° C)
44
ATF750CL-15JU
ATF750CL-15PU
ATF750CL-15SU
ATF750CL-15XU
28J
24P3
24S
24X
Industrial
(-40° C to 85° C)
32. Using “C” Product for Industrial
To use commercial product for industrial ranges, down-grade one speed grade from the Industrial to the Commercial
device (7 ns “X” = 10 ns “U”) and de-rate power by 30%.
Package Type
24D3
24-lead, 0.300" Wide, Non-windowed Ceramic Dual Inline Package (CerDIP)
28J
28-lead, Plastic J-leaded Chip Carrier (PLCC)
28L
28-pad, Non-Windowed Ceramic Leadless Chip Carrier (LCC)
24P3
24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
24S
24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
(1)
24X
Note:
24-lead, 0.173" Wide, Thin Shrink Small Outline (TSSOP)
1. Special order only: TSSOP package requires special thermal management.
17
0776L–PLD–11/08
33. Packaging Information
33.1
24D3 – CerDIP
Dimensions in Millimeters and (Inches).
Controlling dimension: Inches.
MIL-STD 1835 D-9 Config A (Glass Sealed)
32.51(1.280)
31.50(1.240)
PIN
1
7.87(0.310)
7.24(0.285)
27.94(1.100) REF
5.08(0.200)
MAX
0.127(0.005) MIN
SEATING
PLANE
5.08(0.200)
3.18(0.125)
2.45(0.100)BSC
0.46(0.018)
0.20(0.008)
1.65(0.065)
1.14(0.045)
1.52(0.060)
0.38(0.015)
0.66(0.026)
0.36(0.014)
8.13(0.320)
7.37(0.290)
0º~ 15º REF
10.20(0.400) MAX
10/21/03
R
18
2325 Orchard Parkway
San Jose, CA 95131
TITLE
24D3, 24-lead, 0.300" Wide. Non-windowed, Ceramic
Dual Inline Package (Cerdip)
DRAWING NO.
24D3
REV.
B
ATF750C(L)
0776L–PLD–11/08
ATF750C(L)
33.2
28J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
D2/E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AB.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
12.319
–
12.573
D1
11.430
–
11.582
E
12.319
–
12.573
E1
11.430
–
11.582
D2/E2
9.906
–
10.922
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
28J
B
19
0776L–PLD–11/08
33.3
28L – LCC
Dimensions in Millimeters and (Inches).
Controlling dimension: Inches.
MIL-STD 1835 C-4
11.68(0.460)
11.23(0.442)
2.54(0.100)
2.16(0.085)
11.68(0.460)
11.23(0.442)
PIN 1
2.41(0.095)
1.91(0.075)
1.40(0.055)
1.14(0.045)
1.91(0.075)
1.40(0.055)
INDEX CORNER
0.635(0.025)
X 45˚
0.381(0.015)
0.305(0.012)
RADIUS
0.178(0.007)
7.62(0.300) BSC
0.737(0.029)
0.533(0.021)
1.27(0.050) TYP
1.02(0.040) X 45˚
7.62(0.300) BSC
2.16(0.085)
1.65(0.065)
10/21/03
R
20
2325 Orchard Parkway
San Jose, CA 95131
TITLE
28L, 28-pad, Non-windowed, Ceramic Lid, Leadless Chip
Carrier (LCC)
DRAWING NO.
REV.
28L
B
ATF750C(L)
0776L–PLD–11/08
ATF750C(L)
33.4
24P3 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
C
eC
eB
Notes:
1.
2.
This package conforms to JEDEC reference MS-001, Variation AF.
Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
MIN
NOM
MAX
A
–
–
5.334
A1
0.381
–
–
D
31.623
–
32.131
E
7.620
–
8.255
E1
6.096
–
7.112
B
0.356
–
0.559
B1
1.270
–
1.651
L
2.921
–
3.810
C
0.203
–
0.356
eB
–
–
10.922
eC
0.000
–
1.524
SYMBOL
e
NOTE
Note 2
Note 2
2.540 TYP
6/1/04
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
24P3, 24-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
DRAWING NO.
24P3
REV.
D
21
0776L–PLD–11/08
33.5
24S – SOIC
B
D1
D
PIN 1 ID
PIN 1
e
E
A
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
0º ~ 8º
L1
L
SYMBOL
MIN
NOM
MAX
A
–
–
2.65
A1
0.10
–
0.30
D
10.00
–
10.65
D1
7.40
–
7.60
E
15.20
–
15.60
B
0.33
–
0.51
L
0.40
–
1.27
L1
0.23
–
0.32
e
NOTE
1.27 BSC
06/17/2002
R
22
2325 Orchard Parkway
San Jose, CA 95131
TITLE
24S, 24-lead (0.300" body) Plastic Gull Wing Small Outline (SOIC)
DRAWING NO.
REV.
24S
B
ATF750C(L)
0776L–PLD–11/08
ATF750C(L)
33.6
24X – TSSOP
Dimensions in Millimeter and (Inches)*
JEDEC STANDARD MO-153 AD
Controlling dimension: millimeters
0.30(0.012)
0.19(0.007)
4.48(0.176)
6.50(0.256)
4.30(0.169)
6.25(0.246)
PIN 1
0.65(0.0256)BSC
7.90(0.311)
1.20(0.047)MAX
7.70(0.303)
0.15(0.006)
0.05(0.002)
0.20(0.008)
0º ~ 8º
0.09(0.004)
0.75(0.030)
0.45(0.018)
04/11/2001
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
24X, 24-lead (4.4 mm body width) Plastic Thin Shrink Small Outline
Package (TSSOP)
DRAWING NO.
REV.
24X
A
23
0776L–PLD–11/08
34. Revision History
Revision Level – Release Date
History
K – July 2007
Added military-grade devices.
Added fully-green RoHS-compliant devices in select speed grades and packages.
L – November 2008
Removed commercial grade leaded package options.
24
ATF750C(L)
0776L–PLD–11/08
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Atmel Asia
Unit 1-5 & 16, 19/F
BEA Tower, Millennium City 5
418 Kwun Tong Road
Kwun Tong, Kowloon
Hong Kong
Tel: (852) 2245-6100
Fax: (852) 2722-1369
Atmel Europe
Le Krebs
8, Rue Jean-Pierre Timbaud
BP 309
78054 Saint-Quentin-enYvelines Cedex
France
Tel: (33) 1-30-60-70-00
Fax: (33) 1-30-60-71-11
Atmel Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Technical Support
[email protected]
Sales Contact
www.atmel.com/contacts
Product Contact
Web Site
www.atmel.com
Literature Requests
www.atmel.com/literature
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0776L–PLD–11/08
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