ATA8401 - Complete

ATA8401
UHF ASK/FSK Industrial Transmitter
DATASHEET
Features
● Integrated PLL loop filter
● ESD protection (3kV HBM/150V MM)
● High output power (8.0dBm) with low supply current (9.0mA)
● Modulation scheme ASK/FSK
● FSK modulation is achieved by connecting an additional capacitor between the
XTAL load capacitor and the open drain output of the modulating microcontroller
● Easy to design-in due to excellent isolation of the PLL from the PA and power
supply
● Single Li-cell for power supply
● Supply voltage 2.0V to 4.0V in the temperature range of –40°C to +85°C
● Package TSSOP8L
● Single-ended antenna output with high efficient power amplifier
● CLK output for clocking the microcontroller
● One-chip solution with minimum external circuitry
Applications
● Industrial/aftermarket remote keyless entry systems
● Alarm, telemetering, and energy metering systems
● Remote control systems for consumer and industrial markets
● Access control systems
● Home automation
● Home entertainment
● Toys
4984H-INDCO-08/15
1.
Description
The Atmel® ATA8401 is a PLL transmitter IC, which has been developed for the demands of RF low-cost transmission
systems for industrial applications at data rates up to 50kBaud ASK and 32kBaud FSK modulation scheme. The transmitting
frequency range is 300MHz to 350MHz. It can be used in both FSK and ASK systems.
Figure 1-1. System Block Diagram
UHF ASK/FSK
Remote control transmitter
UHF ASK/FSK
Remote control receiver
1 Li cell
Atmel
ATA8401
Keys
Encoder
ATARx9x
Atmel
ATA8201
ATA8203
XTO
4984H–INDCO–08/15
IF Amp
Antenna
VCO
LNA
ATA8401 [DATASHEET]
Control
PLL
Antenna
2
1 to 3
Demod
PLL
LNA
VCO
XTO
Microcontroller
2.
Pin Configuration
Figure 2-1. Pinning TSSOP8L
CLK
PA_ENABLE
ANT2
ANT1
Table 2-1.
Pin
ATA8401
1
8
2
7
3
6
4
5
ENABLE
GND
VS
XTAL
Pin Description
Symbol
Function
Configuration
VS
1
CLK
Clock output signal for microcontroller
The clock output frequency is set by
the crystal to fXTAL/4
100Ω
CLK
100Ω
PA_ENABLE
2
PA_ENABLE
UREF = 1.1V
50kΩ
Switches on power amplifier used for
ASK modulation
20μA
ANT1
3
ANT2
Emitter of antenna output stage
4
ANT1
Open collector antenna output
ANT2
ATA8401 [DATASHEET]
4984H–INDCO–08/15
3
Table 2-1.
Pin
Pin Description (Continued)
Symbol
Function
Configuration
VS
1.5kΩ
5
XTAL
VS
1.2kΩ
Connection for crystal
XTAL
182μA
6
VS
7
GND
8
ENABLE
Supply voltage
See ESD protection circuitry (see Figure 4-5 on page 8)
Ground
See ESD protection circuitry (see Figure 4-5 on page 8)
ENABLE
Enable input
200kΩ
Figure 2-2. Block Diagram
Atmel
ATA8401
Power up/down
f
CLK
ENABLE
4
1
8
f
32
PA_ENABLE
GND
2
7
PDF
CP
ANT2
VS
3
6
LF
ANT1
4
PA
VCO
PLL
4
ATA8401 [DATASHEET]
4984H–INDCO–08/15
XTO
5
XTAL
3.
General Description
This fully integrated PLL transmitter allows particularly simple, low-cost RF miniature transmitters to be assembled. The
VCO is locked to 32 fXTAL, and therefore a 9.8438MHz crystal is needed for a 315MHz transmitter. All other PLL and VCO
peripheral elements are integrated.
The XTO is a series resonance oscillator so that only one capacitor together with a crystal connected in series to GND are
needed as external elements.
The crystal oscillator together with the PLL typically needs < 3ms until the PLL is locked and the CLK output is stable. There
is a wait time of ≥ 3ms until the CLK is used for the microcontroller and the PA is switched on.
The power amplifier is an open-collector output delivering a current pulse, which is nearly independent from the load
impedance. The delivered output power is therefore controllable via the connected load impedance.
This output configuration enables a simple matching to any kind of antenna or to 50. A high power efficiency of
 = Pout/(IS,PA VS) of 40% for the power amplifier results when an optimized load impedance of ZLoad = (255 + j192) is used
at 3V supply voltage.
4.
Functional Description
If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode, consuming only a very small amount of current, so
that a lithium cell used as power supply can work for several years.
With ENABLE = H the XTO, PLL, and the CLK driver are switched on. If PA_ENABLE remains L, only the PLL and the XTO
are running, and the CLK signal is delivered to the microcontroller. The VCO locks to 32 times the XTO frequency.
With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver, and the power amplifier are on. The power amplifier can
be switched on and off with PA_ENABLE. This is used to perform the ASK modulation.
4.1
ASK Transmission
The Atmel® ATA8401 is activated by ENABLE = H. PA_ENABLE must remain L for typically ≥ 3 ms, then the CLK signal can
be taken to clock the microcontroller and the output power can be modulated by means of the PA_ENABLE pin. After
transmission, PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The Atmel ATA8401
is switched back to standby mode with ENABLE = L.
4.2
FSK Transmission
The Atmel ATA8401 is activated by ENABLE = H. PA_ENABLE must remain L for typically ≥ 3ms, then the CLK signal can
be taken to clock the microcontroller, and the power amplifier is switched on with PA_ENABLE = H. The chip is then ready
for FSK modulation. The microcontroller starts to switch on and off the capacitor between the XTAL load capacitor and GND
with an open-drain output port, thus changing the reference frequency of the PLL. If the switch is closed, the output
frequency is lower than if the switch is open. After transmission, PA_ENABLE is switched to L, and the microcontroller
switches back to internal clocking. The Atmel ATA8401 is switched back to standby mode with ENABLE = L.
The accuracy of the frequency deviation with XTAL pulling method is about ±25% when the following tolerances are
considered.
Figure 4-1. Tolerances of Frequency Modulation
VS
CStray1
CStray2
LM
C4
XTAL
CM
RS
C0
Crystal equivalent circuit
C5
CSwitch
Using C4 = 8.2pF ±5%, C5 = 10pF ±5%, a switch port with CSwitch = 3pF ±10%, stray capacitances on each side of the crystal
of CStray1 = CStray2 = 1pF ±10%, a parallel capacitance of the crystal of C0 = 3.2pF ±10%, and a crystal with CM = 13 fF ±10%,
typically results in an FSK deviation of ±21.5kHz with worst case tolerances of ±16.25kHz to ±28.01kHz.
ATA8401 [DATASHEET]
4984H–INDCO–08/15
5
4.3
CLK Output
An output CLK signal is provided for a connected microcontroller. The delivered signal is CMOS compatible if the load
capacitance is lower than 10pF.
4.3.1
Clock Pulse Take-over
The clock of the crystal oscillator can be used for clocking the microcontroller. A special feature of Atmel®’s AVR® is that it
starts with an integrated RC-oscillator to switch on the Atmel ATA8401 with ENABLE = H, and after 3ms assumes the clock
signal of the transmission IC, so that the message can be sent with crystal accuracy.
4.3.2
Output Matching and Power Setting
The output power is set by the load impedance of the antenna. The maximum output power is achieved with a load
impedance of ZLoad,opt = (255 + j192). There must be a low resistive path to VS to deliver the DC current.
The delivered current pulse of the power amplifier is 9mA. The maximum output power is delivered to a resistive load of
400 if the 1.0pF output capacitance of the power amplifier is compensated by the load impedance.
An optimum load impedance of:
ZLoad = 400 || j/(2   1.0pF) = (255 + j192) thus results for the maximum output power of 8 dBm.
The load impedance is defined as the impedance seen from the Atmel ATA8401’s ANT1, ANT2 into the matching network.
Do not confuse this large signal load impedance with a small signal input impedance delivered as input characteristic of RF
amplifiers and measured from the application into the IC instead of from the IC into the application for a power amplifier.
Less output power is achieved by lowering the real parallel part of 400 where the parallel imaginary part should be kept
constant.
Output power measurement can be done with the circuit shown in Figure 4-2. Note that the component values must be
changed to compensate for the individual board parasitics until the Atmel ATA8401 has the right load impedance
ZLoad,opt = (255 + j192). Also the damping of the cable used to measure the output power must be calibrated out.
Figure 4-2. Output Power Measurement at f = 315MHz
VS
C1
1nF
L1
56nH
C2
ANT1
ZLopt
3.3pF
ANT2
Note:
4.4
Z = 50Ω
Power
meter
Rin
50Ω
For 345MHz C2 has to be changed to 2.7pF
Application Circuit
A value of C3 = 68nF/X7R is recommended for the supply-voltage blocking capacitor C3 (see Figure 4-3 on page 7 and
Figure 4-4 on page 8). C1 and C2 are used to match the loop antenna to the power amplifier where C1 typically is 22pF/NP0
and C2 is 10.8pF/NP0 (18pF + 27pF in series). For C2, two capacitors in series should be used to achieve a better tolerance
value and to have the possibility of realizing the ZLoad,opt using standard valued capacitors.
C1, together with the pins of Atmel ATA8401 and the PCB board wires, forms a series resonance loop that suppresses the
1st harmonic. Therefore, the position of C1 on the PCB is important. Normally the best suppression is achieved when C1 is
placed as close as possible to the pins ANT1 and ANT2.
The loop antenna should not exceed a width of 1.5mm, otherwise the Q-factor of the loop antenna is too high.
L1 ([50nH to 100nH) can be printed on PCB. C4 should be selected so that the XTO runs on the load resonance
frequency of the crystal. Normally, a 15pF load-capacitance crystal results in a value of 12pF.
6
ATA8401 [DATASHEET]
4984H–INDCO–08/15
Figure 4-3. ASK Application Circuit
S1
S2
VDD
Atmel AVR
(ATtiny)
BPXY
VS
1
VSS
BPXY
20
BPXY
BPXY
OSC1
7
Atmel
ATA8401
Power up/down
CLK
ENABLE
f
4
1
8
f
32
PA_ENABLE
GND
2
7
PDF
C3
C2
CP
ANT2
VS
3
6
VS
Loop
Antenna
LF
C1
ANT1
XTAL
4
PA
VCO
PLL
L1
XTO
XTAL
5
C4
VS
ATA8401 [DATASHEET]
4984H–INDCO–08/15
7
Figure 4-4. FSK Application Circuit
S1
S2
VDD
Atmel AVR
(ATtiny)
BPXY
VS
1
VSS
BPXY
20
BP42/T2O
BPXY
18
BPXY
OSC1
7
Atmel
ATA8401
Power up/down
CLK
ENABLE
f
4
1
8
f
32
PA_ENABLE
GND
2
7
PDF
C3
CP
C2
ANT2
VS
6
3
Loop
Antenna
LF
C1
VS
C5
ANT1
XTAL
4
PA
VCO
XTO
XTAL
5
PLL
L1
C4
VS
Figure 4-5. ESD Protection Circuit
VS
ANT1
CLK
GND
8
ATA8401 [DATASHEET]
4984H–INDCO–08/15
PA_ENABLE
ANT2
XTAL
ENABLE
5.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Minimum
Maximum
Unit
Supply voltage
VS
5
V
Power dissipation
Ptot
100
mW
Junction temperature
Tj
150
°C
Storage temperature
Tstg
–55
+85
°C
Ambient temperature
Tamb
–55
+85
Input voltage
VmaxPA_ENABLE
–0.3
Note:
1. If VS + 0.3 is higher than 3.7V, the maximum voltage will be reduced to 3.7V.
6.
(VS + 0.3)
V
Thermal Resistance
Parameters
Junction ambient
7.
°C
(1)
Symbol
Value
Unit
RthJA
170
K/W
Electrical Characteristics
VS = 2.0V to 4.0V, Tamb = 25°C unless otherwise specified.
Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 7).
Parameters
Test Conditions
Supply current
Power down,
VENABLE < 0.25V, –40°C to 85°C
VPA-ENABLE < 0.25V, 25°C
(100% correlation tested)
Supply current
Symbol
Min.
Typ.
Max.
Unit
350
nA
nA
IS_Off
< 10
Power up, PA off, VS = 3V,
VENABLE > 1.7V, VPA-ENABLE < 0.25V
IS
3.7
4.8
mA
Supply current
Power up, VS = 3.0V,
VENABLE > 1.7V, VPA-ENABLE > 1.7V
IS_Transmit
9
11.6
mA
Output power
VS = 3.0V, Tamb = 25°C,
f = 315 MHz, ZLoad = (255 + j192)W
8.0
10.5
dBm
Output power variation for the full
temperature range
Tamb = 25°C,
VS = 3.0V
VS = 2.0V
PRef
PRef
–1.5
–4.0
dB
dB
Output power variation for the full
temperature range
Tamb = 25°C,
VS = 3.0V
VS = 2.0V,
POut = PRef + PRef
PRef
PRef
–2.0
–4.5
dB
dB
Achievable output-power range
Selectable by load impedance
8.0
dBm
PRef
POut_typ
fCLK = f0/128
Load capacitance at pin CLK = 10pF
Spurious emission
fO ±1  fCLK
fO ±4  fCLK
Other spurious are lower
Note:
1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V.
6.0
0
–55
–52
ATA8401 [DATASHEET]
4984H–INDCO–08/15
dBc
dBc
9
7.
Electrical Characteristics (Continued)
VS = 2.0V to 4.0V, Tamb = 25°C unless otherwise specified.
Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 7).
Parameters
Test Conditions
Oscillator frequency XTO
(= phase comparator frequency)
fXTO = f0/32
fXTAL = resonant frequency of the XTAL,
CM ≤ 10fF, load capacitance selected
accordingly
Tamb = 25°C
Symbol
Min.
fXTO
PLL loop bandwidth
Typ.
Max.
Unit
fXTAL
ppm
250
kHz
Phase noise of phase comparator
Referred to fPC = fXT0,
25kHz distance to carrier
–116
–110
dBc/Hz
In-loop phase noise PLL
25kHz distance to carrier
–86
–80
dBc/Hz
Phase noise VCO
At 1MHz
At 36MHz
–94
–125
–90
–121
dBc/Hz
dBc/Hz
350
MHz
Frequency range of VCO
fVCO
300
Clock output frequency (CMOS
microcontroller compatible)
Voltage swing at pin CLK
f0/128
CLoad ≤ 10pF
Series resonance R of the crystal
V0h
V0l
VS  0.8
Rs
Capacitive load at pin XT0
MHz
VS  0.2
V
V
110

7
pF
FSK modulation frequency rate
Duty cycle of the modulation signal =
50%
0
32
kHz
ASK modulation frequency rate
Duty cycle of the modulation signal =
50%
0
50
kHz
Low level input voltage
High level input voltage
Input current high
0.25
ENABLE input
20
V
V
µA
0.25
VS(1)
5
V
V
µA
VIl
VIh
IIn
Low level input voltage
VIl
PA_ENABLE input
VIh
High level input voltage
IIn
Input current high
Note:
1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V.
10
ATA8401 [DATASHEET]
4984H–INDCO–08/15
1.7
1.7
Ordering Information
Extended Type Number
Package
MOQ
ATA8401C-6AQY-66
TSSOP8L
5000 pcs
Taped and reeled, Pb-free
Package Information
3±0.1
0.1±0.05
3±0.1
+0.06
0.31-0.07
0.65 nom.
+0.0
0.85±0.05
+0.05
Dimensions in mm
1-0.15
9.
Remarks
0.15-0.025
8.
3.8±0.3
4.9±0.1
3 x 0.65 = 1.95 nom.
8
5
technical drawings
according to DIN
specifications
1
4
03/15/04
TITLE
Package Drawing Contact:
[email protected]
Package: TSSOP 8L
GPC
DRAWING NO.
REV.
6.543-5083.01-4
2
ATA8401 [DATASHEET]
4984H–INDCO–08/15
11
10.
Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No.
History
4984H-INDCO-08/15
Section 8 “Ordering Information” on page 11 updated
4984G-INDCO-07/14
Put document in the latest template
4984F-INDCO-08/12
Features on page 1 changed
4984E-INDCO-03/12
4984D-INDCO-12/10
Features on page 1 changed
Section 8 “Ordering Information” on page 11 changed
Section 1 “Description” on page 1 changed
Section 7 “Electrical Characteristics” on page 10 changed
Section 4.3.1 “Clock Pulse Take-over” on page 5 changed
4984C-INDCO-04/09
Figure 4-3 “ASK Application Circuit” on page 7 changed
Figure 4-4 “FSK Application Circuit” on page 8 changed
4984B-INDCO-11/08
12
ATA8401 [DATASHEET]
4984H–INDCO–08/15
Put document in the latest template
Section 4.3.1 “Clock Pulse Take-over” on page 5 changed
XXXXXX
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© 2014 Atmel Corporation. / Rev.: 4984H–INDCO–08/15
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