ATWINC1500B-MU IEEE 802.11 b/g/n Network Controller SoC DATASHEET Description Atmel® ATWINC1500B is a single chip IEEE® 802.11 b/g/n Radio/Baseband/MAC network controller optimized for low-power mobile applications. ATWINC1500B supports single stream 1x1 802.11n mode providing up to 72Mbps PHY rate. ATWINC1500B features fully integrated Power Amplifier, LNA, Switch, and Power Management. ATWINC1500B also features an on-chip microcontroller and integrated Flash memory for system software. Implemented in 65nm CMOS technology, the ATWINC1500B offers very low power consumption while simultaneously providing high performance and minimal bill of materials. The ATWINC1500B supports 2- and 3-wire Bluetooth® coexistence protocols. The ATWINC1500B provides multiple peripheral interfaces including UART, SPI, I2C the only external clock source needed for the ATWINC1500B is a high-speed crystal or oscillator with a wide range of reference clock frequencies supported (12-40MHz). The ATWINC1500B is available in QFN packaging. Features IEEE 802.11 b/g/n 20MHz (1x1) solution Single spatial stream in 2.4GHz ISM band Integrated PA and T/R Switch Superior Sensitivity and Range via advanced PHY signal processing Advanced Equalization and Channel Estimation Advanced Carrier and Timing Synchronization Wi-Fi Direct and Soft-AP support Supports IEEE 802.11 WEP, WPA, and WPA2 Security Supports China WAPI security Superior MAC throughput via hardware accelerated two-level A-MSDU/AMPDU frame aggregation and block acknowledgement On-chip memory management engine to reduce host load Integrated Flash memory for system software SPI, UART, and I2C host interfaces 2- or 3-wire Bluetooth coexistence interface Operating temperature range of -40°C to +85°C Power save modes: – <4µA Power Down mode typical @3.3V I/O Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 – 380uA Doze mode with chip settings preserved (used for beacon monitoring) – On-chip low power sleep oscillator – Fast host wake-up from Doze mode by a pin or host I/O transaction Fast boot options: – On-Chip Boot ROM (firmware instant boot) – SPI Flash boot (firmware patches and state variables) – Low-leakage on-chip memory for state variables – Fast AP re-association (150ms) On-Chip Network Stack to offload MCU: – Integrated Network IP stack to minimize host CPU requirements – Network features: TCP, UDP, DHCP, ARP, HTTP, SSL, and DNS Hardware accelerators for Wi-Fi and SSL security to improve connection time Hardware accelerator for IP checksum Hardware accelerators for OTA security 2 Atmel ATWINC1500B-MU [DATASHEET] 2 Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 Ta bl e of Conte nts 1 Ordering Information and IC Marking ........................................................................ 5 2 Block Diagram ............................................................................................................. 5 3 Pinout and Package Information ................................................................................ 6 3.1 3.2 4 Electrical Specifications ............................................................................................. 9 4.1 4.2 4.3 5 7.2 7.3 MAC 7.1.1 7.1.2 PHY 7.2.1 7.2.2 Radio 7.3.1 7.3.2 13 Features ................................................................................................................................. 13 Description.............................................................................................................................. 13 14 Features ................................................................................................................................. 14 Description.............................................................................................................................. 14 14 Receiver Performance ............................................................................................................ 14 Transmitter Performance ........................................................................................................ 16 External Interfaces .................................................................................................... 17 8.1 8.2 8.3 8.4 8.5 8.6 9 Processor ............................................................................................................................................ 12 Memory Subsystem............................................................................................................................. 12 Non-volatile Memory (eFuse) .............................................................................................................. 12 WLAN Subsystem ...................................................................................................... 13 7.1 8 Crystal Oscillator ................................................................................................................................. 10 Low Power Oscillator........................................................................................................................... 11 CPU and Memory Subsystems ................................................................................. 12 6.1 6.2 6.3 7 Absolute Ratings ................................................................................................................................... 9 Recommended Operating Conditions ................................................................................................... 9 DC Electrical Characteristics ............................................................................................................... 10 Clocking 10 5.1 5.2 6 Pin Description ...................................................................................................................................... 6 Package Description ............................................................................................................................. 8 I2C Slave Interface .............................................................................................................................. 17 I2C Master Interface ............................................................................................................................ 19 SPI Slave Interface.............................................................................................................................. 19 UART 22 Wi-Fi/Bluetooth Coexistence ............................................................................................................... 23 GPIOs 23 Power Management ................................................................................................... 24 9.1 9.2 9.3 9.4 Power Architecture .............................................................................................................................. 24 Power Consumption ............................................................................................................................ 25 9.2.1 Description of Device States................................................................................................... 25 9.2.2 Current Consumption in Various Device States...................................................................... 25 9.2.3 Restrictions for Power States ................................................................................................. 26 Power-Up/Down Sequence ................................................................................................................. 26 Digital I/O Pin Behavior during Power-Up Sequences......................................................................... 28 Atmel ATWINC1500B-MU [DATASHEET] Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 3 3 10 Reference Design ...................................................................................................... 29 10.1 Reference Schematic .......................................................................................................................... 29 10.2 Reference BOM .................................................................................................................................. 30 11 Reflow Profile Information ........................................................................................ 31 11.1 Storage Condition................................................................................................................................ 31 11.1.1 Moisture Barrier Bag Before Opened ..................................................................................... 31 11.1.2 Moisture Barrier Bag Open ..................................................................................................... 31 11.2 Stencil Design ..................................................................................................................................... 31 11.3 Baking Conditions ............................................................................................................................... 31 11.4 Soldering and Reflow Condition .......................................................................................................... 31 11.4.1 Reflow Oven ........................................................................................................................... 31 12 Reference Documentation and Support................................................................... 33 12.1 Reference Documents......................................................................................................................... 33 13 Revision History ........................................................................................................ 34 4 Atmel ATWINC1500B-MU [DATASHEET] 4 Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 1 Ordering Information and IC Marking Table 1-1. Ordering Details Atmel official part number (for ordering) ATWINC1500B-MU 2 Package Type IC Marking 5x5 QFN in Tape and Reel ATWINC1500B Block Diagram Figure 2-1. ATWINC1500B Block Diagram Vbatt SDIO SPI I2C UART x2 Bluetooth Coexistance RTC Clock PMU XO GPIO WINC1500B Host Interface 802.11bgn Forward Error Correction Microcontroller 802.11bgn OFDM Channel Estimation / Equalization Rx Digital Core 802.11bgn MAC Flash PLL RAM 802.11bgn Coding 802.11bgn iFFT X ADC ~ Tx Digital Core DPD DAC X Atmel ATWINC1500B-MU [DATASHEET] Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 5 5 3 Pinout and Package Information 3.1 Pin Description ATWINC1500B is offered in an exposed pad 40-pin QFN package. This package has an exposed paddle that must be connected to the system board ground. The QFN package pin assignment is shown in Figure 3-1. The color shading is used to indicate the pin type as follows: Green – power Red – analog Blue – digital I/O Yellow – digital input Grey – unconnected or reserved The ATWINC1500B pins are described in Table 3-1. Figure 3-1. Pin Assignment Table 3-1. Pin Description Pin # 6 Pin Name Pin Type Description 1 TP_P Analog Test Pin/Customer No Connect 2 VDD_RF_RX Power Tuner RF Supply (see Section 9.1) 3 VDD_AMS Power Tuner BB Supply (see Section 9.1) 4 VDD_RF_TX Power Tuner RF Supply (see Section 9.1) 5 VDD_BATT_PPA Power PA 1st Stage Supply (see Section 9.1) 6 VDD_BATT_PA Power PA 2nd Stage Supply (see Section 9.1) Atmel ATWINC1500B-MU [DATASHEET] 6 Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 Pin # Pin Name Pin Type Description 7 RFIOP Analog Pos RF Differential I/O 8 RFION Analog Neg. RF Differential I/O 9 SDIO_SPI_CFG Digital Input Tie to 1 for SPI, 0 for SDIO 10 GPIO0/HOST_WAKE Digital I/O, Programmable Pull-Up GPIO0/SLEEP Mode Control 11 GPIO2/IRQN Digital I/O, Programmable Pull-Up GPIO2/Device Interrupt 12 SD_DAT3 Digital I/O, Programmable Pull-Up SDIO Data3 13 SD_DAT2/SPI_RXD Digital I/O, Programmable Pull-Up SDIO Data2/SPI Data RX 14 VDDC Power Digital Core Power Supply (see Section 9.1) 15 VDDIO Power Digital I/O Power Supply (see Section 9.1) 16 SD_DAT1/SPI_SSN Digital I/O, Programmable Pull-Up SDIO Data1/SPI Slave Select 17 SD_DAT0/SPI_TXD Digital I/O, Programmable Pull-Up SDIO Data0/SPI Data TX 18 SD_CMD/SPI_SCK Digital I/O, Programmable Pull-Up SDIO Command/SPI Clock 19 SD_CLK Digital I/O, Programmable Pull-Up SDIO Clock 20 VBATT_BUCK Power Battery Supply for DC/DC Converter (see Section 9.1) 21 VSW Power Switching output of DC/DC Converter (see Section 9.1) 22 VREG_BUCK Power Core Power from DC/DC Converter (see Section 9.1) 23 CHIP_EN Analog PMU Enable 24 GPIO1/RTC_CLK Digital I/O, Programmable Pull-Up GPIO1/32kHz Clock Input 25 TEST_MODE Digital Input Test Mode – Customer Tie to GND 26 VDDIO Power Digital I/O Power Supply (see Section 9.1) 27 VDDC Power Digital Core Power Supply (see Section 9.1) 28 GPIO3 Digital I/O, Programmable Pull-Up GPIO3 29 GPIO4 Digital I/O, Programmable Pull-Up GPIO4 30 GPIO5 Digital I/O, Programmable Pull-Up GPIO5 31 GPIO6 Digital I/O, Programmable Pull-Up GPIO6 32 I2C_SCL Digital I/O, Programmable Pull-Up I2C Slave Clock (high-drive pad, see Table 4-3) 33 I2C_SDA Digital I/O, Programmable Pull-Up I2C Slave Data (high-drive pad, see Table 4-3) 34 RESETN Digital Input Active-Low Hard Reset 35 XO_N Analog Crystal Oscillator N 36 XO_P Analog Crystal Oscillator P 37 VDD_SXDIG Power SX Power Supply (see Section 9.1) 38 VDD_VCO Power VCO Power Supply (see Section 9.1) 39 VDDIO_A Power Tuner VDDIO Power Supply (see Section 9.1) 40 TP_N Analog Test Pin/Customer No Connect 41 PADDLE VSS Power Connect to System Board Ground Atmel ATWINC1500B-MU [DATASHEET] Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 7 7 3.2 Package Description The ATWINC1500B QFN package information is provided in Table 3-2. Table 3-2. QFN Package Information Parameter Value Units Tolerance Package Size 5x5 mm ±0.1mm QFN Pad Count 40 Total Thickness 0.85 QFN Pad Pitch 0.40 Pad Width 0.20 Exposed Pad size 3.7x3.7 ±0.05mm mm mm The ATWINC1500B 40L QFN package view is shown in Figure 3-2. Figure 3-2. QFN Package The QFN package is a qualified Green Package. 8 Atmel ATWINC1500B-MU [DATASHEET] 8 Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 4 Electrical Specifications 4.1 Absolute Ratings Table 4-1. Absolute Maximum Ratings Characteristic Symbol Min. Max. Core Supply Voltage VDDC -0.3 1.5 I/O Supply Voltage VDDIO -0.3 5.0 Battery Supply Voltage VBATT -0.3 5.0 Digital Input Voltage VIN -0.3 VDDIO Analog Input Voltage VESDHBM -0.3 1.5 -1000, -2000 (see notes below) +1000, +2000 (see notes below) -65 150 ESD Human Body Model Storage Temperature TA Unit V ºC Junction Temperature 125 RF input power max 23 Notes: 1. 2. 3. 4.2 dBm VIN corresponds to all the digital pins. VAIN corresponds to the following analog pins: VDD_RF_RX, VDD_RF_TX, VDD_AMS, RFIOP, RFION, XO_N, XO_P, VDD_SXDIG, VDD_VCO. For VESDHBM, each pin is classified as Class 1, or Class 2, or both: The Class 1 pins include all the pins (both analog and digital) The Class 2 pins are all digital pins only VESDHBM is ±1kV for Class1 pins. VESDHBM is ±2kV for Class2 pins Recommended Operating Conditions Table 4-2. Recommended Operating Conditions Characteristics Symbol Min. Typ. Max. Unit V I/O Supply Voltage VDDIO 2.7 3.3 3.6 Battery Supply Voltage VBATT 3.0 3.6 4.2 Operating Temperature Notes: 1. 2. 3. -40 85 ºC I/O supply voltage is applied to the following pins: VDDIO_A, VDDIO. Battery supply voltage is applied to following pins: VDD_BATT_PPA, VDD_BATT_PA, VBATT_BUCK. Refer to Section 9.1 and Table 9-3 for the details of power connections. Atmel ATWINC1500B-MU [DATASHEET] Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 9 9 4.3 DC Electrical Characteristics Table 4-3 provides the DC characteristics for the ATWINC1500B digital pads. Table 4-3. Electrical Characteristics Characteristic Min. Typ. Max. Input Low Voltage VIL -0.30 0.65 Input High Voltage VIH VDDIO-0.60 VDDIO+0.30 Unit V Output Low Voltage VOL 0.45 Output High Voltage VOH VDDIO-0.50 Output Loading 20 Digital Input Load 6 pF Pad Drive Strength (regular pads1) Pad Drive Strength (high-drive Note: 1. 8 13.5 16 27 mA The following are high-drive pads: I2C_SCL, I2C_SDA; all other pads are regular. 5 Clocking 5.1 Crystal Oscillator Table 5-1. pads1) Crystal Oscillator Parameters Parameter Crystal Resonant Frequency Min. Typ. Max. Unit 12 26 40 MHz 50 150 Ω Crystal Equivalent Series Resistance Stability – Initial Offset1 -100 100 Stability - Temperature and Aging -25 25 ppm Note: 1. Initial offset must be calibrated to maintain ±25ppm in all operating conditions. This calibration is performed during final production testing. The block diagram in Figure 5-1(a) shows how the internal Crystal Oscillator (XO) is connected to the external crystal. The XO has 5pF internal capacitance on each terminal XO_P and XO_N. To bypass the crystal oscillator with an external reference, an external signal capable of driving 5pF can be applied to the XO_N terminal as shown Figure 5-1(b). 10 Atmel ATWINC1500B-MU [DATASHEET] 1 Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 0 Figure 5-1. XO Connections External Clock XO_N XO_P XO_N XO_P ATWINC1500B ATWINC1500B (a) (b) (a) Crystal Oscillator is Used (b) Crystal Oscillator is Bypassed Table 5-2 specifies the electrical and performance requirements for the external clock. Table 5-2. Bypass Clock Specification Parameter Min. Max. Unit Comments Oscillation frequency 12 32 MHz Must be able to drive 5pF load @ desired frequency Voltage swing 0.5 1.2 Vpp Must be AC coupled Stability – Temperature and Aging -25 +25 ppm -130 dBc/Hz Phase Noise Jitter(RMS) 5.2 <1psec At 10kHz offset Based on integrated phase noise spectrum from 1kHz to 1MHz Low Power Oscillator ATWINC1500B has an internally-generated 32kHz clock to provide timing information for various sleep functions. Alternatively, ATWINC1500B allows for an external 32kHz clock to be used for this purpose, which is provided through Pin 24 (RTC_CLK). Software selects whether the internal clock or external clock is used. The internal low-power clock is ring-oscillator based and has accuracy within 10,000ppm. When using the internal low-power clock, the advance wakeup time in beacon monitoring mode has to be increased by about 1% of the sleep time to compensate for the oscillator inaccuracy. For example, for the DTIM interval value of 1, wakeup time has to be increased by 1ms. For any application targeting very low power consumption, an external 32kHz RTC clock should be used. Atmel ATWINC1500B-MU [DATASHEET] Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 11 1 1 6 CPU and Memory Subsystems 6.1 Processor ATWINC1500B has a Cortus APS3 32-bit processor. This processor performs many of the MAC functions, including but not limited to association, authentication, power management, security key management, and MSDU aggregation/de-aggregation. In addition, the processor provides flexibility for various modes of operation, such as STA and AP modes. 6.2 Memory Subsystem The APS3 core uses a 128KB instruction/boot ROM along with a 160KB instruction RAM and a 64KB data RAM. ATWINC1500B also has 4Mb of Flash memory, which can be used for system software. In addition, the device uses a 128KB shared RAM, accessible by the processor and MAC, which allows the APS3 core to perform various data management tasks on the TX and RX data packets. 6.3 Non-volatile Memory (eFuse) ATWINC1500B has 768 bits of non-volatile eFuse memory that can be read by the CPU after device reset. This non-volatile one-time-programmable (OTP) memory can be used to store customer-specific parameters, such as MAC address; various calibration information, such as TX power, crystal frequency offset, etc.; and other software-specific configuration parameters. The eFuse is partitioned into six 128-bit banks. Each bank has the same bit map, which is shown in Figure 6-1. The purpose of the first 80 bits in each bank is fixed, and the remaining 48 bits are general-purpose software dependent bits, or reserved for future use. Since each bank can be programmed independently, this allows for several updates of the device parameters following the initial programming, e.g. updating MAC address. Refer to ATWINC1500B Programming Guide for the eFuse programming instructions. Flags 8 Bank 0 F 48 MAC ADDR 8 G 16 FO Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 128 Bits 12 Atmel ATWINC1500B-MU [DATASHEET] 1 Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 2 1 15 Freq. Offset 7 Used 1 TX Gain Correc tion 1 Used 4 MAC ADDR Used 3 Reserved 1 Invalid Used 1 eFuse Bit Map Version Figure 6-1. 7 WLAN Subsystem The WLAN subsystem is composed of the Media Access Controller (MAC) and the Physical Layer (PHY). The following two subsections describe the MAC and PHY in detail. 7.1 MAC 7.1.1 Features The ATWINC1500B IEEE 802.11 MAC supports the following functions: IEEE 802.11b/g/n IEEE 802.11e WMM QoS EDCA/PCF multiple access categories traffic scheduling Advanced IEEE 802.11n features: 7.1.2 – Transmission and reception of aggregated MPDUs (A-MPDU) – Transmission and reception of aggregated MSDUs (A-MSDU) – Immediate Block Acknowledgement – Reduced Interframe Spacing (RIFS) Support for IEEE 802.11i and WFA security with key management – WEP 64/128 – WPA-TKIP – 128-bit WPA2 CCMP (AES) Support for WAPI security Advanced power management – Standard 802.11 Power Save Mode – Wi-Fi Alliance WMM-PS (U-APSD) RTS-CTS and CTS-self support Supports either STA or AP mode in the infrastructure basic service set mode Supports independent basic service set (IBSS) Description The ATWINC1500B MAC is designed to operate at low power while providing high data throughput. The IEEE 802.11 MAC functions are implemented with a combination of dedicated datapath engines, hardwired control logic, and a low-power, high-efficiency microprocessor. The combination of dedicated logic with a programmable processor provides optimal power efficiency and real-time response while providing the flexibility to accommodate evolving standards and future feature enhancements. Dedicated datapath engines are used to implement data path functions with heavy computational requirements. For example, an FCS engine checks the CRC of the transmitting and receiving packets, and a cipher engine performs all the required encryption and decryption operations for the WEP, WPA-TKIP, WPA2 CCMP-AES, and WAPI security requirements. Control functions which have real-time requirements are implemented using hardwired control logic modules. These logic modules offer real-time response while maintaining configurability via the processor. Examples of hardwired control logic modules are the channel access control module (implements EDCA/HCCA, Beacon TX control, interframe spacing, etc.), protocol timer module (responsible for the Network Access Vector, back-off timing, timing synchronization function, and slot management), MPDU handling module, aggregation/deaggregation module, block ACK controller (implements the protocol requirements for burst block communication), and TX/RX control FSMs (coordinate data movement between PHY-MAC interface, cipher engine, and the DMA interface to the TX/RX FIFOs). Atmel ATWINC1500B-MU [DATASHEET] Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 13 1 3 The MAC functions implemented solely in software on the microprocessor have the following characteristics: Functions with high memory requirements or complex data structures. Examples are association table management and power save queuing. Functions with low computational load or without critical real-time requirements. Examples are authentication and association. Functions which need flexibility and upgradeability. Examples are beacon frame processing and QoS scheduling. 7.2 PHY 7.2.1 Features The ATWINC1500B IEEE802.11 PHY supports the following functions: 7.2.2 Single antenna 1x1 stream in 20MHz channels Supports IEEE 802.11b DSSS-CCK modulation: 1, 2, 5.5, 11Mbps Supports IEEE 802.11g OFDM modulation: 6, 9, 12,18, 24, 36, 48, 54Mbps Supports IEEE 802.11n HT modulations MCS0-7, 20MHz, 800 and 400ns guard interval: 6.5, 7.2, 13.0, 14.4, 19.5, 21.7, 26.0, 28.9, 39.0, 43.3, 52.0, 57.8, 58.5, 65.0, 72.2Mbps IEEE 802.11n mixed mode operation Per packet TX power control Advanced channel estimation/equalization, automatic gain control, CCA, carrier/symbol recovery, and frame detection Description The ATWINC1500B WLAN PHY is designed to achieve reliable and power-efficient physical layer communication specified by IEEE 802.11b/g/n in single stream mode with 20MHz bandwidth. Advanced algorithms have been employed to achieve maximum throughput in a real world communication environment with impairments and interference. The PHY implements all the required functions such as FFT, filtering, FEC (Viterbi decoder), frequency and timing acquisition and tracking, channel estimation and equalization, carrier sensing and clear channel assessment, as well as the automatic gain control. 7.3 Radio 7.3.1 Receiver Performance Radio Performance under Typical Conditions: VBATT=3.6V; VDDIO=3.3V; temp.: 25°C. Table 7-1. Receiver Performance Parameter Description Frequency Sensitivity 802.11b Min. Typ. 2,412 1Mbps DSS -98 2Mbps DSS -94 5.5Mbps DSS -92 11Mbps DSS -88 6Mbps OFDM -90 9Mbps OFDM -89 Max. Unit 2,484 MHz dBm Sensitivity 802.11g 14 Atmel ATWINC1500B-MU [DATASHEET] 1 Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 4 Parameter Sensitivity 802.11n (BW=20MHz) Maximum Receive Signal Level Adjacent Channel Rejection Cellular Blocker Immunity Description Min. Typ. 12Mbps OFDM -88 18Mbps OFDM -85 24Mbps OFDM -83 36Mbps OFDM -80 48Mbps OFDM -76 54Mbps OFDM -74 MCS 0 -89 MCS 1 -87 MCS 2 -85 MCS 3 -82 MCS 4 -77 MCS 5 -74 MCS 6 -72 MCS 7 -70.5 1-11Mbps DSS 0 6-54Mbps OFDM 0 MCS 0 – 7 0 1Mbps DSS (30MHz offset) 50 11Mbps DSS (25MHz offset) 43 6Mbps OFDM (25MHz offset) 40 54Mbps OFDM (25MHz offset) 25 MCS 0 – 20MHz BW (25MHz offset) 40 MCS 7 – 20MHz BW (25MHz offset) 20 776-794MHz CDMA -14 824-849MHz GSM -10 880-915MHz GSM -10 1710-1785MHz GSM -15 1850-1910MHz GSM -15 1850-1910MHz WCDMA -24 1920-1980MHz WCDMA -24 Max. Atmel ATWINC1500B-MU [DATASHEET] Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 Unit dBm dB dBm 15 1 5 7.3.2 Transmitter Performance Radio Performance under Typical Conditions: VBATT=3.6V; VDDIO=3.3V; temp.: 25°C. Table 7-2. Transmitter Performance Parameter Description Frequency Typ. 2,412 Output Power (1) ON_Transmit 802.11b 1Mbps 19.5 802.11b 11Mbps 20.5 802.11g 6Mbps 19.5 802.11g 54Mbps 17.5 802.11n MCS 0 18.0 802.11n MCS 7 15.5 Max. Unit 2,484 MHz dBm TX Power Accuracy ±1.5 (2) dB Carrier Suppression 30.0 dBc Harmonic Output Power Notes: 16 Min. 1. 2. 2nd -33 3rd -38 Measured at 802.11 spec compliant EVM/Spectral Mask. Measured at RF Pin assuming 50Ω differential. Atmel ATWINC1500B-MU [DATASHEET] 1 Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 6 dBm/Hz 8 External Interfaces ATWINC1500B external interfaces include: I2C Slave for control SPI Slave and SDIO Slave for control and data transfer I2C Master for external EEPROM Two UARTs for debug, control, and data transfer General Purpose Input/Output (GPIO) pins Wi-Fi/Bluetooth coexistence interface With the exception of the SPI Slave and SDIO Slave host interfaces, which are selected using the dedicated SDIO_SPI_CFG pin, the other interfaces can be assigned to various pins by programming the corresponding pin muxing control register for each pin to a specific value between 0 and 6.The default values of these registers are 0, which is GPIO mode. The summary of the available interfaces and their corresponding pin MUX settings is shown in Table 8-1. For specific programming instructions refer to ATWINC1500B Programming Guide. Table 8-1. 8.1 Pin-MUX Matrix of External Interfaces I2C Slave Interface The I2C Slave interface, used primarily for control by the host processor, is a two-wire serial interface consisting of a serial data line (SDA, Pin 33) and a serial clock (SCL, Pin 32). It responds to the seven bit address value 0x60. The ATWINC1500B I2C supports I2C bus Version 2.1 - 2000 and can operate in standard mode (with data rates up to 100Kb/s) and fast mode (with data rates up to 400Kb/s). The I2C Slave is a synchronous serial interface. The SDA line is a bidirectional signal and changes only while the SCL line is low, except for STOP, START, and RESTART conditions. The output drivers are open-drain to perform wire-AND functions on the bus. The maximum number of devices on the bus is limited by only the maximum capacitance specification of 400pF. Data is transmitted in byte packages. For specific information, refer to the Philips Specification entitled “The I2C -Bus Specification, Version 2.1”. The I2C Slave timing is provided in Figure 8-1 and Table 8-2. Atmel ATWINC1500B-MU [DATASHEET] Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 17 1 7 Figure 8-1. I2C Slave Timing Diagram tPR tSUDAT tHDDAT tBUF tSUSTO SDA tHL tLH tLH tWL SCL tHDSTA tHL tWH tPR fSCL Table 8-2. tPR tSUSTA I2C Slave Timing Parameters Parameter Symbol Min. Max. SCL Clock Frequency fSCL 0 SCL Low Pulse Width tWL 1.3 SCL High Pulse Width tWH 0.6 SCL, SDA Fall Time tHL 300 SCL, SDA Rise Time tLH 300 START Setup Time tSUSTA 0.6 START Hold Time tHDSTA 0.6 SDA Setup Time tSUDAT 100 400 Units Remarks kHz µs ns This is dictated by external components µs 0 SDA Hold Time ns tHDDAT Master Programming Option 40 18 STOP Setup time tSUSTO 0.6 Bus Free Time Between STOP and START tBUF 1.3 Glitch Pulse Reject tPR 0 µs Atmel ATWINC1500B-MU [DATASHEET] 1 Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 8 Slave and Master Default 50 ns 8.2 I2C Master Interface ATWINC1500B provides an I2C bus master, which is intended primarily for accessing an external EEPROM memory through a software-defined protocol. The I2C Master is a two-wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA can be configured on one of the following pins: SD_CLK (pin 19), GPIO1 (pin 24), GPIO6 (pin 31), or I2C_SDA (pin 33). SCL can be configured on one of the following pins: GPIO0 (pin 10), SD_DAT3 (pin 12), GPIO4 (pin 29), or I2C_SCL (pin 32). For more specific instructions refer to ATWINC1500B Programming Guide. The I2C Master interface supports three speeds: Standard mode (100kb/s) Fast mode (400kb/s) High-speed mode (3.4Mb/s) The timing diagram of the I2C Master interface is the same as that of the I2C Slave interface (see Figure 8-1). The timing parameters of I2C Master are shown in Table 8-3. Table 8-3. I2C Master Timing Parameters Standard Mode Parameter Fast Mode High-Speed Mode Symbol Units Min. Max. 100 Min. 0 Max. 400 Min. 0 Max. SCL Clock Frequency fSCL 0 3400 SCL Low Pulse Width tWL 4.7 1.3 0.16 SCL High Pulse Width tWH 4 0.6 0.06 SCL Fall Time tHLSCL 300 300 10 40 SDA Fall Time tHLSDA 300 300 10 80 SCL Rise Time tLHSCL 1000 300 10 40 SDA Rise Time tLHSDA 1000 300 10 80 START Setup Time tSUSTA 4.7 0.6 0.16 START Hold Time tHDSTA 4 0.6 0.16 SDA Setup Time tSUDAT 250 100 10 SDA Hold Time tHDDAT 5 40 0 STOP Setup time tSUSTO 4 0.6 0.16 Bus Free Time Between STOP and START tBUF 4.7 1.3 Glitch Pulse Reject tPR kHz µs ns µs ns 8.3 70 µs 0 50 ns SPI Slave Interface ATWINC1500B provides a Serial Peripheral Interface (SPI) that operates as a SPI slave. The SPI Slave interface can be used for control and for serial I/O of 802.11 data. The SPI Slave pins are mapped as shown in Table 8-4. The RXD pin is same as Master Output, Slave Input (MOSI), and the TXD pin is same as Master Input, Slave Output (MISO). The SPI Slave is a full-duplex slave-synchronous serial interface that is available immediately following reset when pin 9 (SDIO_SPI_CFG) is tied to VDDIO. Atmel ATWINC1500B-MU [DATASHEET] Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 19 1 9 Table 8-4. SPI Slave Interface Pin Mapping Pin # SPI Function 9 CFG: Must be tied to VDDIO 16 SSN: Active Low Slave Select 18 SCK: Serial Clock 13 RXD: Serial Data Receive (MOSI) 17 TXD: Serial Data Transmit (MISO) When the SPI is not selected, i.e., when SSN is high, the SPI interface will not interfere with data transfers between the serial-master and other serial-slave devices. When the serial slave is not selected, its transmitted data output is buffered, resulting in a high impedance drive onto the serial master receive line. The SPI Slave interface responds to a protocol that allows an external host to read or write any register in the chip as well as initiate DMA transfers. For the details of the SPI protocol and more specific instructions refer to ATWINC1500B Programming Guide. The SPI Slave interface supports four standard modes as determined by the Clock Polarity (CPOL) and Clock Phase (CPHA) settings. These modes are illustrated in Table 8-5 and Figure 8-2. The red lines in Figure 8-2 correspond to Clock Phase = 0 and the blue lines correspond to Clock Phase = 1. Table 8-5. SPI Slave Modes Mode CPOL CPHA 0 0 0 1 0 1 2 1 0 3 1 1 Figure 8-2. SPI Slave Clock Polarity and Clock Phase Timing CPOL = 0 SCK CPOL = 1 SSN CPHA = 0 RXD/TXD (MOSI/MISO) 20 CPHA = 1 z 1 z Atmel ATWINC1500B-MU [DATASHEET] 2 Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 0 2 1 3 2 4 3 5 4 6 5 7 6 8 7 z 8 z The SPI Slave timing is provided in Figure 8-3 and Table 8-6. Figure 8-3. SPI Slave Timing Diagram Table 8-6. SPI Slave Timing Parameters Parameter Symbol Min. Max. Units Clock Input Frequency fSCK Clock Low Pulse Width tWL 5 Clock High Pulse Width tWH 5 Clock Rise Time tLH 5 Clock Fall Time tHL 5 Input Setup Time tISU 5 Input Hold Time tIHD 5 Output Delay tODLY 0 Slave Select Setup Time tSUSSN 5 Slave Select Hold Time tHDSSN 5 48 MHz ns 20 Atmel ATWINC1500B-MU [DATASHEET] Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 21 2 1 8.4 UART ATWINC1500B has two Universal Asynchronous Receiver/Transmitter (UART) interfaces for serial communication: UART1 and UART2. The UARTs are compatible with the RS-232 standard, where ATWINC1500B operates as Data Terminal Equipment (DTE). UART1 has a 2-pin interface without flow control (RXD/TXD), where RXD (received data) can be enabled on one of five alternative pins and TXD (transmitted data) can be enabled on one of seven alternative pins by programming their corresponding pin MUX control registers (see Table 8-1). UART2 has a 4-pin interface with flow control (RXD/TXD/CTS/RTS), where RXD (received data) can be enabled on one of two alternative pins, TXD (transmitted data) can be enabled on one of two alternative pins, CTS (clear to send) can be enabled on one of two alternative pins, and RTS (request to send) can be enabled on one of two alternative pins by programming their corresponding pin MUX control registers (see Table 8-1). Both UARTs feature programmable baud rate generation with fractional clock division, which allows transmission and reception at a wide variety of standard and non-standard baud rates. The UART input clock is selectable between XO×2, XO, XO÷2, and XO÷4, which corresponds to 52MHz, 26MHz, 13MHz, and 6.5MHz for the typical XO frequency (26MHz). The clock divider value is programmable as 13 integer bits and 3 fractional bits (with 8.0 being the smallest recommended value for normal operation). This results in the maximum baud rate of 52MHz/8.0 = 6.5MBd for typical XO frequency. Both UARTs can be configured for seven or eight bit operation, with or without parity, with four different parity types (odd, even, mark, or space), and with one or two stop bits. They also have RX and TX FIFOs, which ensure reliable high speed reception and low software overhead transmission. FIFO size is 4x8 for both RX and TX direction. The UARTs also have status registers showing the number of received characters available in the FIFO and various error conditions, as well the ability to generate interrupts based on these status bits. The RTS and CTS are used for hardware flow control; they MUST be connected to the host MCU UART and enabled for the UART interface to be functional. UART2 supports standard flow control using CTS and RTS signals – UART2 can be programmed to enable or disable flow control. CTS is an active low input. When it is asserted (low) UART2 will transmit data; when it becomes de-asserted (high) UART2 will finish transmitting the current byte (if it is in progress) and will not resume transmitting until CTS becomes asserted again. RTS is an active low output. It becomes asserted (low) when the RX FIFO in UART2 has space; it becomes de-asserted (high) when there is not enough space in the RX FIFO. An example of UART receiving or transmitting a single packet is shown in Figure 8-4. This example shows 7-bit data (0x45), odd parity, and two stop bits. For more specific instructions refer to ATWINC1500B Programming Guide. Figure 8-4. 22 Example of UART RX or TX Packet Atmel ATWINC1500B-MU [DATASHEET] 2 Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 2 8.5 Wi-Fi/Bluetooth Coexistence ATWINC1500 supports 2-wire and 3-wire Wi-Fi/Bluetooth Coexistence signaling conforming to the IEEE 802.15.2-2003 standard, Part 15.2. The type of coexistence interface used (2 or 3 wire) is chosen to be compatible with the specific Bluetooth device used in a given application. Coexistence interface can be enabled on several alternative pins by programming their corresponding pin MUX control register to 6 (see Table 8-1, where any pin marked “IO_COE” in the “Mux6” column can be configured for any function of the coexistence interface). Table 8-7 shows a usage example of the 2-wire interface using the GPIO3 and GPIO4 pins; 3-wire interface using the GPIO3, GPIO4, and GPIO5 pins; for more specific instructions on configuring Coexistence refer to ATWINC1500 Programming Guide. Table 8-7. 8.6 Coexistence Pin Assignment Example Pin Name Pin # Function GPIO3 28 BT_Req GPIO4 29 GPIO5 GPIO6 Target 2-wire 3-wire BT is requesting to access the medium to transmit or receive. Goes high on TX or RX slot. Used Used WL_Act Device response to the BT request. High - BT_req is denied and BT slot blocked. Used Used 30 BT_Pri Priority of the BT packets in the requested slot. High to indicate high priority and low for normal. Not Used Used 31 Ant_SW Direct control on Antenna (coex bypass). Optional Optional GPIOs Nine General Purpose Input/Output (GPIO) pins, labeled GPIO 0-8, are available to allow for application specific functions. Each GPIO pin can be programmed as an input (the value of the pin can be read by the host or internal processor) or as an output (the output values can be programmed by the host or internal processor), where the default mode after power-up is input. GPIOs 7 and 8 are only available when the host does not use the SDIO interface, which shares two of its pins with these GPIOs. Therefore, for SDIO-based applications, seven GPIOs (0-6) are available. For more specific usage instructions refer to ATWINC1500B Programming Guide. Atmel ATWINC1500B-MU [DATASHEET] Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 23 2 3 9 Power Management 9.1 Power Architecture ATWINC1500B uses an innovative power architecture to eliminate the need for external regulators and reduce the number of off-chip components. This architecture is shown in Figure 9-1. The Power Management Unit (PMU) has a DC/DC Converter that converts VBATT to the core supply used by the digital and RF/AMS blocks. Table 9-1 shows the typical values for the digital and RF/AMS core voltages. The PA and eFuse are supplied by dedicated LDOs, and the VCO is supplied by a separate LDO structure. Figure 9-1. 24 Power Architecture Atmel ATWINC1500B-MU [DATASHEET] 2 Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 4 Table 9-1. PMU Output Voltages Parameter Typical RF/AMS Core Voltage (VREG_BUCK) 1.35V Digital Core Voltage (VDDC) 1.10V The power connections in Figure 9-1 provide a conceptual framework for understanding the ATWINC1500B power architecture. Refer to the reference design in Chapter 10 for an example of power supply connections, including proper isolation of the supplies used by the digital and RF/AMS blocks. 9.2 Power Consumption 9.2.1 Description of Device States ATWINC1500B has several Devices States: ON_Transmit – Device is actively transmitting an 802.11 signal. Highest output power and nominal current consumption ON_Receive – Device is actively receiving an 802.11 signal. Lowest sensitivity and nominal current consumption ON_Doze – Device is on but is neither transmitting nor receiving Power_Down – Device core supply off (Leakage) IDLE connect – Device is connected with 1 DTIM beacon interval The following pins are used to switch between the ON and Power_Down states: CHIP_EN – Device pin (pin #23) used to enable DC/DC Converter VDDIO – I/O supply voltage from external supply In the ON states, VDDIO is on and CHIP_EN is high (at VDDIO voltage level). To switch between the ON states and Power_Down state CHIP_EN has to change between high and low (GND) voltage. When VDDIO is off and CHIP_EN is low, the chip is powered off with no leakage (also see Section 9.2.3). 9.2.2 Current Consumption in Various Device States Table 9-2. Current Consumption Device State Code Rate Output Power, dBm Current Consumption (1) IVBATT IVDDIO 802.11b 1Mbps 19.5 294 mA 22mA 802.11b 11Mbps 20.5 290 mA 22mA 802.11g 6Mbps 19.5 292 mA 22mA 802.11g 54Mbps 17.5 250 mA 22mA 802.11n MCS 0 18.0 289 mA 22mA 802.11n MCS 7 15.5 244 mA 22mA 802.11b 1Mbps N/A 52.5mA 22mA 802.11b 11Mbps N/A 52.5mA 22mA 802.11g 6Mbps N/A 55.0mA 22mA ON_Transmit ON_Receive Atmel ATWINC1500B-MU [DATASHEET] Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 25 2 5 Device State Output Power, dBm Current Consumption (1) IVBATT IVDDIO 802.11g 54Mbps N/A 57.5mA 22mA 802.11n MCS 0 N/A 54.0mA 22mA 802.11n MCS 7 N/A 58.5mA 22mA ON_Doze N/A N/A 380µA <10µA Power_Down N/A N/A <0.5µA <3.5µA Note: 9.2.3 Code Rate 1. Conditions: VBATT @3.6v, VDDIO @2.8V, 25°C Restrictions for Power States When no power supplied to the device, i.e., the DC/DC Converter output and VDDIO are both off (at ground potential). In this case, a voltage cannot be applied to the device pins because each pin contains an ESD diode from the pin to supply. This diode will turn on when voltage higher than one diode-drop is supplied to the pin. If a voltage must be applied to the signal pads while the chip is in a low power state, the VDDIO supply must be on, so the SLEEP or Power_Down state must be used. Similarly, to prevent the pin-to-ground diode from turning on, do not apply a voltage that is more than one diode-drop below ground to any pin. 9.3 Power-Up/Down Sequence The power-up/down sequence for ATWINC1500 is shown in Figure 9-2. The timing parameters are provided in Table 9-3. Figure 9-2. Power Up/Down Sequence VBATT tA t A' VDDIO tB t B' CHIP_EN tC t C' RESETN XO Clock Table 9-3. Parameter tA 26 Power-Up/Down Sequence Timing Min. 0 Max. Unit ms Description VBATT rise to VDDIO rise Atmel ATWINC1500B-MU [DATASHEET] 2 Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 6 Notes VBATT and VDDIO can rise simultaneously or can be tied together. VDDIO must not rise before VBATT. Parameter Min. Max. Unit Description Notes tB 0 VDDIO rise to CHIP_EN rise CHIP_EN must not rise before VDDIO. CHIP_EN must be driven high or low, not left floating. tC 5 CHIP_EN rise to RESETN rise This delay is needed because XO clock must stabilize before RESETN removal. RESETN must be driven high or low, not left floating. tA’ 0 VDDIO fall to VBATT fall VBATT and VDDIO can fall simultaneously or can be tied together. VBATT must not fall before VDDIO. tB’ 0 CHIP_EN fall to VDDIO fall VDDIO must not fall before CHIP_EN. CHIP_EN and RESETN can fall simultaneously. tC’ 0 RESETN fall to VDDIO fall VDDIO must not fall before RESETN. RESETN and CHIP_EN can fall simultaneously. Atmel ATWINC1500B-MU [DATASHEET] Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 27 2 7 9.4 Digital I/O Pin Behavior during Power-Up Sequences Table 9-4 represents digital I/O pin states corresponding to device power modes. Table 9-4. Digital I/O Pin Behavior in Different Device States Device state CHIP_EN RESETN Output Driver Input driver Pull-Up/Down resistor (96kΩ) Power_Down: core supply off High Low Low Disabled (Hi-Z) Disabled Disabled Power-On Reset: core supply on, hard reset on High High Low Disabled (Hi-Z) Disabled Enabled Power-On Default: core supply on, device out of reset but not programmed yet High High High Disabled (Hi-Z) Enabled Enabled High Programmed by firmware for each pin: Enabled or Disabled Opposite of Output Driver state Programmed by firmware for each pin: Enabled or Disabled On_Doze/ On_Transmit/ On_Receive: core supply on, device programmed by firmware 28 VDDIO High High Atmel ATWINC1500B-MU [DATASHEET] 2 Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 8 DNI C22 0 Antenna Matching Network. Place right next to antenna DNI C21 L2 E1 ANTENNA Low Pass Filter For Harmonics 0.5pF R2 L3 DNI R3 2.0nH L9 C17 L8 C32 3.3nH 7 8 6.8pF Y1 26MHz Values Shown are initial v alues f or cry stal CL=8pF but must be adjusted f or each board design. C16 C15 35 36 9 25 VDDIO 0.7pF C33 6.8pF 6.8pF 6.8pF 24 C24 C23 1 40 External 32.768KHz clock may be used instead of on chip sleep clock. (Use RTC pin). 3.3nH 1.0pF 1.0pF ATWINC1500 XO_N XO_P RTC_MUX SDIO_SPI_CFG TEST_MODE RFIOP RFION TPP TPN U1 Place C1 next to pins 2 & 4. Place C19 next to pin 38. 0.01uF C1 FB2 BLM03AG121SN1 2 1 C11 2.2uF VDDIO VDDC VBAT 2 FB3 1 C7 1.0uF VREG_BUCK VSW CHIP_EN RESETN Wake GPIO_6 GPIO_5 GPIO_4 GPIO_3 SD_DAT3 SD_DAT2_SPI_RXD SD_DAT1_SPI_SSN SD_DAT0_SPI_TXD SD_CMD_SPI_SCK SD_CLK IRQN I2C_SCL I2C_SDA 2.2uF 6.3V C3 22 21 L5 1uH UART_TxD SPI_MOSI SPI_SSN SPI_MISO SPI_SCK UART_RxD IRQN I2C_SCL I2C_SDA L5 = 15nH is required in series with L1 = 1uH to reduce switching noise RF interf erence. 15nH L1 0 0 0 R16 R17 R18 23 34 10 0 0 0 0 0 0 0 R20 4.7K 0 Ohm resistors are placeholders in case f ilter resistors are required to reduce RF noise. R12 R6 R8 R5 R13 R14 R11 R19 4.7K VDDIO VDDC Place C8 & C12 next to pins 14 & 27 31 30 29 28 12 13 16 17 18 19 11 32 33 VDDIO Place C4, C5 and C6 next to pins 15, 26 & 39 BLM03AG121SN1 C19 0.1uF Place C2 next to pin 3. Place C11 next to pin 37. C4 0.1uF FB1 BLM03AG121SN1 2 C6 0.1uF 1 C5 0.1uF 1P3V C2 2.2uF 2 4 3 37 38 VDDRF_RX VDD_RF_TX VDD_AMS VDD_SXDIG VDD_VCO 39 15 26 VDDIO_A VDDIO_0 VDDIO_1 VSS 41 27 14 VDDC2 VDDC1 5 6 VBAT_PPA VBAT_PA 20 2.2uF 6.3V C10 1P3V VDDIO VBAT WLAN_Wake required if UART is the only host interf ace used. If SPI or SDIO is used, Wake pin is not required and should be lef t unconnected. Chip_En Reset_n WLAN_Wake Connect Chip_En and Resetn to host GPIO pins that def ault low or high impedance with a pull down resistor at power on. VDDIO VBAT Figure 10-1. VBat_buck C8 2.2uF 10.1 C12 2.2uF 10 Reference Design This chapter provides information on the schematic design the ATWINC1500B. Reference Schematic ATWINC1500B Reference Schematic Atmel ATWINC1500B-MU [DATASHEET] Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 29 2 9 10.2 Reference BOM Figure 10-2. 30 ATWINC1500B Reference BOM Atmel ATWINC1500B-MU [DATASHEET] 3 Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 0 11 Reflow Profile Information This chapter provides guidelines for reflow processes in getting the Atmel module soldered to the customer’s design. 11.1 Storage Condition 11.1.1 Moisture Barrier Bag Before Opened A moisture barrier bag must be stored in a temperature of less than 30°C with humidity under 85% RH. The calculated shelf life for the dry-packed product shall be 12 months from the date the bag is sealed. 11.1.2 Moisture Barrier Bag Open Humidity indicator cards must be blue, <30%. 11.2 Stencil Design The recommended stencil is laser-cut, stainless-steel type with thickness of 100µm to 130µm and approximately a 1:1 ratio of stencil opening to pad dimension. To improve paste release, a positive taper with bottom opening 25µm larger than the top can be utilized. Local manufacturing experience may find other combinations of stencil thickness and aperture size to get good results. 11.3 Baking Conditions This module is rated at MSL level 3. After sealed bag is opened, no baking is required within 168 hours so long as the devices are held at ≤30°C/60% RH or stored at <10% RH. The module will require baking before mounting if: 11.4 The sealed bag has been open for >168 hours Humidity Indicator Card reads >10% SIPs need to be baked for 8 hours at 125°C Soldering and Reflow Condition 11.4.1 Reflow Oven It is strongly recommended that a reflow oven equipped with more heating zones and Nitrogen atmosphere be used for lead-free assembly. Nitrogen atmosphere has shown to improve the wet-ability and reduce temperature gradient across the board. It can also enhance the appearance of the solder joints by reducing the effects of oxidation. The following bullet items should also be observed in the reflow process: Some recommended pastes include NC-SMQ® 230 flux and Indalloy® 241 solder paste made up of 95.5 Sn/3.8 Ag/0.7 Cu or SENJU N705-GRN3360-K2-V Type 3, no clean paste Allowable reflow soldering times: 2 times based on the following reflow soldering profile (see Figure 111) Temperature profile: Reflow soldering shall be done according to the following temperature profile (see Figure 11-1) Peak temp: 250°C Atmel ATWINC1500B-MU [DATASHEET] Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 31 3 1 Figure 11-1. 32 Solder Reflow Profile Atmel ATWINC1500B-MU [DATASHEET] 3 Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 2 12 Reference Documentation and Support 12.1 Reference Documents Atmel offers a set of collateral documentation to ease integration and device ramp. The following list of documents available on Atmel web or integrated into development tools. Title Content Datasheet This Document Design Files Package User Guide, Schematic, PCB layout, Gerber, BOM and System notes on: RF/Radio Full Test Report, radiation pattern, design guidelines, temperature performance, ESD. Platform Getting Started Guide How to use package: Out of the Box starting guide, HW limitations and notes, SW Quick start guidelines. HW Design Guide Best practices and recommendations to design a board with the product, Including: Antenna Design for Wi-Fi (layout recommendations, types of antennas, impedance matching, using a power amplifier etc.), SPI/UART protocol between Wi-Fi SoC and the Host MCU. SW Design Guide Integration guide with clear description of: High level Arch, overview on how to write a networking application, list all API, parameters and structures. Features of the device, SPI/handshake protocol between device and host MCU, with flow/sequence/state diagram, timing. SW Programmer Guide Explain in details the flow chart and how to use each API to implement all generic use cases (e.g. start AP, start STA, provisioning, UDP, TCP, http, TLS, p2p, errors management, connection/transfer recovery mechanism/state diagram) - usage and sample App note For a complete listing of development-support tools & documentation, visit http://www.atmel.com/, or contact the nearest Atmel field representative. Atmel ATWINC1500B-MU [DATASHEET] Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 33 3 3 13 Revision History Doc Rev. 42487B 42487A 34 Date Comments 03/2016 1. 2. 3. 4. 5. 6. 7. 8. Updated device drawing to include note to solder the paddle pad to GND in Figure 3-2. Revised table in transmit performance Table 7-2. Revised Chapter 9 text and current consumption table information in Table 9-2. Updated schematic figure in Figure 10-1. Added Schematic BOM in Figure 10-2. Added Chapter 11 Reflow Profile Information. Added Flow Control note in Section 8.4 Removed preliminary numbers note from performance numbers Table 9-2. 07/2015 DS update to RevB offering Changes from WINC1500A (42353D) to WINC1500B: 1. Added second UART, increased UART data rates 2. Increased instruction RAM size from 128KB to 160KB 3. Updated pin mux table: added new options for various interfaces 4. Improved description of Coexistence interface 5. Added VDD_VCO switch and connection in the power architecture 6. Updated power consumption numbers 7. Updated reference schematic 8. Changed RTC_CLK pad definition from pull-down to pull-up 9. Changed pin list to add GPIOs 3,4,5,6 - chip pinout identical WINC and WILC 10. Added hardware accelerators in feature list (SSL security, IP checksum, OTA security) 11. Modified sections 9.2.1 and 9.2.2 to add high-power and low-power modes and current consumption numbers 12. Updated radio performance in Table 7-1 and Table 7-2 13. Fixed typos for SPI Slave interface timing in Table 8-6 14. Fixed typos for battery supply name: changed from VBAT to VBATT 15. Corrected Table 8-7 16. Corrected Power Down and Doze mode current in Table 9-2 and in feature list 17. Corrected Table 4-3 and added high-drive pads reference in Table 3-1 18. Miscellaneous minor updates and corrections Atmel ATWINC1500B-MU [DATASHEET] 3 Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016 4 Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 │ www.atmel.com © 2016 Atmel Corporation. / Rev.: Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016. Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. ARM®, ARM Connected® logo, and others are the registered trademarks or trademarks of ARM Ltd. Other terms and product names may be trademarks of others. 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