WILC1000-MR110PA DATASHEET IEEE 802.11 b/g/n Link Controller SoC Datasheet Description The ATWILC1000-MR110P is a low-power consumption 802.11 b/g/n IoT (Internet of Things) module which is specifically optimized for low power IoT applications. The highly integrated module features small form factor (21.5mm x 14.5mm x 3.4mm) while fully integrating Power Amplifier, LNA, Switch, Power Management, and PCB antenna. With seamless roaming capabilities and advanced security, it could be interoperable with various vendors’ 802.11b/g/n Access Points in wireless LAN. The module provides SPI and SDIO to interface to host controller. Features • IEEE 802.11 b/g/n 20MHz (1x1) solution • Single spatial stream in 2.4GHz ISM band • Integrated PA and T/R Switch • Superior Sensitivity and Range via advanced PHY signal processing • Advanced Equalization and Channel Estimation • Advanced Carrier and Timing Synchronization • Wi-Fi Direct and Soft-AP support • Supports IEEE 802.11 WEP, WPA, WPA2 Security • Supports China WAPI security • Superior MAC throughput via hardware accelerated two-level A-MSDU/A-MPDU frame aggregation and block acknowledgement • On-chip memory management engine to reduce host load • SPI, SDIO, UART, and I C host interfaces 2 • 2/3 wire Bluetooth coexistence interface • Operating temperature range of -40°C to +85°C • Power save modes: – <1µA Deep Power Down mode typical @3.3V I/O – 280µA Doze mode with chip settings preserved (used for beacon monitoring) – On-chip low power sleep oscillator – Fast host wake-up from Doze mode by a pin or host I/O transaction Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 Ta bl e of Conte nts 1 Ordering Information and Module Marking................................................................ 4 2 Block Diagram ............................................................................................................. 5 3 Pin-Out and Package Information .............................................................................. 6 3.1 3.2 4 Electrical Specifications ............................................................................................. 9 4.1 4.2 5 6.2 6.3 7.2 7.3 7.4 7.5 SPI Interface ....................................................................................................................................... 13 7.1.1 Overview................................................................................................................................. 13 7.1.2 SPI Timing .............................................................................................................................. 14 UART Interface ................................................................................................................................... 15 SDIO Interface .................................................................................................................................... 15 7.3.1 Overview................................................................................................................................. 15 7.3.2 Features ................................................................................................................................. 16 7.3.3 SDIO Timing ........................................................................................................................... 16 2 I C Interface ........................................................................................................................................ 17 7.4.1 Overview................................................................................................................................. 17 2 7.4.2 I C Timing ............................................................................................................................... 17 Wi-Fi/Bluetooth Coexistence ............................................................................................................... 18 Description of Device States ............................................................................................................... 19 Controlling the Device States .............................................................................................................. 19 Restrictions for Power States .............................................................................................................. 19 Power-Up/Down Sequence ................................................................................................................. 19 Digital I/O Pin Behavior during Power-Up Sequences......................................................................... 21 Notes on Interfacing to the ATWILC1000-MR110P .................................................. 21 9.1 2 .............................................................................................................................................. 10 Features ................................................................................................................................. 10 Description.............................................................................................................................. 11 .............................................................................................................................................. 11 Features ................................................................................................................................. 11 Description.............................................................................................................................. 11 .............................................................................................................................................. 12 Power Consumption .................................................................................................. 19 8.1 8.2 8.3 8.4 8.5 9 MAC 6.1.1 6.1.2 PHY 6.2.1 6.2.2 Radio External Interfaces .................................................................................................... 13 7.1 8 Processor .............................................................................................................................................. 9 Memory Subsystem............................................................................................................................... 9 Non-Volatile Memory (EFuse) ............................................................................................................... 9 WLAN Subsystem ...................................................................................................... 10 6.1 7 Absolute Ratings ................................................................................................................................... 9 Recommended Operating Ratings ........................................................................................................ 9 CPU and Memory Subsystems ................................................................................... 9 5.1 5.2 5.3 6 Pin Description ...................................................................................................................................... 6 Module Outline Drawings ...................................................................................................................... 8 Programmable Pull Up Resistors ........................................................................................................ 21 ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 10 Recommended Footprint (Unit: mm) ........................................................................ 22 11 RF Performance Placement Guidelines ................................................................... 22 12 Recommended Reflow Profile .................................................................................. 23 13 Module Schematics ................................................................................................... 24 14 Module Bill of Materials (BOM) ................................................................................. 24 15 Application Reference Design .................................................................................. 26 16 Reference Documentation & Support ...................................................................... 28 16.1 Reference Documents......................................................................................................................... 28 17 Revision History ........................................................................................................ 29 ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 3 1 Ordering Information and Module Marking Table 1-1. Ordering Code Package Description ATWILC1000-MR110PA 22x15mm Certified module with ATWILC1000A-Mu chip and PCB antenna Figure 1-2. 4 Ordering Details Marking Information ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 2 Block Diagram Figure 2-1. Block Diagram VBAT Switching Regulator Printed 2.4GHz Antenna VBAT Chip_En VDDIO I2C RX/TX SDIO~_SPI_CFG BALUN SPI/SDIO GPIO3 GPIO4 ATWILC1000A 802.11 B,G,N SOC GPIO5 GPIO6 IRQN 26 Mhz Crystal Chip_En WAKE RESET UART GND ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 5 3 Pin-Out and Package Information 3.1 Pin Description Figure 3-1. Pin Assignment Table 3-1. Pin Description NO Name 1 GPIO_6 Type Description I/O General purpose I/O. I/O I C Slave Clock. Can be configured as either mas2 ter or slave. I C interface is only used for test purposes. This pin should be brought to a test point only. Do not add a pull-up resistor. I/O I C Slave Data. Can be configured as either master 2 or slave. I C interface is only used for test purposes. This pin should be brought to a test point only. Do not add a pull-up resistor. Programmable Pull-up Resistor 2 2 I2C_SCL 2 3 6 I2C_SDA ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 Yes NO Name Type Programmable Pull-up Resistor Description 4 RESET_N I Active-Low Hard Reset. When asserted to a low level, the module will be placed in a reset state. When asserted to a high level, the module will run normally. Connect to a host output that defaults low at power up. If the output floats, add a 1M ohm pull-down resistor if necessary to ensure a low level at power up. 5 NC - No connect Yes 6 NC - No connect No 7 NC - No connect 8 NC - No connect 9 GND_1 - GND 10 SDIO~_SPI_CFG I Tie to VDDIO through a 1M ohm resistor to enable the SPI interface. Connect to ground to enable SDIO interface. No 11 WAKE I Host Wake control. Can be used to wake up the module from Doze mode. Connect to a host GPIO. No 12 GND_2 - GND 13 IRQN O ATWINC1500 Device Interrupt. No SD_DAT3/UART_TXD SDIO=I/O UART=O SDIO Data Line 3 from ATWILC1000-MR110P when module is configured for SDIO. UART Transmit Output from ATWILC1000 when module is configured for SPI. Yes SD_DAT2/SPI_RXD SDIO=I/O SPI=I SDIO Data Line 2 signal from ATWILC1000-MR110P when module is configured for SDIO. SPI MOSI (Master Out Slave In) pin when module is configured for SPI. Yes SD_DAT1/SPI_SSN SDIO=I/O SPI=I SDIO Data Line 1 from ATWILC1000-MR110P when module is configured for SDIO. Active Low SPI Slave Select from ATWILC1000 when module is configured for SPI. Yes 17 SD_DAT0/SPI_TXD SDIO=I/O SPI=O SDIO Data Line 0 from ATWILC1000-MR110P when module is configured for SDIO. SPI MISO (Master In Slave Out) pin from ATWILC1000 when module is configured for SPI. Yes 18 SD_CMD/SPI_CLK SDIO=I/O SPI=I SDIO CMD Line from ATWILC1000-MR110P when module is configured for SDIO. SPI Clock from ATWILC1000 when module is configured for SPI. Yes 19 SD_CLK/UART_RXD SDIO=I UART=I SDIO Clock Line from ATWILC1000-MR110P when module is configured for SDIO. UART Receive input to ATWILC1000 when module is configured for SPI. Yes 20 VBATT - Battery power supply Yes 21 GPIO_1 I General Purpose I/O. Yes 14 15 16 Yes ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 7 NO 3.2 Name Description Programmable Pull-up Resistor 22 CHIP_EN I Module enable. High level enables module, low level places module in Power Down mode. Connect to a host Output that defaults low at power up. If the output floats, add a 1MΩ pull-down resistor if necessary to ensure a low level at power up. 23 VDDIO - I/O Power Supply. Must match host I/O voltage. 24 1P3V_TP - 1.3V VDD Core Test Point 25 GPIO_3 - General purpose I/O. Yes 26 GPIO_4 I/O General purpose I/O. Yes 27 GPIO_5 I/O General purpose I/O. Yes 28 GND_3 - GND Module Outline Drawings Figure 3-2. 8 Type Module Drawings ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 No 4 Electrical Specifications 4.1 Absolute Ratings Table 4-1. 4.2 Voltages Symbol Description Min. Max. Unit VBAT Input supply Voltage -0.3 5.5 V VDDIO SPI, SDIO, GPIO Voltage -0.3 3.6 V Recommended Operating Ratings Table 4-2. Pin Recommended Operating Ratings Test Conditions: -40ºC - +85ºC Symbol Min. Typ. Max. Unit VBAT 3.0 3.6 4.2 V VDDIO 1.8 3.3 3.6 V Note: The voltage of VDDIO is dependent on system I/O voltage. 5 CPU and Memory Subsystems 5.1 Processor ATWILC1000A has a Cortus APS3 32-bit processor. This processor performs many of the MAC functions, including but not limited to association, authentication, power management, security key management, and MSDU aggregation/de-aggregation. In addition, the processor provides flexibility for various modes of operation, such as STA and AP modes. 5.2 Memory Subsystem The APS3 core uses a 128KB instruction/boot ROM along with a 128KB instruction RAM and a 64KB data RAM. In addition, the device uses a 128KB shared RAM, accessible by the processor and MAC, which allows the APS3 core to perform various data management tasks on the TX and RX data packets. 5.3 Non-Volatile Memory (EFuse) ATWILC1000A has 768 bits of non-volatile EFuse memory that can be read by the CPU after device reset. This non-volatile one-time-programmable (OTP) memory can be used to store customer-specific parameters, such as MAC address; various calibration information, such as TX power, crystal frequency offset, etc.; and other software-specific configuration parameters. The EFuse is partitioned into six 128-bit banks. Each bank has the same bit map, which is shown in Figure 5-1. The purpose of the first 80 bits in each bank is fixed, and the remaining 48 bits are general-purpose software dependent bits, or reserved for future use. Since each bank can be programmed independently, this allows for several updates of the device parameters following the initial programming, e.g. updating MAC address. Refer to ATWILC1000A Programming Guide for the EFuse programming instructions. ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 9 Bank 0 F 7 8 48 MAC ADDR G 1 15 Freq. Offset Reserved Version Flags 8 1 Used 1 TX Gain Correc tion 4 Used 3 1 Invalid Used 1 EFuse Bit Map MAC ADDR Used Figure 5-1. 16 FO Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 128 Bits 6 WLAN Subsystem The WLAN subsystem is composed of the Media Access Controller (MAC) and the Physical Layer (PHY). The following two subsections describe the MAC and PHY in detail. 6.1 MAC 6.1.1 Features The ATWILC1000A IEEE802.11 MAC supports the following functions: • IEEE 802.11b/g/n • IEEE 802.11e WMM QoS EDCA/PCF multiple access categories traffic scheduling • Advanced IEEE 802.11n features: • 10 – Transmission and reception of aggregated MPDUs (A-MPDU) – Transmission and reception of aggregated MSDUs (A-MSDU) – Immediate Block Acknowledgement – Reduced Interframe Spacing (RIFS) Support for IEEE802.11i and WFA security with key management – WEP 64/128 – WPA-TKIP – 128-bit WPA2 CCMP (AES) • Support for WAPI security • Advanced power management – Standard 802.11 Power Save Mode – Wi-Fi Alliance WMM-PS (U-APSD) • RTS-CTS and CTS-self support • Supports either STA or AP mode in the infrastructure basic service set mode • Supports independent basic service set (IBSS) ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 6.1.2 Description The ATWILC1000A MAC is designed to operate at low power while providing high data throughput. The IEEE 802.11 MAC functions are implemented with a combination of dedicated datapath engines, hardwired control logic, and a low-power, high-efficiency microprocessor. The combination of dedicated logic with a programmable processor provides optimal power efficiency and real-time response while providing the flexibility to accommodate evolving standards and future feature enhancements. Dedicated datapath engines are used to implement data path functions with heavy computational. For example, an FCS engine checks the CRC of the transmitting and receiving packets, and a cipher engine performs all the required encryption and decryption operations for the WEP, WPA-TKIP, WPA2 CCMP-AES, and WAPI security requirements. Control functions which have real-time requirements are implemented using hardwired control logic modules. These logic modules offer real-time response while maintaining configurability via the processor. Examples of hardwired control logic modules are the channel access control module (implements EDCA/HCCA, Beacon TX control, interframe spacing, etc.), protocol timer module (responsible for the Network Access Vector, back-off timing, timing synchronization function, and slot management), MPDU handling module, aggregation/de-aggregation module, block ACK controller (implements the protocol requirements for burst block communication), and TX/RX control FSMs (coordinate data movement between PHY-MAC interface, cipher engine, and the DMA interface to the TX/RX FIFOs). The MAC functions implemented solely in software on the microprocessor have the following characteristics: • Functions with high memory requirements or complex data structures. Examples are association table management and power save queuing. • Functions with low computational load or without critical real-time requirements. Examples are authentication and association. • Functions which need flexibility and upgradeability. Examples are beacon frame processing and QoS scheduling. 6.2 PHY 6.2.1 Features The ATWILC1000A IEEE802.11 PHY supports the following functions: 6.2.2 • Single antenna 1x1 stream in 20MHz channels • Supports IEEE 802.11b DSSS-CCK modulation: 1, 2, 5.5, 11Mbps • Supports IEEE 802.11g OFDM modulation: 6, 9, 12,18, 24, 36, 48, 54Mbps • Supports IEEE 802.11n HT modulations MCS0-7, 20MHz, 800 and 400ns guard interval: 6.5, 7.2, 13.0, 14.4, 19.5, 21.7, 26.0, 28.9, 39.0, 43.3, 52.0, 57.8, 58.5, 65.0, 72.2Mbps • IEEE 802.11n mixed mode operation • Per packet TX power control • Advanced channel estimation/equalization, automatic gain control, CCA, carrier/symbol recovery, and frame detection Description The ATWILC1000A WLAN PHY is designed to achieve reliable and power-efficient physical layer communication specified by IEEE 802.11 b/g/n in single stream mode with 20MHz bandwidth. Advanced algorithms have been employed to achieve maximum throughput in a real world communication environment with impairments and interference. The PHY implements all the required functions such as FFT, filtering, FEC (Viterbi decoder), frequency and timing acquisition and tracking, channel estimation and equalization, carrier sensing and clear channel assessment, as well as the automatic gain control. ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 11 6.3 Radio Table 6-1. Radio Performance under Typical Conditions: VBAT=3.6V; VDDIO=3.3V; Temp: 25ºC Feature Description Module Part Number ATWILC1000-MR110P WLAN Standard IEEE 802.11b/g/n, Wi-Fi compliant Host Interface SPI, SDIO Dimension L x W x H: 21.5 x 14.5 x 1.5 (typical) mm Frequency Range 2.412GHz ~ 2.4835GHz (2.4GHz ISM Band) Number of Channels 11 for North America, 13 for Europe, and 14 for Japan Modulation 802.11b: DQPSK, DBPSK, CCK 802.11g/n: OFDM/64-QAM,16-QAM, QPSK, BPSK 802.11b/11Mbps: 19dBm ± 1.5dB @ EVM -9dB 1 Output Power 802.11g/54Mbps: 14.5dBm ± 2dB @ EVM -25dB 802.11n/65Mbps: 13dBm ± 2dB @ EVM -28dB Receive Sensitivity (11n,20MHz) @10% PER Receive Sensitivity (11g) @10% PER Receive Sensitivity (11b) @8% PER - MCS=0 PER @ -90 ± 1dBm, typical - MCS=1 PER @ -86 ± 1dBm, typical - MCS=2 PER @ -84 ± 1dBm, typical - MCS=3 PER @ -81.5 ± 1dBm, typical - MCS=4 PER @ -78 ± 1dBm, typical - MCS=5 PER @ -74 ± 1dBm, typical - MCS=6 PER @ -72.5 ± 1dBm, typical - MCS=7 PER @ -71.5 ± 1dBm, typical - 6Mbps PER @ -91 ± 1dBm, typical - 9Mbps PER @ -89 ± 1dBm, typical - 12Mbps PER @ -88.5 ± 1dBm, typical - 18Mbps PER @ -86.5 ± 1dBm, typical - 24Mbps PER @ -84 ± 1dBm, typical - 36Mbps PER @ -78.5 ± 1dBm, typical - 48Mbps PER @ -77 ± 1dBm, typical - 54Mbps PER @ -75 ± 1dBm, typical - 1Mbps PER @ -98 ± 1dBm, typical - 2Mbps PER @ -95 ± 1dBm, typical - 5.5Mbps PER @ -93 ± 1dBm, typical - 11Mbps PER @ -89 ± 1dBm, typical 802.11b: 1, 2, 5.5, 11Mbps Data Rate 802.11g: 6, 9, 12, 18, 24, 36, 48, 54Mbps 12 ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 Feature Description Data Rate 802.11n: 6.5, 13, 19.5, 26, 39, 52, 58.5, 65Mbps Data Rate (20MHz ,short GI,400ns) 802.11n: 7.2, 14.4, 21.7, 28.9, 43.3, 57.8, 65,72.2Mbps 802.11b: 0dBm typical Maximum Input Level 802.11g/n: -5dBm typical 2 Operating temperature -40°C to 85°C Storage temperature -40°C to 85°C Humidity Operating Humidity 10% to 95% Non-Condensing Storage Humidity 5% to 95% Non-Condensing Notes: 1. 2. Measured at 802.11 spec compliant EVM/Spectral Mask. RF performance guaranteed for Temp range -30 to 85deg. 1dB derating in performance at -40deg. 7 External Interfaces 7.1 SPI Interface 7.1.1 Overview When the module is configured for SPI mode by connecting the SDIO~_SPI_CFG pin to VDDIO, the ATWILC1000-MR110P has a Serial Peripheral Interface (SPI) that operates as a SPI slave. The SPI interface can be used for control and for serial I/O of 802.11 data. The SPI pins are mapped as shown in Table 7-1. The SPI is a full-duplex slave-synchronous serial interface that is available immediately following reset when pin 10 (SPI_CFG) is tied to VDDIO. Table 7-1. SPI Interface Pin Mapping Pin # SPI Function 10 CFG: Must be tied to VDDIO 16 SSN: Active Low Slave Select 15 MOSI: Serial Data Receive 18 SCK: Serial Clock 17 MISO: Serial Data Transmit When the SPI is not selected, i.e., when SSN is high, the SPI interface will not interfere with data transfers between the serial-master and other serial-slave devices. When the serial slave is not selected, its transmitted data output is buffered, resulting in a high impedance drive onto the MISO line. The SPI interface responds to a protocol that allows an external host to read or write any register in the chip as well as initiate DMA transfers. The SPI SSN, MOSI, MISO and SCK pins of the ATWILC1000-MR110P have internal programmable pull-up resistors (see Section 8.1). These resistors should be programmed to be disabled. Otherwise, if any of the SPI pins are driven to a low level while the ATWILC1000-MR110P is in the low power sleep state, current will flow from the VDDIO supply through the pull-up resistors, increasing the current consumption of the module. ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 13 7.1.2 SPI Timing The SPI timing is provided in Figure 7-1 and Table 7-2. 14 Figure 7-1. SPI Timing Diagram (SPI Mode CPOL=0, CPHA=0) Table 7-2. SPI Slave Timing Parameters Parameter Symbol Clock Input Frequency fSCK Clock Low Pulse Width tWL 15 ns Clock High Pulse Width tWH 15 ns Clock Rise Time tLH 10 ns Clock Fall Time tHL 10 ns Input Setup Time tISU 5 ns Input Hold Time tIHD 5 ns Output Delay tODLY 0 Slave Select Setup Time tSUSSN 5 ns Slave Select Hold Time tHDSSN 5 ns ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 Min Max Units 48 MHz 20 ns Remarks 7.2 UART Interface When the module is configured for SPI mode by connecting the SDIO~_SPI_CFG pin to VDDIO, the ATWILC1000-MR110P has a Universal Asynchronous Receiver/Transmitter (UART) interface available on pins J14 and J19. It can be used for control or data transfer if the baud rate is sufficient for a given application. The UART is compatible with the RS-232 standard, where NMC1000 operates as Data Terminal Equipment (DTE). It has a two-pin RXD/TXD interface. The UART features programmable baud rate generation with fractional clock division, which allows transmission and reception at a wide variety of standard and non-standard baud rates. The UART input clock is selectable between 10MHz, 5MHz, 2.5MHz, and 1.25MHz. The clock divider value is programmable as 13 integer bits and three fractional bits (with 8.0 being the smallest recommended value for normal operation). This results in the maximum supported baud rate of 10MHz/8.0 = 1.25MBd. The UART can be configured for seven or eight bit operation, with or without parity, with four different parity types (odd, even, mark, or space), and with one or two stop bits. It also has Rx and Tx FIFOs, which ensure reliable high speed reception and low software overhead transmission. FIFO size is 4x8 for both Rx and Tx direction. The UART also has status registers showing the number of received characters available in the FIFO and various error conditions, as well the ability to generate interrupts based on these status bits. An example of UART receiving or transmitting a single packet is shown in Figure 7-2. This example shows 7-bit data (0x45), odd parity, and two stop bits. See the ATWILC1000-MR110P Programming Guide for information on configuring the UART. Figure 7-2. Example of UART Rx or Tx Packet 7.3 SDIO Interface 7.3.1 Overview When the module is configured for SDIO mode by connecting the SDIO~_SPI_CFG pin to Ground, the ATWILC1000-MR110P has a SDIO interface. The SDIO interface can be used for control and for serial I/O of 802.11 data. The SDIO pins are mapped as shown in 0. The SDIO interface is available immediately following reset when pin 10 (SPI_CFG) is tied to ground. The ATWILC1000-MR110P SDIO is a full speed interface. The interface supports the 1-bit/4-bit SD transfer mode at the clock range of 0-50MHz. The Host can use this interface to read and write from any register within the chip as well as configure the ATWILC1000-MR110P for data DMA. ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 15 Table 7-3. ATWILC1000 SDIO Interface Pin Mapping Pin # SDIO Function 10 CFG: Must be tied to ground 14 DAT3: Data 3 15 DAT2: Data 2 16 DAT1: Data 1 17 DAT0: Data 0 18 CMD: Command 19 CLK: Clock When the SDIO card is inserted into an SDIO aware host, the detection of the card will be via the means described in SDIO specification. During the normal initialization and interrogation of the card by the host, the card will identify itself as an SDIO device. The host software will obtain the card information in a tuple (linked list) format and determine if that card’s I/O function(s) are acceptable to activate. If the card is acceptable, it will be allowed to power up fully and start the I/O function(s) built into it. The SD memory card communication is based on an advanced 9-pin interface (Clock, Command, 4 Data and 3 Power lines) designed to operate at maximum operating frequency of 50MHz. 7.3.2 7.3.3 Features • Meets SDIO card specification version 2.0 • Host clock rate variable between 0 and 50MHz • 1 bit/4-bit SD bus modes supported • Allows card to interrupt host • Responds to Direct read/write (IO52) and Extended read/write (IO53) transactions • Supports Suspend/Resume operation SDIO Timing Figure 7-3. SDIO Timing Diagram fpp tWL SD_CLK tWH tHL tLH tISU tIH Inputs tODLY(MAX) tODLY(MIN) Outputs Table 7-4. Parameter 16 SDIO Timing Parameters Symbol ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 Min Max Units Parameter Symbol Min Max Units Clock Input Frequency fPP 0 50 MHz Clock Low Pulse Width tWL 10 ns Clock High Pulse Width tWH 10 ns Clock Rise Time tLH 10 ns Clock Fall Time tHL 10 ns Input Setup Time tISU 5 ns Input Hold Time tIH 5 ns Output Delay tODLY 0 7.4 I2C Interface 7.4.1 Overview 14 ns 2 ATWILC1000-MR110P provides an I C bus slave that allows the host processor to read or write any register in 2 the chip. ATWILC1000-MR110P supports I C bus Version 2.1 – 2000. 2 The I C interface, used primarily for debug, is a two-wire serial interface consisting of a serial data line (SDA, Pin 17) and a serial clock (SCL, Pin 18). It responds to the seven bit address value 0x60. The ATWILC1000-MR110P 2 I C interface can operate in standard mode (with data rates up to 100Kb/s) and fast mode (with data rates up to 400Kb/s). 2 The I C is a synchronous serial interface. The SDA line is a bidirectional signal and changes only while the SCL line is low, except for STOP, START, and RESTART conditions. The output drivers are open-drain to perform wire-AND functions on the bus. The maximum number of devices on the bus is limited by only the maximum capacitance specification of 400pF. Data is transmitted in byte packages. 2 For specific information, refer to the Philips Specification entitled “The I C -Bus Specification, Version 2.1”. 7.4.2 2 I C Timing 2 The I C timing is provided in Figure 7-4 and Table 7-5. Figure 7-4. 2 I C Timing Diagram tPR tSUDAT tHDDAT tBUF tSUSTO SDA tHL tLH tLH tWL SCL tHDSTA tHL tWH tPR fSCL Table 7-5. tPR tSUSTA 2 I C Timing Parameters Parameter Symbol Min Max Units SCL Clock Frequency fSCL 0 400 kHz Remarks ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 17 7.5 Parameter Symbol Min Max SCL Low Pulse Width tWL 1.3 µs SCL High Pulse Width tWH 0.6 µs SCL, SDA Fall Time tHL 300 ns SCL, SDA Rise Time tLH 300 ns START Setup Time tSUSTA 0.6 µs START Hold Time tHDSTA 0.6 µs SDA Setup Time tSUDAT 100 ns SDA Hold Time tHDDAT 0 40 ns ns STOP Setup time tSUSTO 0.6 µs Bus Free Time Between STOP and START tBUF 1.3 µs Glitch Pulse Reject tPR 0 50 Units Remarks This is dictated by external components Slave and Master Default Master Programming Option ns Wi-Fi/Bluetooth Coexistence ATWILC1000A supports 2-wire and 3-wire Wi-Fi/Bluetooth Coexistence signaling conforming to the IEEE 802.15.2-2003 standard, Part 15.2. The type of coexistence interface used (2 or 3 wire) is chosen to be compatible with the specific Bluetooth device used in a given application. Table 7-6 shows a usage example of the 2-wire interface using the GPIO3 and GPIO4 pins; 3-wire interface using the GPIO3, GPIO4, and GPIO5 pins; for more specific instructions on configuring Coexistence refer to ATWILC1000A Programming Guide. Table 7-6. 18 Coexistence Pin Assignment Example Pin Name Function Target Pin # 2-wire 3-wire GPIO3 BT_Req BT is requesting to access the medium to transmit or receive. Goes high on TX or RX slot. 28 Used Used GPIO4 BT_Pri Priority of the BT packets in the requested slot. High to indicate high priority and low for normal. 29 Not Used Used GPIO5 WL_Act Device response to the BT request. High - BT_req is denied and BT slot blocked. 30 Used Used GPIO6 Ant_SW Direct control on Antenna (coex bypass). 31 Not Used Optional ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 8 Power Consumption 8.1 Description of Device States ATWILC1000A has several Devices States: 8.2 • ON_Transmit – Device is actively transmitting an 802.11 signal • ON_Receive – Device is actively receiving an 802.11 signal • ON_Doze – Device is on but is neither transmitting nor receiving • Power_Down – Device core supply off (Leakage) Controlling the Device States Table 8-1 shows how to switch between the device states using the following: • CHIP_EN – Device pin (pin #23) used to enable DC/DC Converter • VDDIO – I/O supply voltage from external supply Table 8-1. Device States Power Consumption Device State CHIP_EN VDDIO IVBATT IVDDIO ON_Transmit VDDIO On 230mA @ 18dBm 29mA ON_Receive VDDIO On 68mA 29mA ON_Doze VDDIO On 280µA <10µA Power_Down GND On <0.5µA <0.2µA Note: 8.3 1. 1 Conditions: VBAT @ 3.6v, [email protected]. Restrictions for Power States When no power supplied to the device, i.e., the DC/DC Converter output and VDDIO are both off (at ground potential). In this case, a voltage cannot be applied to the device pins because each pin contains an ESD diode from the pin to supply. This diode will turn on when voltage higher than one diode-drop is supplied to the pin. If a voltage must be applied to the signal pads while the chip is in a low power state, the VDDIO supply must be on, so the SLEEP or Power_Down state must be used. Similarly, to prevent the pin-to-ground diode from turning on, do not apply a voltage that is more than one diode-drop below ground to any pin. 8.4 Power-Up/Down Sequence The power-up/down sequence for ATWILC1000A is shown in Figure 8-1. The timing parameters are provided in Table 8-2. ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 19 Figure 8-1. Power Up/Down Sequence VBATT tA t A' VDDIO tB t B' CHIP_EN tC t C' RESETN XO Clock Table 8-2. 20 Power-Up/Down Sequence Timing Parameter Min tA Max Units Description Notes 0 ms VBATT rise to VDDIO rise VBATT and VDDIO can rise simultaneously or can be tied together. VDDIO must not rise before VBATT. tB 0 ms VDDIO rise to CHIP_EN rise CHIP_EN must not rise before VDDIO. CHIP_EN must be driven high or low, not left floating. tC 5 ms CHIP_EN rise to RESETN rise This delay is needed because XO clock must stabilize before RESETN removal. RESETN must be driven high or low, not left floating. tA’ 0 ms VDDIO fall to VBATT fall VBATT and VDDIO can fall simultaneously or can be tied together. VBATT must not fall before VDDIO. tB’ 0 ms CHIP_EN fall to VDDIO fall VDDIO must not fall before CHIP_EN. CHIP_EN and RESETN can fall simultaneously. tC’ 0 ms RESETN fall to VDDIO fall VDDIO must not fall before RESETN. RESETN and CHIP_EN can fall simultaneously. ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 8.5 Digital I/O Pin Behavior during Power-Up Sequences Table 8-3 represents digital IO Pin states corresponding to device power modes. Table 8-3. Digital I/O Pin Behavior in Different Device States Device State VDDIO CHIP_EN RESETN Output Driver Input Driver Pull Up/Down Resistor (96Ω) Power_Down: core supply off High Low Low Disabled (Hi-Z) Disabled Disabled Power-On Reset: core supply on, hard reset on High High Low Disabled (Hi-Z) Disabled Enabled Power-On Default: core supply on, device out of reset but not programmed yet High High High Disabled (Hi-Z) Disabled Enabled High Programmed by firmware for each pin: Enabled or Disabled Opposite of Output Driver state Programmed by firmware for each pin: Enabled or Disabled On_Doze/ On_Transmit/ On_Receive: core supply on, device programmed by firmware High High 9 Notes on Interfacing to the ATWILC1000-MR110P 9.1 Programmable Pull Up Resistors The ATWILC1000-MR110P provides programmable pull-up resistors on various pins. The purpose of these resistors is to keep any unused input pins from floating which can cause excess current to flow through the input buffer from the VDDIO supply. Any unused module pin on the ATWILC1000-MR110P should leave these pull-up resistors enabled so the pin will not float. The default state at power up is for the pull-up resistor to be enabled. However, any pin which is used should have the pull-up resistor disabled. The reason for this is that if any pins are driven to a low level while the ATWILC1000-MR110P is in the low power sleep state, current will flow from the VDDIO supply through the pull-up resistors, increasing the current consumption of the module. Since the value of the pull-up resistor is approximately 100KΩ, the current through any pull-up resistor that is being driven low will be VDDIO/100K. For VDDIO = 3.3V, the current through each pull-up resistor that is driven low would be approximately 3.3V/100K = 33µA. Pins which are used and have had the programmable pull-up resistor disabled should always be actively driven to either a high or low level and not be allowed to float. See the ATWILC1000-MR110P Programming Guide for information on enabling/disabling the programmable pull up resistors. ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 21 10 Recommended Footprint (Unit: mm) Figure 10-1. 11 Footprint Drawing RF Performance Placement Guidelines It is critical to follow the recommendations listed below to achieve the best RF performance: 22 • Module must be placed on main board - printed antenna area must overlap with the carrier board. The portion of the module containing the antenna should not stick out over the edge of the main board. The antenna is designed to work properly when it is sitting directly on top of a 1.5mm thick printed circuit board. • If the module is placed at the edge of the main board, a minimum 22mm by 5mm area directly under the antenna must be clear of all metal on all layers of the board. “In-land” placement is acceptable; however deepness of keep-out area must grove to: module edge to main board edge plus 5mm. DO NOT PLACE MODULE IN THE MIDDLE OF THE MAIN BOARD OR FAR AWAY FROM THE MAIN BOARD EDGE. • Keep away from antenna, as far as possible, large metal objects to avoid electromagnetic field blocking. • Do not enclose the antenna within a metal shield. • Keep any components which may radiate noise or signals within the 2.4GHz – 2.5GHz frequency band far away from the antenna or better yet, shield those components. Any noise radiated from the main board in this frequency band will degrade the sensitivity of the module. • Contact Atmel for assistance if any other placement is required. ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 12 Recommended Reflow Profile Refer to IPC/JEDEC standard. Peak Temperature : <250°C Number of Times: 2 times maximum Figure 12-1. Typical Reflow Profile ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 23 13 Module Schematics Table 13-1. 14 Module Bill of Materials (BOM) Table 14-1. 24 ATWINC1500-MR210PA Schematic ATWILC1000-MR110P BOM ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 WiFi shielded module with DC/DC, discrete balun, no load switch, with printed antenna Revised: Thursday, September 11, 2014 ATWILC1000-MR110P Revision: A Footprint Reference Value Description Manufacturer Part Number 1 2 C5,C12 1.0uF CAP,CER,1.0uF,20%,X5R,0402,6.3V Panasonic ECJ-0EB0J105M CS0402 2 2 1000PF CAP CER 1000PF 50V 10% X7R 0402 Murata GRM155R71H102KA01D CS0402 3 7 1 1 2 C1,C14 C2,C3,C4,C8,C9,C10, C11 C13 C17 C23,C24 0.1uF 22pF 4.7uF 1pF CAP,CER,0.1uF,10%,X5R,0402,10V AVX 0402ZD104KAT2A CS0402 CAP,CER,22pF,5%,NPO,0402,50V Murata GRM1555C1H220JZ01 CS0402 CAP CER 4.7UF 4V 20% X5R 0402 Murata CAP CER 1PF 50V NP0 0201 Murata GRM155R60G475ME47D GRM0335C1H1R0CA01D CS0201 C6,C7 C15,C16 C19 C21 C20 C18,C22 FB1,FB2,FB3 L1 L2,L5 R1 R2 R3 R4 U1 U2 U3 Y1 PCB Shield 10PF 1.8PF 10uF 0 1.8PF DNI BLM15AG121SN1 2.2uH 3.3nH 261k 6.8PF 301k 0 CAP CER 10PF 50V 1% NP0 0402 Murata GRM1555C1H100FA01D CS0402 CAP CER 1.8PF 50V NP0 0201 Murata GRM0335C1H1R8CA01D CS0201 CAP CER 10UF 4V 20% X5R 0402 Murata RES 0.0 OHM 1/20W JUMP 0201 SMD Panasonic GRM155R60G106ME44D ERJ-1GN0R00C RS0201 CAP CER 1.8PF 50V NP0 0201 Murata GRM0335C1H1R8CA01D CS0201 Item Qty 4 5 6 7 8 9 10 11 2 2 1 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 3 1 2 1 1 1 1 1 1 1 1 1 1 CS0402 CS0402 FERRITE,120 OHM @100MHz,0402 Murata BLM15AG121SN1 FBS0402 POWER INDUCTOR,2.2uH,20%,1250mA,0.22ohms,0603 Murata LPS0603 INDUCTOR 3.3+/-0.2NH 750MA 0201 Murata LQM18PN2R2MFRL LQP03TN3N3C02D RES 261K OHM 1/10W 1% 0402 SMD Panasonic ERJ-2RKF2613X RS0402 LS0201 CAP,CER,6.8pF,NPO,0402,50V Murata GRM1555C1H6R8CA01 CS0402 RES 301K OHM 1/10W 1% 0402 SMD Panasonic RES 0.0 OHM 1/20W JUMP 0201 SMD Panasonic ERJ-2RKF3013X ERJ-1GN0R00C RS0201 ATWILC1000A-MU IC, WiFi, 40QFN Atmel ATWILC1000A-MU 40QFN FT440Aa DNI 26.000MHz - 1.5MHz, 600mA, Synchronous Step-Down Converter FMD FT440Aa SOT23-5 CRYSTAL 26MHZ 10PF SMD Abracon Createk Createk ABM10-26.000MHZ-D30-T3 4 SMD ATWILC1000-MR110PA Metal Shield RS0402 NMI RF Shield rev1 Revision A - Initial release to production ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 25 15 Application Reference Design The ATWILC1000-MR110PA reference design schematic is shown in Figure 15-1. Figure 15-1. 26 WILC1000-MR110PA SDIO ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 Figure 15-2. WILC1000-MR110PA SPI ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 27 16 Reference Documentation & Support 16.1 Reference Documents Atmel offers a set of collateral documentation to ease integration and device ramp. The following list of documents available on Atmel web or integrated into development tools. To enable fast development contact your local FAE or visit the http://www.atmel.com/. Title Content Datasheet This Document Design Files Package User Guide, Schematic, PCB layout, Gerber, BOM & System notes on: RF/Radio Full Test Report, radiation pattern, design guidelines, temperature performance, ESD. Platform Getting Started Guide How to use package: Out of the Box starting guide, HW limitations and notes, SW Quick start guidelines. HW Design Guide Best practices and recommendations to design a board with the product, Including: Antenna Design for Wi-Fi (layout recommendations, types of antennas, impedance matching, using a power amplifier etc), SPI/UART protocol between Wi-Fi SoC and the Host MCU. SW Design Guide Integration guide with clear description of: High level Arch, overview on how to write a networking application, list all API, parameters and structures. Features of the device, SPI/handshake protocol between device and host MCU, with flow/sequence/state diagram, timing. SW Programmer Guide Explain in details the flow chart and how to use each API to implement all generic use cases (e.g. start AP, start STA, provisioning, UDP, TCP, http, TLS, p2p, errors management, connection/transfer recovery mechanism/state diagram) - usage & sample App note For a complete listing of development-support tools & documentation, visit http://www.atmel.com/, or contact the nearest Atmel field representative. 28 ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 17 Revision History Doc Rev. Date Comments 42380D 03/2015 Updated Figure 10-1 Footprint Drawing. 42380C 02/2015 Product name and marking updates. 42380B 10/2014 Product name corrected from ATWILC1000-MR110P to ATWILC1000-MR110PA. 42380A 10/2014 Initial document release. ATWILC1000-MR110PA [DATASHEET] Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 29 Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 │ www.atmel.com © 2015 Atmel Corporation. / Rev.: Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015. Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. ARM®, ARM Connected® logo, and others are the registered trademarks or trademarks of ARM Ltd. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade. Atmel-42380D-WILC1000-MR110PA-SmartConnect-Datasheet_032015 30 ATWILC1000-MR110PA [DATASHEET]