AT25512 - Complete

AT25512
SPI Serial EEPROM
512-Kbit (65,536 x 8)
DATASHEET
Features

Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Datasheet Describes Mode 0 Operation

Low-voltage Operation


̶



1.8 (VCC = 1.8V to 5.5V)
20MHz Clock Rate (4.5V to 5.5V)
128-byte Page Mode and Byte Write Operation Supported
Block Write Protection
̶



Protect ¼, ½, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware
and Software Data Protection
Self-timed Write Cycle (5ms Max)
High Reliability
̶
̶



Endurance: 1,000,000 Write Cycles
Data Retention: 40 Years
Lead-free/Halogen-free Devices
8-lead JEDEC SOIC, 8-lead TSSOP, and 8-pad UDFN Packages
Die Sale Options: Wafer Form, Waffle Pack, and Bumped Die
Description
The Atmel® AT25512 provides 524,288 bits of Serial Electrically Erasable
Programmable Read-Only Memory (EEPROM) organized as 65,536 words of
8 bits each. The device is optimized for use in many industrial and commercial
applications where low-power and low-voltage operation are essential. The
devices are available in space saving 8-lead JEDEC SOIC, 8-lead TSSOP, and
8-pad UDFN packages. In addition, the device operates from 1.8V to 5.5V.
The AT25512 is enabled through the Chip Select pin (CS) and accessed via a
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no
separate erase cycle is required before write.
Block Write Protection is enabled by programming the status register with top ¼,
top ½, or entire array of Write Protection. Separate program enable and program
disable instructions are provided for additional data protection. Hardware Data
Protection is provided via the WP pin to protect against inadvertent write attempts
to the status register. The HOLD pin may be used to suspend any serial
communication without resetting the serial sequence.
Atmel-5165J-SEEPROM-AT25512-Datasheet_012015
1.
Pin Configurations and Pinouts
Figure 1.
Pin Configurations
Name
Function
CS
Chip Select
SO
Serial Data Output
WP
Write Protect
GND
Ground
SI
Serial Data Input
SCK
Serial Data Clock
HOLD
Suspends Serial Input
VCC
Power Supply
(Top View)
CS
1
8
VCC
2
7
HOLD
WP
3
6
SCK
GND
4
5
SI
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
8-pad UDFN
(Top View)
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
Drawings are not to scale.
Absolute Maximum Ratings*
Operating Temperature . . . . . . . . . . .-55C to +125C
Storage Temperature . . . . . . . . . . . . .-65C to +150C
Voltage on any pin
with respect to ground . . . . . . . . . . . . . -1.0V to +7.0V
Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . .5.0mA
2
8-lead TSSOP
(Top View)
SO
Note:
2.
8-lead SOIC
AT25512 [DATASHEET]
Atmel-5165J-SEEPROM-AT25512-Datasheet_012015
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
3.
Block Diagram
Figure 3-1.
Block Diagram
VCC
Status
Register
GND
Memory Array
65,536 x 8
Address
Decoder
Data
Register
Output
Buffer
SI
CS
WP
SCK
Mode
Decode
Logic
Clock
Generator
SO
HOLD
AT25512 [DATASHEET]
Atmel-5165J-SEEPROM-AT25512-Datasheet_012015
3
4.
Electrical Specifications
Table 4-1.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25C, f = 1.0MHz, VCC = 5.0V (unless otherwise noted).
Symbol
Test Conditions
COUT
CIN
Note:
1.
Table 4-2.
Max
Units
Conditions
Output Capacitance (SO)
8
pF
VOUT = 0V
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
VIN = 0V
This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = 1.8V to 5.5V, (unless otherwise noted).
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Max
Units
1.8
5.5
V
Supply Voltage
2.7
5.5
V
VCC3
Supply Voltage
4.5
5.5
V
ICC1
Supply Current
VCC = 5.0V at 20MHz,
SO = Open, Read
9.0
10.0
mA
ICC2
Supply Current
VCC = 5.0V at 10MHz,
SO = Open, Read, Write
5.0
7.0
mA
ICC3
Supply Current
VCC = 5.0V at 1MHz,
SO = Open, Read, Write
2.2
3.5
mA
ISB1
Standby Current
VCC = 1.8V, CS = VCC
0.2
3.0
μA
ISB2
Standby Current
VCC = 2.7V, CS = VCC
0.5
3.0
μA
ISB3
Standby Current
VCC = 5.0V, CS = VCC
2.0
5.0
μA
IIL
Input Leakage
VIN = 0V to VCC
-3.0
3.0
μA
IOL
Output Leakage
VIN = 0V to VCC, TAC = 0C to 70C
-3.0
3.0
μA
VIL(1)
Input Low-voltage
-1.0
VCC x 0.3
V
VIH(1)
Input High-voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low-voltage
0.4
V
VOH1
Output High-voltage
VOL2
Output Low-voltage
VOH2
Output High-voltage
Note:
4
1.
Test Condition
3.6  VCC  5.5V
1.8V  VCC  3.6V
Min
IOL = 3.0mA
IOH = 1.6mA
VIL min and VIH max are reference only and are not tested.
AT25512 [DATASHEET]
Atmel-5165J-SEEPROM-AT25512-Datasheet_012015
VCC -0.8
IOL = 0.15mA
IOH = 100μA
Typ
V
0.2
VCC -0.2
V
V
Table 4-3.
AC Characteristics
Applicable over recommended operating range from TAI = -40C to + 85C, VCC = As Specified, CL = 1 TTL Gate and 30pF
(unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
fSCK
SCK Clock Frequency
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
0
0
0
20
10
5
MHz
tRI
Input Rise Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
2
2
2
μs
tFI
Input Fall Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
2
2
2
μs
tWH
SCK High Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
20
40
80
ns
tWL
SCK Low Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
20
40
80
ns
tCS
CS High Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
100
100
200
ns
tCSS
CS Setup Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
100
100
200
ns
tCSH
CS Hold Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
100
100
200
ns
tSU
Data In Setup Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
5
10
20
ns
tH
Data In Hold Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
5
10
20
ns
tHD
Hold Setup Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
5
10
20
ns
tCD
Hold Hold Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
5
10
20
ns
tV
Output Valid
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
0
0
0
tHO
Output Hold Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
0
0
0
20
40
80
ns
ns
AT25512 [DATASHEET]
Atmel-5165J-SEEPROM-AT25512-Datasheet_012015
5
Table 4-3.
AC Characteristics (Continued)
Applicable over recommended operating range from TAI = -40C to + 85C, VCC = As Specified, CL = 1 TTL Gate and 30pF
(unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
tLZ
Hold to Output Low Z
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
0
0
0
25
50
100
ns
tHZ
Hold to Output High Z
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
25
50
100
ns
tDIS
Output Disable Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
25
50
100
ns
tWC
Write Cycle Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
5
5
5
ms
Endurance(1)
5.0V, 25C, Page Mode
Note:
5.
1.
1,000,000
Write Cycles
This parameter is characterized and is not 100% tested. Contact Atmel for further information.
Serial Interface Description
Master: The device that generates the serial clock.
Slave: Because the Serial Clock pin (SCK) is always an input, AT25512 always operates as a slave.
Transmitter/Receiver: AT25512 has separate pins designated for data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
Serial Opcode: After the device is selected with CS going low, the first byte will be received. This byte contains
the opcode that defines the operations to be performed.
Invalid Opcode: If an invalid opcode is received, no data will be shifted into AT25512, and the Serial Output pin
(SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the
serial communication.
Chip Select: AT25512 is selected when the CS pin is low. When the device is not selected, data will not be
accepted via the SI pin, and the SO pin will remain in a high impedance state.
Hold: The HOLD pin is used in conjunction with the CS pin to select AT25512. When the device is selected and
a serial sequence is underway, Hold can be used to pause the serial communication with the master device
without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle
during Hold). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.
Write Protect: The Write Protect pin (WP) will allow normal read/write operations when held high. When the
WP pin is brought low, and WPEN bit is one, all write operations to the status register are inhibited. WP going
low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been
initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is
blocked when the WPEN bit in the status register is zero. This will allow the user to install the AT25512 device in
a system with the WP pin tied to ground, and still be able to write to the status register. All WP pin functions are
enabled when the WPEN bit is set to one.
6
AT25512 [DATASHEET]
Atmel-5165J-SEEPROM-AT25512-Datasheet_012015
Figure 5-1.
SPI Serial Interface
Master:
Microcontroller
Data Out (MOSI)
Data In (MISO)
Serial Clock (SPI CK)
SS0
SS1
SS2
SS3
Slave:
AT25512
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
AT25512 [DATASHEET]
Atmel-5165J-SEEPROM-AT25512-Datasheet_012015
7
6.
Functional Description
The AT25512 is designed to interface directly with the Synchronous Serial Peripheral Interface (SPI) of the 6800
type series of microcontrollers.
The AT25512 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained
in Table 7-3. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low
CS transition.
Table 6-1.
Instruction Set For AT25512
Instruction Name
Instruction Format
Operation
WREN
0000 X110
Set Write Enable Latch
WRDI
0000 X100
Reset Write Enable Latch
RDSR
0000 X101
Read Status Register
WRSR
0000 X001
Write Status Register
READ
0000 X011
Read Data from Memory Array
WRITE
0000 X010
Write Data to Memory Array
Write Enable (WREN): The device will power-up in the write disable state when VCC is applied. All
programming instructions must therefore be preceded by a Write Enable instruction.
Write Disable (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables
all programming modes. The WRDI instruction is independent of the status of the WP pin.
Read Status Register (RDSR): The Read Status Register instruction provides access to the status register.
The ready/busy and write enable status of the device can be determined by the RDSR instruction. Similarly, The
Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 6-2.
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
Table 6-3.
Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = 0 (RDY) indicates the device is ready.
Bit 0 = 1 indicates the write cycle is in progress.
Bit 1 (WEN)
Bit 1 = 0 indicates the device is not write enabled. Bit 1 = 1 indicates the device is write enabled.
Bit 2 (BP0)
See Table 6-4 on page 9.
Bit 3 (BP1)
See Table 6-4 on page 9.
Bits 4  6 are zeros when the device is not in an internal write cycle.
Bit 7 (WPEN)
See Table 6-5 on page 9.
Bits 0  7 are ones during an internal write cycle.
8
AT25512 [DATASHEET]
Atmel-5165J-SEEPROM-AT25512-Datasheet_012015
Write Status Register (WRSR): The WRSR instruction allows the user to select one of four levels of protection.
AT25512 is divided into four array segments:
None or
Top quarter (¼) or
Top half (½) or
All of the memory segments can be protected




Any of the data within any selected segment will therefore be read only. The block write protection levels and
corresponding status register control bits are shown in Table 6-4.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the
regular memory cells (e.g. WREN, tWC, RDSR).
Table 6-4.
Block Write Protect Bits
Status Register Bits
Array Addresses Protected
Level
BP1
BP0
AT25512
0
0
0
None
1(¼)
0
1
C000h – FFFFh
2(½)
1
0
8000h – FFFFh
3(All)
1
1
0000h – FFFFh
The WRSR instruction also allows the user to enable or disable the Write Protect (WP) pin through the use of
the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the
WPEN bit is one. Hardware Write Protection is disabled when either the WP pin is high or the WPEN bit is zero.
When the device is Hardware Write Protected, writes to the Status Register, including the Block Protect bits and
the WPEN bit, and the Block Protect sections in the memory array are disabled. Writes are only allowed to
sections of the memory which are not block protected.
Note:
When the WPEN bit is hardware write protected, it cannot be changed back to zero, as long as the WP
pin is held low.
Table 6-5.
WPEN Operation
WPEN
WP
WEN
Protected Blocks
Unprotected Blocks
Status Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
AT25512 [DATASHEET]
Atmel-5165J-SEEPROM-AT25512-Datasheet_012015
9
Read Sequence (READ): Reading the AT25512 via the SO pin requires the following sequence. After the CS
line is pulled low to select a device, the Read op-code is transmitted via the SI line followed by the byte address
to be read (see Table 6-6). Upon completion, any data on the SI line will be ignored. The data (D7 – D0) at the
specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven
high after the data comes out. The read sequence can be continued since the byte address is automatically
incremented and data will continue to be shifted out. When the highest address is reached, the address counter
will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle.
Write Sequence (WRITE): In order to program the AT25512, two separate instructions must be executed.
First, the device must be write enabled via the Write Enable (WREN) Instruction. Then a Write instruction may
be executed. Also, the address of the memory location(s) to be programmed must be outside the protected
address field location selected by the block write protection level. During an internal write cycle, all commands
will be ignored except the RDSR instruction.
A write instruction requires the following sequence. After the CS line is pulled low to select the device, the Write
opcode is transmitted via the SI line followed by the byte address and the data (D7 – D0) to be programmed
(see Table 6-6). Programming will start after the CS pin is brought high. (The low-to-high transition of the CS pin
must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.
The ready/busy status of the device can be determined by initiating a Read Status Register (RDSR) instruction.
If Bit 0 = 1, the write cycle is still in progress. If Bit 0 = 0, the write cycle has ended. Only the Read Status
Register instruction is enabled during the write programming cycle.
The AT25512 is capable of a 128-byte Page Write operation. After each byte of data is received, the seven low
order address bits are internally incremented by one; the high order bits of the address will remain constant. If
more than 128 bytes of data are transmitted, the address counter will roll over and the previously written data
will be overwritten. AT25512 is automatically returned to the write disable state at the completion of a write
cycle.
Note:
If the device is not Write Enabled (WREN), the device will ignore the Write instruction and will return to
the standby state, when CS is brought high. A new CS falling edge is required to re-initiate the serial
communication.
Table 6-6.
10
Address Key
Address
AT25512
AN
A15  A0
AT25512 [DATASHEET]
Atmel-5165J-SEEPROM-AT25512-Datasheet_012015
7.
Timing Diagrams (SPI Mode 0 (0, 0))
Figure 7-1.
Synchronous Data Timing
tCS
VIH
CS
VIL
tCSS
tCSH
VIH
tWH
SCK
tWL
VIL
tSU
tH
VIH
SI
Valid In
VIL
tV
VOH
tDIS
HI-Z
HI-Z
SO
tHO
VOL
Figure 7-2.
WREN Timing
CS
SCK
SI
WREN Opcode
HI-Z
SO
Figure 7-3.
WRDI Timing
CS
SCK
SI
SO
WRDI Opcode
HI-Z
AT25512 [DATASHEET]
Atmel-5165J-SEEPROM-AT25512-Datasheet_012015
11
Figure 7-4.
RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
Instruction
Data Out
High-impedance
SO
7
6
5
4
3
2
1
0
8
9
10
11
12
13
14
15
MSB
Figure 7-5.
WRSR Timing
CS
0
1
2
3
4
5
6
7
SCK
Data In
SI
6
5
4
3
2
1
0
High-impedance
SO
Figure 7-6.
7
Instruction
Read Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
Byte Address
SI
Instruction
15 14 13
...
3
2
1
0
Data Out
SO
High-impedance
7
MSB
12
AT25512 [DATASHEET]
Atmel-5165J-SEEPROM-AT25512-Datasheet_012015
6
5
4
3
2
1
0
Figure 7-7.
Write Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
Byte Address
SI
SO
Figure 7-8.
Instruction
15 14 13
...
3
2
Data Out
1
0
7
6
5
4
3
2
1
0
High-impedance
Hold Timing
CS
tHDN
tHDN
SCK
tHDS
tHDS
HOLD
tHZ
SO
tLZ
AT25512 [DATASHEET]
Atmel-5165J-SEEPROM-AT25512-Datasheet_012015
13
8.
Part Marking Scheme
AT25512: Package Marking Information
8-lead TSSOP
8-lead SOIC
8-lead DFN
6.0 x 4.9 mm Body
ATHYWW
5F 1 @
AAAAAAA
ATMLHYWW
5F 1
@
AAAAAAAA
Note 1:
ATMLHYWW
5F 1
@
AAAAAAAA
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT25512
Truncation Code ###:5F
Date Codes
Y = Year
2: 2012
3: 2013
4: 2014
5: 2015
Voltages
6: 2016
7: 2017
8: 2018
9: 2019
M = Month
A: January
B: February
...
L: December
WW = Work Week of Assembly
02: Week 2
04: Week 4
...
52: Week 52
Country of Assembly
Lot Number
@ = Country of Assembly
AAA...A = Atmel Wafer Lot Number
Trace Code
% = Minimum Voltage
1: 1.8V min
Grade/Lead Finish Material
H: Industrial/NiPdAu
Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code)
Example: AA, AB.... YZ, ZZ
AT: Atmel
ATM: Atmel
ATML: Atmel
8/21/12
TITLE
25512SM, AT25512 Standard Package Marking Information
Package Mark Contact:
[email protected]
14
AT25512 [DATASHEET]
Atmel-5165J-SEEPROM-AT25512-Datasheet_012015
DRAWING NO.
REV.
25512SM
C
9.
Ordering Code Detail
AT 2 5 5 1 2 x x - Y H - T
Atmel Designator
Shipping Carrier Option
B = Bulk (Tubes)
T = Tape and Reel, Standard Quantity Option
Product Family
25 = Standard SPI
Serial EEPROM
Device Density
512 = 512 kilobit
Product Variation
xx = Applies to select packages only.
See ordering code table for
variation details.
Package Device Grade or
Wafer/Die Thickness
H = Green, NiPdAu Lead Finish
Industrial Temperature Range
(-40°C to +85°C)
11 = 11mil Wafer Thickness
Package Option
S
T
Y
W
= JEDEC SOIC
= TSSOP
= UDFN
= Wafer Unsawn
AT25512 [DATASHEET]
Atmel-5165J-SEEPROM-AT25512-Datasheet_012015
15
10.
Ordering Information
Delivery Information
Atmel Ordering Code
Lead Finish
Package
AT25512N-SH-B
Form
Quantity
Bulk (Tubes)
100 per Tube
Tape and Reel
4,000 per Reel
Bulk (Tubes)
100 per Tube
Tape and Reel
5,000 per Reel
Tape and Reel
5,000 per Reel
Operation
Range
8S1
AT25512N-SH-T
AT25512-TH-B
NiPdAu
(Lead-free/Halogen-free)
8X
AT25512-TH-T
AT25512Y7-YH-T
AT25512-W-11(1)
Note:
1.
8Y7
N/A
Wafer Sale
Industrial
Temperature
(-40C to 85C)
Note 1
Available in waffle pack, tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die
available upon request. Please contact Atmel for more details.
Package Type
16
8S1
8-lead, 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8X
8-lead, 4.4mm body, Plastic Thin Shrink Small Outline Package (TSSOP)
8Y7
8-pad, 6.0x4.9mm body, 1.27mm pitch, UltraThin SAP, Dual No Lead Package (Sawn) (UDFN)
AT25512 [DATASHEET]
Atmel-5165J-SEEPROM-AT25512-Datasheet_012015
11.
Packaging Information
11.1
8S1 — 8-lead JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
SYMBOL MIN
A
1.35
NOM
MAX
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
6/22/11
Package Drawing Contact:
[email protected]
TITLE
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
GPC
SWB
DRAWING NO.
REV.
8S1
G
AT25512 [DATASHEET]
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17
11.2
8X — 8-lead TSSOP
C
1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
A
b
A1
e
D
SYMBOL
Side View
Notes:
COMMON DIMENSIONS
(Unit of Measure = mm)
A2
1. This drawing is for general information only.
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
MIN
NOM
MAX
A
-
-
1.20
A1
0.05
-
0.15
A2
0.80
1.00
1.05
D
2.90
3.00
3.10
2, 5
E
NOTE
6.40 BSC
E1
4.30
4.40
4.50
3, 5
b
0.19
0.25
0.30
4
e
L
0.65 BSC
0.45
L1
C
0.60
0.75
1.00 REF
0.09
-
0.20
2/27/14
TITLE
Package Drawing Contact:
[email protected]
18
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
AT25512 [DATASHEET]
Atmel-5165J-SEEPROM-AT25512-Datasheet_012015
GPC
TNR
DRAWING NO.
8X
REV.
E
8Y7 — 8-pad UDFN
PIN 1 INDEX AREA
A
PIN 1 ID
D1
11.3
D
E1
L
A1
E
e
b
e1
A
COMMON DIMENSIONS
(Unit of Measure = mm)
Note: Soldering the large thermal pad is
optional, but not recommended.
No electrical connection is accomplished
to the device through this pad, so if soldered
it should be tied to ground.
SYMBOL
MIN
NOM
MAX
A
–
–
0.60
A1
0.00
–
0.05
D
5.80
6.00
6.20
E
4.70
4.90
5.10
D1
3.30
3.40
3.50
E1
3.90
4.00
4.10
b
0.35
0.40
0.45
e
1.27 TYP
e1
3.81 REF
L
Package Drawing Contact:
[email protected]
0.50
0.60
NOTE
0.70
TITLE
GPC
8Y7, 8-lead 6.0x4.9mm body, 1.27mm pitch,
UltraThin SAP, Dual No Lead Package (Sawn)(UDFN)
YAF
11/21/08
DRAWING NO. REV.
8Y7
AT25512 [DATASHEET]
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D
19
12.
Revision History
Doc. Rev.
Date
Comments
5165J
01/2015
5165I
07/2013
5165H
08/2012
5165G
09/2009
Updated Part Marking Scheme.
5165F
03/2009
Changed Maximum Operating Voltage from 4.3V to 6.25V in the Absolute Maximum Ratings
Table on page 2.
5165E
08/2008
Updated for 1.8V - 5.5V operation.
5165D
05/2008
Added part marking diagram information.
5165C
08/2007
Updated the 8X package outline drawing and the ordering information section.
Correct ordering code table from 8A2 to 8X package option.
Updated footers and disclaimer page.
Updated part markings and package drawings.
Updated template.
Changed address bit number to seven on page 9.
Removed Preliminary status.
Changed spacing on table notes.
5165B
06/2007
Reworked figure 4-8.
Updated to new template.
Changed status to Preliminary.
5165A
20
01/2007
Initial document release.
AT25512 [DATASHEET]
Atmel-5165J-SEEPROM-AT25512-Datasheet_012015
XXXXXX
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© 2015 Atmel Corporation. / Rev.: Atmel-5165J-SEEPROM-AT25512-Datasheet_012015.
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