ATF16V8C - Complete

ATF16V8C
High Performance Electrically-Erasable PLD
DATASHEET
Features

Industry Standard Architecture
Emulates Many 20-pin PALs®
Low-cost, Easy to Use Software Tools
̶
̶

High Speed Electrically-Erasable Programmable Logic Devices (EE PLD)
̶
5ns Maximum Pin-to-pin Delay

Low Power, 100μA Pin Controlled Power-down Mode Option
CMOS and TTL Compatible Inputs and Outputs

Advanced Flash Technology

̶
̶
Input and I/O Pin Keeper Circuits
̶
Reprogrammable
100% Tested

High Reliability CMOS Process
̶
̶
̶
̶




20 Year Data Retention
100 Erase/Write Cycles
2,000V ESD Protection
200mA Latchup Immunity
Commercial and Industrial Temperature Ranges
Dual-in-line and Surface Mount Packages in Standard Pinouts
PCI Compliant
Green (ROHS Compliant) Package Options Available
Description
The Atmel® ATF16V8C is a high performance EECMOS Programmable Logic Device
(PLD) which utilizes the Atmel proven Electrically-Erasable (EE) Flash memory
technology. Offered options include speeds down to 5ns and a 100μA pin-controlled
power-down mode. All speed ranges are specified over the full 5V ± 10% range for
industrial temperature range, and 5V ± 5% for commercial range 5V devices.
The ATF16V8C incorporates a super set of the generic architectures, which allows
direct replacement of the 16R8 family and most 20-pin combinatorial PLDs. Eight
outputs are each allocated eight product terms. Three different modes of operation
are configured automatically with software and allow highly complex logic functions to
be realized.
The ATF16V8C can significantly reduce total system power, thereby enhancing
system reliability and reducing power supply costs. When Pin 4 is configured as
the power-down control pin, supply current drops to less than 100μA whenever
the pin is high. If the power-down feature isn't required for a particular application,
Pin 4 may be used as a logic input. Also, the pin-keeper circuits eliminate the
need for external pull-up resistors along with their attendant power consumption.
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
Pin Configurations and Pinouts
Pin Configurations and Pinouts
Function
CLK
Clock
I
Logic Inputs
I/O
Bidirectional Buffers
OE
Output Enable
20-lead PDIP
(Top View)
(Top View)
GND
Ground
2.
19
1
20
16
6
15
7
8
14
I8
GND
I9/OE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/CLK
I1
I2
PD/I3
I4
I5
I6
I7
I8
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE
Block Diagram
Figure 2-1.
Block Diagram
10 Input Pins (1)
Note:
2
2
17
13
Power-Down
18
5
9
PD
4
12
+5V Supply
PD/I3
I4
I5
I6
I7
11
VCC
20-lead PLCC
I2
I1
I/CLK
VCC
I/O
Pin
3
Figure 1-1.
10
1.
1.
Programmable
Interconnect
and
Combinatorial
Logic Array
Includes optional PD control pin.
ATF16V8C [DATASHEET]
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
Logic
Option
(Up to 8 Flip-flops)
8 I/O Pins
3.
Electrical Characteristics
3.1
Absolute Maximum Ratings*
*Notice: Stresses beyond those listed under “Absolute
maximum ratings” may cause permanent
damage to the device. This is a stress rating
only, and functional operation of the device at
these or any other conditions beyond those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect device reliability.
Temperature Under Bias . . . . . . . . . . . . . . . . -40C to +85C
Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C
Voltage on Any Pin with Respect
to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to +7.0V(1)
Voltage on Input Pins with Respect
to Ground During Programming . . . . . . . . . -2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground . . . . . . . . . . . . . . . . . . . -2.0V to +14.0V(1)
Note:
3.2
1.
Pin Capacitance
Table 3-1.
Pin Capacitance
Typ
Max
Units
Conditions
CIN
5
8
pF
VIN = 0V
COUT
6
8
pF
VOUT = 0V
Note:
3.3
Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20ns. Maximum output
pin voltage is VCC + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20ns.
1.
Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
DC and AC Operating Conditions
Table 3-2.
DC and AC Operating Conditions
Operating Temperature (Ambient)
VCC Power Supply
Commercial
Industrial
0C to 70C
-40C to 85C
5V ± 5%
5V ± 10%
ATF16V8C [DATASHEET]
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
3
3.4
DC Characteristics
Figure 3-1.
Symbol
Parameter
Condition
Max
Units
IIL
Input or
I/O Low Leakage Current
0  VIN  VIL (Max)
-10.0
μA
IIH
Input or
I/O High Leakage Current
3.5  VIN  VCC
10.0
μA
ICC1(1)
Power Supply Current,
Standby
15MHz, VCC = Max,
VIN = 0, VCC, Outputs Open
Com.
115
mA
Ind.
130
mA
IPD
Power Supply Current,
Power-down Mode
VCC = Max, VIN = 0, VCC
IOS
Output Short Circuit Current
VOUT = 0.5V;
VCC = 5V; TA = 25°C
VIL
Input Low Voltage
Min < VCC < Max
VIH
Input High Voltage
VOL
Output Low Voltage
VCC = Min; All Outputs
IOL = 24mA
VOH
Output High Voltage
VCC = Min
IOL = -4.0mA
IOL
Output Low Current
VCC = Min
IOH
Output High Current
VCC = Min
Note:
4
DC Characteristics
1.
All ICC parameters measured with outputs open.
ATF16V8C [DATASHEET]
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
Min
Typ
Com.
10
100
μA
Ind.
10
105
μA
-150
mA
-0.5
0.8
V
2.0
VCC + 1
V
0.5
V
Com., Ind.
2.4
V
Com.
24.0
mA
Ind.
12.0
mA
Com., Ind.
-4.0
mA
3.5
AC Characteristics
Table 3-3.
AC Characteristics
-5
-7
Symbol
Parameter
tPD
Input or Feedback to Non-registered Output
tCF
Clock to Feedback
tCO
Clock to Output
1
tS
Input or Feedback Setup Time
3
5
ns
tH
Input Hold Time
0
0
ns
tP
Clock Period
6
8
ns
tW
Clock Width
3
4
ns
fMAX
Min
Max
Min
Max
Units
1
5
3
7.5
ns
3
ns
5
ns
3
4
2
External Feedback 1/(tS + tCO)
142
100
MHz
Internal Feedback 1/(tS + tCF)
166
125
MHz
No Feedback 1/(tP)
166
125
MHz
tEA
Input to Output Enable – Product Term
2
6
3
9
ns
tER
Input to Output Disable – Product Term
2
5
2
9
ns
tPZX
OE Pin to Output Enable
2
5
2
6
ns
tPXZ
OE Pin to Output Disable
1.5
5
1.5
6
ns
Figure 3-2.
AC Waveforms
Inputs, I/O
Reg. Feedback
tS
tH
tW
CLK
tW
tP
tER, tPXZ
tCO
Registered
Outputs
Combinatorial
Outputs
Note:
1.
HIGH Z
Output
Valid
tPD
tEA, tPZX
tEA, tPZX
tER, tPXZ
Output
Valid
Output
Valid
Output
Valid
HIGH Z
Output
Valid
Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
ATF16V8C [DATASHEET]
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
5
3.6
Power-up Reset
Registers of the ATF16V8C are designed to reset during power-up. At a point delayed slightly from VCC crossing
VRST, all registers will be reset to the low state. As a result, the registered output state will always be high on
power-up.
This feature is critical for state machine initialization; however, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the following conditions are required:
1.
2.
3.
The VCC rise must be monotonic, from below 0.7V.
After reset occurs, all input and feedback setup times must be met before driving the clock term high.
The signals from which the clock is derived must remain stable during tPR.
Figure 3-3.
Power
Power-up Reset
VRST
tPR
Registered
Outputs
tS
tW
Clock
Table 3-4.
6
Power-up Reset Parameters
Parameter
Description
Typ
Max
Units
tPR
Power-up Reset Time
600
1,000
ns
VRST
Power-up Reset Voltage
3.8
4.5
V
ATF16V8C [DATASHEET]
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
3.7
Power-down Mode
The ATF16V8C includes an optional pin controlled power-down feature. Device Pin 4 can be configured as the
power-down pin. When this feature is enabled and the power-down pin is high, total current consumption drops
to less than 100μA. In the power-down mode, all output data and internal logic states are latched and held. All
registered and combinatorial output data remains valid. Any outputs that were in a high-Z state at the onset of
power-down will remain at high-Z. During power-down, all input signals except the power-down pin are blocked.
The input and I/O pin-keeper circuits remain active to insure that pins do not float to indeterminate levels. This
helps to further reduce system power.
Selection of the power-down option is specified in the ATF16V8C logic design file. The logic compiler will
include this option selection in the otherwise standard 16V8 JEDEC fuse file. When the power-down feature is
not specified in the design file, Pin 4 is available as a logic input, and there is no power-down pin. This allows
the ATF16V8C to be programmed using any existing standard 16V8 fuse file.
Note:
3.7.1
Some programmers list the JEDEC-compatible 16V8C (No PD used) separately from the non-JEDEC
compatible 16V8CEXT (EXT for extended features).
Power-down AC Characteristics
Table 3-5.
Power-down AC Characteristics(1)(2)(3)
-5
-7
Symbol
Parameter
Min
tIVDH
Valid Input Before PD High
5.0
7.5
ns
tGVDH
Valid OE Before PD High
0
0
ns
tCVDH
Valid Clock Before PD High
0
0
ns
tDHIX
Input Don’t Care After PD High
5.0
7.5
ns
tDHGX
OE Don’t Care After PD High
5.0
7.5
ns
tDHCX
Clock Don’t Care After PD High
5.0
7.5
ns
tDLIV
PD Low to Valid Input
5.0
7.5
ns
tDLGV
PD Low to Valid OE
15.0
20.0
ns
tDLCV
PD Low to Valid Clock
15.0
20.0
ns
tDLOV
PD Low to Valid Output
20.0
25.0
ns
Notes:
1.
2.
3.
Max
Min
Max
Units
Output data is latched and held.
HI-Z outputs remain HI-Z.
Clock and input transitions are ignored.
ATF16V8C [DATASHEET]
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
7
3.8
Input Test Waveforms and Measurement Levels
3.0V
AC
Driving
Levels
1.5V
AC
Measurement
Level
0.0V
Note:
3.9
tR, tF < 1.5ns (10% to 90%)
Output Test Loads
5.0V
R1 = 200Ω
Output
Pin
R2 = 200Ω
4.
CL = 50pF
Registered Output Preload
Registers of the ATF16V8C are provided with circuitry to allow loading of each register with either a high or a
low. This feature will simplify testing since any state can be forced into the registers to control test sequencing.
A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the
JEDEC file preload sequence will be done automatically by approved programmers.
5.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF16V8C fuse patterns. Once programmed,
fuse verify and preload are inhibited; however, the 64-bit user signature remains accessible.
The security fuse will be programmed last, as its effect is immediate.
8
ATF16V8C [DATASHEET]
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
6.
Input and I/O Pin-keeper Circuits
The ATF16V8C contains internal input and I/O pin-keeper circuits. These circuits allow each ATF16V8C pin to
hold its previous value even when it is not being driven by an external source or by the device’s output buffer.
This helps insure that all logic array inputs are at known, valid logic levels. This reduces system power by
preventing pins from floating to indeterminate levels. By using pin-keeper circuits rather than pull-up resistors,
there is no DC current required to hold the pins in either logic state (high or low).
These pin-keeper circuits are implemented as weak feedback inverters, as shown in the Input Diagram below.
These keeper circuits can easily be over driven by standard TTL- or CMOS-compatible drivers. The typical
overdrive current required is 40μA.
Figure 6-1.
Input Diagram
VCC
100K
Input
ESD
Protection
Circuit
Figure 6-2.
I/O Diagram
VCC
OE
I/O
Data
VCC
Input
100K
ATF16V8C [DATASHEET]
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
9
7.
Functional Logic Diagram Description
The logic option and functional diagrams describe the ATF16V8C architecture. Eight configurable macrocells
can be configured as a registered output, combinatorial I/O, combinatorial output, or dedicated input.
The ATF16V8C can be configured in one of three different modes. Each mode makes the ATF16V8C look like a
different device. Most PLD compilers can choose the right mode automatically. The user can also force the
selection by supplying the compiler with a mode selection. The determining factors would be the usage of
register versus combinatorial outputs and dedicated outputs versus outputs with output enable control.
The ATF16V8C universal architecture can be programmed to emulate many 20-pin PAL devices. These
architectural subsets can be found in each of the configuration modes described in the following pages. The
user can download the listed subset device JEDEC programming file to the PLD programmer, and the
ATF16V8C can be configured to act like the chosen device. Check with your programmer manufacturer for this
capability.
Unused product terms are automatically disabled by the compiler to decrease power consumption. A security
fuse, when programmed, protects the content of the ATF16V8C. Eight bytes (64 fuses) of user signature are
accessible to the user for purposes such as storing project name, part number, revision, or date. The user
signature is accessible regardless of the state of the security fuse.
Table 7-1.
Compiler Mode Selection
Registered
CUPL, Atmel-CUPL
With PD ENABLE
10
ATF16V8C [DATASHEET]
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
Complex
Simple
Auto select
G16V8MS
G16V8MA
G16V8AS
G16V8A
G16V8CPMS
G16V8CPMA
G16V8CPAS
G16V8CP
8.
Macrocell Configuration
Software compilers support the three different OMC modes as different device types. These device types are
listed in the table below. Most compilers have the ability to automatically select the device type, generally based
on the register usage and output enable (OE) usage. Register usage on the device forces the software to
choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose the simple mode only when all outputs are
dedicated combinatorial without OE control. The different device types listed in the table can be used to override
the automatic device selection by the software. For further details, refer to the compiler software manuals.
When using compiler software to configure the device, the user must pay special attention to the following
restrictions in each mode.
In Registered mode, Pin 1 and Pin 11 are permanently configured as clock and output enable, respectively.
These pins cannot be configured as dedicated inputs in the registered mode.
In Complex mode, Pin 1 and Pin 11 become dedicated inputs and use the feedback paths of Pin 19 and Pin 12
respectively. Because of this feedback path usage, Pin 19 and Pin 12 do not have the feedback option in this
mode.
In simple mode, all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two
inner most pins (pins 15 and 16) will not have the feedback option as these pins are always configured as
dedicated combinatorial output.
8.1
ATF16V8C Registered Mode
PAL device emulation/PAL replacement. The registered mode is used if one or more registers are required.
Each macrocell can be configured as either a registered or combinatorial output or I/O, or as an input. For a
registered output or I/O, the output is enabled by the OE pin, and the register is clocked by the CLK pin. Eight
product terms are allocated to the sum term. For a combinatorial output or I/O, the output enable is controlled by
a product term, and seven product terms are allocated to the sum term. When the macrocell is configured as an
input, the output enable is permanently disabled.
Any register usage will make the compiler select this mode. The following registered devices can be emulated
using this mode:

16R8

16RP8

16R6

16RP6

16R4

16RP4
ATF16V8C [DATASHEET]
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
11
Figure 8-1.
Registered Configuration for Registered Mode(1)(2)
CLK
D
XOR
Q
Q
OE
Notes:
1.
2.
Figure 8-2.
Pin 1 controls common CLK for the registered outputs.
Pin 11 controls common OE for the registered outputs.
Pin 1 and Pin 11 are permanently configured as CLK and OE.
The development software configures all the architecture control bits and checks for proper pin usage
automatically.
Combinatorial Configuration for Registered Mode(1)(2)
XOR
Notes:
12
1.
2.
Pin 1 and Pin 11 are permanently configured as CLK and OE.
The development software configures all the architecture control bits and checks for proper pin usage
automatically.
ATF16V8C [DATASHEET]
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
Figure 8-3.
Registered Mode Logic Diagram
CLK
1
Input Lines
0
4
8
12
16
20
24
28
Output
Logic
19
Output
Logic
18
Output
Logic
17
Output
Logic
16
Output
Logic
15
Output
Logic
14
Output
Logic
13
Output
Logic
12
2
3
4
5
6
7
8
9
11
Note:
1.
Input not available if power-down mode is enabled.
ATF16V8C [DATASHEET]
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
13
9.
ATF16V8C Complex Mode
PAL device emulation/PAL replacement. In the complex mode, combinatorial output and I/O functions are
possible. Pins 1 and 11 are regular inputs to the array. Pins 13 through 18 have pin feedback paths back to the
AND-array, which makes full I/O capability possible. Pins 12 and 19 (outermost macrocells) are outputs only.
They do not have input capability. In this mode, each macrocell has seven product terms going to the sum term
and one product term enabling the output.
Combinatorial applications with an OE requirement will make the compiler select this mode. The following
devices can be emulated using this mode:



16L8
16H8
16P8
Figure 9-1.
Complex Mode Option
0
1
7
XOR
Pins 12 and 19 do not have this feedback path.
10.
ATF16V8C Simple Mode
PAL device emulation/PAL replacement. In the simple mode, eight product terms are allocated to the sum
term. Pins 15 and 16 (center macrocells) are permanently configured as combinatorial outputs. Other
macrocells can be either inputs or combinatorial outputs with pin feedback to the AND-array. Pins 1 and 11 are
regular inputs.
The compiler selects this mode when all outputs are combinatorial without OE control. The following simple
PALs can be emulated using this mode:




10L8 10H8 10P8
12L6 12H6 12P6
14L4 14H4 14P4
16L2 16H2 16P2
Figure 10-1.
Simple Mode Option
VCC
0
1
0
7
XOR
Pins 15 and 16 do not have this feedback path.
* Pins 15 and 16 are always enabled.
14
ATF16V8C [DATASHEET]
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
S1*
Figure 10-2.
Complex Mode Logic Diagram
1
Input Lines
0
4
8
12
16
20
24
28
Output
Logic
19
Output
Logic
18
Output
Logic
17
Output
Logic
16
Output
Logic
15
Output
Logic
14
Output
Logic
13
Output
Logic
12
2
3
4
5
6
7
8
9
11
Note:
1.
Input not available if power-down mode is enabled.
ATF16V8C [DATASHEET]
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
15
Figure 10-3.
Simple Mode Logic Diagram
1
Input Lines
0
4
8
12
16
20
24
28
Output
Logic
19
Output
Logic
18
Output
Logic
17
Output
Logic
16
Output
Logic
15
Output
Logic
14
Output
Logic
13
Output
Logic
12
2
3
4
5
6
7
8
11
9
Note:
16
1.
Input not available if power-down mode is enabled.
ATF16V8C [DATASHEET]
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ATF16V8C [DATASHEET]
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18
ATF16V8C [DATASHEET]
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ATF16V8C [DATASHEET]
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
19
11.
Ordering Information
11.1
Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD (ns)
tS (ns)
tCO (ns)
Ordering Code
Package
Operation Range
5
3
4
ATF16V8C-5JX
20J
Commercial
(0C to 70C)
7.5
5
5
ATF16V8C-7JU
20J
ATF16V8C-7PU
20P3
Package type
20J
20P3
20
20-lead, Plastic J-leaded Chip Carrier (PLCC)
20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
ATF16V8C [DATASHEET]
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
Industrial
(-40C to 85C)
12.
Package Drawings
12.1
20J — 20-lead PLCC
PIN NO. 1
1.14(0.045) X 45°
1.14(0.045) X 45°
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
e
E1
E
D2/E2
B1
B
A2
D1
A1
D
A
0.51(0.020)MAX
45° MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102mm) maximum
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
9.779
–
10.033
D1
8.890
–
9.042
E
9.779
–
10.033
E1
8.890
–
9.042
D2/E2
7.366
–
8.382
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
Package Drawing Contact:
[email protected]
TITLE
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO. REV.
20J
ATF16V8C [DATASHEET]
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
B
21
12.2
20P3 — 20-lead PDIP
20
11
E1
1
10
D
E
e
See
Lead Detail
A2 A
BASE PLANE
-CSEATING PLANE
C
L
A1
b
GAGE
PLANE
eA
L
b2
.015
j 0.10 m C
c
eB
Z Z
COMMON DIMENSIONS
(UNIT OF MEASURE=MM)
eC
Lead Detail
Notes:
1. This package conforms to JEDEC reference MS-001,
Variation AD.
2. Dimensions D and E1 do not include mold Flash or
Protrusion. Mold Flash or Protrusion shall not exceed
0.25 mm (0.010").
Symbol
A
A1
A2
b
b2
c
D
E
E1
L
e
eA
eB
eC
Min.
0.381
2.921
0.356
1.143
0.203
24.892
7.620
6.096
2.921
0.000
Nom.
3.302
0.457
1.524
0.254
26.162
7.874
6.350
3.302
2.54 BSC
7.62 BSC
-
Max.
5.334
4.953
0.588
1.778
0.356
26.924
8.255
7.112
3.810
Note
Note 2
Note 2
10.922
1.524
1/6/12
Package Drawing Contact:
[email protected]
22
ATF16V8C [DATASHEET]
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
TITLE
20P3, 20-lead, 0.300”/7.62 mm Wide Plastic Dual
Inline Package (PDIP)
GPC
DRAWING NO.
PQD
20P3
REV.
F
13.
Revision History
Doc. Rev.
Date
0425I
03/2014
0425H
03/2011
Comments
Remove “-10JI” and “-7SU” ordering codes and 20S and 20X package drawings.
Update package drawings, template, logos, and disclaimer page.
Added green (ROHS compliant) package options.
Removed lead based packages from ordering section.
ATF16V8C [DATASHEET]
Atmel-0425I-PLD-ATF16V8C-Datasheet_032014
23
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