ATA6838C - Complete

ATA6838C
Hex Half-bridge Driver with Serial Input Control
DATASHEET
Features
● Six half-bridge outputs formed by six high-side and six low-side drivers
● Capable of switching all kinds of loads (such as DC motors, bulbs, resistors,
capacitors and inductors)
● RDSon typically 1.0 at 25°C, maximum 1.8 at 150°C
● Up to 950-mA output current
● Very low total quiescent current IS < 2µA in standby mode
● Outputs short-circuit protected
● Overtemperature prewarning and protection
● Undervoltage protection
● Various diagnosis functions such as shorted output, open load, overtemperature
and power supply fail
● Serial data interface
● Operation voltage up to 40V
● Daisy chaining possible
● Serial interface 5V compatible, up to 2MHz clock frequency
● QFN24 5mm x 5mm power package
9237G-AUTO-02/15
1.
Description
The Atmel® ATA6838C is a fully protected hex half-bridge driver designed in Smart Power SOI technology, used to control
up to six different loads by a microcontroller in automotive and industrial applications.
Each of the six high-side and six low-side drivers is capable of driving currents up to 950mA. The drivers are internally
connected to form six half-bridges and can be controlled separately from a standard serial data interface. Therefore, all kinds
of loads, such as bulbs, resistors, capacitors and inductors, can be combined. The IC especially supports the application of
H-bridges to drive DC motors.
Protection is guaranteed in terms of short-circuit conditions, overtemperature and undervoltage. Various diagnosis functions
and a very low quiescent current in standby mode make a wide range of applications possible.
Automotive qualification referring to conducted interferences, EMC protection and ESD protection gives added value and
enhanced quality for the exacting requirements of automotive applications.
Figure 1-1. Block Diagram QFN24
S
I
S
C
T
O
L
D
H
S
6
L
S
6
H
S
5
L
S
5
H
S
4
L
S
4
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
3, 4
VS
Input register
Ouput register
DI
19
P
S
F
I
N
H
S
C
D
H
S
6
Serial interface
L
S
6
H
S
5
L
S
5
H
S
4
L
S
4
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
Charge
pump
L
S
1
T
P
CLK
18
CS
17
INH
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
UV
protection
Fault
Detect
14
12
Control
logic
DO
13
VCC
Power on
reset
24
GND
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
16
Fault
Detect
GND
Thermal
protection
15
GND
7
11
OUT1
2
ATA6838C [DATASHEET]
9237G–AUTO–02/15
8
5
2
OUT2
OUT3
OUT4
23
OUT5
20
OUT6
GND
2.
Pin Configuration
2.1
QFN24
NC
OUT5
OUT5 SENSE
OUT6 SENSE
OUT6
DI
Figure 2-1. Pinning QFN 24, 5  5, 0.65mm Pitch
1
2
3
4
5
6
24 23 22 21 20 19
18
17
16
15
14
13
7 8 9 10 11 12
CLK
CS
GND SENSE
NC
VCC
DO
NC
OUT2
OUT2 SENSE
OUT1 SENSE
OUT1
INH
OUT4 SENSE
OUT4
VS
VS
OUT3
OUT3 SENSE
Note:
YWW
ATAxyz
ZZZZZ
AL
Date code (Y = Year above 2000, WW = week number)
Product name
Wafer lot number
Assembly sub-lot number
Table 2-1.
Pin Description QFN24
Pin
Symbol
Function
1
OUT4
SENSE
Only for testability in final test
2
OUT4
3
VS
Power supply output stages HS4, HS5 and HS6
4
VS
Power supply output stages HS1, HS2 and HS3
5
OUT3
6
OUT3
SENSE
7
NC
8
OUT2
9
OUT2
SENSE
Only for testability in final test
10
OUT1
SENSE
Only for testability in final test
11
OUT1
12
INH
Half-bridge output 4; formed by internally connected power MOS high-side switch 4 and
low-side switch 4 with internal reverse diodes; short circuit protection; overtemperature
protection; diagnosis for short and open load
Output 3; see pin 1
Only for testability in final test
Internal bond to GND
Output 2; see pin 1
Output 1; see pin 1
Inhibit input; 5V logic input with internal pull down; low = standby, high = normal operation
ATA6838C [DATASHEET]
9237G–AUTO–02/15
3
Table 2-1.
Pin Description QFN24 (Continued)
Pin
Function
13
DO
Serial data output; 5V CMOS logic level tri-state output for output (status) register data;
sends 16-bit status information to the microcontroller (LSB is transferred first). Output will
remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate
on one data output line only
14
VCC
Logic supply voltage (5V)
15
NC
16
4
Symbol
Internal bond to GND
GND SENSE Ground; reference potential; internal connection to the lead frame; cooling tab
17
CS
Chip select input; 5V CMOS logic level input with internal pull up;
low = serial communication is enabled, high = disabled
18
CLK
Serial clock input; 5V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (fmax = 2MHz)
19
DI
20
OUT6
21
OUT6
SENSE
Only for testability in final test
22
OUT5
SENSE
Only for testability in final test
23
OUT5
24
NC
ATA6838C [DATASHEET]
9237G–AUTO–02/15
Serial data input; 5V CMOS logic level input with internal pull down; receives serial data from
the control device; DI expects a 16-bit control word with LSB being transferred first
Output 6; see pin 1
Output 5; see pin 1
Internal bond to GND
3.
Functional Description
3.1
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and is accepted on
the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the
rising edge of the CS signal. When CS is high, pin DO is in a tri-state condition. This output is enabled on the falling edge of
CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears.
LSB (bit 0, TP) is transferred first.
Figure 3-1. Data Transfer Input Data Protocol
CS
DI
SRR
0
LS1
HS1
LS2
HS2
LS3
HS3
1
2
3
4
5
6
SLS1
SHS1 SLS2 SHS2
LS4
HS4
LS5
HS5
LS6
7
8
9
10
11
SLS4
SHS4
SLS5
SHS5 SLS6
HS6
12
OLD
13
SCT
14
SI
15
CLK
DO
TP
SLS3 SHS3
SHS6
SCD
INH
PSF
Table 3-1.
Input Data Protocol
Bit
Input Register
0
SRR
Status register reset (high = reset; the bits PSF, SCD and overtemperature shutdown
in the output data register are set to low)
1
LS1
Controls output LS1 (high = switch output LS1 on)
2
HS1
Controls output HS1 (high = switch output HS1 on)
3
LS2
See LS1
4
HS2
See HS1
5
LS3
See LS1
6
HS3
See HS1
7
LS4
See LS1
8
HS4
See HS1
9
LS5
See LS1
10
HS5
See HS1
11
LS6
See LS1
12
HS6
See HS1
13
OLD
Open load detection (low = on)
14
SCT
Programmable time delay for short circuit
(shutdown delay high/low = 12ms/1.5ms)
15
SI
Function
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the digital part is still
powered)
ATA6838C [DATASHEET]
9237G–AUTO–02/15
5
Table 3-2.
Output Data Protocol
Bit
Output (Status) Register
0
TP
1
Status LS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is switched off)
2
Status HS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is switched off)
3
Status LS2
Description see LS1
4
Status HS2
Description see HS1
5
Status LS3
Description see LS1
6
Status HS3
Description see HS1
7
Status LS4
Description see LS1
8
Status HS4
Description see HS1
9
Status LS5
Description see LS1
Status HS5
Description see HS1
11
Status LS6
Description see LS1
12
Status HS6
Description see HS1
13
SCD
Short circuit detected: set high, when at least one output is switched off by a
short circuit condition
14
INH
Inhibit: this bit is controlled by software (bit SI in input register) and hardware
inhibit (pin INH). High = standby, low = normal operation
Table 3-3.
PSF
Power supply fail: undervoltage at pin VS detected
Bit 0 to 15 = high: overtemperature shutdown
Status of the Input Register After Power on Reset
Bit 15 Bit 14
(SI)
(SCT)
6
Temperature prewarning: high = warning
(overtemperature shutdown see remark below)
10
15
Note:
H
Function
H
Bit 13
(OLD)
Bit 12
(HS6)
Bit 11
(LS6)
Bit 10
(HS5)
Bit 9
(LS5)
Bit 8
(HS4)
Bit 7
(LS4)
Bit 6
(HS3)
Bit 5
(LS3)
Bit 4
(HS2)
Bit 3
(LS2)
H
L
L
L
L
L
L
L
L
L
L
ATA6838C [DATASHEET]
9237G–AUTO–02/15
Bit 2 Bit 1 Bit 0
(HS1) (LS1) (SRR)
L
L
L
3.2
Power-supply Fail
In case of undervoltage at pin VS, an internal timer is started. When during a permanent undervoltage the delay time (tdUV) is
reached, the power supply fail bit (PSF) in the output register is set and all outputs are disabled. When normal voltage is
present again, the outputs are enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the input
register.
3.3
Open-load Detection
If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each
low-side switch is turned on (open-load detection current IHS1-6, ILS1-6). If VVS – VHS1-6 or VLS1-6 is lower than the open-load
detection threshold (open-load condition), the corresponding bit of the output in the output register is set to high. Switching
on an output stage with OLD bit set to low disables the open load function for this output.
3.4
Overtemperature Protection
If the junction temperature exceeds the thermal prewarning threshold, TjPW set, the temperature prewarning bit (TP) in the
output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The
TP bit can be read without transferring a complete 16-bit data word: with CS = high to low, the state of TP appears at pin DO.
After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the
state of the input and output registers.
If the junction temperature exceeds the thermal shutdown threshold, Tj switch off, the outputs are disabled and all bits in the
output register are set high. The outputs can be enabled again when the temperature falls below the thermal shutdown
threshold, Tj switch on, and when a high has been written to the SRR bit in the input register. Thermal prewarning and
shutdown threshold have hysteresis.
3.5
Short-circuit Protection
The output currents are limited by a current regulator. Current limitation takes place when the overcurrent limitation and
shutdown threshold (IHS1-6, ILS1-6) are reached. Simultaneously, an internal timer is started. The shorted output is disabled
when during a permanent short the delay time (tdSd) programmed by the short-circuit timer bit (SCT) is reached. Additionally,
the short-circuit detection bit (SCD) is set. If the temperature prewarning bit TP in the output register is set during a short, the
shorted output is disabled after tdSd and SCD bit is set. By writing a high to the SRR bit in the input register, the SCD bit is
reset and the disabled outputs are enabled.
3.6
Inhibit
There are two ways to inhibit the Atmel® ATA6838C:
● Set bit SI in the input register to 0
●
Switch pin INH to 0V
In both cases, all output stages are turned off but the serial interface stays active. The output stages can be activated again
by bit SI = 1 (when INH = VCC) or by pin INH switched back to VCC (when SI = 1).
ATA6838C [DATASHEET]
9237G–AUTO–02/15
7
4.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All values refer to GND pins.
Parameters
Pin QFN24
Symbol
Value
Unit
Supply voltage
3, 4
VVS
–0.3 to +40
V
Supply voltage t < 0.5s; IS > –2A
3, 4
VVS
–1
V
Supply voltage difference
VS_pin5(3) – VS_pin10(4)
3, 4
VVS
150
mV
Logic supply voltage
Logic input voltage
Logic output voltage
Input current
Output current
14
VVCC
–0.3 to +7
V
17-19
VDI, VCLK, VCS
–0.3 to VVCC +0.3
V
13
VDO
–0.3 to VVCC +0.3
V
12, 17-19
IINH, IDI, ICLK, ICS
–10 to +10
mA
13
IDO
–10 to +10
mA
Output current
2, 5, 8, 11, 20, 23
IOUT1 to IOUT6
Internally limited, see
“Output Specification” in
Section 7. “Electrical
Characteristics” on page 9
Output voltage
2, 5, 8, 11, 20, 23
OUT1 to OUT6
–0.3 to +40
V
Junction temperature range
Tj
–40 to +150
°C
Storage temperature range
TSTG
–55 to +150
°C
5.
Thermal Resistance
Table 5-1.
QFN24: Depends on the PCB-board
Parameter
Test Conditions
Junction pin
Junction ambient
8
ATA6838C [DATASHEET]
9237G–AUTO–02/15
Pin
Symbol
16
Min.
Typ.
Max.
Unit
RthJP
<5
K/W
RthJA
35
K/W
6.
Operating Range
Parameter
Test Conditions
Pin QFN24
Symbol
Min.
Typ.
Max.
Unit
40
V
Supply voltage
3, 4
VVS
VUV(1)
Logic supply voltage
14
VVCC
4.75
5.25
V
12, 17-19
VINH, VDI,
VCLK, VCS
–0.3
VVCC
V
2
MHz
+150
°C
Logic input voltage
Serial interface clock
frequency
fCLK
Junction temperature range
7.
Tj
–40
Electrical Characteristics
7.5V < VS < 40V; 4.75 < VCC < 5.25V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters
Max.
Unit
Type*
IVS
2
µA
A
14
IVCC
20
µA
A
4.75V < VVCC < 5.25V,
INH or bit SI = low,
TJ = –40°C
14
IVCC
30
µA
A
1.3 Supply current (VS)
VVS < 28V normal
operation, all output
stages off
3, 4
IVS
1.2
mA
A
1.4 Supply current (VS)
VVS < 28V normal
operation, all output low
stages on, no load
3, 4
IVS
10
mA
A
1.5 Supply current (VS)
VVS < 28V normal
operation, all output
high stages on, no load
3, 4
IVS
16
mA
A
1.6 Supply current (VCC)
4.75V < VVCC < 5.25V,
normal operation
14
IVCC
150
µA
A
3, 4
IVS
5
mA
A
59
kHz
A
1
Test Conditions
Pin QFN24
Symbol
3, 4
4.75V < VVCC < 5.25V,
INH or bit SI = low
Quiescent current
(VCC)
1.7 Discharge current (VS) VVS = 40V, INH = low
2
2.1
Typ.
Current Consumption
VS = 33V
VCC = 0V or
Total quiescent current
VCC = 5V, bit SI = low or
1.1 (VS and all outputs to
VCC = 5V, pin INH = low
VS)
Output pins to VS and
GND
1.2
Min.
0.8
Internal Oscillator Frequency
Frequency (time base
for delay timers)
fOSC
24.3
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90%
of final level. Device not in standby for t > 1ms.
ATA6838C [DATASHEET]
9237G–AUTO–02/15
9
7.
Electrical Characteristics (Continued)
7.5V < VS < 40V; 4.75 < VCC < 5.25V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters
3
Test Conditions
Pin QFN24
Symbol
Min.
Typ.
Max.
Unit
Type*
14
VVCC
2.3
2.7
3.0
V
A
tdPor
30
95
160
µs
A
5.5
7.0
V
A
V
A
20
ms
A
Undervoltage Detection, Power-on Reset
3.1
Power-on reset
threshold
3.2
Power-on reset delay
time
3.3
Undervoltage detection
threshold
14
VUV
3.4
Undervoltage detection
hysteresis
14
VUV
3.5
Undervoltage detection
delay
After switching on VVCC
0.4
tdUV
4.95
4.1 Thermal prewarning
TjPWset
120
145
170
°C
B
4.2 Thermal prewarning
TjPWreset
105
130
155
°C
B
Thermal prewarning
4.3
hysteresis
TjPW
K
C
4
Thermal Prewarning and Shutdown
15
4.4 Thermal shutdown
Tj switch off
150
175
200
°C
B
4.5 Thermal shutdown
Tj switch on
135
160
185
°C
B
Thermal shutdown
4.6
hysteresis
Tj switch off
K
C
Ratio thermal
4.7 shutdown/thermal
prewarning
Tj switch off/
1.05
1.2
C
1.05
1.2
C
TjPW set
Ratio thermal
4.8 shutdown/thermal
prewarning
5
15
Tj switch on/
TjPW reset
Output Specification (LS1-LS6, HS1-HS6) 7.5V < VVS < 40V
5.1 On resistance
IOut = 600mA
2, 5, 8, 11,
20, 23
RDS OnL
1.8

A
5.2 On resistance
IOut = –600mA
2, 5, 8, 11,
20, 23
RDS OnH
1.8

A
High-side output
VOut1-6 = 0V
leakage current
5.3
(total quiescent current all output stages off
see 1.1)
2, 5, 8, 11,
20, 23
IOut1-6
µA
A
Low-side output
VOut1-6 = VS
leakage current
5.4
(total quiescent current all output stages off
see 1.1)
2, 5, 8, 11,
20, 23
IOut1-6
120
µA
A
15
mJ
D
1710
mA
A
5.5
Inductive shutdown
energy
2, 5, 8, 11,
20, 23
Woutx
5.6
Overcurrent limitation
V = 13V
and shutdown threshold VS
2, 5, 8, 11,
20, 23
ILS1-6
–15
950
1250
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90%
of final level. Device not in standby for t > 1ms.
10
ATA6838C [DATASHEET]
9237G–AUTO–02/15
7.
Electrical Characteristics (Continued)
7.5V < VS < 40V; 4.75 < VCC < 5.25V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters
Test Conditions
Pin QFN24
Symbol
Min.
Typ.
Max.
Unit
Type*
–1250
–950
mA
A
5.7
Overcurrent limitation
V = 13V
and shutdown threshold VS
2, 5, 8, 11,
20, 23
IHS1-6
–1710
5.8
Overcurrent limitation
20V < VVS < 40V
and shutdown threshold
2, 5, 8, 11,
20, 23
ILS1-6
950
2100
mA
C
5.9
Overcurrent limitation
20V < VVS < 40V
and shutdown threshold
2, 5, 8, 11,
20, 23
IHS1-6
–2100
–950
mA
C
5.10
Overcurrent shutdown
delay time
Input register
bit 14 (SCT) = low
VVS = 13V
tdSd
0.45
1.3
2.1
ms
A
5.11
Overcurrent shutdown
delay time
Input register
bit 14 (SCT) = High
VVS = 13V
tdSd
4.8
9
15
ms
A
5.12
High-side open load
detection current
Input register bit 13
(OLD) = low, output off
2, 5, 8, 11,
20, 23
IOut1-6H
–1.5
–0.4
mA
A
5.13
Low-side open load
detection current
Input register bit 13
(OLD) = low, output off
2, 5, 8, 11,
20, 23
IOut1-6L
0.45
1.75
mA
A
5.14
Open load detection
current ratio
2, 5, 8, 11,
20, 23
IOLoutLX/
IOLoutHX
1.05
5.15
High-side open load
detection voltage
Input register bit 13
(OLD) = low, output off
2, 5, 8, 11,
20, 23
VOut1-6H
0.6
2.5
V
A
5.16
Low-side open load
detection voltage
Input register bit 13
(OLD) = low, output off
2, 5, 8, 11,
20, 23
VOut1-6L
0.7
2.1
V
A
5.17
High-side output switch VVS = 13V
on delay(1)
RLoad = 30
tdon
20
µs
A
5.18
Low-side output switch VVS = 13V
on delay(1)
RLoad = 30
tdon
20
µs
A
5.19
High-side output switch VVS =13V
off delay(1)
RLoad = 30
tdoff
20
µs
A
5.20
Low-side output switch VVS =13V
off delay(1)
RLoad = 30
tdoff
3
µs
A
Dead time between
V =13V
5.21 corresponding high- and VS
RLoad = 30
low-side switches
6
1.2
2
tdon – tdoff
0.7
µs
A
0.3 
VVCC
V
A
0.7 
VVCC
V
A
Inhibit Input
6.1
Input voltage low-level
threshold
12
VIL
6.2
Input voltage high-level
threshold
12
VIH
6.3
Hysteresis of input
voltage
12
VI
100
700
mV
A
IPD
10
80
µA
A
6.4 Pull-down current
VINH = VVCC
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90%
of final level. Device not in standby for t > 1ms.
ATA6838C [DATASHEET]
9237G–AUTO–02/15
11
7.
Electrical Characteristics (Continued)
7.5V < VS < 40V; 4.75 < VCC < 5.25V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters
7
Test Conditions
Pin QFN24
Symbol
Min.
Typ.
0.3 
VVCC
Max.
Unit
Type*
V
A
0.7 
VVCC
V
A
Serial Interface: Logic Inputs DI, CLK, CS
7.1
Input voltage low-level
threshold
17-19
VIL
7.2
Input voltage high-level
threshold
17-19
VIH
7.3
Hysteresis of input
voltage
17-19
VI
50
500
mV
A
7.4
Pull-down current pin
DI, CLK
18, 19
IPDSI
2
50
µA
A
17
IPUSI
–50
–2
µA
A
13
VDOL
0.5
V
A
V
A
µA
A
7.5 Pull-up current pin CS
8
VDI, VCLK = VVCC
VCS= 0V
Serial Interface: Logic Output DO
8.1 Output voltage low level IOL = 3mA
8.2
Output voltage high
level
IOL = –1mA
13
VDOH
VVCC –
0.7V
8.3
Leakage current
(tri-state)
VCS = VVCC,
0V < VDO < VVCC
13
IDO
–10
10
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90%
of final level. Device not in standby for t > 1ms.
8.
Serial Interface: Timing
Parameters
Test Conditions
QFN24
Number in
Timing
Diagram
(Figure 8-1
on page 13) Symbol
Min.
Typ.
Max.
Unit
DO enable after CS falling edge CDO = 100pF
13
1
tENDO
200
ns
DO disable after CS rising edge CDO = 100pF
13
2
tDISDO
200
ns
DO fall time
CDO = 100pF
13
-
tDOf
100
ns
DO rise time
CDO = 100pF
13
-
tDOr
100
ns
DO valid time
CDO = 100pF
200
ns
13
10
tDOVal
CS setup time
17
4
tCSSethl
225
ns
CS setup time
17
8
tCSSetlh
225
ns
tCSh
17
ms
CS high time
Input register bit 14 (SCT) = high
17
9
CS high time
Input register bit 14 (SCT) = low
17
9
tCSh
2.1
ms
CLK high time
18
5
tCLKh
225
ns
CLK low time
18
6
tCLKl
225
ns
CLK period time
18
-
tCLKp
500
ns
CLK setup time
18
7
tCLKSethl
225
ns
CLK setup time
18
3
tCLKSetlh
225
ns
DI setup time
19
11
tDIset
40
ns
DI hold time
19
12
tDIHold
40
ns
12
ATA6838C [DATASHEET]
9237G–AUTO–02/15
Figure 8-1. Serial Interface Timing Diagram with Item Numbers
1
2
CS
DO
9
CS
4
7
CLK
5
3
6
8
DI
11
CLK
10
12
DO
Inputs DI, CLK, CS: High level = 0.7 x VCC, low level = 0.3 x VCC
Output DO: High level = 0.8 x VCC, low level = 0.2 x VCC
ATA6838C [DATASHEET]
9237G–AUTO–02/15
13
9.
Noise and Surge Immunity
Parameters
Test Conditions
Value
Conducted interferences
ISO 7637-1
Level 4(1)
Interference suppression
VDE 0879 Part 2
Level 5
ESD (Human Body Model)
ESD S 5.1
4kV
CDM (Charge Device Model)
ESD STM5.3
750V for corner pins
(SO package only)
500V all other pins
MM (Machine Model)
Note:
1. Test pulse 5: Vvbmax = 40V
ESD STM5.2
200V
14
ATA6838C [DATASHEET]
9237G–AUTO–02/15
10.
Application Circuit
Figure 10-1. Application Circuit
S
I
VCC
O
L
D
H
S
6
L
S
6
H
S
5
L
S
5
L
S
4
H
S
4
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
VS
S
R
R
BYT41D
VS
U5021M Enable
Watchdog
Input register
Ouput register
Trigger
Reset
S
C
T
DI
P
S
F
I
N
H
S
C
D
H
S
6
+
Serial interface
L
S
6
H
S
5
L
S
5
H
S
4
L
S
4
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
Charge
pump
L
S
1
Vbatt
24V
GND
T
P
GND
GND
CLK
Microcontroller
GND
CS
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
VCC
UV
protection
Fault
Detect
INH
Control
logic
DO
VCC
Power on
reset
+
VCC
5V
GND
VCC
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
GND
Thermal
protection
GND
GND
OUT1
M
10.1
OUT2
M
OUT3
M
OUT4
M
OUT5
OUT6
M
Application Notes
●
●
Connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins.
●
Recommended value for capacitors at VCC:
Electrolytic capacitor C > 10µF in parallel with a ceramic capacitor C = 100nF.
●
To reduce thermal resistance, place cooling areas on the PCB as close as possible to GND pins and to the die paddle
in QFN24.
●
The sense pins OUTx SENSE can either be left open or can be connected to the adjacent OUTx pin. Never use the
sense pins OUTx SENSE as power outputs.
Recommended value for capacitors at VS:
Electrolytic capacitor C > 22µF in parallel with a ceramic capacitor C = 100nF.
Value for electrolytic capacitor depends on external loads, conducted interferences and reverse-conducting current
IHSX (see Section 4. “Absolute Maximum Ratings” on page 8).
ATA6838C [DATASHEET]
9237G–AUTO–02/15
15
11.
Ordering Information
Extended Type Number
Package
ATA6838C-PXQW-1
12.
QFN24
Remarks
Pb-free, 6k, taped and reeled
Package Information
Top View
D
24
1
E
PIN 1 ID
technical drawings
according to DIN
specifications
6
A
Side View
A3
A1
Dimensions in mm
Bottom View
D2
7
12
13
COMMON DIMENSIONS
E2
6
1
Z
18
24
19
Z 10:1
L
e
b
(Unit of Measure = mm)
Symbol
MIN
NOM
MAX
A
0.8
0.85
0.9
A1
A3
0.0
0.16
0.035
0.21
0.05
0.26
D
4.9
5
5.1
D2
3.5
3.6
3.7
E
4.9
5
5.1
E2
3.5
3.6
3.7
L
0.35
0.4
0.45
b
e
0.2
0.25
0.65
0.3
NOTE
10/18/13
TITLE
Package Drawing Contact:
[email protected]
16
ATA6838C [DATASHEET]
9237G–AUTO–02/15
Package: VQFN_5x5_24L
Exposed pad 3.6x3.6
GPC
DRAWING NO.
REV.
6.543-5132.02-4
1
13.
Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No.
9237G-AUTO-02/15
History
Section 11 “Ordering Information” on page 16 updated
Section 12 “Package Information” on page 16 updated
9237F-AUTO-05/12
Set datasheet from “Preliminary” to “Standard”
9237E-AUTO-03/12
Section 3.5 “Short-circuit Protection” on page 7 updated
9237D-AUTO-12/11
Section 7 “Electrical Characteristics” numbers 3.5, 5.10, 5.13 and 5.16 on page 10 to
11 updated
9237C-AUTO-10/11
Section 10.1 “Application Notes” on page 15 updated
ATA6838C [DATASHEET]
9237G–AUTO–02/15
17
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F: (+1)(408) 436.4200
|
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© 2015 Atmel Corporation. / Rev.: 9237G–AUTO–02/15
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