AT24C11 Automotive - Mature

Features
•
•
•
•
•
•
•
•
Low Voltage and Standard Voltage Operation: 2.7 (VCC = 2.7V to 5.5V)
Internally Organized 128 x 8
Two-wire Serial Interface
Bidirectional Data Transfer Protocol
1 MHz Compatibility
4-Byte Page Write Mode
Self-Timed Write Cycle (5 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade and Lead-Free/Halogen-Free Devices Available
• 8-lead JEDEC SOIC and 8-lead TSSOP Packages
Two-wire
Automotive
Temperature
Serial EEPROM
Description
The AT24C11 provides 1024 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 128 words of 8 bits each. The device is
optimized for use in many automotive applications where low power and low voltage
operation are essential. The AT24C11 is available in space saving 8-lead JEDEC
SOIC and 8-lead TSSOP packages and is accessed via a Two-wire serial interface. In
addition, the entire family is available in 2.7V (2.7V to 5.5V).
1K (128 x 8)
Table 0-1.
Note: Not recommended for new
design; please refer to
AT24C01B Automotive
datasheet.
Pin Configuration
Pin Name
Function
NC
No Connect
SDA
Serial Data
SCL
Serial Clock Input
TEST
Test Input (GND or VCC)
8-lead TSSOP
NC
NC
NC
GND
1
2
3
4
8
7
6
5
AT24C11
8-lead SOIC
VCC
TEST
SCL
SDA
NC
NC
NC
GND
1
2
3
4
8
7
6
5
VCC
TEST
SCL
SDA
Rev. 5093E–SEEPR–8/07
Absolute Maximum Ratings*
Operating Temperature..................................–55°C to +125°C
*NOTICE:
Storage Temperature .....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground .................................... –1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Block Diagram
VCC
GND
WP
START
STOP
LOGIC
SCL
SDA
SERIAL
CONTROL
LOGIC
LOAD
DEVICE
ADDRESS
COMPARATOR
A2
A1
A0
R/W
EN
H.V. PUMP/TIMING
COMP
LOAD
DATA RECOVERY
INC
DATA WORD
ADDR/COUNTER
Y DEC
X DEC
Figure 0-1.
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
EEPROM
SERIAL MUX
DOUT/ACK
LOGIC
DIN
DOUT
1. Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM
device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain
driven and may be wire-ORed with any number of other open-drain or open collector devices.
2
AT24C11
5093E–SEEPR–8/07
AT24C11
2. Memory Organization
AT24C11, 1K SERIAL EEPROM: Internally organized with 32 pages of 4 bytes each. The 1K
requires a 7-bit data word address for random word addressing.
Table 2-1.
Pin Capacitance
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +2.7V to +5.5V
Symbol
Test Condition
Max
Units
Condition
CI/O
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
CIN
Input Capacitance (A0, A1, A2, SCL)
6
pF
VIN = 0V
Table 2-2.
DC Characteristics
Applicable over recommended operating range from: TAE = –40°C to +125°C, VCC = +2.7V to +5.5V (unless otherwise
noted)
Symbol
Parameter
Max
Units
VCC1
Supply Voltage
2.7
5.5
V
VCC2
Supply Voltage
4.5
5.5
V
ICC
Supply Current VCC = 5.0V
READ at 100 kHz
0.4
1.0
mA
ICC
Supply Current VCC = 5.0V
WRITE at 100 kHz
2.0
3.0
mA
ISB1
Standby Current VCC = 1.8V
VIN = VCC or VSS
0.6
3.0
µA
ISB2
Standby Current VCC = 2.5V
VIN = VCC or VSS
1.4
4.0
µA
ISB3
Standby Current VCC = 2.7V
VIN = VCC or VSS
1.6
4.0
µA
ISB4
Standby Current VCC = 5.0V
VIN = VCC or VSS
8.0
18.0
µA
ILI
Input Leakage Current
VIN = VCC or VSS
0.10
3.0
µA
ILO
Output Leakage Current
VOUT = VCC or VSS
0.05
3.0
µA
VIL
Test Condition
Min
Typ
(1)
–0.6
VCC × 0.3
V
(1)
VCC × 0.7
VCC + 0.5
V
Input Low Level
VIH
Input High Level
VOL2
Output Low Level VCC = 3.0V
IOL = 2.1 mA
0.4
V
Output Low Level VCC = 1.8V
IOL = 0.15 mA
0.2
V
VOL1
Note:
1. VIL min and VIH max are reference only and are not tested.
3
5093E–SEEPR–8/07
Table 2-3.
AC Characteristics
Applicable over recommended operating range from T A = –40°C to +125°C, VCC = +2.7V to
+5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted)
2.7V, 5.0V
Symbol
Parameter
Min
fSCL
Clock Frequency, SCL
tLOW
Clock Pulse Width Low
0.4
µs
tHIGH
Clock Pulse Width High
0.4
µs
tAA
Clock Low to Data Out Valid
0.05
tBUF
Time the bus must be free before a new
transmission can start(1)
0.5
µs
tHD.STA
Start Hold Time
0.25
µs
tSU.STA
Start Set-up Time
0.6
µs
tHD.DAT
Data In Hold Time
0
µs
tSU.DAT
Data In Set-up Time
100
ns
(1)
Max
Units
1000
kHz
0.55
µs
tR
Inputs Rise Time
0.3
µs
tF
Inputs Fall Time(1)
100
ns
tSU.STO
Stop Set-up Time
tDH
Data Out Hold Time
tWR
Write Cycle Time
Endurance(1)
5.0V, 25°C, Page Mode
Note:
0.25
µs
50
ns
5
1M
ms
Write
Cycles
1. This parameter is ensured by characterization only.
3. Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (see Figure 3-3 on
page 6). Data changes during SCL high periods will indicate a start or stop condition as defined
below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see Figure 3-4 on page 6).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition which terminates all communications. After a read sequence, the stop command will place the EEPROM
in a standby power mode (see Figure 3-4 on page 6).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. Any device on the system bus receiving data (when communicating
with the EEPROM) must pull the SDA bus low to acknowledge that it has successfully received
each word. This must happen during the ninth clock cycle after each word received and after all
other system devices have freed the SDA bus. The EEPROM will likewise acknowledge by pulling SDA low after receiving each address or data word (see Figure 3-5 on page 6).
4
AT24C11
5093E–SEEPR–8/07
AT24C11
STANDBY MODE: The AT24C11 features a low power standby mode which is enabled: (a)
upon power-up and (b) after the receipt of the STOP bit and the completion of any internal
operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part
can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create
a start condition as SDA is high.
Figure 3-1.
Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
tHIGH
tF
tR
tLOW
SCL
tSU.STA
tLOW
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA IN
tAA
tDH
tBUF
SDA OUT
Figure 3-2.
Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th BIT
ACK
WORDn
(1)
twr
STOP
CONDITION
Note:
START
CONDITION
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
5
5093E–SEEPR–8/07
Figure 3-3.
Data Validity
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
Figure 3-4.
Start and Stop Definition
SDA
SCL
START
Figure 3-5.
STOP
Output Acknowledge
1
SCL
8
9
DATA IN
DATA OUT
START
6
ACKNOWLEDGE
AT24C11
5093E–SEEPR–8/07
AT24C11
4. Write Operations
BYTE WRITE: Following a start condition, a write operation requires a 7-bit data word address
and a low write bit. Upon receipt of this address, the EEPROM will again respond with a zero
and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM
will output a zero and the addressing device, such as a microcontroller, must terminate the write
sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle
to the nonvolatile memory. All inputs are disabled during this write cycle, tWR, and the EEPROM
will not respond until the write is complete (see refer to Figure 5-1 on page 8).
PAGE WRITE: The AT24C11 is capable of a 4-byte page write.
A page write is initiated the same as a byte write but the microcontroller does not send a stop
condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to three more data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 5-2 on page 8).
The data word address lower 2 bits are internally incremented following the receipt of each data
word. The higher five data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than four data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten. Access to 1 additional page is available upon request.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond with
a zero allowing the read or write sequence to continue.
5. Read Operations
Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to one. There are two read operations:
byte read and sequential read.
BYTE READ: A byte read is initiated with a start condition followed by a 7-bit data word address
and a high read bit. The AT24C11 will respond with an acknowledge and then serially output 8
data bits. The microcontroller does not respond with a zero but does generate a following stop
condition (see Figure 5-3 on page 8).
SEQUENTIAL READ: Sequential reads are initiated the same as a byte read. After the microcontroller receives an 8-bit data word, it responds with an acknowledge. As long as the
EEPROM receives an acknowledge, it will continue to increment the data word address and
serially clock out sequential data words. When the memory address limit is reached, the data
word address will “roll over” and the sequential read will continue. The sequential read operation
is terminated when the microcontroller does not respond with an input zero but does generate a
following stop condition (see Figure 5-4 on page 8).
7
5093E–SEEPR–8/07
Figure 5-1.
Byte Write
Figure 5-2.
Page Write
Figure 5-3.
Byte Read
Figure 5-4.
Sequential Read
8
AT24C11
5093E–SEEPR–8/07
AT24C11
AT24C11 Ordering Information
Ordering Code
Package
AT24C11N-10SQ-2.7
AT24C11-10TQ-2.7
8S1
8A2
Operation Range
Lead-free/Halogen-free/
Automotive Temperature
(–40°C to 85°C)
Package Type
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
–2.7
Low-Voltage (2.7V to 5.5V)
9
5093E–SEEPR–8/07
Packaging Information
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
A1
D
Side View
MIN
NOM
MAX
A
1.35
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.00
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
∅
0˚
–
8˚
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
R
10
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
8S1
REV.
B
AT24C11
5093E–SEEPR–8/07
AT24C11
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
b
D
MIN
NOM
MAX
NOTE
2.90
3.00
3.10
2, 5
3, 5
E
e
D
A2
6.40 BSC
E1
4.30
4.40
4.50
A
–
–
1.20
A2
0.80
1.00
1.05
b
0.19
–
0.30
e
Side View
L
0.65 BSC
0.45
L1
Notes:
4
0.60
0.75
1.00 REF
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
8A2
REV.
B
11
5093E–SEEPR–8/07
Revision History
12
Doc. Rev.
Date
Comments
5093E
8/2007
Updated to new Template
Updated common figures
Added Note to first page
5093D
1/2007
Removed PDIP package offering
Removed PB parts
5093C
9/2006
Revision history implemented; Removed
‘Preliminary’ status from datasheet.
AT24C11
5093E–SEEPR–8/07
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5093E–SEEPR–8/07
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