ATA663211 - Complete

ATA663211
LIN Transceiver
DATASHEET
Features
● Supply voltage up to 40V
● Operating voltage VS = 5V to 28V
● Very low supply current
● Sleep mode: typically 9µA
● Fail-safe mode: typically 80µA
● Normal mode: typically 250µA
● Fully compatible with 3.3V and 5V devices
● LIN physical layer according to LIN 2.0, 2.1, 2.2, 2.2A and SAEJ2602-2
● Wake-up capability via LIN bus (100µs dominant)
● External wake-up via WKin pin (100µs low level)
● INH output to control an external voltage regulator or to switch the master pull-up
● Wake-up source recognition
● TXD time-out timer
● Bus pin is over-temperature and short-circuit protected vs. GND and battery
● Advanced EMC and ESD performance
● Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications
Rev.1.3”
● Interference and damage protection according to ISO7637
● Qualified according to AEC-Q100
● Package: SO8, DFN8 with wettable flanks (Moisture Sensitivity Level 1)
9359C-AUTO-10/14
1.
Description
The Atmel® ATA663211 is a fully integrated LIN transceiver designed in compliance with the LIN specification 2.0, 2.1, 2.2,
2.2A and SAEJ2602-2. It interfaces the LIN protocol handler and the physical layer. The device is designed to handle the
low-speed data communication in vehicles, for example, in convenience electronics. Improved slope control at the LIN bus
ensures data communication up to 20Kbaud. Sleep mode guarantees minimal current consumption even in the case of a
floating bus line or a short circuit on the LIN bus to GND.
Figure 1-1.
Block Diagram
7
VS
6
LIN
5
GND
Atmel ATA663211
RXD
1
Receiver
+
RF-Filter
Wake-up bus timer
TXD
TXD
Time-out
Timer
4
Short-circuit and
overtemperature
protection
Slew rate control
VS
VS
WKin
3
Wake-up
Timer
Control
Unit
with
Mode
Selection
EN
ATA663211 [DATASHEET]
9359C–AUTO–10/14
Sleep
Mode
8
2
2
Normal/
Fail-safe
Mode
INH
2.
Pin Configuration
Figure 2-1. Pinning DFN8 and SO8
RXD
EN
WKin
TXD
Table 2-1.
DFN8
3x3
INH
VS
LIN
GND
RXD
EN
WKin
TXD
1
2
3
4
8
7
SO8
6
5
INH
VS
LIN
GND
Pin Description
Pin
Symbol
1
RXD
Function
Receive data output
2
EN
3
WKin
High voltage input for local wake-up request. If not needed, connect directly to VS
4
TXD
Transmit data input
5
GND
Ground, heat slug
6
LIN
LIN bus line input/output
7
VS
Supply voltage
8
INH
Battery-related high-side switch output for controlling an external voltage regulator or to
switch off the LIN master pull-up resistor; switched on after a wake-up request
Backside
Enables normal mode if the input is high
Heat slug, internally connected to the GND pin
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3.
Pin Description
3.1
Supply Pin (VS)
LIN operating voltage is VS = 5V to 28V. Undervoltage detection is implemented to disable transmission if VS falls below typ.
4.5V, thereby avoiding false bus messages. After switching on VS, the IC starts in fail-safe mode and the INH output is
switched on.
The supply current in sleep mode is typically 9µA.
3.2
Ground Pin (GND)
The IC does not affect the LIN bus in the event of GND disconnection. It is able to handle a ground shift of up to 11.5% of VS.
3.3
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown as well as an internal pull-up resistor according to LIN
specification 2.x is implemented. The voltage range is from –27V to +40V. This pin exhibits no reverse current from the LIN
bus to VS, even in the event of a GND shift or VBat disconnection. The LIN receiver thresholds comply with the LIN protocol
specification.
The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope-controlled.
During a short circuit at LIN to VBat, the output limits the output current to IBUS_LIM. Due to the power dissipation, the chip
temperature exceeds TLINoff and the LIN output is switched off. The chip cools down and after a hysteresis of Thys, switches
the output on again. RXD stays on high because LIN is high.
During a short circuit from LIN to GND the IC can be switched into sleep mode and even in this case the current
consumption is lower than 100µA. If the short-circuit disappears, the IC starts with a remote wake-up.
The reverse current is < 2µA at pin LIN during loss of VBat. This is optimal behavior for bus systems where some slave nodes
are supplied from battery or ignition.
3.4
Input/Output (TXD)
In normal mode the TXD pin is the microcontroller interface for controlling the state of the LIN output. TXD must be pulled to
ground in order to drive the LIN bus low. If TXD is high, the LIN output transistor is turned off and the bus is in the recessive
state. If the TXD pin stays at GND level while switching into normal mode, it must be pulled to high level longer than 10µs
before the LIN driver can be activated. This feature prevents the bus line from being accidentally driven to dominant state
after normal mode has been activated (also in case of a short circuit at TXD to GND). During fail-safe mode, this pin is used
as output and signals the fail-safe source.
The TXD pin provides a pull-down resistor in order to have a defined level if TXD is disconnected.
An internal timer prevents the bus line from being driven permanently in the dominant state. If TXD is forced to low longer
than tdom > 20ms, the LIN bus driver is switched to the recessive state. Nevertheless, when switching to sleep mode, the
actual level at the TXD pin is relevant.
To reactivate the LIN bus driver, switch TXD to high (>10µs).
3.5
Output Pin (RXD)
In normal mode this pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is indicated by a
high level at RXD; LIN low (dominant state) is indicated by a low level at RXD.
The output is an open drain; therefore, it is compatible with a 3.3V or 5V power supply. The AC characteristics are defined by
an external pull-up resistor of 4.7kOhm to 5V and a load capacitor of 20pF.
In unpowered mode, RXD is switched off.
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ATA663211 [DATASHEET]
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3.6
Enable Input Pin (EN)
The enable input pin controls the operating mode of the device. If EN is high, the circuit is in normal mode, with transmission
paths from TXD to LIN and from LIN to RXD both active.
If EN is switched to low while TXD is still high, the device is forced to sleep mode. No data transmission is then possible, and
current consumption is reduced to IVSsleep typ. 9µA.
The EN pin provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected.
3.7
Inhibit Output Pin (INH)
This pin is used to control an external voltage regulator or to switch the LIN master pull-up resistor ON/OFF in case the
device is used in a master node. The inhibit pin provides an internal switch toward the VS pin which is protected by
temperature monitoring. If the device is in normal or fail-safe mode, the inhibit high-side switch is turned on. When the device
is in sleep mode, the inhibit switch is turned off, thus disabling the voltage regulator or other connected external devices.
A wake-up event on the LIN bus or at the WKin pin switches the INH pin to the VS level. After a system power-up (VS rises
from zero), the INH pin switches to the VS level automatically.
3.8
WKin Pin
This pin is a high-voltage input used for waking up the device from sleep mode. It is usually connected to an external switch
in the application to generate a local wake-up. A pull-up current source with typically 10µA is implemented. The voltage
threshold for a wake-up signal is typically 2V below the VS voltage.
If a local wake up is not needed in the application, the WKin pin can be connected directly to the VS pin.
ATA663211 [DATASHEET]
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4.
Functional Description
4.1
Physical Layer Compatibility
Because the LIN physical layer is independent of higher LIN layers (e.g., LIN protocol layer), all nodes with a LIN physical
layer according to revision 2.x can be mixed with LIN physical layer nodes based on earlier versions (i.e., LIN 1.0, LIN 1.1,
LIN 1.2, LIN 1.3) without any restrictions.
4.2
Operating Modes
Figure 4-1. Operating Modes
a: VS > VVS_th_U_F_up (2.4V)
b: VS < VVS_th_U_down (1.9V)
c: Bus wake-up event (LIN)
d: e: VS < VVS_th_N_F_down (3.9V)
f: VS > VVS_th_F_N_up (4.9V)
g: Local WAKE event (WKin)
Unpowered Mode
All circuitry OFF
a
b
Fail-safe Mode
(c + g) & f
EN = 0
&f
Communication: OFF
Wake-up Signalling
Undervoltage Signalling
INH output switched ON
EN = 1
&f
b
e
Sleep Mode
Communication: OFF
INH output switched OFF
Table 4-1.
EN = 1
Normal Mode
&f
Go to sleep
command EN = 0
Communication: ON
INH output switched ON
Operating Modes
Operating Mode
Fail-safe
Transceiver
INH
LIN
OFF
ON, except
VS <
TXD
RXD
Recessive
Signaling fail-safe sources (see Table 4-2)
Follows data transmission
VVS_th_N_F_down
6
Normal
ON
ON
TXDdependent
Sleep/Unpowered
OFF
OFF
Recessive
ATA663211 [DATASHEET]
9359C–AUTO–10/14
High
High
Low
Low
4.2.1
Normal Mode
This is the normal transmitting and receiving mode of the LIN Interface, in accordance with LIN specification 2.x.
4.2.2
Sleep Mode
A falling edge at EN switches the IC into sleep mode. In sleep mode the transmission path is disabled and the device is in
low-power mode. Supply current from VBat is typically 9μA. In sleep mode the INH pin is switched off. The internal
termination between the LIN pin and VS pin is disabled. Only a weak pull-up current (typical 10μA) between the LIN pin and
VS pin is present. Sleep mode can be activated independently from the actual level on the LIN or WKin pin.
If the TXD pin is short-circuited to GND, it is possible to switch to sleep mode via EN after t > tdom.
4.2.3
Fail-Safe Mode
The device automatically switches to fail-safe mode at system power-up or after a wake-up event. The INH output is
switched on and the LIN transceiver is switched off. The IC stays in this mode until EN is switched to high. The IC then
changes to normal mode. During fail-safe mode the TXD pin is an output and, together with the RXD output pin, signals the
fail-safe source.
If the device enters fail-safe mode coming from the normal mode (EN=1) due to an VS undervoltage condition
(VS < VVS_th_N_F_down), it is possible to switch into sleep mode by a falling edge at the EN input. With this feature the current
consumption can be further reduced.
A wake-up event from sleep mode is signalled to the microcontroller using the RXD pin and the TXD pin. A VS undervoltage
condition is also signalled at these two pins. The coding is shown in the table below.
Table 4-2.
Signaling in Fail-safe Mode
Fail-Safe Sources
TXD
RXD
LIN wake-up (LIN pin)
Low
Low
Local wake-up (WKin pin)
Low
High
VSth (battery) undervoltage detection (VS < 3.9V)
High
Low
ATA663211 [DATASHEET]
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4.3
Wake-up Scenarios from Sleep Mode
4.3.1
Remote Wake-up via LIN Bus
4.3.1.1 Remote Wake-up from Sleep Mode
A voltage lower than the LIN pre-wake detection VLINL at the LIN pin activates the internal LIN receiver and starts the wakeup detection timer. A falling edge at the LIN pin, followed by a dominant bus level maintained for a certain period of time
(> tBUS) and following a rising edge at the LIN pin result in a remote wake-up request and the device switches to fail-safe
mode. The INH pin is activated (switches to VS) and the internal termination resistor is switched on. The remote wake-up
request is indicated by a low level at pin RXD and interrupts the microcontroller.
Figure 4-2. LIN Wake-up from Sleep Mode
Fail-safe Mode
Normal Mode
Bus wake-up filtering time
(tBUS)
LIN bus
High
INH
Low or floating
RXD
Low
TXD
External
voltage
regulator
Low (strong pull-down)
On state
Off state
Regulator wake-up time delay
EN High
EN
Node in sleep state
Microcontroller start-up
delay time
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ATA663211 [DATASHEET]
9359C–AUTO–10/14
4.3.2
Local Wake-up via WKin Pin
A falling edge at the WKin pin followed by a low level maintained for a certain period of time (> tWKin) result in a local wake-up
request and the device switches to fail-safe mode. The INH pin is activated (switches to VS) and the internal slave
termination resistor is switched on.
The local wake-up request is indicated by a low level at the TXD pin and a high level at the RXD pin, generating an interrupt
for the microcontroller. Even when the WKin pin is low, it is possible to switch to sleep mode via the EN pin. In this case, the
wake-up signal has to be switched to high > 10µs before the negative edge at WKin starts a new local wake-up request.
Figure 4-3. Local Wake-up from Wake-up Switch
Fail-safe Mode
Normal Mode
State change
WKin
High
INH
Low or floating
High
RXD
TXD
Low (strong pull-down)
Wake filtering time
External
voltage
regulator
tWKin
On state
Off state
Regulator wake-up time delay
EN High
EN
Node in sleep state
Microcontroller start-up
delay time
ATA663211 [DATASHEET]
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4.3.3
Wake-up Source Recognition
The device can distinguish between different wake-up sources. The wake-up source can be read on the TXD and RXD pin in
fail-safe mode. These flags are immediately reset if the microcontroller sets the EN pin to high and the IC is in normal mode.
Table 4-3.
4.4
Signaling in Fail-safe Mode
Fail-Safe Sources
TXD
RXD
LIN wake-up (LIN pin)
Low
Low
Local wake-up (WKin pin)
Low
High
VSth (battery) undervoltage detection (VS < 3.9V)
High
Low
Behavior under Low Supply Voltage Condition
After the battery voltage has been connected to the application circuit, the voltage at the VS pin increases according to the
block capacitor used in the application (see Fig. 5-1 on page 15). If VVS is higher than the minimum VS operation threshold
VVS_th_U_F_up, the IC mode changes from unpowered mode to fail-safe mode, the INH output is switched on and the LIN
transceiver can be activated.
If during sleep mode the voltage level of VVS drops below the undervoltage detection threshold VVS_th_N_F_down (typ. 4.3V),
the operation mode is not changed and no wake-up is possible. Only if the supply voltage on pin VS drops below the VS
operation threshold VVS_th_U_down (typ. 2.05V), does the IC switch to unpowered mode.
If during normal mode the voltage level on the VS pin drops below the VS undervoltage detection threshold VVS_th_N_F_down
(typ. 4.3V), the IC switches to fail-safe mode. This means the LIN transceiver is disabled in order to avoid malfunctions or
false bus messages. If the supply voltage VS drops further below the VS operation threshold VVS_th_U_down (typ. 2.05V), the
IC switches to unpowered mode and the INH output switches off.
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ATA663211 [DATASHEET]
9359C–AUTO–10/14
5.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Supply voltage VS
Symbol
Min.
VS
Logic pins voltage levels (RxD, TxD, EN,
NRES)
Logic output DC currents
ILogic
LIN
- DC voltage
- Pulse time < 500ms
INH
-DC voltage
WKin voltage levels
- DC voltage
-Transient voltage according to ISO7637
(coupling 1nF), (with 2.7K serial resistor)
INH
VWKin
ESD according to IBEE LIN EMC
Test specification 1.0 following IEC 61000-4-2
- Pin VS, LIN to GND, WKin (with ext.
circuitry acc. applications diagram)
Typ.
Max.
Unit
–0.3
+40
V
–0.3
+5.5
V
–5
+5
mA
–27
+40
+43.5
V
V
–0.3
Vs + 0,3
V
–0.3
+40
–150
+100
V
±6
KV
±6
±5
KV
KV
±3
KV
CDM ESD STM 5.3.1
±750
V
Machine Model ESD
AEC-Q100-RevF(003)
±200
V
ESD HBM following STM5.1
with 1.5k/100pF
- Pin VS, LIN, INH to GND
- Pin WKin to GND
HBM ESD
ANSI/ESD-STM5.1
JESD22-A114
AEC-Q100 (002)
Junction temperature
Tj
–40
+150
°C
Storage temperature
Ts
–55
+150
°C
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6.
Thermal Characteristics DFN8
Parameters
Symbol
Min.
Typ.
Max.
Unit
Thermal resistance junction to heat slug
RthjC
10
K/W
Thermal resistance junction to ambient, where
heat slug is soldered to PCB according to JEDEC
Rthja
50
K/W
Thermal shutdown
Toff
Thermal shutdown hysteresis
Thys
7.
150
165
180
°C
10
°C
Thermal Characteristics SO8
Parameters
Symbol
Thermal resistance junction ambient
RthJA
Special heat sink at GND (pin 5) on PCB (fused
lead frame to pin 5)
RthJA
Min.
Typ.
Max.
Unit
145
K/W
80
K/W
Thermal shutdown
Toff
150
165
180
°C
Thermal shutdown hysteresis
Thys
5
10
20
°C
8.
Electrical Characteristics
5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
1
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Type*
VS pin
1.1 Nominal DC voltage range
1.3
Pin
Supply current in sleep
mode
VS
VS
5
13.5
28
V
A
Sleep mode
VLIN > VS – 0.5V
VS < 14V, T = 27°C
VS
IVSsleep
3
9
15
µA
B
Sleep mode
VLIN > VS – 0.5V
VS < 14V
VS
IVSsleep
3
11
18
µA
A
Sleep mode, VLIN = 0V
bus shorted to GND
VS < 14V
VS
IVSsleep_short
20
50
100
µA
A
1.4
Supply current in normal
mode
Bus recessive
VS < 14V
VS
IVSrec
150
250
320
µA
A
1.5
Supply current in normal
mode
Bus dominant (internal
LIN pull-up resistor active)
VS < 14V
VS
IVSdom
200
700
950
µA
A
1.6
Supply current in fail-safe Bus recessive
mode
VS < 14V
VS
IVSfail
40
80
110
µA
A
VS
VVS_th_N_F_down
3.9
4.3
4.7
V
A
VS
VVS_th_F_N_up
4.1
4.6
4.9
V
A
VS
VVS_hys_F_N
0.1
0.25
0.4
V
A
VS undervoltage threshold Decreasing supply voltage
1.7 (switching from normal to
Increasing supply voltage
fail-safe mode)
1.8
VS undervoltage
hysteresis
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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ATA663211 [DATASHEET]
9359C–AUTO–10/14
8.
Electrical Characteristics (Continued)
5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
VS operation threshold
1.9 (switching to unpowered
mode)
Switch to unpowered mode
VS
VVS_th_U_down
1.9
2.05
2.3
V
A
Switch from unpowered to
fail-safe mode
VS
VVS_th_U_F_up
2.0
2.25
2.4
V
A
VS
VVS_hys_U
0.1
0.2
0.3
V
A
0.2
0.4
V
A
1.10
2
VS undervoltage
hysteresis
RXD output pin (open drain)
Low-level output sink
capability
Normal mode,
VLIN = 0V, IRXD = 2mA
RXD
VRXDL
2.3 High-level leakage current
Normal mode
VLIN = VS, VRXD = 5V
RXD
IRXDH
-3
+3
µA
A
3.1 Low-level voltage input
TXD
VTXDL
–0.3
+0.8
V
A
3.2 High-level voltage input
TXD
VTXDH
2
5.5
V
A
VTXD = 5V
TXD
RTXD
150
300
k
A
3.6 Low-level leakage current VTXD = 0V
TXD
ITXD
–3
+3
µA
A
Low-level output sink
3.7 current at wake-up
request
TXD
ITXD
2
8
mA
A
4.1 Low-level voltage input
EN
VENL
–0.3
+0.8
V
A
4.2 High-level voltage input
EN
VENH
2
5.5
V
A
200
k
A
2.1
3
TXD input/output pin
3.5 Pull-down resistor
4
Fail-safe Mode
VTXD = 0.4V
200
2.5
EN input pin
4.3 Pull-down resistor
VEN = 5V
EN
REN
50
4.4 Low-level input current
VEN = 0V
EN
IEN
–3
+3
µA
A
WKin
VWKinH
VS – 1V
VS +
0.3V
V
A
VWKinL
–1
VS –
3.3V
V
A
6
125
WKin input pin
6.1 High-level input voltage
6.2 Low-level input voltage
Initializes a wake-up signal
WKin
6.3 WKin pull-up current
VS < 28V, VWKin = 0V
WKin
IWKin
–30
6.4 High-level leakage current VS = 28V, VWKin = 28V
WKin
IWKinL
–5
Debounce time of low
6.5 pulse for wake-up via
WKin
WKin
tWKin
50
VWKin = 0V
–10
100
µA
A
+5
µA
A
150
µs
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA663211 [DATASHEET]
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8.
Electrical Characteristics (Continued)
5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Normal or fail-safe mode
INH
RDSon,INH
7.2 Leakage current
Transceiver in sleep mode,
VINH = 0V/28V, VS = 28V
INH
Ileak,INH
7.3 High-level voltage
Normal or fail-safe mode
IINH = –15mA
INH
VINH
7
7.1
10
10.1
Min.
Typ.
Max.
Unit
Type*
12
25

A
–3
+3
µA
A
VS – 0.75
VS
V
A
INH output pin
Switch on resistance
between VS and INH
LIN bus driver: bus load conditions:
Load 1 (small): 1nF, 1k; Load 2 (large): 10nF, 500; External Pull-up RRXD = 4.7k ; CRXD = 20pF, Load 3 (medium): 6.8nF,
660 characterized on samples
12.7 and 12.8 specifies the timing parameters for proper operation at 20kb/s and 12.9 and 12.10 at 10.4kb/s
Driver recessive output
voltage
Load1/Load2
LIN
VBUSrec
10.2 Driver dominant voltage
VVS = 7V
Rload = 500
LIN
10.3 Driver dominant voltage
VVS = 18V
Rload = 500
10.4 Driver dominant voltage
0.9  VS
VS
V
A
V_LoSUP
1.2
V
A
LIN
V_HiSUP
2
V
A
VVS = 7V
Rload = 1000
LIN
V_LoSUP_1k
0.6
V
A
10.5 Driver dominant voltage
VVS = 18V
Rload = 1000
LIN
V_HiSUP_1k
0.8
V
A
10.6 Pull-up resistor to VS
The serial diode is
mandatory
LIN
RLIN
20
47
k
A
1.0
V
D
200
mA
A
mA
A
30
10.7
Voltage drop at the serial In pull-up path with Rslave
ISerDiode = 10mA
diodes
LIN
VSerDiode
0.4
10.8
LIN current limitation
VBUS = VBat_max
LIN
IBUS_LIM
40
120
LIN
IBUS_PAS_dom
–1
–0.35
Driver off
8V < VBat < 18V
8V < VBUS < 18V
VBUS ≥ VBat
LIN
IBUS_PAS_rec
Leakage current when
control unit disconnected
GNDDevice = VS
from ground.
10.11
V = 12V
Loss of local ground must Bat
0V < VBUS < 18V
not affect communication
in the residual network
LIN
IBUS_NO_gnd
Leakage current at
disconnected battery.
Node has to sustain the VBat disconnected
10.12 current that can flow under VSUP_Device = GND
this condition. Bus must 0V < VBUS < 18V
remain operational under
this condition.
LIN
IBUS_NO_bat
Input leakage current
Input leakage current at
driver off
10.9 the receiver including pullVBUS = 0V
up resistor as specified
VBat = 12V
Leakage current LIN
10.10
recessive
–10
10
20
µA
A
+0.5
+10
µA
A
0.1
2
µA
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
14
ATA663211 [DATASHEET]
9359C–AUTO–10/14
8.
Electrical Characteristics (Continued)
5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
Pin
Symbol
Max.
Unit
Type*
LIN
CLIN
20
pF
D
VBUS_CNT =
(Vth_dom + Vth_rec)/2
LIN
VBUS_CNT
0.525 
VS
V
A
11.2 Receiver dominant state
VEN = 5V
LIN
VBUSdom
11.3 Receiver recessive state
VEN = 5V
LIN
VBUSrec
–27
0.4  VS
V
A
0.6  VS
40
V
A
LIN
VBUShys
0.028 
VS
0.175 
VS
V
A
LIN
VLINH
VS – 2V
VS +
0.3V
V
A
Activates the LIN receiver
LIN
VLINL
–27
VS – 3.3V
V
A
VLIN = 0V
LIN
tbus
50
100
150
µs
A
Time delay for mode
12.2 change from fail-safe into VEN = 5V
normal mode via EN pin
EN
tnorm
5
15
20
µs
A
Time delay for mode
12.3 change from normal mode VEN = 0V
to sleep mode via EN pin
EN
tsleep
5
15
20
µs
A
Time delay for mode
12.4 change from sleep mode VEN = 5V
to normal mode via EN pin
EN
ts_norm
150
300
µs
A
VTXD = 0V
TXD
tdom
20
40
60
ms
A
12.7 Duty cycle 1
THRec(max) = 0.744  VS
THDom(max) = 0.581  VS
VS = 7.0V to 18V
tBit = 50µs
D1 = tbus_rec(min)/(2  tBit)
LIN
D1
0.396
12.8 Duty cycle 2
THRec(min) = 0.422  VS
THDom(min) = 0.284  VS
VS = 7.6V to 18V
tBit = 50µs
D2 = tbus_rec(max)/(2  tBit)
LIN
D2
12.9 Duty cycle 3
THRec(max) = 0.778  VS
THDom(max) = 0.616  VS
VS = 7.0V to 18V
tBit = 96µs
D3 = tbus_rec(min)/(2  tBit)
LIN
D3
12.10 Duty cycle 4
THRec(min) = 0.389  VS
THDom(min) = 0.251  VS
VS = 7.6V to 18V
tBit = 96µs
D4 = tbus_rec(max)/(2  tBit)
LIN
D4
10.13
11
11.1
Test Conditions
Capacitance on pin LIN to
GND
Center of receiver
threshold
11.5
Pre-wake detection LIN
high-level input voltage
11.6
Pre-wake detection LIN
low-level input voltage
12.1
12.5
Typ.
LIN bus receiver
11.4 Receiver input hysteresis Vhys = Vth_rec – Vth_dom
12
Min.
0.475 
VS
0.5 
VS
0.1 x VS
Internal timers
Dominant time for
wake-up via LIN bus
TXD dominant time-out
time
A
0.581
0.417
A
A
0.590
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA663211 [DATASHEET]
9359C–AUTO–10/14
15
8.
Electrical Characteristics (Continued)
5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
12.11
Slope time falling and
rising edge at LIN
Test Conditions
Pin
Symbol
Min.
VS = 7.0V to 18V
LIN
tSLOPE_fall
tSLOPE_rise
3.5
Typ.
Max.
Unit
Type*
22.5
µs
A
6
µs
A
+2
µs
A
Receiver electrical AC parameters of the LIN physical layer
LIN receiver, RXD load conditions: CRXD = 20pF, RRXD = 4.7k
13
13.1
Propagation delay of
receiver
Symmetry of receiver
13.2 propagation delay rising
edge minus falling edge
VS = 7.0V to 18V
trx_pd = max(trx_pdr , trx_pdf)
RXD
trx_pd
VS = 7.0V to 18V
trx_sym = trx_pdr – trx_pdf
RXD
trx_sym
–2
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Figure 8-1. Definition of Bus Timing Characteristics
tBit
tBit
tBit
TXD
(Input to transmitting node)
tBus_dom(max)
tBus_rec(min)
Thresholds of
receiving node1
THRec(max)
VS
(Transceiver supply
of transmitting node)
THDom(max)
LIN Bus Signal
Thresholds of
receiving node2
THRec(min)
THDom(min)
tBus_dom(min)
tBus_rec(max)
RXD
(Output of receiving node1)
trx_pdf(1)
trx_pdr(1)
RXD
(Output of receiving node2)
trx_pdr(2)
16
ATA663211 [DATASHEET]
9359C–AUTO–10/14
trx_pdf(2)
9.
Application Circuits
Figure 9-1. Typical Application Circuit
D1
VBAT
C1
10µF/50V
12V
5V
VCC
C5
C4
100nF
2.2µF
R7
4.7kΩ
R4
10kΩ
D2
R2
1kΩ
VCC
RXD
Atmel
ATA663211
EN
Microcontroller
R3
WKin
2.7kΩ
GND
S1
Note:
Master node
pull up
INH
VS
DFN8
3x3
TXD
C2
100nF
LIN
LIN
C3
220pF
GND
GND
external
wakeswitch
Heat slug must always be connected to GND.
ATA663211 [DATASHEET]
9359C–AUTO–10/14
17
10.
Ordering Information
Extended Type Number
Package
Remarks
ATA663211-GBQW
DFN8
LIN transceiver, Pb-free, 6k, taped and reeled
ATA663211-GAQW
SO8
LIN transceiver, Pb-free, 4k, taped and reeled
11.
Package Information
Figure 11-1. DFN8
Top View
D
8
E
PIN 1 ID
technical drawings
according to DIN
specifications
1
A
A3
A1
Dimensions in mm
Side View
Partially Plated Surface
Bottom View
4
COMMON DIMENSIONS
E2
1
Z
8
(Unit of Measure = mm)
5
e
D2
L
Z 10:1
Symbol
MIN
NOM
MAX
A
0.8
0.85
0.9
A1
A3
0
0.16
0.035
0.21
0.05
0.26
D
2.9
3
3.1
D2
2.3
2.4
2.5
E
2.9
3
3.1
E2
1.5
1.6
1.7
L
0.35
0.4
0.45
b
e
0.25
0.3
0.65
0.35
NOTE
b
10/11/13
TITLE
Package Drawing Contact:
[email protected]
18
ATA663211 [DATASHEET]
9359C–AUTO–10/14
Package: VDFN_3x3_8L
Exposed pad 2.4x1.6
GPC
DRAWING NO.
REV.
6.543-5165.03-4
1
Figure 11-2. SO8
E1
L
A
b
A2
A1
C
D
e
8
E
5
technical drawings
according to DIN
specifications
Dimensions in mm
1
4
COMMON DIMENSIONS
Pin 1 identity
(Unit of Measure = mm)
Symbol
MIN
NOM
MAX
A
1.5
1.65
1.8
A1
0.1
0.15
0.25
A2
1.4
1.47
1.55
D
4.8
4.9
5
E
5.8
6
6.2
E1
3.8
3.9
4
L
0.4
0.65
0.9
C
0.15
0.2
0.25
b
0.3
0.4
0.5
e
NOTE
1.27 BSC
05/08/14
TITLE
Package Drawing Contact:
[email protected]
Package: SO8
GPC
DRAWING NO.
REV.
6.543-5185.01-4
1
ATA663211 [DATASHEET]
9359C–AUTO–10/14
19
12.
Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No.
History
SO8 package added
9359C-AUTO-10/14
Number 3.5 in Section 8 “Electrical Characteristics” on page 13 update
Section 10 “Ordering Information” on page 18 updated
20
ATA663211 [DATASHEET]
9359C–AUTO–10/14
XXXXXX
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