AT30TS74 - Complete

AT30TS74
9- to 12-bit Selectable, ±1.0°C Accurate
Digital Temperature Sensor
DATASHEET
Features



Single 1.7V to 5.5V Supply
Measures Temperature From -55C to +125C
Highly Accurate Temperature Measurements Requiring No External
Components
̶
̶
±1.0C Accuracy (Typical) Over the -20C to +100C Range
±1.0C Accuracy (Typical) Over the -10C to +100C Range (WLCSP Only)
±2.0C Accuracy (Typical) Over the -40C to +125C Range
̶

User-configurable Resolution
̶



9 to 12 bits (0.5C to 0.0625C)
User-configurable High and Low Temperature Limits
ALERT Output Pin for Indicating Temperature Alarms
2-Wire I2C and SMBus™ Compatible Serial Interface
̶
Supports SMBus Timeout
Supports SMBus Alert and Alert Response Address (ARA)
Selectable Addressing Allows Up to Eight Devices on the Same Bus
̶
̶
2

I C High-Speed (HS) Mode Compatible

Built-in noise Suppression Filtering for Clock and Data Input Signals
Low-power Dissipation
̶

̶
3.4MHz Maximum Clock Frequency
85μA Active Current (Typical) During Temperature Measurements

Shutdown Mode to Minimize Power Consumption

One-Shot Mode for Single Temperature Measurement While in Shutdown
Mode
Pin and Software Compatible to Industry-standard LM75-type Devices
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
̶


̶
̶
̶
̶
̶
1μA Shutdown Current (Typical)
8-lead SOIC (150mil)
8-lead MSOP (3.0 x 3.0mm)
8-pad Ultra Thin DFN (UDFN — 2.0 x 3.0 x 0.6mm)
4-ball WLCSP
5-ball WLCSP
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
Description
The Atmel® AT30TS74 is a complete, precise temperature monitoring device designed for use in a variety of
applications which require the measuring of local temperatures as an integral part of the system's function
and/or reliability. The AT30TS74 device combines a high-precision digital temperature sensor, programmable
high and low temperature alarms, and a 2-Wire I2C and SMBus (System Management Bus) compatible serial
interface into a single compact package.
The temperature sensor can measure temperatures over the full -55C to +125C temperature range and has a
maximum accuracy of ±2.0C from -20C to +100C. The result of the digitized temperature measurements are
stored in one of the AT30TS74 internal registers, which is readable at any time through the device's serial
interface.
The AT30TS74 utilizes flexible, user-programmable internal registers to configure the temperature sensor's
performance and response to high and low temperature conditions. A dedicated alarm output activates if the
temperature measurement exceeds the user-defined temperature and fault count limits. To reduce current
consumption and save power, the AT30TS74 features a Shutdown mode which turns off all internal circuitry
except for the internal Power-On Reset (POR) and serial interface circuits.
The AT30TS74 is factory-calibrated and requires no external components to measure temperature. With its
flexibility and high-degree of accuracy, the AT30TS74 is ideal for extended temperature measurements in a
wide variety of communication, computer, consumer, environmental, industrial, and instrumentation
applications.
2
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
T a b l e o f C o n te n ts
1.
Pin Descriptions and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.
Device Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
3.2
3.3
3.4
4.
4.5
5.4
Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1
OS Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2
R1:R0 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3
FT1:FT0 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.4
POL Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.5
CMP/INT Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.6
SD Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLOW and THIGH Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
17
20
21
21
21
22
22
22
23
SMBus Features and I2C General Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1
6.2
6.3
7.
WLCSP (Wafer Level Chip Scale Package) Device Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
High-Speed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Temperature Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Temperature Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4.1
Fault Tolerance Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4.2
Comparator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4.3
Interrupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Shutdown Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5.1
One-Shot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1
5.2
5.3
6.
7
7
7
8
Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1
4.2
4.3
4.4
5.
Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acknowledge (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
No-Acknowledge (NACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBus Alert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SMBus Timeout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
General Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC and AC Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Sensor Accuracy and Conversion Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Test Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
27
28
29
29
30
31
31
31
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
3
8.
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.1
8.2
9.
Atmel Ordering Code Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Green Package Options (Pb/Halide-free/RoHS Compliant) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Part Marking Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.1
10.2
10.3
10.4
10.5
8S1 — 8-lead JEDEC SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8XM — 8-lead MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8MA2 — 8-pad UDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4U-3 — 4-ball WLCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5U-5 — 5-ball WLCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
36
37
38
39
11. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.1
No Errata. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
1.
Pin Descriptions and Pinouts
Table 1.
Pin Description
Symbol
Name and Function
SCL
Serial Clock: This pin is used to provide a clock to the device and is used to control
the flow of data to and from the device. Command and input data present on the
SDA pin is always latched in on the rising edge of SCL, while output data on the
SDA pin is always clocked out on the falling edge of SCL.
Asserted
State
Type
—
Input
—
Input/Output
—
Output
—
Input
—
Power
—
Power
The SCL pin must either be forced high when the serial bus is idle or pulled-high
using an external pull-up resistor.
Serial Data: The SDA pin is an open-drain bidirectional input/output pin used to
serially transfer data to and from the device.
SDA
The SDA pin must be pulled-high using an external pull-up resistor and may be
wire-ANDed with any number of other open-drain or open-collector pins from other
devices on the same bus.
Alert: The ALERT pin is an open-drain output pin used to indicate when the
temperature goes beyond the user-programmed temperature limits. The ALERT pin
can be operated in one of two different modes (Interrupt or Comparator mode) as
defined by the CMP/INT bit in the Configuration Register. The ALERT pin defaults
to an active-low output upon device power-up or reset but can be reconfigured as
an active-high output by setting the POL bit in the Configuration Register.
ALERT
This pin can be wire-ANDed together with ALERT pins from other devices on the
same bus. When wire-ANDing pins together, the ALERT pin should be configured
as an active-low output so that when a single ALERT pin on the common alert bus
goes active, the entire common alert bus will go low and the host controller will be
properly notified since other ALERT pins that may be in the inactive-high state will
not mask the true alert signal. In an SMBus environment, the SMBus host can
respond by sending an SMBus ARA (Alert Response Address) command to
determine which device on the SMBus generated the alert signal.
The ALERT pin must be pulled-high using an external pull-up resistor even when it
is not used. Care must also be taken to prevent this pin from being shorted directly
to ground without a resistor at any time whether during testing or normal operation.
A2-0
Address Inputs: The A2-0 pins are used to select the device address and
correspond to the three least-significant bits (LSBs) of the I2C/SMBus 7-bit slave
address. These pins can be directly connected in any combination to VCC or GND,
and by utilizing the A2-0 pins, up to eight devices may be addressed on a single bus.
The A2-0 pins are internally pulled to GND and may be left floating; however, it is
highly recommended the A2-0 pins always be directly connected to VCC or GND to
ensure a known address state.
For the 4-ball WLCSP offering, see Section 4.1 for additional information.
VCC
GND
Device Power Supply: The VCC pin is used to supply the source voltage to the
device.
Operations at invalid VCC voltages may produce spurious results and should not be
attempted.
Ground: The ground reference for the power supply. GND should be connected to
the system ground.
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
5
Figure 1.
Pin Configurations
8-SOIC
8-MSOP
8-UDFN
(Top View)
(Top View)
(Top View)
1
SDA
8
SDA
1
8
VCC
SDA
1
8
VCC
SCL
2
7
SCL
2
7
A0
A0
A0
ALERT
3
6
A1
ALERT
3
6
A1
GND
4
5
A2
GND
4
5
A2
VCC
SCL
2
7
ALERT
3
6
A1
GND
4
5
A2
5-ball WLCSP
(Top View)
4-ball WLCSP
(Top View)
SCL
SDA
GND
VCC
VCC
VSS
ALRT
SDA
SCL
.
Note: Drawings are not to scale.
2.
Block Diagram
Figure 2-1.
Block Diagram
Pointer
Register
Configuration
Register
THIGH Limit
Register
TLOW Limit
Register
I2C/SMBus
Interface
Control
and
Logic
SCL
SDA
A2-0
6
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
A/D
Converter
Temperature
Sensor
3
ALERT
Temperature
Register
Digital
Comparator
3.
Device Communication
The AT30TS74 operates as a slave device and utilizes a simple 2-Wire I2C and SMBus compatible digital serial
interface to communicate with a host controller, commonly referred to as the bus Master. The Master initiates
and controls all Read and Write operations to the slave devices on the serial bus, and both the Master and the
slave devices can transmit and receive data on the bus.
The serial interface is comprised of just two signal lines:


Serial Clock (SCL):
The SCL pin is used to receive the clock signal from the Master.
Serial Data (SDA):
The bidirectional SDA pin is used to receive command and data information from the Master as well as to
send data back to the Master.
Data is always latched into the AT30TS74 on the rising edge of SCL and always output from the device on the
falling edge of SCL. Both the SCL and SDA pin incorporate integrated spike suppression filters and Schmitt
Triggers to minimize the effects of input spikes and bus noise.
All command and data information is transferred with the Most-Significant Bit (MSB) first. During bus
communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data has been
transferred, the receiving device must respond with either an Acknowledge (ACK) or a No-acknowledge (NACK)
response bit during a ninth clock cycle (ACK/NACK clock cycle) generated by the Master. Therefore, nine clock
cycles are required for every one byte of data transferred. There are no unused clock cycles during any Read or
Write operation, so there must not be any interruptions or breaks in the data stream during each data byte
transfer and ACK or NACK clock cycle.
During data transfers, data on the SDA pin must only change while SCL is low, and the data must remain stable
while SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop condition will
occur. Start and Stop conditions are used to initiate and end all serial bus communication between the Master
and the slave devices. The number of data bytes transferred between a Start and a Stop condition is not limited
and is determined by the Master.
In order for the serial bus to be idle, both the SCL and SDA pins must be in the logic-high state at the same time.
3.1
Start Condition
A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is stable in the
logic-high state. The Master uses a Start condition to initiate any data transfer sequence, and the Start condition
must precede any command. The AT30TS74 will continuously monitor the SDA and SCL pins for a Start
condition, and the device will not respond unless one is given.
3.2
Stop Condition
A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable in the
logic-high state. The Master uses the Stop condition to end a data transfer sequence to the AT30TS74 which
will subsequently return to the idle state. The Master can also utilize a repeated Start condition instead of a Stop
condition to end the current data transfer if the Master will perform another operation.
3.3
Acknowledge (ACK)
After every byte of data received, the AT30TS74 must acknowledge to the Master it has successfully received
the data byte by responding with an ACK. This is accomplished by the Master first releasing the SDA line and
providing the ACK/NACK clock cycle (a ninth clock cycle for every byte). During the ACK/NACK clock cycle, the
AT30TS74 must output a Logic 0 (ACK) for the entire clock cycle such that the SDA line must be stable in the
logic-low state during the entire high period of the clock cycle.
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
7
3.4
No-Acknowledge (NACK)
When the AT30TS74 is transmitting data to the Master, the Master can indicate it is done receiving data and
wants to end the operation by sending a NACK response to the AT30TS74 instead of an ACK response. This is
accomplished by the Master outputting a Logic 1 during the ACK/NACK clock cycle. At which point, the
AT30TS74 will release the SDA line so the Master can then generate a Stop condition.
In addition, the AT30TS74 can use a NACK to respond to the Master instead of an ACK for certain invalid
operation cases such as an attempt to write to a Read-only Register (e.g. an attempt to write to the Temperature
Register).
Figure 3-1.
Start, Stop, and ACK
SCK
Data
Must be
Stable
Data
Must be
Stable
Data
Must be
Stable
1
2
8
9
SDA
Start
Condition
8
Data
Change
Allowed
Data
Change
Allowed
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
Data
Change
Allowed
Data
Change
Allowed
ACK
Stop
Condition
4.
Device Operation
Commands used to configure and control the operation of the AT30TS74 are sent to the device from the Master
via the serial interface. Likewise, the Master can read the temperature data from the AT30TS74 via the serial
interface. However, since multiple slave devices can reside on the serial bus, each slave device must have its
own unique 7-bit address so that the Master can access each device independently.
For the AT30TS74, the first four MSBs of its 7-bit address are the device type identifier and are fixed at 1001.
The remaining three LSBs correspond to the states of the hard-wired A2-0 address pins. For the WLCSP product
offering, see Section 4.1 for additional information on how the device address bits are handled.
Example:
If the A2-0 pins are connected to GND, then the 7-bit device address would be 1001000.
In order for the Master to select and access the AT30TS74, the Master must first initiate a Start condition.
Following the Start condition, the Master must output the device address byte. The device address byte consists
of the 7-bit device address plus a Read/Write (R/W) control bit, which indicates whether the Master will be
performing a Read or a Write to the AT30TS74. If the R/W control bit is a Logic 1, then the Master will be
reading data from the AT30TS74. Alternatively, if the R/W control bit is a Logic 0, then the Master will be writing
data to the AT30TS74.
Table 4-1.
Bit 7
AT30TS74 Address Byte
Bit 6
Bit 5
Bit 4
Bit 3
Device Type Identifier
1
0
0
Bit 2
Bit 1
Device Address
1
A2
A1
Bit 0
Read/Write
A0
R/W
If the 7-bit address sent by the Master matches that of the AT30TS74, then the device will respond with an ACK
after it has received the full address byte. If there is an address mismatch, then the AT30TS74 will respond with
a NACK and return to the idle state.
4.1
WLCSP (Wafer Level Chip Scale Package) Device Addressing
The AT30TS74 is offered in a space saving WLCSP to minimize PCB (Printed Circuit Board) area requirements.
Because of the WLCSP dimensions and to maintain a standard ball size and pitch, only four balls can be placed
on the WLCSP; therefore, there are no hard-wired A2-0 device address pins (pins 5, 6, and 7) available like in
other standard eight pin packages where the user can select the desired hard-wired device address
combination.
However, the AT30TS74 WLCSP product is still available with all eight device address combinations via
ordering a unique part number where each part number variant is internally configured by Atmel with a different
hard-wired A2-0 address as shown in Table 4-2.
Example:
If the desired hard-wired A2-0 device address is 001, then the correct part number to order is the
AT30TS74-UFM11-T and this device will only ACK when the Master initiates a Start condition followed by
a device address byte with matching device address bits (A2=0, A1=0, A0 =1) plus a Read/Write (R/W)
control bit. Otherwise, the AT30TS74 WLCSP will respond with a NACK and return to the idle
state.
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Atmel-8897F-DTS-AT30TS74-Datasheet_012016
9
Table 4-2.
AT30TS74 WLCSP Device Addresses
Device Type Identifier
A1
A0
R/W
I2C Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AT30TS74-UFM10-T
1001 000X
1
0
0
1
0
0
0
X
AT30TS74-UFM11-T
1001 001X
1
0
0
1
0
0
1
X
AT30TS74-UFM12-T
1001 010X
1
0
0
1
0
1
0
X
AT30TS74-UFM13-T
1001 011X
1
0
0
1
0
1
1
X
AT30TS74-UFM14-T
1001 100X
1
0
0
1
1
0
0
X
AT30TS74-UFM15-T
1001 101X
1
0
0
1
1
0
1
X
AT30TS74-UFM16-T
1001 110X
1
0
0
1
1
1
0
X
AT30TS74-UFM17-T
1001 111X
1
0
0
1
1
1
1
X
AT30TS74-U1FMAB-T
1001 000X
1
0
0
1
0
0
0
X
AT30TS74-U1FMBB-T
1001 001X
1
0
0
1
0
0
1
X
AT30TS74-U1FMCB-T
1001 010X
1
0
0
1
0
1
0
X
AT30TS74-U1FMDB-T
1001 011X
1
0
0
1
0
1
1
X
AT30TS74-U1FMEB-T
1001 100X
1
0
0
1
1
0
0
X
AT30TS74-U1FMFB-T
1001 101X
1
0
0
1
1
0
1
X
AT30TS74-U1FMGB-T
1001 110X
1
0
0
1
1
1
0
X
AT30TS74-U1FMHB-T
1001 111X
1
0
0
1
1
1
1
X
Part Number
Note:
4.2
A2
Please contact Atmel for availability of slave address options 011,100,101,110, and 111.
High-Speed Mode
The AT30TS74 supports the I2C High-Speed (HS) mode allowing it to operate at clock frequencies up to
3.4MHz. In order to put the AT30TS74 into the HS mode, the Master must first initiate a Start condition followed
by the HS mode master code of 00001XXX. Since the HS mode master code is meant to be recognized by all
slave devices which support the HS mode, the AT30TS74 will not ACK the HS mode master code. Instead, the
Master will output a NACK during the ACK/NACK clock cycle.
Once the AT30TS74 receives the HS mode master code, it will switch its input filters on SDA and SCL to the HS
mode to allow transfers up to 3.4MHz. The device will then return to the idle state and wait for a repeated Start
condition before the next operation can occur.
To begin the next operation, the Master must issue a repeated Start condition followed by the device address
byte. The AT30TS74 will continue to operate in the HS mode until the Master sends a Stop condition; therefore,
the Master should use repeated Start conditions to begin new operations rather than a Stop-Start sequence.
Once the AT30TS74 receives a Stop condition, the device will switch its input and output filters back to the
standard I2C mode.
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Figure 4-1.
High-Speed Mode
1
2
3
4
5
6
7
8
9
X
X
X
1
SCK
Master Code
SDA
0
0
0
0
1
MSB
Start
by
Master
4.3
NACK
from
Master
Repeated
Start
by
Master
Temperature Measurements
The AT30TS74 utilizes a band-gap type temperature sensor with an internal sigma-delta Analog-to-Digital
Converter (ADC) to measure and convert the temperature reading into a digital value with a selectable
resolution as high as 0.0625C. The measured temperature is calibrated in degrees Celsius; therefore, a lookup
table or conversion routine is necessary for applications that wish to deal in degrees Fahrenheit.
The result of the digitized temperature measurements are stored in the internal Temperature Register of the
AT30TS74, which is readable at any time through the device's serial interface. When in the normal operating
mode, the device performs continuous temperature measurements and updates the contents of the
Temperature Register (see Section 5.2, “Temperature Register”) after each analog-to-digital conversion.
The resolution of the temperature measurement data can be configured to 9, 10, 11, or 12 bits which corresponds
to temperature increments of 0.5C, 0.25C, 0.125C, and 0.0625C, respectively. Selecting the temperature
resolution is done using the R1 and R0 bits in the Configuration Register (see Section 5.3, “Configuration
Register”). The ADC conversion time does increase with each bit of higher resolution, so careful consideration
should be given to the resolution versus conversion time relationship. The default resolution after device
power-up or reset is nine bits, which retains backwards compatibility to industry-standard LM75-type devices.
With 12 bits of resolution, the AT30TS74 can theoretically measure a temperature range of 255C (-128C to
+127C); however, the device is only designed to measure temperatures over a range of -55C to +125C.
4.4
Temperature Alarm
After the measured temperature value has been stored into the Temperature Register, the data will be
compared with both the high and low temperature limits defined by the values stored in the THIGH Limit Register
and TLOW Limit Register. If the comparison results in a valid fault condition (see Section 4.4.1, “Fault Tolerance
Limits”), then the device will activate the ALERT output pin.
The polarity and function of the ALERT pin can be configured by using specific bits in the Configuration
Register. The ALERT pin defaults to the active low state after device power-up or reset but can be reconfigured
to active high by setting the POL bit in the Configuration Register to a Logic 1. The function of the ALERT pin
changes based on the Alarm Thermostat mode, which can be configured to either Comparator mode (see
Section 4.4.2, “Comparator Mode”) or Interrupt mode (see Section 4.4.3, “Interrupt Mode”) by using the
CMP/INT bit in the Configuration Register. The Comparator mode is the default operating mode after the device
powers up or resets.
The value of the high temperature limit stored in the THIGH Limit Register must be greater than the value of the
low temperature limit stored in the TLOW Limit Register in order for the ALERT function to work properly;
otherwise, the ALERT pin will output erroneous results and will falsely signal temperature alarms.
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11
4.4.1
Fault Tolerance Limits
A temperature fault occurs if the measured temperature meets or exceeds either the high temperature limit set
by the THIGH Limit Register or the low temperature limit set by the TLOW Limit Register. To prevent false alarms
due to environmental or temperature noise, the device incorporates a fault tolerance queue that requires
consecutive temperature faults to occur before resulting in a valid fault condition. The fault tolerance queue
value is controlled by the FT1 and FT0 bits in the Configuration Register and can be set to a single fault count of
1 or a count of 2, 4, or 6 consecutive faults.
An internal counter that automatically increments after a temperature fault is used to determine if the fault
tolerance queue setting has been met. After incrementing the fault counter, the device will compare the count to
the fault tolerance queue setting to see if a valid fault condition should be triggered. Once a valid fault condition
occurs, the device will activate the ALERT output pin. If the most recent measured temperature does not meet
or exceed the high or low temperature limit, then the internal fault counter will be reset back to zero.
Figure 4-2 shows a sample temperature profile and how each temperature fault would impact the internal fault
counter.
Figure 4-2.
Fault Count Example
THIGH Limit
Temperature
TLOW Limit
Temperature Measurements/Conversions
4.4.2
Comparator Mode
When the device operates in the Comparator mode, then the ALERT pin goes active if the measured
temperature meets or exceeds the high temperature limit set by the THIGH Limit Register and a valid fault
condition exists (the consecutive number of temperature faults has been reached). The ALERT pin will return to
the inactive state after the measured temperature drops below the TLOW Limit Register value the appropriate
number of times to create a subsequent valid fault condition. The ALERT pin only changes state based on the
high and low temperature limits and fault conditions; reading from or writing to any register or putting the device
into Shutdown mode will not affect the state of the ALERT pin. The high temperature limit set by the THIGH Limit
Register must be greater than the low temperature limit set by the TLOW Limit Register in order for the ALERT
pin to activate correctly.
If switching from Interrupt mode to Comparator mode while the ALERT pin is already active, then the ALERT pin
will remain active until the measured temperature is below the TLOW Limit Register value the appropriate number
of times to create a valid fault condition.
The ALERT pin will return to the inactive state if the device receives the General Call Reset command. In
addition, the state of the Configuration Register will return to the power-on default state, and the device will
remain in the Comparator mode.
Figure 4-3 illustrates both the active high and active low ALERT pin response for a sample temperature profile
with the device configured for the Comparator mode and a fault tolerance queue setting of two.
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Figure 4-3.
Comparator Mode (Fault Tolerance Queue = 2)
THIGH Limit
Temperature
TLOW Limit
ALERT
(Active High, POL = 1)
ALERT
(Active Low, POL = 0)
Temperature Measurements/Conversions
4.4.3
Interrupt Mode
Similar to the Comparator mode, when the device operates in the Interrupt mode, the ALERT pin will go active if
the measured temperature meets or exceeds the high temperature limit set by the THIGH Limit Register and a
valid fault condition exists (the consecutive number of temperature faults has been reached). Unlike the
Comparator mode, however, the ALERT pin will remain active until one of three normal operation events takes
place: any one of the device's registers is read, the device responds to an SMBus Alert Response Address
(ARA), or the device is put into Shutdown mode.
Once the ALERT pin returns to the inactive state, it will not go active again until the measured temperature
drops below the low temperature limit set by the TLOW Limit Register for the appropriate number of consecutive
faults. Again, the ALERT pin will remain active until one of the device's registers is read, the device responds to
an SMBus ARA, or the device is placed into the Shutdown mode.
After the ALERT pin becomes inactive again, the cycle will repeat itself with the ALERT pin going active after the
measured temperature meets or exceeds the THIGH Limit Register value for the proper number of consecutive
faults. This process is cyclical between THIGH and TLOW temperature alarms (e.g. THIGH event, ALERT clear,
TLOW event, ALERT clear, THIGH event, ALERT clear, TLOW event, etc.).
In order for the ALERT pin to normally become active for the first time in the Interrupt Mode, the first event must
be a THIGH temperature alarm event. Therefore, even if the measured temperature initially starts off between the
THIGH and TLOW limits and then drops below the TLOW temperature limit and has met valid fault conditions, the
ALERT pin will still not go active. The high temperature limit set by the THIGH Limit Register must be greater than
the low temperature limit set by the TLOW Limit Register in order for the ALERT pin to activate correctly.
If switching from Comparator mode to Interrupt mode while the ALERT pin is already active, then the ALERT pin
will remain active until it is cleared by one of the events already detailed: any one of the device's registers is
read, the device responds to an SMBus ARA, or the device is put into Shutdown mode. The ALERT pin will also
return to the inactive state if the device receives the General Call Reset command. When reset, the state of the
Configuration Register will return to the power-on default state which will put the device back into the
Comparator mode.
AT30TS74 [DATASHEET]
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13
Figures 4-4 and Figure 4-5 show both the active high and active low ALERT pin response for a sample
temperature profile with the device configured for the Interrupt mode and a fault tolerance queue setting of two.
Figure 4-5 illustrates how the ALERT pin output would look if there was a longer delay between the ALERT
trigger and the reading of a register.
Figure 4-4.
Interrupt Mode (Fault Tolerance Queue = 2)
THIGH Limit
Temperature
TLOW Limit
ALERT
(Active High, POL = 1)
Read Register
Read Register
Read Register
ALERT
(Active Low, POL = 0)
Temperature Measurements/Conversions
Figure 4-5.
Interrupt Mode (Fault Tolerance Queue = 2) Delay Before Reading Register
THIGH Limit
Temperature
TLOW Limit
ALERT
(Active High, POL = 1)
Read Register
ALERT
(Active Low, POL = 0)
Temperature Measurements/Conversions
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Read Register
4.5
Shutdown Mode
To reduce current consumption and save power, the device features a Shutdown mode that disables all internal
device circuitry except for the serial interface and POR circuits. While in the Shutdown mode, the internal
temperature sensor is not active, so no temperature measurements will be made. Entering and exiting the
Shutdown mode is controlled by the SD bit in the Configuration Register.
Entering the Shutdown mode can affect the ALERT pin depending on the Alarm Thermostat mode. If the device
is configured to operate in the Interrupt mode, then the ALERT pin will go inactive when the device enters the
Shutdown mode. However, the ALERT pin will not change states if the device is operating in the Comparator
mode.
The fault count information will not change when the device enters or exits the Shutdown mode. Therefore, the
number of previous temperature faults recorded by the internal fault counter will be retained unless the device is
power-cycled or reset. When exiting the Shutdown mode, the ALERT pin will go active if operating in Interrupt
mode, a valid fault condition exists, and the THIGH and TLOW event cycles are maintained (i.e. THIGH event before
entering Shutdown mode followed by a TLOW event when exiting Shutdown mode).
4.5.1
One-Shot Mode
The AT30TS74 features a One-Shot Temperature mode that allows the device to perform a single temperature
measurement while in the Shutdown mode. By keeping the device in the Shutdown mode and utilizing the OneShot mode, the AT30TS74 can remain in a lower power state and only go active to take temperature
measurements on an as-needed basis. The internal fault counter will be updated when taking a temperature
measurement using the One-Shot mode; therefore, a valid fault condition can be generated by the One-Shot
temperature measurements. If operating in Comparator mode, then the fault condition will cause the ALERT pin
to go either active or inactive depending on if the fault condition is a result of a THIGH or TLOW event. If operating
in Interrupt mode, the fault condition will cause the ALERT pin to pulse active for a short duration of time to
indicate a THIGH or TLOW event has occurred. The ALERT pin will then return to the inactive state.
The One-Shot mode is controlled using the OS bit in the Configuration Register (see Section 5.3.1, “OS Bit”).
AT30TS74 [DATASHEET]
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15
5.
Registers
The AT30TS74 contains five registers (a Pointer Register and four data registers) that are used to control the
operational mode and performance of the temperature sensor, store the user-defined high and low temperature
limits, and store the digitized temperature measurements. All accesses to the device are performed using these
five registers. In order to read from and write to one of the device's four data registers, the user must first select
a desired data register by utilizing the Pointer Register.
Table 5-1.
Registers
Register
Address
Read/Write
Size
Power-on Default
Pointer Register
n/a
W
8-bit
00h
Temperature Register
00h
R
16-bit
0000h
Configuration Register
01h
R/W
16-bit
0000h
TLOW Limit Register
02h
R/W
16-bit
4B00h (75C)
THIGH Limit Register
03h
R/W
16-bit
5000h (80C)
The Configuration Register, despite being 16-bits wide, is compatible to industry standard LM75-type
temperature sensors that use an 8-bit wide register in that only the first 8-bits of the Configuration Register need
to be written to or read from.
5.1
Pointer Register
The 8-bit Write-only Pointer Register is used to address and select which one of the device's four data registers
(Temperature Register, Configuration Register, TLOW Limit Register, or THIGH Limit Register) will be read from or
written to.
For Read operations from the AT30TS74, once the Pointer Register is set to point to a particular data register, it
remains pointed to that same data register until the Pointer Register value is changed.
Example:
If the user sets the Pointer Register to point to the Temperature Register, then all subsequent
reads from the device will output data from the Temperature Register until the Pointer Register
value is changed.
For Write operations to the AT30TS74, the Pointer Register value must be refreshed each time a Write to the
device is to be performed, even if the same data register is going to be written to a second time in a row.
Example:
If the Pointer Register is set to point to the Configuration Register, once the subsequent Write
operation to the Configuration Register has completed, the user cannot write again into the
Configuration Register without first setting the Pointer Register value again. As long as a Write
operation is to be performed, the device will assume that the Pointer Register value is the first
data byte received after the address byte.
Since only four data registers are available for access, only the two LSBs (P1 and P0) of the Pointer Register
are used; the remaining six bits (P7-P2) of the Pointer Register should always be set to zero to allow for future
migration paths to other temperature sensor devices that have more than four data registers. Table 5-2 shows
the bit assignments of the Pointer Register and the associated pointer addresses of the data registers available.
Attempts to write any values other than those listed in Table 5-2 into the Pointer Register will be ignored by the
device, and the contents of the Pointer Register will not be changed. However, the device will respond back to
the Master with an ACK to indicate that the device successfully received a data byte even though no operation
will be performed.
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Table 5-2.
Pointer Register and Address Assignments
Pointer Register Value
P7
P6
P5
P4
P3
P2
P1
P0
Associated
Address
0
0
0
0
0
0
0
0
00h
Temperature Register
0
0
0
0
0
0
0
1
01h
Configuration Register
0
0
0
0
0
0
1
0
02h
TLOW Limit Register
0
0
0
0
0
0
1
1
03h
THIGH Limit Register
Register Selected
To set the value of the Pointer Register, the Master must first initiate a Start condition followed by the AT30TS74
device address byte (1001AAA0 where “AAA” corresponds to the hard-wired A2-0 address pins). After the
AT30TS74 has received the proper address byte, the device will send an ACK to the Master. The Master must
then send the appropriate data byte to the AT30TS74 to set the value of the Pointer Register.
After device power-up or reset, the Pointer Register defaults to 00h which is the Temperature Register location;
therefore, the Temperature Register can be read from immediately after device power-up or reset without
having to set the Pointer Register.
Figure 5-1.
Write Pointer Register
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
P1
P0
0
SCK
Address Byte
SDA
1
0
0
1
A
Pointer Register Byte
A
A
0
0
MSB
Start
by
Master
5.2
P7
P6
P5
P4
P3
P2
MSB
ACK
from
Slave
ACK
from
Slave
Stop
by
Master
Temperature Register
The Temperature Register is a 16-bit Read-only Register that stores the digitized value of the most recent
temperature measurement. The temperature data value is represented in the twos complement format, and,
depending on the resolution selected, up to 12 bits of data will be available for output with the remaining LSBs
being fixed in the Logic 0 state. The Temperature Register can be read at any time, and since temperature
measurements are performed in the background, reading the Temperature Register does not affect any other
operation that may be in progress.
The MSB (bit 15) of the Temperature Register contains the sign bit of the measured temperature value with a
zero indicating a positive number and a one indicating a negative number. The remaining MSBs of the
Temperature Register contain the temperature value in the twos complement format. Table 5-3 details the
Temperature Register format for the different selectable resolutions, and Table 5-4 shows some examples for
12-bit resolution Temperature Register data values and the associated temperature readings.
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Table 5-3.
Temperature Register Format
Upper Byte
Lower Byte
Resolution
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
12 bits
Sign
TD
TD
TD
TD
TD
TD
TD
TD
TD
TD
TD
0
0
0
0
11 bits
Sign
TD
TD
TD
TD
TD
TD
TD
TD
TD
TD
0
0
0
0
0
10 bits
Sign
TD
TD
TD
TD
TD
TD
TD
TD
TD
0
0
0
0
0
0
9 bits
Sign
TD
TD
TD
TD
TD
TD
TD
TD
0
0
0
0
0
0
0
Note:
TD = Temperature Data
Table 5-4.
12-bit Resolution Temperature Data/Values Examples
Temperature Register Data
Temperature
Binary Value
Hex Value
+125°C
0111 1101 0000 0000
7D00h
+100°C
0110 0100 0000 0000
6400h
+75°C
0100 1011 0000 0000
4B00h
+50.5°C
0011 0010 1000 0000
3200h
+25.25°C
0001 1001 0100 0000
1940h
+10.125°C
0000 1010 0010 0000
0A20h
+0.0625°C
0000 0000 0001 0000
0010h
0°C
0000 0000 0000 0000
0000h
-0.0625°C
1111 1111 1111 0000
FFF0h
-10.125°C
1111 0101 1110 0000
F5E0h
-25.25°C
1110 0111 1100 0000
E7C0h
-50.5°C
1100 1110 1000 0000
CE80h
-55°C
1100 1001 0000 0000
C900h
After each temperature measurement and digital conversion is complete, the new temperature data is loaded
into the Temperature Register if the register is not currently being read. If a Read is in progress, then the
previous temperature data will be output.
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In order to read the most recent temperature measurement data, the Pointer Register must be set or have been
previously set to 00h. If the Pointer Register has already been set to 00h, the Temperature Register can be read
by having the Master first initiate a Start condition followed by the AT30TS74 device address byte (1001AAA1
where “AAA” corresponds to the hard-wired A2-0 address pins). After the AT30TS74 has received the proper
address byte, the device will send an ACK to the Master. The Master can then read the upper byte of the
Temperature Register. After the upper byte of the Temperature Register has been clocked out of the
AT30TS74, the Master must send an ACK to indicate that it is ready for the lower byte of the temperature data.
The AT30TS74 will then clock out the lower byte of the Temperature Register, after which the Master must send
a NACK to end the operation. When the AT30TS74 receives the NACK, it will release the SDA line so that the
Master can send a Stop or repeated Start condition. If the Master does not send a NACK but instead sends an
ACK after the lower byte of the Temperature Register has been clocked out, then the device will repeat the
sequence by outputting new temperature data starting with the upper byte of the Temperature Register.
If 8-bit temperature resolution is satisfactory, then the lower byte of the Temperature Register does not need to
be read. In this case, the Master would send a NACK instead of an ACK after the upper byte of the Temperature
Register has been clocked out of the AT30TS74. When the AT30TS74 receives the NACK, the device will know
that it should not send out the lower byte of the Temperature Register and will instead release the SDA line so
the Master can send a Stop or repeated Start condition.
The Temperature Register defaults to 0000h after device power-up or reset; therefore, the system should wait
the maximum conversion time (tCONV) for the selected resolution before attempting to read valid temperature
data. Since the Temperature Register is a Read-only register, any attempts to write to the register will be
ignored, and the device will subsequently respond by sending a NACK back to the Master.
Figure 5-2.
Read Temperature Register — 16 Bits
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
D0
1
SCK
Address Byte
SDA
1
0
0
1
A
Temperature Register Upper Byte
A
A
1
0
D15 D14 D13 D12 D11 D10 D9
MSB
D8
0
D7
D6
D5
D4
D3
D2
D1
MSB
MSB
Start
by
Master
Note:
Temperature Register Lower Byte
ACK
from
Slave
NACK
from
Master
ACK
from
Master
Stop
by
Master
Assumes the Pointer Register was previously set to point to the Temperature Register.
Figure 5-3.
Read Temperature Register — 8 Bits
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
D8
1
SCK
Address Byte
SDA
1
0
0
1
A
Temperature Register Upper Byte
A
A
1
0
MSB
Start
by
Master
Note:
D15 D14 D13 D12 D11 D10 D9
MSB
ACK
from
Slave
NACK
from
Master
Stop
by
Master
Assumes the Pointer Register was previously set to point to the Temperature Register.
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19
5.3
Configuration Register
The Configuration Register is used to control key operational modes and settings of the device such as the
One-Shot mode, the temperature conversion resolution, the fault tolerance queue, the ALERT pin polarity, the
Alarm Thermostat mode, and the Shutdown mode. The Configuration Register is a 16-bit wide Read/Write
register; however, only the first 8-bits of the register are actually used while the least-significant 8-bits are
reserved for future use to provide an upward migration path to other temperature sensor devices that have
enhanced features. Since only the most-significant eight bits of the Configuration Register are used, the device
is backwards compatible to industry standard LM75-type temperature sensors that use 8-bit wide registers.
After device power-up or reset, the Configuration Register defaults to 0000h; therefore, the system should
update the Configuration Register with the desired settings prior to attempting to read the Temperature Register
unless the default Configuration Register settings are satisfactory for the application.
Table 5-5.
Bit
15
14:13
12:11
Configuration Register
Name
OS
R1:R0
FT1:FT0
Type
One-Shot Mode
Conversion Resolution
Fault Tolerance Queue
R/W
R/W
R/W
10
POL
ALERT Pin Polarity
R/W
9
CMP/INT
Alarm Thermostat Mode
R/W
8
7:0
SD
RFU
Shutdown Mode
Reserved for Future Use
Description
0
Normal Operation (Default)
1
Perform One-Shot Measurement
(Valid in Shutdown Mode Only)
00
9-bits (Default)
01
10-bits
10
11-bits
11
12-bits
00
Alarm after 1 Fault (Default)
01
Alarm after 2 Consecutive Faults
10
Alarm after 4 Consecutive Faults
11
Alarm after 6 Consecutive Faults
0
ALERT pin is Active Low (Default)
1
ALERT pin is Active High
0
Comparator Mode (Default)
1
Interrupt Mode
0
Temperature Sensor Performing Active
Measurements (Default)
1
Temperature Sensor Disabled and Device In
Shutdown Mode
0
Reserved for Future Use
R/W
R
To set the value of the Configuration Register, the Master must first initiate a Start condition followed by the
AT30TS74's device address byte (1001AAA0 where “AAA” corresponds to the hard-wired A2-0 address pins).
After the AT30TS74 has received the proper address byte, the device will send an ACK to the Master. The
Master must then send the appropriate Pointer Register byte of 01h to select the Configuration Register. After
the Pointer Register byte of 01h has been sent, the AT30TS74 will send another ACK to the Master. After
receiving the ACK from the AT30TS74, the Master must then send the appropriate data byte to the AT30TS74
20
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
to set the value of the Configuration Register. Only the first data byte sent to the AT30TS74 will be recognized
as valid data; any subsequent bytes received by the device will simply be ignored. If the Master does not send a
complete byte of Configuration Register data prior to issuing a Stop or repeated Start condition, then the
AT30TS74 will ignore the data and the contents of the Configuration Register will be unchanged.
5.3.1
OS Bit
The OS bit is used to enable the One-Shot Temperature Measurement mode. When a Logic 1 is written to the
OS bit while the AT30TS74 is in the Shutdown mode, the device will become active and perform a single
temperature measurement and conversion. After the Temperature Register has been updated with the
measured temperature data, the device will return to the low-power Shutdown mode and clear the OS bit.
Writing a one to the OS bit when the device is not in the Shutdown mode will have no affect. When reading the
Configuration Register, the OS bit will always be read as a Logic 0.
5.3.2
R1:R0 Bits
The R1 and R0 bits are used to select the conversion resolution of the internal sigma-delta ADC. Four possible
resolutions can be set to maximize for either higher resolution or faster conversion times. The R1 and R0 bits
default to the Logic 0 state after device power-up or reset to retain backwards compatibility to industry-standard
LM75-type devices.
Table 5-6.
5.3.3
Conversion Resolution
R1
R0
Conversion Resolution
Conversion Time
0
0
9 bits
0.5°C
25ms
0
1
10 bits
0.25°C
50ms
1
0
11 bits
0.125°C
100ms
1
1
12 bits
0.0625°C
200ms
FT1:FT0 Bits
The FT1 and FT0 bits are used to set the fault tolerance queue value which defines how many consecutive
faults must occur before the ALERT pin will be activated (see Section 4.4.1, “Fault Tolerance Limits”). The FT1
and FT0 bit settings provide four different fault values as detailed in Table 5-7. After the device powers up or
resets, both the FT1 and FT0 bits will default to the Logic 0 state.
Table 5-7.
Fault Tolerance Queue
NVFT1
NVFT0
Consecutive Faults Required
0
0
1
0
1
2
1
0
4
1
1
6
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21
5.3.4
POL Bit
The ALERT pin polarity is controlled by the POL bit. When the POL bit is in the Logic 0 state, the ALERT pin will
be an active low output (the default setting after device power-up or reset). To configure the ALERT pin as an
active high output, the POL bit must be set to the Logic 1 state.
5.3.5
CMP/INT Bit
The CMP/INT bit controls whether the device will operate in the Comparator mode or the Interrupt mode. Setting
the CMP/INT bit to the Logic 0 state will put the device into the Comparator mode (default after device power-up
or reset). Alternatively, when the CMP/INT bit is set to the Logic 1 state, then the device will operate in the
Interrupt mode. The function of the ALERT pin changes based on the CMP/INT bit setting.
5.3.6
SD Bit
The SD bit is used to enable or disable the device's Shutdown mode. When the SD bit is in the Logic 0 state
(default after device power-up or reset), the device will be in the normal operational mode and perform
continuous temperature measurements and conversions. When the SD bit is set to the Logic 1 state, the device
will finish the current temperature measurement and conversion and will store the result in the Temperature
Register, after which the device will then enter the Shutdown mode.
Resetting the SD bit back to a Logic 0 will return the device to the normal operating mode.
Figure 5-4.
Write to Configuration Register
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
D8
0
SCK
Address Byte
SDA
1
0
0
1
A
Pointer Register Byte
A
A
0
0
0
MSB
0
0
0
0
0
1
0
D15 D14 D13 D12 D11 D10 D9
MSB
Start
by
Master
Figure 5-5.
0
Configuration Register Upper Byte
MSB
ACK
from
Slave
ACK
from
Slave
ACK
from
Slave
Read from Configuration Register
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
D8
1
SCK
Configuration Register Upper Byte
Address Byte
SDA
1
0
0
1
A
A
A
1
0
MSB
Start
by
Master
Note:
22
D15 D14 D13 D12 D11 D10 D9
MSB
ACK
from
Slave
NACK
from
Master
Stop
by
Master
Assumes the Pointer Register was previously set to point to the Configuration Register.
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
Stop
by
Master
5.4
TLOW and THIGH Limit Registers
The 16-bit TLOW and THIGH Limit Registers store the user-programmable lower and upper temperature limits for
the temperature alarm. Like the Temperature Register, the temperature data values of the TLOW and THIGH Limit
Registers are stored in the twos complement format with the MSB (bit 15) of the registers containing the sign bit
(zero indicates a positive number and a one indicates a negative number).
As with the Temperature Register, the resolution selected by the R1 and R0 bits of the Configuration Register
will determine how many bits of the TLOW and THIGH Limit Registers will be used. Therefore, when writing to the
TLOW and THIGH Limit Registers, up to 12 bits of data will be recognized by the device with the remaining LSBs
being internally fixed to the Logic 0 state. Similarly, when reading from the registers, up to 12 bits of data will be
output from the device with the remaining LSBs fixed in the Logic 0 state.
Table 5-8.
TLOW Limit Register and THIGH Limit Register Format
Upper Byte
Lower Byte
Resolution
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
12 bits
Sign
TD
TD
TD
TD
TD
TD
TD
TD
TD
TD
TD
0
0
0
0
11 bits
Sign
TD
TD
TD
TD
TD
TD
TD
TD
TD
TD
0
0
0
0
0
10 bits
Sign
TD
TD
TD
TD
TD
TD
TD
TD
TD
0
0
0
0
0
0
9 bits
Sign
TD
TD
TD
TD
TD
TD
TD
TD
0
0
0
0
0
0
0
Note:
TD = Temperature Data
To set the value of either the TLOW or THIGH Limit Register, the Master must first initiate a Start condition followed
by the AT30TS74 device address byte (1001AAA0 where “AAA” corresponds to the hard-wired A2-0 address
pins). After the AT30TS74 has received the proper address byte, the device will send an ACK to the Master.
The Master must then send the appropriate Pointer Register byte of 02h to select the TLOW Limit Register or 03h
to select the THIGH Limit Register. After the Pointer Register byte has been sent, the AT30TS74 will send
another ACK to the Master. After receiving the ACK from the AT30TS74, the Master must then send two data
bytes to the AT30TS74 to set the value of the TLOW or THIGH Limit Register. Any subsequent bytes sent to the
AT30TS74 will simply be ignored by the device. If the Master does not send two complete bytes of data prior to
issuing a Stop or repeated Start condition, then the AT30TS74 will ignore the data and the contents of the
register will not be changed.
In order to read the TLOW or THIGH Limit Register, the Pointer Register must be set or have been previously set to
02h to select the TLOW Limit Register or 03h to select the THIGH Limit Register (if the previous operation was a
Write to one of the registers, then the Pointer Register will already be set for that particular limit register). If the
Pointer Register has already been set appropriately, the TLOW or THIGH Limit Register can be read by having the
Master first initiate a Start condition followed by the AT30TS74 device address byte (1001AAA1 where “AAA”
corresponds to the hard-wired A2-0 address pins). After the AT30TS74 has received the proper address byte,
the device will send an ACK to the Master. The Master can then read the upper byte of the TLOW or THIGH Limit
Register. After the upper byte of the register has been clocked out of the AT30TS74, the Master must send an
ACK to indicate that it is ready for the lower byte of data. The AT30TS74 will then clock out the lower byte of the
register, after which the Master must send a NACK to end the operation. When the AT30TS74 receives the
NACK, it will release the SDA line so that the Master can send a Stop or repeated Start condition. If the Master
does not send a NACK but instead sends an ACK after the lower byte of the register has been clocked out, then
the device will repeat the sequence by outputting the data again starting with the upper byte of the register.
AT30TS74 [DATASHEET]
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23
The TLOW Limit Register defaults to 4B00h (+75°C) and the THIGH Limit Register defaults to 5000h (+80°C) after
the device powers up or resets; therefore, both registers will need to be modified after power-up/reset if these
default temperature limits are not satisfactory for the application. The value of the high temperature limit stored
in the THIGH Limit Register must be greater than the value of the low temperature limit stored in the TLOW Limit
Register in order for the ALERT function to work properly; otherwise, the ALERT pin will output erroneous
results and will falsely signal temperature alarms. In addition, changing either value of the THIGH or TLOW Limit
Register will cause the internal fault counter to reset back to zero.
Figure 5-6.
Write to TLOW or THIGH Limit Register
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
P1
P0
0
SCK
Address Byte
SDA
1
0
0
1
A
Pointer Register Byte
A
A
0
0
0
MSB
0
0
0
0
0
MSB
Start
by
Master
ACK
from
Slave
ACK
from
Slave
1
2
3
4
5
6
7
8
9
1
2
TLOW or THIGH Limit Register
Upper Byte
D15 D14 D13 D12 D11 D10
D9
3
4
5
6
7
8
9
D0
0
TLOW or THIGH Limit Register
Lower Byte
D8
0
D7
MSB
D6
D5
D4
D3
D2
D1
MSB
ACK
from
Slave
ACK
from
Slave
Stop
by
Master
Read from TLOW or THIGH Limit Register
Figure 5-7.
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
D0
1
SCK
TLOW or THIGH Limit Register
Upper Byte
Address Byte
SDA
1
0
0
1
A
A
A
1
0
MSB
Start
by
Master
Note:
24
D15 D14 D13 D12 D11 D10 D9
TLOW or THIGH Limit Register
Lower Byte
D8
0
MSB
ACK
from
Slave
D7
D6
D5
D4
D3
ACK
from
Master
Assumes the Pointer Register was previously set to point to the TLOW or THIGH Limit Register.
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
D2
D1
MSB
NACK
from
Master
Stop
by
Master
6.
SMBus Features and I2C General Call
6.1
SMBus Alert
The AT30TS74 utilizes the ALERT pin to support the SMBus Alert function when the Alarm Thermostat mode is
set to the Interrupt mode (the CMP/INT bit of the Configuration Register is set to one) and the ALERT pin
polarity is set to active low (the POL bit of the Configuration Register is set to zero). The AT30TS74 is a
slave-only device, and normally, slave devices on the SMBus cannot signal to the Master that they want to
communicate. However, the AT30TS74 uses the SMBus Alert function (the ALERT pin) to signal to the Master
that it wants to communicate.
Several SMBus Alert pins from different slave devices can be connected to a common SMBus Alert input on the
Master. When the SMBus Alert input on the Master is pulled low by one of the slave devices, the Master can
perform a specialized Read operation from the slave devices to determine which device sent the SMBus Alert
signal.
The specialized Read operation is known as an SMBus ARA and requires that the Master first initiate a Start
condition followed by the SMBus ARA code of 00011001. The slave device that generated the SMBus Alert
signal will respond to the Master with an ACK. After sending the ACK, the slave device will then output its own
device address (1001AAA for the AT30TS74 where “AAA” corresponds to the hard-wired A2-0 address pins) on
the bus. Since the device address is seven bits long, the remaining eighth bit (the LSB) is used as an indicator
to notify the Master which temperature limit caused the alarm (the LSB will be a Logic 1 if the THIGH limit was met
or exceeded, and the LSB will be a Logic 0 if the TLOW limit was exceeded).
The SMBus ARA can activate several slave devices at the same time; therefore, if more than one slave
responds, standard SMBus arbitration rules apply and the device with the lowest address wins the arbitration.
The device winning the arbitration will clear its SMBus Alert output after it has responded to the SMBus ARA
and provided its device address. All other devices with higher addresses do not generate an ACK and continue
to hold their SMBus Alert outputs low until cleared. The Master will continue to issue SMBus ARA sequences
until all slave devices which generated an SMBus Alert signal have responded and cleared their SMBus Alert
outputs.
Figure 6-1.
SMBus Alert
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCK
SMBus ARA Code
SDA
0
0
0
1
1
0
AT30TS74 Device Address Byte
0
1
0
MSB
Start
by
Master
Note:
1
0
0
1
A2
A1
A0 Limit
1
MSB
ACK
from
Slave
NACK
from
Master
Stop
by
Master
The Limit bit (the LSB) of the device address byte will be one or zero depending on if the THIGH or TLOW limit was
exceeded.
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25
6.2
SMBus Timeout
The AT30TS74 supports the SMBus Timeout feature in which the AT30TS74 will reset its serial interface and
release the SMBus (stop driving the bus and let SDA float high) if the SCL pin is held low for more than the
minimum tTIMEOUT specification. The AT30TS74 will be ready to accept a new Start condition before tTIMEOUT
maximum has elapsed.
Figure 6-2.
SMBus Timeout
tTIMEOUT (MAX)
tTIMEOUT (MIN)
SCL
Device will release Bus and
be ready to accept a new
Start Condition within this Time
6.3
General Call
The AT30TS74 will respond to an I2C general call address (0000000) from the Master only if the eighth bit (the
LSB) of the general call address byte is zero. If the general call address byte is 00000000, then the device will
send an ACK to the Master and await a command byte from the Master.
If the Master sends a command byte of 04h, then the AT30TS74 will re-latch the status of its address pins in
case the system has assigned a new address to the device. If the Master sends a command byte of 06h
(General Call Reset), then the AT30TS74 will re-latch the status of its address pins and perform a reset
sequence. The reset sequence will reset all registers to their power-up defaults, and the device will be busy for
a maximum time of tPOR during the Reset operation.
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7.
Electrical Specifications
7.1
Absolute Maximum Ratings*
Temperature under Bias. . . . . . . . -40°C to +125°C
Storage Temperature . . . . . . . . . . -65°C to +150°C
Supply voltage
with respect to ground . . . . . . . . . . . -0.5V to +7.0V
ALERT Pin . . . . . . . . . . . . . . . . -0.5V to VCC + 0.3V
All input voltages
with respect to ground . . . . . . . -0.5V to VCC + 0.5V
All other output voltages
with respect to ground . . . . . . . -0.5V to VCC + 0.5V
7.2
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. Functional operation of the device at these
ratings or any other conditions beyond those indicated
in the operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability. Voltage extremes referenced in the “Absolute
Maximum Ratings” are intended to accommodate short
duration undershoot/overshoot conditions and does not
imply or guarantee functional device operation at these
levels for any extended period of time.
Pull-up voltages applied to the ALERT pin that exceed
the “Absolute Maximum Ratings” may forward bias to
the ESD protection circuitry. Doing so may result in
improper device function and may corrupt temperature
measurements.
DC and AC Operating Range
AT30TS74
Operating Temperature (Case)
-55C to +125C(1)(2)
Industrial High Temperature
VCC Power Supply
Notes:
1.
2.
1.7V to 5.5V
Device operation is guaranteed from -40°C to +125°C.
Device operation is not guaranteed at -55°C but ensured by characterization.
AT30TS74 [DATASHEET]
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27
7.3
DC Characteristics
Symbol
Parameter
ICC1
Active Current,
Bus Inactive
Typ(1)
Max
60
85
65
95
85
125
120
160
150
225
225
325
235
500
610
800
1.7V ≤ VCC ≤ 2.0V
0.4
2.5
2.7V ≤ VCC ≤ 3.6V
0.6
3.5
4.5V ≤ VCC ≤ 5.5V
1.2
5.5
1.7V ≤ VCC ≤ 2.0V
110
160
130
200
180
280
210
425
550
750
VCC Range
Condition
Min
1.7V ≤ VCC ≤ 2.0V
2.7V ≤ VCC ≤ 3.6V
Active Temperature
Conversions
4.5V ≤ VCC ≤ 5.5V
1.7V ≤ VCC ≤ 2.0V
Active Current,
Bus Active
ICC2
2.7V ≤ VCC ≤ 3.6V
4.5V ≤ VCC ≤ 5.5V
Active Current,
Bus Active
ICC3
Shutdown Mode
Current, Bus Inactive
ISD1
Shutdown Mode
Current, Bus Active
ISD2
2.2V ≤ VCC ≤ 3.6V
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 3.6V
Active Temperature
Conversions,
fSCL = 400kHz
Active Temperature
Conversions,
fSCL = 3.4MHz
fSCL = 400kHz
4.5V ≤ VCC ≤ 5.5V
μA
μA
μA
μA
μA
ISD3
Shutdown Mode
Current, Bus Active
ILI
Input Leakage Current
VIN = CMOS levels
±1
μA
ILO
Output Leakage
Current
VOUT = CMOS levels
±1
μA
VIL
Input Low Voltage
0.3 x VCC
V
VIH
Input High Voltage
VOL1
Output Low Voltage
IOL = 3mA
0.4
V
VOL2
Output Low Voltage,
ALERT Pin
IOL = 4mA
0.4
V
Note:
28
2.2V ≤ VCC ≤ 3.6V
Units
1.
4.5V ≤ VCC ≤ 5.5V
fSCL = 3.4MHz
0.7 x VCC
V
Typical values characterized at TA = +25°C at VCC = 1.8V, 3.0V and 5.0V unless otherwise noted.
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
μA
7.4
Temperature Sensor Accuracy and Conversion Characteristics
Symbol
TACC
Sensor Accuracy
TRES
Conversion Resolution
tCONV
Notes:
7.5
Parameter
Conversion Time
1.
2.
Typ(1)
Max
TA = -20°C to +100°C
±1.0
±2.0
TA = -10°C to +100°C, WLCSP
±1.0
±2.0
TA = -40°C to +125°C
±2.0
±3.0
TA = -55°C to +125°C(2)
±3.0
Condition
Min
Selectable 9 to 12 bits
0.5 (9 bits)
Units
C
0.0625 (12 bits)
C
ms
9-bit Resolution
25
37.5
10-bit Resolution
50
75
11-bit Resolution
100
150
12-bit Resolution
200
300
Typical values characterized at VCC = 3.3V, TA = +25°C unless otherwise noted.
Sensor accuracy characterized to this range but not tested or guaranteed.
AC Characteristics
Symbol
Parameter
VCC = 1.7V to 3.6V
VCC < 2.2V
VCC = 2.2V to 3.6V
Fast Mode
Fast Mode Plus
High-Speed Mode
Min
(2)
Max
Min
400
(2)
Min
Max
Units
1000
(2)
3400
kHz
fSCL
Serial Clock Frequency
1
tSCLH
Clock High Time
600
260
60
ns
tSCLL
Clock Low Time
1300
500
160
ns
tR
Clock/Data Input Rise Time
(1)
(1)
1
Max
1
300
120
100
ns
300
120
100
ns
tF
Clock/Data Input Fall Time
tSUDAT
Data In Setup Time
100
50
10
ns
tHDDAT
Data In Hold Time
0
0
0
ns
tV
Output Valid Time
tOH
Output Hold Time
tBUF
900
350
80
ns
0
0
0
ns
Bus Free Time Between Stop and Start
Condition
1300
500
160
ns
tSUSTA
Repeated Start Condition Setup Time
(SCL High to SDA Low)
100
50
50
ns
tHDSTA
Start Condition Hold Time (SDA Low to
SCL Low)
100
50
50
ns
tSUSTO
Stop Condition Setup Time (SCL High
to SDA High)
600
50
50
ns
tNS
Noise Suppression Input Filter Time
tTIMEOUT
SMBus Timeout Time
CLOAD
Capacitive Load for SCL and SDA
Lines(1)
Notes:
1.
2.
100
25
75
400
50
25
75
400
25
10
ns
75
ms
100
pF
These parameters are determined through product characterization and are not tested 100% in production.
Minimum clock frequency must be at least 1KHz to avoid activating the SMBus timeout feature.
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
29
SMBus/I2C Timing Diagram
Figure 7-1.
tSCKH
tR
tSCKL
tF
SCL
tOH
tSUDAT
tSUSTO
tSUSTA
tBUF
tV
SDA
IN
IN
OUT
OUT
IN
Start
Condition
7.6
tHDSTA
tHDDAT
Stop
Condition
Start
Condition
Repeated Start
Condition
Power-Up Conditions
Symbol
Parameter
tPOR
Power-On Reset Time
VPOR
Power-On Reset Voltage Range
Figure 7-2.
Min
Power-Up Timing
VCC
Device Access Permitted
VCC (min)
tPOR
VPOR (max)
VPOR (min)
Do Not Attempt
Device Access
During this Time
Time
30
IN
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
Max
Units
1
ms
1.6
V
7.7
Pin Capacitance
Symbol
Parameter
CI/O(1)
(1)
CIN
Note:
7.8
1.
Min
Max
Units
Input/Output Capacitance (SDA and ALERT pins)
VI/O = 0V
8
pF
Input Capacitance (A2-0 and SCL pins)
VIN = 0V
6
pF
Not 100% tested (value guaranteed by design and characterization).
Input Test Waveforms and Measurement Levels
AC
Input
Levels
0.9VCC
VCC
2
AC
Measurement
Level
0.1VCC
tR, tF < 5ns (10% to 90%)
7.9
Output Test Load
Device
Under
Test
100pF
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
31
8.
Ordering Information
8.1
Atmel Ordering Code Detail
AT 3 0 T S 7 4 - S S 8 M 1 0 - B
Atmel Designator
Product Family
30TS = Digital Temp. Sensor
Device Type
Shipping Carrier Option
B = Bulk (Tubes)
T = Tape and Reel
Slave Address/Customer Specific Option
10 or AB = 1001 000X
11 or BB = 1001 001X
12 or CB = 1001 010X
13 or DB = 1001 011X
14 or EB = 1001 100X
15 or FB = 1001 101X
16 or GB = 1001 110X
17 or HB = 1001 111X
Slave Address
Slave Address
Slave Address
Slave Address
Slave Address
Slave Address
Slave Address
Slave Address
Voltage Option
M = 1.7V to 5.5V
Device Grade
8 = Green, NiPdAu Lead Finish
Industrial High Temperature Range
(–40°C to +125°C) Accuracy Guaranteed
F = Green, Matte Tin Lead Finish or SnAgCu Ball
Industrial High Temperature Range
(–40°C to +125°C) Accuracy Guaranteed
Package Option
SS = 8-lead, 0.15" wide SOIC
XM = 8-lead, 3.00 x 3.00mm MSOP
MA = 8-pad, 2.00 x 3.00 x 0.60mm
U = 4-ball WLCSP
U1 = 5-ball WLCSP
32
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
8.2
Green Package Options (Pb/Halide-free/RoHS Compliant)
Ordering Code
(1)
Package
AT30TS74-SS8M-B
Lead Finish
I2C
Address
Max. Freq.
(kHz)
1.7V to 5.5V
3400
Industrial High
Temperature
(-55°C to +125°C)
1.7V to 5.5V
3400
Industrial High
Temperature
(-55°C to +125°C)
Operation Range
8S1
AT30TS74-SS8M-T
AT30TS74-XM8M-B
8XM
AT30TS74-XM8M-T
AT30TS74-MA8M-T
NiPdAu
8MA2
AT30TS74-UFM10-T
1001 000X
AT30TS74-UFM11-T
1001 001X
AT30TS74-UFM12-T
1001 010X
(2)
AT30TS74-UFM13-T
AT30TS74-UFM14-T(2)
1001 011X
4U-3
1001 100X
AT30TS74-UFM15-T(2)
1001 101X
AT30TS74-UFM16-T(2)
1001 110X
(2)
AT30TS74-UFM17-T
AT30TS74-U1FMAB-T
AT30TS74-U1FMBB-T
AT30TS74-U1FMDB-T
SnAgCu
1001 111X
(Lead-free/Halogen-free)
1001 000X
1001 001X
AT30TS74-U1FMCB-T
1001 010X
(2)
AT30TS74-U1FMEB-T(2)
5U-5
1001 011X
1001 100X
AT30TS74-U1FMFB-T(2)
1001 101X
AT30TS74-U1FMGB-T(2)
1001 110X
(2)
1001 111X
AT30TS74-U1FMHB-T
Notes:
Operating
Voltage
1. The shipping carrier option code is not marked on the devices.
2. Please contact Atmel for availability of slave address options 011,100,101, 110, and 111.
Package Type
8S1
8-lead, 0.15” wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8XM
8-lead, 3.00mm x 3.00mm, Plastic Miniature Small Outline (MSOP)
8MA2
8-pad, 2.00mm x 3.00mm x 0.60mm, Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead (UDFN)
4U-3
4-ball, 2 x 2 Grid Array, Wafer Level Chip Scale (WLCSP)
5U-5
5-ball, 3x3 Array, 0.40mm pitch, Wafer Level Chip Scale Package (WLCSP)
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
33
9.
Part Marking Detail
AT30TS74: Package Marking Information
8-lead SOIC
8-lead MSOP
ATML8YWW
T9 &
@
AAAAAAAA
8-lead UDFN
T9
8& XX
YWW@
4-ball/5-ball WLCSP
2.0 x 3.0 mm Body
%&
T9
YXX
T9
8&@
YXX
Note 1:
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT30TS74
Truncation Code ###: T9
Date Codes
Y = Year
4: 2014
5: 2015
6: 2016
7: 2017
Slave Address
8: 2018
9: 2019
0: 2020
1: 2021
M = Month
A: January
B: February
...
L: December
WW = Work Week of Assembly
02: Week 2
04: Week 4
...
52: Week 52
Country of Assembly
Lot Number
@ = Country of Assembly
AAA...A = Atmel Wafer Lot Number
Voltage
& = Voltage
% = Slave Address
A: Address 000 E: Address 100
B: Address 001 F: Address 101
C: Address 010 G: Address 110
D: Address 011 H: Address 111
Grade/Lead Finish Material
8: Industrial (C)
(-40°C to 125°C)/NiPdAu
M: 1.7V min
Trace Code
Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code)
Example: AA, AB.... YZ, ZZ
AT: Atmel
ATM: Atmel
ATML: Atmel
1/26/16
TITLE
AT30TS74SM, AT30TS74 Package Marking Information
Package Mark Contact:
[email protected]
34
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
DRAWING NO.
REV.
30TS74SM
D
10.
Packaging Information
10.1
8S1 — 8-lead JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
MIN
NOM
MAX
–
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
SYMBOL
A
D
4.90 BSC
E
6.00 BSC
E1
3.90 BSC
e
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
NOTE
3/6/2015
Package Drawing Contact:
[email protected]
TITLE
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
GPC
SWB
DRAWING NO.
REV.
8S1
H
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
35
10.2
8XM — 8-lead MSOP
TOP VIEW
3
2
END VIEW
Pin 1
1
-B-
E
CL
E1
N
b
A2
3
2X
(N/2 TIPS)
3
1
N
C B A
2
SEE
DETAIL "A"
0.05 S
0.20
BOTTOM VIEW
1
SIDE VIEW
0.25
BSC
A
e
0.07 R. MIN
2 PLACES
SEATING PLANE
k 0.10 C 4
A1
-HD
1
θ
L 2
-C-
SEATING
PLANE
DETAIL 'A'
-A-
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
A
-
-
1.10
NOTE
A1
0.05
0.10
0.15
A2
0.75
0.85
0.95
1. Dimensions "D" & "E1" do not include mold flash or
protrusions, and are measured at Datum Plane -H- .
mold flash or protrusions shall not exceed 0.15 mm per side.
b
0.25
-
0.40
D
2.90
3.00
3.10
1
2. Dimension is the length of terminal for soldering to a substrate.
E
3. Terminal positions are shown for reference only.
E1
3.10
1
4. Formed leads shall be planar with respect to one another
within 0.10mm at the seating plane.
5. Datums -A- and -B- to be determined by datum plane -H- .
e
2
NOTES:
4.90 BSC
2.90
3.00
0.65 BSC
L
0.40
0.55
0.80
θ
0°
4°
8°
5/19/15
TITLE
Package Drawing Contact:
[email protected]
36
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
8XM, 8-lead 3.0 x 3.0 mm Body, 0.65 mm pitch,
Plastic Thin Shrink Small Outline Package
(TSSOP/MSOP)
GPC
DRAWING NO.
REV.
TZD
8XM
B
10.3
8MA2 — 8-pad UDFN
E
1
8
Pin 1 ID
2
7
3
6
4
5
D
C
TOP VIEW
A2
SIDE VIEW
A
C
A1
E2
b (8x)
8
7
1
D2
6
3
5
4
e (6x)
K
L (8x)
BOTTOM VIEW
Notes:
COMMON DIMENSIONS
(Unit of Measure = mm)
2
Pin#1 ID
1. This drawing is for general information only. Refer to
Drawing MO-229, for proper dimensions, tolerances,
datums, etc.
2. The Pin #1 ID is a laser-marked feature on Top View.
3. Dimensions b applies to metallized terminal and is
measured between 0.15 mm and 0.30 mm from the
terminal tip. If the terminal has the optional radius on
the other end of the terminal, the dimension should
not be measured in that radius area.
4. The Pin #1 ID on the Bottom View is an orientation
feature on the thermal pad.
SYMBOL
MIN
NOM
MAX
A
0.50
0.55
0.60
A1
0.0
0.02
0.05
A2
-
-
0.55
D
1.90
2.00
2.10
D2
1.40
1.50
1.60
E
2.90
3.00
3.10
E2
1.20
1.30
1.40
b
0.18
0.25
0.30
C
NOTE
3
0.152 REF
L
0.35
e
0.40
0.45
0.50 BSC
K
0.20
-
-
11/2/15
Package Drawing Contact:
[email protected]
TITLE
8MA2, 8-pad 2 x 3 x 0.6mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No-Lead
Package (UDFN)
GPC
DRAWING NO.
REV.
YNZ
8MA2
H
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
37
10.4
4U-3 — 4-ball WLCSP
TOP VIEW
BALL SIDE
A
Pin 1
2
1
2
1
A
A
D
D1
B
B
E
B
b
E1
n 0.015 m C
j
n 0.05 m C A B
d 0.015 C
A2
* Drawing not to Scale
SIDE VIEW
A
d 0.075 C
COMMON DIMENSIONS
(Unit of Measure = mm)
C
A1
Pin Assignment Matrix
A
SYMBOL
MIN
TYP
MAX
A
0.460
0.499
0.538
A1
0.164
-
0.224
0.280
0.305
0.330
1
2
A2
E
See Atmel for Details
VDD
GND
D
See Atmel for Details
E1
B
SDA
SCL
0.400 BSC
D1
b
NOTE
0.400 BSC
0.239
0.269
0.299
10/23/13
Package Drawing Contact:
[email protected]
38
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
TITLE
4U-3, 4-ball 2x2 Array Wafer Level Chip Scale
Package (WLCSP)
GPC
DRAWING NO.
REV.
GEZ
4U-3
A
10.5
5U-5 — 5-ball WLCSP
TOP VIEW
1
2
k 0.015
BOTTOM SIDE
(4X)
A
3
3
A
2
1
A
B
B
E
e1
e2
C
C
db
D
d0.015 m C
v d 0.05 m C A B
d1
B
SIDE VIEW
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SEATING PLANE
C
k 0.075
A2
C
A1
PIN ASSIGNMENT MATRIX
A
1
2
3
VCC
n/a
VSS
B
n/a
ALRT
n/a
C
SDA
n/a
SCL
SYMBOL
MIN
TYP
MAX
A
0.260
0.295
0.330
A1
—
0.080
—
A2
—
0.215
—
D
Contact Atmel for details
E
Contact Atmel for details
d1
0.400 BSC
e1
0.693 BSC
e2
0.400 BSC
b
—
0.185
NOTE
3
—
Note: 1. Dimensions are NOT to scale.
2. Solder ball composition is 95.5Sn-4.0Ag-0.5Cu.
3. Product offered with Back Side Coating
1/13/16
Package Drawing Contact:
[email protected]
TITLE
5U-5, 5-ball, 3x3 Array, 0.40mm Pitch
Wafer Level Chip Scale Package (WLCSP)
GPC
DRAWING NO.
REV.
GPX
5U-5
A
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
39
11.
Errata
11.1
No Errata
40
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
12.
Revision History
Doc. Rev.
Date
Comments
8897F
01/2016
Add 5U-5 5-ball WLCSP package options and update 8MA2 package drawing.
8897E
09/2015
Remove preliminary status. Update 8S1, 8XM, and 8MA2 package drawings.
8897D
10/2014
Update the DC Characteristics and the AC Characteristics tables.
8897C
09/2014
Update Power-up table and figure, and 8MA2 package drawing.
8897B
06/2014
Update part markings and disclaimer page.
8897A
02/2014
Initial document release.
AT30TS74 [DATASHEET]
Atmel-8897F-DTS-AT30TS74-Datasheet_012016
41
XXXXXX
Atmel Corporation
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T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
|
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© 2016 Atmel Corporation. / Rev.: Atmel-8897F-DTS-AT30TS74-Datasheet_012016.
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