AT27C516 - Mature

Features
• Fast Read Access Time – 45 ns
• Low Power CMOS Operation
•
•
•
•
•
•
•
– 100 µA Max Standby
– 30 mA Max Active at 5 MHz
JEDEC Standard Packages
– 44-Lead PLCC
– 40-Lead VSOP
5V ± 10% Power Supply
High Reliability CMOS Technology
– 2000V ESD Protection
– 200 mA Latchup Immunity
Rapid Programming Algorithm µ 50 µs/Word (Typical)
CMOS and TTL Compatible Inputs and Outputs
Integrated Product Identification Code
Industrial Temperature Range
512K (32K x 16)
OTP EPROM
AT27C516
1. Description
The AT27C516 is a low-power, high-performance 524,288-bit one-time programmable
read-only memory (OTP EPROM) organized 32K by 16 bits. It requires only one 5V
power supply in normal read mode operation. Any word can be accessed in less than
45 ns, eliminating the need for speed reducing WAIT states. The by-16 organization
make this part ideal for high-performance 16- and 32-bit microprocessor systems.
In read mode, the AT27C516 typically consumes 15 mA. Standby mode supply current is typically less than 10 µA.
The AT27C516 is available in industry-standard JEDEC-approved one-time programmable (OTP) plastic PLCC and VSOP packages. The device features two-line control
(CE, OE) to eliminate bus contention in high-speed systems.
With 32K word storage capability, the AT27C516 allows firmware to be stored reliably
and to be accessed by the system without the delays of mass storage media.
Atmel’s AT27C516 have additional features to ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program
the part and guarantees reliable programming. Programming time is typically only
50 µs/word. The Integrated Product Identification Code electronically identifies the
device and manufacturer. This feature is used by industry standard programming
equipment to select the proper programming algorithms and voltages.
0362E–EPROM–1/08
2. Pin Configurations
Pin Name
Function
A0 - A14
Addresses
O0 - O15
Outputs
CE
Chip Enable
OE
Output Enable
PGM
Program Strobe
NC
No Connect
Note:
2.1
Both GND pins must be connected.
40-lead VSOP (Type 1) Top View
A9
A10
A11
A12
A13
A14
NC
NC
PGM
VCC
VPP
CE
O15
O14
O13
O12
O11
O10
O9
O8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
O0
O1
O2
O3
O4
O5
O6
O7
GND
44-lead PLCC Top View
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
7
8
9
10
11
12
13
14
15
16
17
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
O3
O2
O1
O0
OE
NC
A0
A1
A2
A3
A4
O12
O11
O10
O9
O8
GND
NC
O7
O6
O5
O4
6
5
4
3
2
1
44
43
42
41
40
O13
O14
O15
CE
VPP
NC
VCC
PGM
NC
NC
A14
2.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Note: PLCC Package Pins 1 and 23 are Don’t Connect.
2
AT27C516
0362E–EPROM–1/08
AT27C516
3. System Considerations
Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may
exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high
frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This
capacitor should be connected between the VCC and Ground terminals of the device, as close
to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit
boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again
connected between the VCC and Ground terminals. This capacitor should be positioned as
close as possible to the point where the power supply is connected to the array.
4. Block Diagram
5. Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on A9 with
Respect to Ground ......................................-2.0V to +14.0V(1)
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
VPP Supply Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is
VCC + 0.75V DC which may overshoot to +7.0 volts for pulses of less than 20 ns.
3
0362E–EPROM–1/08
6. Operating Modes
Mode/Pin
CE
OE
PGM
Ai
VPP
Outputs
Read
VIL
VIL
X(1)
Ai
X
DOUT
Output Disable
X
VIH
X
X
X
High Z
(5)
Standby
VIH
X
X
X
X
High Z
Rapid Program(2)
VIL
VIH
VIL
Ai
VPP
DIN
PGM Verify
VIL
VIL
VIH
Ai
VPP
DOUT
PGM Inhibit
VIH
X
X
X
VPP
High Z
VCC
Identification Code
Product Identification(4)
Notes:
VH(3)
VIL
VIL
A9 =
A0 = VIH or VIL
A1 - A14 = VIL
X
1. X can be VIL or VIH.
2. Refer to Programming Characteristics.
3. VH = 12.0 ± 0.5V.
4. Two identifier bytes may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled
low (VIL) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte.
5. Standby VCC current (ISB) is specified with VPP = VCC. VCC > VPP will cause a slight increase in ISB.
7. DC and AC Operating Conditions for Read Operation
AT27C516
-45
-70
-40°C - 85°C
-40°C - 85°C
5V ± 10%
5V ± 10%
Industrial Operating Temperature (Case)
VCC Power Supply
8. DC and Operating Characteristics for Read Operation
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
IPP1
(2)
Max
Units
VIN = 0V to VCC
±1
µA
Output Leakage Current
VOUT = 0V to VCC
±5
µA
VPP(1)
VPP = VCC
10
µA
ISB1 (CMOS), CE = VCC ± 0.3V
100
µA
ISB2 (TTL), CE = 2.0 to VCC + 0.5V
1
mA
f = 5 MHz, IOUT = 0 mA, CE = VIL
30
mA
Read/Standby Current
Min
ISB
VCC(1) Standby Current
ICC
VCC Active Current
VIL
Input Low Voltage
-0.6
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VOL
Output Low Voltage
IOL = 2.1 mA
0.4
V
Output High Voltage
IOH = -400 µA
VOH
Notes:
2.4
V
1. VCC must be applied simultaneously with or before VPP, and removed simultaneously with or after VPP.
2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP.
4
AT27C516
0362E–EPROM–1/08
AT27C516
9. AC Waveforms for Read Operation(1)
10. AC Characteristics for Read Operation
AT27C516
-45
Symbol
tACC
(3)
Parameter
Condition
Min
-70
Max
Min
Max
Units
Address to Output Delay
CE = OE = VIL
45
70
ns
tCE(2)
CE to Output Delay
OE = VIL
45
70
ns
tOE(2)(3)
OE to Output Delay
CE = VIL
20
25
ns
tDF(4)(5)
OE or CE High to Output Float, whichever occurred first
20
25
ns
tOH
Output Hold from Address, CE or OE, Whichever
Occurred First
Notes:
7
7
ns
1. Timing measurement reference level is 1.5V for -45 devices. Input AC drive levels are VIL = 0.0V and VIH = 3.0V. Timing measurement reference levels for all other speed grades are VOL = 0.8V and VOH = 2.0V. Input AC drive levels are VIL = 0.45V
and VIH = 2.4V.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE.
3. OE may be delayed up to tACC - tOE after the address is valid without impact on tACC.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
5
0362E–EPROM–1/08
11. Input Test Waveforms and Measurement Levels
For -45, and -70 devices only:
tR, tF < 5 ns (10% to 90%)
12. Output Test Load
Note:
CL = 100 pF including jig
capacitance, except -45
and -70 devices, where
CL = 30 pF.
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
COUT
Note:
6
Typ
Max
Units
Conditions
4
10
pF
VIN = 0V
8
12
pF
VOUT = 0V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
AT27C516
0362E–EPROM–1/08
AT27C516
14. Programming Waveforms(1)
Notes:
1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH.
2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the AT27C516 at 0.1 µF capacitor is required across VPP and ground to suppress spurious
voltage transients.
7
0362E–EPROM–1/08
15. DC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Limits
Symbol
Parameter
Test Conditions
ILI
Input Load Current
VIN = VIL, VIH
VIL
Input Low Level
VIH
Input High Level
VOL
Output Low Voltage
IOL = 2.1 mA
VOH
Output High Voltage
IOH = -400 µA
ICC2
VCC Supply Current (Program and Verify)
IPP2
VPP Supply Current
VID
A9 Product Identification Voltage
Min
Max
Units
±10
µA
-0.6
0.8
V
2.0
VCC + 0.1
V
0.4
V
2.4
V
CE = PGM = VIL
11.5
50
mA
30
mA
12.5
V
Max
Units
16. AC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Limit
(1)
Symbol
Parameter
Test Conditions
tAS
Address Setup Time
2
µs
tCES
CE Setup Time
2
µs
tOES
OE Setup Time
2
µs
tDS
Data Setup Time
2
µs
tAH
Address Hold Time
0
µs
tDH
Data Hold Time
2
µs
tDFP
OE High to Output Float Delay(2)
tVPS
VPP Setup Time
tVCS
VCC Setup Time
Input Rise and Fall Times:
(10% to 90%) 20 ns
Input Pulse Levels:
0.45V to 2.4V
0
Input Timing Reference Level:
0.8V to 2.0V
(3)
tPW
PGM Program Pulse Width
tOE
Data Valid from OE
tPRT
VPP Pulse Rise Time During
Programming
Notes:
Min
Output Timing Reference Level:
0.8V to 2.0V
130
ns
2
µs
2
µs
47.5
52.5
µs
150
ns
50
ns
1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven –
see timing diagram.
3. Program Pulse width tolerance is 50 µsec ± 5%.
17. Atmel’s AT27C516 Integrated Product Identification Code
Pins
A0
O15-O8
O7
O6
O5
O4
O3
O2
O1
O0
Hex
Data
Manufacturer
0
0
0
0
0
1
1
1
1
0
001E
Device Type
1
0
1
1
1
1
0
0
1
0
00F2
Codes
8
AT27C516
0362E–EPROM–1/08
AT27C516
18. Rapid Programming Algorithm
A 50 µs PGM pulse width is used to program. The address is set to the first location. VCC is
raised to 6.5V and VPP is raised to 13.0V. Each address is first programmed with one 50 µs
PGM pulse without verification. Then a verification/reprogramming loop is executed for each
address. In the event a word fails to pass verification, up to 10 successive 50 µs pulses are
applied with a verification after each pulse. If the word fails to verify after 10 pulses have been
applied, the part is considered failed. After the word verifies properly, the next address is
selected until all have been checked. VPP is then lowered to 5.0V and VCC to 5.0V. All words
are read again and compared with the original data to determine if the device passes or fails.
9
0362E–EPROM–1/08
19. Ordering Information
19.1
Standard Package
ICC (mA)
tACC
(ns)
Active
Standby
45
30
0.1
70
Notes:
1.
2.
19.2
tACC
(ns)
Ordering Code
Package
AT27C516-45JI
AT27C516-45VI
44J
40V(2)
AT27C516-70JI
AT27C516-70VI
44J
40V(2)
Operation Range
Industrial
(-40° C to 85° C)
Not recommended for new designs. Use Green package option.
The 40-lead VSOP package is not recommended for new designs.
Green Package Option (Pb/Halide-free)
ICC (mA)
Active
Standby
30
0.1
45
Ordering Code
Package
AT27C516-45JU
70
44J
AT27C516-70JU
Operation Range
Industrial
(-40° C to 85° C)
Package Type
44J
44-lead, Plastic J-leaded Chip Carrier (PLCC)
40V
40-lead, Plastic Thin Small Outline Package (VSOP)
10
AT27C516
0362E–EPROM–1/08
AT27C516
20. Package Information
20.1
44J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
D2/E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
17.399
–
17.653
D1
16.510
–
16.662
E
17.399
–
17.653
E1
16.510
–
16.662
D2/E2
14.986
–
16.002
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
44J
B
11
0362E–EPROM–1/08
20.2
40V – VSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
13.80
14.00
14.20
D1
12.30
12.40
12.50
Note 2
E
9.90
10.00
10.10
Note 2
L
0.50
0.60
0.70
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-142, Variation CA.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
L1
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
NOTE
0.50 BASIC
10/18/01
R
12
2325 Orchard Parkway
San Jose, CA 95131
TITLE
40V, 40-lead (10 x 14 mm Package) Plastic Thin Small Outline
Package, Type I (VSOP)
DRAWING NO.
REV.
40V
B
AT27C516
0362E–EPROM–1/08
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0362E–EPROM–1/08
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