AT24C512C - Complete

AT24C512C
I2C-Compatible (2-wire) Serial EEPROM
512-Kbit (65,536 x 8)
DATASHEET
Features

Low-voltage and Standard-voltage Operation
̶
̶







Internally Organized as 65,536 x 8 (512K)
I2C-Compatible (2-Wire) Serial Interface
Schmitt Triggers, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
400kHz (1.7V) and 1MHz (2.5V, 5.5V) Compatibility
Write Protect Pin for Hardware Data Protection
128-byte Page Write Mode
̶



Partial Page Writes Allowed
Random and Sequential Read Modes
Self-timed Write Cycle (5ms Max)
High Reliability
̶
Endurance: 1,000,000 Write Cycles
Data Retention: 40 Years
̶

Green Package Options (Pb/Halide-free/RoHS Compliant)
̶

VCC = 1.7V to 3.6V
VCC = 2.5V to 5.5V
8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-pad UDFN,
8-ball WLCSP, and 8-ball VFBGA Packages
Die sale Options: Wafer Form and Tape and Reel Available
Description
The Atmel® AT24C512C provides 524,288 bits of Serial Electrically Erasable and
Programmable Read-Only Memory (EEPROM) organized as 65,536 words of
8 bits each. The cascadable feature of the device allows up to eight devices to
share a common 2-wire bus. The device is optimized for use in many industrial
and commercial applications where low-power and low-voltage operation are
essential. The devices are available in space-saving 8-lead JEDEC SOIC, 8-lead
EIAJ SOIC, 8-lead TSSOP, 8-pad UDFN, 8-ball WLCSP, and 8-ball VFBGA
packages. In addition, the entire family is available in 1.7V to 3.6V and 2.5V to
5.5V versions.
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
1.
Pin Configurations and Pinouts
Figure 1.
Pin Configurations
Pin Name
Function
A0, A1, A2
Address Inputs
GND
Ground
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
VCC
Power Supply
8-lead SOIC
8-lead TSSOP
A0
1
8
VCC
A1
2
7
WP
A2
3
6
SCL
GND
4
5
SDA
A0
A1
A2
GND
1
2
3
4
Top View
8-pad UDFN
A0
A1
A2
GND
VCC
WP
SCL
SDA
8
7
6
5
Top View
8-ball WLSCP
SDA
VCC
SCL
A2
WP
A1
GND
A0
Top View
VCC
WP
SCL
SDA
Top View
A0
1
8
VCC
A1
2
7
WP
A2
3
6
SCL
GND
4
5
SDA
Top View
Drawings are not to scale.
Absolute Maximum Ratings
Operating Temperature . . . . . . . . . . .-55°C to +125°C
Storage Temperature . . . . . . . . . . . . .-65°C to +150°C
Voltage on any pin
with respect to ground . . . . . . . . . . . . . -1.0V to +7.0V
Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . .5.0mA
2
8
7
6
5
8-ball VFBGA
Note:
2.
1
2
3
4
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the
device at these or any other conditions beyond those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
3.
Block Diagram
Figure 3-1.
Block Diagram
VCC
GND
WP
Start
Stop
Logic
Serial
Control
Logic
LOAD
Device
Address
Comparator
A2
A1
A0
R/W
EN
H.V. Pump/Timing
COMP
LOAD
Data Recovery
INC
Data Word
Addr/counter
Y DEC
X DEC
SCL
SDA
EEPROM
Serial MUX
DOUT/ACK
Logic
DIN
DOUT
4.
Pin Descriptions
Serial Clock (SCL) — The SCL input is used to positive-edge clock data into each EEPROM device and negativeedge clock data out of each device.
Serial Data (SDA) — The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven, and may
be wire-ORed with any number of other open-drain or open-collector devices.
Device Addresses (A2, A1, A0) — The A2, A1, and A0 pins are device address inputs that are hardwired or left not
connected for compatibility with other Atmel AT24Cxx devices. When the pins are hardwired, as many as eight
512K devices may be addressed on a single bus system (see Section 7. “Device Addressing” on page 9 for more
details). If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due
to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the
address pins to a known state. When using a pull-up resistor, Atmel recommends using 10k or less.
Write Protect (WP) — The Write Protect input, when connected to GND, allows normal write operations. When
WP pin is connected directly to VCC, all write operations to the memory are inhibited. If the pin is left floating, the
WP pin will be internally pulled down to GND; however, due to capacitive coupling that may appear during
customer applications, Atmel recommends always connecting the WP pin to a known state. When using a pull-up
resistor, Atmel recommends using 10k or less.
Table 4-1.
Write Protect
WP Pin Status
Part of the Array Protected
At VCC
Full Array
At GND
Normal Read/Write Operations
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
3
5.
Memory Organization
AT24C512C, 512-Kbit Serial EEPROM: The 512K is internally organized as 512 pages of 128 bytes each.
Random word addressing requires a 16-bit data word address.
5.1
Pin Capacitance
Table 5-1.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25C, f = 1.0MHz, VCC = 5.5V.
Symbol
Test Condition
CI/O
CIN
Note:
5.2
1.
Max
Units
Conditions
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
Input Capacitance (A0, A1, A2, SCL)
6
pF
VIN = 0V
This parameter is characterized and is not 100% tested.
DC Characteristics
Table 5-2.
DC Characteristics
Applicable over recommended operating range from: TAI = -40C to +85C, VCC = 1.7V to 3.6V or 2.5V to 5.5V (unless
otherwise noted).
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Supply Voltage
ICC1
Supply Current
VCC = 3.6V
ICC2
Supply Current
VCC = 5.0V
ISB1
Standby Current
ISB2
Standby Current
ILI
Input Leakage Current
VIN = VCC or VSS
ILO
Output Leakage
Current
VOUT = VCC or VSS
VIL
Input Low Level(1)
VIH
Input High Level(1)
VOL1
Output Low Level
VCC = 1.7V
VOL2
Output Low Level
VCC = 3.0V
Note:
4
1.
Test Condition
VCC = 1.7V
VCC = 3.6V
VCC = 2.5V
VCC = 5.5V
Max
Units
1.7
3.6
V
2.5
5.5
V
Read at 400kHz
1.0
mA
Write at 400kHz
3.0
mA
Read at 400kHz
2.0
mA
Write at 400kHz
3.0
mA
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
Typ
1.0
μA
3.0
μA
2.0
μA
6.0
μA
0.10
3.0
μA
0.05
3.0
μA
-0.6
VCC x 0.3
V
VCC x 0.7
VCC + 0.5
V
IOL = 0.15mA
0.2
V
IOL = 2.1mA
0.4
V
VIN = VCC or VSS
VIN = VCC or VSS
VIL min and VIH max are reference only, and are not tested.
AT24C512C [DATASHEET]
Min
5.3
AC Characteristics
Table 5-3.
AC Characteristics
Applicable over recommended operating range from TAI = -40C to +85C, VCC = 1.7V to 3.6V or 2.5V to 5.5V (where
applicable), CL = 100pF (unless otherwise noted). Test conditions are listed in Note 2.
1.7V
Min
2.5V, 5.0V
Symbol
Parameter
Max
Min
fSCL
Clock Frequency, SCL
tLOW
Clock Pulse Width Low
1.3
0.4
μs
tHIGH
Clock Pulse Width High
0.6
0.4
μs
tI
Noise Suppression Time(1)
tAA
Clock Low to Data Out Valid
0.05
tBUF
Time the bus must be free before a new
transmission can start(1)
1.3
0.5
μs
tHD.STA
Start Hold Time
0.6
0.25
μs
tSU.STA
Start Set-up Time
0.6
0.25
μs
tHD.DAT
Data In Hold Time
0
0
μs
tSU.DAT
Data In Set-up Time
100
100
ns
tR
Inputs Rise Time(1)
400
100
(1)
0.9
0.05
Max
Units
1000
kHz
50
ns
0.55
μs
0.3
0.3
μs
300
100
ns
tF
Inputs Fall Time
tSU.STO
Stop Set-up Time
0.6
0.25
μs
tDH
Data Out Hold Time
50
50
ns
tWR
Write Cycle Time
(1)
Endurance
Notes:
1.
2.
25°C, Page Mode, 3.3V
5
5
1,000,000
ms
Write Cycles
This parameter is ensured by characterization only.
AC measurement conditions:

RL (connects to VCC): 1.3k (2.5V, 5V), 10k (1.7V)

Input pulse voltages: 0.3VCC to 0.7VCC

Input rise and fall times:  50ns

Input and output timing reference voltages: 0.5VCC
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
5
6.
Device Operation
Clock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin
may change only during SCL low time periods. Data changes during SCL high periods will indicate a Start or
Stop condition as defined below.
Figure 6-1.
Data Validity
SDA
SCL
Data Stable
Data Stable
Data
Change
Start Condition: A high-to-low transition of SDA with SCL high is a Start condition, which must precede any
other command.
Stop Condition: A low-to-high transition of SDA with SCL high is a Stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power mode.
Figure 6-2.
Start and Stop Definition
SDA
SCL
Start
6
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
Stop
Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.
Figure 6-3.
Output Acknowledge
1
SCL
8
9
Data In
Data Out
Start
Acknowledge
Standby Mode: The AT24C512C features a low-power standby mode, which is enabled:


Upon power-up and
After the receipt of the Stop condition and the completion of any internal operations.
Software Reset: After an interruption in protocol, power loss, or system reset, any 2-wire part can be protocol
reset by following these steps:
1.
Create a Start condition (if possible).
2.
3.
Clock nine cycles.
Create another Start condition followed by a Stop condition, as shown in Figure 6-4 below.
The device should be ready for the next communication after above steps have been completed. In the event
that the device is still non-responsive or remains active on the SDA bus, a power cycle must be used to reset
the device.
Figure 6-4.
Software Reset
Dummy Clock Cycles
SCL
1
Start
Condition
2
3
8
9
Start
Condition
Stop
Condition
SDA
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
7
Figure 6-5.
Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
tHIGH
tF
tR
tLOW
SCL
tSU.STA
tLOW
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA IN
tAA
tDH
tBUF
SDA OUT
Figure 6-6.
Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th Bit
ACK
WORDN
(1)
tWR
Stop
Condition
Note:
8
1.
Start
Condition
The write cycle time, tWR, is the time from a valid Stop condition of a write sequence to the end of the internal
clear/write cycle.
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
7.
Device Addressing
The 512K EEPROM requires an 8-bit device address word following a Start condition to enable the chip for a
read or write operation. The device address word consists of a mandatory ‘1010’ sequence for the first four
most-significant bits (see Figure 7-1 below). This is common to all 2-wire EEPROM devices.
The 512K uses the three device address bits, A2, A1, and A0, to allow as many as eight devices on the same
bus. These bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an
internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is
high, and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a valid compare is not made, the
device will return to a standby state.
Figure 7-1.
512K
Device Address
1
0
1
0
A2
A1
MSB
8.
A0
R/W
LSB
Write Operations
Byte Write: A Byte Write operation requires two 8-bit data word addresses following the device address word
and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero, and then the
part is to receive an 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero.
The addressing device, such as a microcontroller, then must terminate the write sequence with a Stop condition.
At this time, the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are
disabled during this write cycle, and the EEPROM will not respond until the write is complete (see Figure 8-1).
Figure 8-1.
Byte Write
S
T
A
R
T
Device
Address
W
R
I
T
E
First
Word Address
Second
Word Address
S
T
O
P
Data
SDA Line
M
S
B
R A
/ C
W K
A
C
K
A
C
K
A
C
K
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
9
Page Write: The 512-Kbit EEPROM is capable of 128-byte page writes.
A Page Write is initiated the same way as a byte write, but the microcontroller does not send a Stop condition
after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word,
the microcontroller can transmit up to 127 more data words. The EEPROM will respond with a zero after each
data word received. The microcontroller must terminate the page write sequence with a Stop condition and the
internally timed write cycle will begin.
The lower seven bits of the data word address are internally incremented following the receipt of each data
word. The higher data word address bits are not incremented, retaining the memory page row location. When
the word address, internally generated, reaches the page boundary, the following byte is placed at the
beginning of the same page. If more than 128 data words are transmitted to the EEPROM, the data word
address will roll-over, and the previous data will be overwritten. The address roll over during write is from the
last byte of the current page to the first byte of the same page.
Figure 8-2.
Page Write
S
T
A
R
T
Device
Address
W
R
I
T
E
First
Word Address (n)
Second
Word Address (n)
Data (n)
S
T
O
P
Data (n + x)
SDA Line
M
S
B
R A
/ C
WK
A
C
K
A
C
K
A
C
K
A
C
K
Acknowledge Polling: Once the internally-timed write cycle has started and the EEPROM inputs are disabled,
Acknowledge Polling can be initiated. This involves sending a Start condition followed by the device address
word. The read/write select bit is representative of the operation desired. Only if the internal write cycle has
completed will the EEPROM respond with a zero, allowing the read or write sequence to continue.
Data Security: AT24C512C has a hardware data protection scheme that allows the user to write protect the
entire memory when the WP pin is at VCC.
10
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
9.
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit
in the device address word is set to one. There are three types of read operations: Current Address Read,
Random Address Read, and Sequential Read.
9.1
Current Address Read
The internal data word address counter maintains the last address accessed during the last read or write
operation, incremented by one. This address stays valid between operations as long as the chip power is
maintained. The address roll-over during read is from the last byte of the last memory page to the first byte of
the first page.
Once the device address with the read/write select bit set to one is clocked in and acknowledged by the
EEPROM, the current address data word is serially clocked out on the SDA line. The microcontroller does not
respond with an zero, but does generate a following Stop condition.
Figure 9-1.
Current Address Read
S
T
A
R
T
Device
Address
R
E
A
D
S
T
O
P
Data
SDA Line
M
S
B
9.2
R A
/ C
W K
N
O
A
C
K
Random Read
A Random Read requires an initial byte write sequence to load in the data word address. This is known as a
“dummy write” operation. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another Start condition. The microcontroller
now initiates a current address read by sending a device address with the read/write select bit high. The
EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not
respond with a zero, but does generate a following Stop condition.
Figure 9-2.
Random Read
S
T
A
R
T
Device
Address
W
R
I
T
E
First Word
Address
S
T
A
R
T
Second Word
Address
Device
Address
R
E
A
D
S
T
O
P
Data (n)
SDA LINE
M
S
B
R A
/ C
W K
A
C
K
L A
S C
B K
R A
/ C
WK
N
O
A
C
K
Dummy Write
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
11
9.3
Sequential Read
Sequential Reads are initiated by either a Current Address Read or a Random Address Read. After the
microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an
acknowledge, it will continue to increment the data word address and serially clock out sequential data words.
When the memory address limit is reached, the data word address will roll-over and the sequential read will
continue. The Sequential Read operation is terminated when the microcontroller does not respond with a zero
but does generate a following Stop condition.
Figure 9-3.
Sequential Read
S
T
A
R
T
Device
Address
W
R
I
T
E
First Word
Address
Second Word
Address
...
SDA LINE
M
S
B
R A
/ C
W K
L A
S C
B K
A
C
K
Dummy Write
S
T
A
R
T
Device
Address
R
E
A
D
Data (n)
Data (n + 1)
Data (n + 2)
S
T
O
P
Data (n + x)
...
R A
/ C
K
W
12
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
A
C
K
A
C
K
A
C
K
N
O
A
C
K
10.
Ordering Code Detail
AT 2 4 C 5 1 2 C - S S H M x x - T
Atmel Designator
Product Family
24C = Standard I2C-compatible
Serial EEPROM
Shipping Carrier Option
B = Bulk (Tubes)
T = Tape and Reel, Standard Quantity Option
E = Tape and Reel, Expanded Quantity Option
Product Variation
xx = Applies to select packages only.
See ordering table for variation details.
Device Density
512 = 512k
Operating Voltage
M = 1.7V to 3.6V
D = 2.5V to 5.5V
Device Revision
Package Device Grade or
Wafer/Die Thickness
H = Green, NiPdAu Lead Finish,
Industrial Temperature Range
(-40°C to +85°C)
U = Green, Matte Sn Lead Finish,
Industrial Temperature Range
(-40°C to +85°C)
11 = 11mil Wafer Thickness
Package Option
SS
=
S
=
X
=
MA =
U1
=
C
=
WWU =
JEDEC SOIC
EIAJ SOIC
TSSOP
UDFN
WLCSP, 3x5 Grid Array
VFBGA
Wafer Unsawn
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
13
11.
Part Markings
AT24C512C: Package Marking Information
8-lead EIAJ
8-lead SOIC
8-lead TSSOP
ATHYWW
###% @
AAAAAAA
ATMLHYWW
###%
@
AAAAAAAA
ATMLHYWW
###%
@
AAAAAAAA
8-ball WLCSP
8-pad UDFN
8-ball VFBGA
2.0 x 3.0 mm Body
1.5 x 2.0 mm Body
###
H%@
YXX
Note 1:
ATMEL
###%
UYMXX
###U
YMXX
PIN 1
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT24C512C
Truncation Code: ### = 2FC
Date Codes
Y = Year
3: 2013
4: 2014
5: 2015
6: 2016
Voltages
7: 2017
8: 2018
9: 2019
0: 2020
M = Month
A: January
B: February
...
L: December
WW = Work Week of Assembly
02: Week 2
04: Week 4
...
52: Week 52
Country of Assembly
Lot Number
@ = Country of Assembly
AAA...A = Atmel Wafer Lot Number
Trace Code
% = Minimum Voltage
M: 1.7V min
D: 2.5V min
Grade/Lead Finish Material
H: Industrial/NiPdAu
U: Industrial/Matte Tin
Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code)
Example: AA, AB.... YZ, ZZ
AT: Atmel
ATM: Atmel
ATML: Atmel
3/25/13
TITLE
Package Mark Contact:
[email protected]
14
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
24C512CSM, AT24C512C Package Marking Information
DRAWING NO.
REV.
24C512CSM
E
12.
Ordering Information
Delivery Information
Atmel Ordering Code
Lead Finish
Package
Voltage
AT24C512C-SSHM-B
Form
Quantity
Bulk (Tubes)
100 per Tube
Tape and Reel
4,000 per Reel
Bulk (Tubes)
100 per Tube
Tape and Reel
4,000 per Reel
Bulk (Tubes)
95 per Tube
Tape and Reel
2,000 per Reel
Bulk (Tubes)
95 per Tube
Tape and Reel
2,000 per Reel
Bulk (Tubes)
100 per Tube
Tape and Reel
5,000 per Reel
Bulk (Tubes)
100 per Tube
Operation
Range
1.7V to 3.6V
AT24C512C-SSHM-T
8S1
AT24C512C-SSHD-B
2.5V to 5.5V
AT24C512C-SSHD-T
AT24C512C-SHM-B
1.7V to 3.6V
AT24C512C-SHM-T
8S2
AT24C512C-SHD-B
AT24C512C-SHD-T
NiPdAu
2.5V to 5.5V
(Lead-free/Halogen-free)
AT24C512C-XHM-B
1.7V to 3.6V
AT24C512C-XHM-T
Industrial
Temperature
(-40C to 85C)
8X
AT24C512C-XHD-B
2.5V to 5.5V
AT24C512C-XHD-T
5,000 per Reel
AT24C512C-MAHM-T
5,000 per Reel
8MA2
AT24C512C-MAHM-E
15,000 per Reel
Tape and Reel
AT24C512C-U1UM-T(1)
AT24C512C-CUM-T
8U-8
1.7V to 3.6V
SnAgCu
(Lead-free/Halogen-free)
5,000 per Reel
8U2-1
AT24C512C-CUMHY-T
AT24C512C-WWU11M(2)
Notes:
N/A
Wafer Sale
Note 2
1. WLCSP Package: CAUTION: Exposure to ultraviolet (UV) light can degrade the data stored in the EEPROM cells.
Therefore, customers who use a WLCSP product must ensure that exposure to ultraviolet light
does not occur
2. For wafer sales, please contact Atmel sales.
Package Type
8S1
8-lead, 0.150” wide, Plastic Gull Wing, Small Outline (JEDEC SOIC)
8S2
8-lead, 0.208” wide, Plastic Gull Wing, Small Outline (EIAJ SOIC)
8X
8-lead, 4.40mm body, Plastic Thin Shrink Small Outline (TSSOP)
8MA2
8-pad, 2.00mm x 3.00mm body, 0.50mm Pitch, Ultra Thin Dual No Lead (UDFN)
8U-8
8-ball, 3 x 5 Grid Array, Wafer Level Chip Scale (WLCSP)
8U2-1
8-ball, 2.35mm x 3.73mm body, 0.75mm pitch, Small Die Ball Grid Array (VFBGA)
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
15
13.
Package Information
13.1
8S1 — 8-lead JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
SYMBOL MIN
A
1.35
NOM
MAX
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
6/22/11
Package Drawing Contact:
[email protected]
16
TITLE
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
GPC
SWB
DRAWING NO.
REV.
8S1
G
13.2
8S2 — 8-lead EIAJ SOIC
TOP VIEW
END VIEW
C
1
E
E1
L
8
q
SIDE VIEW
e
b
A
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
SYMBOL
A
D
Notes: 1. This drawing is for general information only; refer to EIAJ
Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs aren't
included.
3. Determines the true geometric position.
4. Values b,C apply to plated terminal. The standard thickness
of the plating layer shall measure between 0.007 to .021 mm.
MIN
MAX
NOM
1.70
NOTE
2.16
A1
0.05
0.25
b
0.35
0.48
4
C
0.15
0.35
4
D
5.13
5.35
E1
5.18
5.40
E
7.70
8.26
L
0.51
0.85
q
0°
e
2
8°
1.27 BSC
3
11/10/14
TITLE
Package Drawing Contact:
[email protected]
8S2, 8-lead, 0.208” Body, Plastic
Small Outline Package (EIAJ)
GPC
DRAWING NO.
REV.
STN
8S2
G
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
17
13.3
8X — 8-lead TSSOP
C
1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
A
b
A1
e
D
SYMBOL
Side View
Notes:
COMMON DIMENSIONS
(Unit of Measure = mm)
A2
1. This drawing is for general information only.
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
MIN
NOM
MAX
A
-
-
1.20
A1
0.05
-
0.15
A2
0.80
1.00
1.05
D
2.90
3.00
3.10
2, 5
4.40
4.50
3, 5
0.25
0.30
4
E
6.40 BSC
E1
4.30
b
0.19
e
L
0.65 BSC
0.45
L1
C
NOTE
0.60
0.75
1.00 REF
0.09
-
0.20
2/27/14
TITLE
Package Drawing Contact:
[email protected]
18
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
GPC
TNR
DRAWING NO.
8X
REV.
E
13.4
8MA2 — 8-pad UDFN
E
1
8
Pin 1 ID
2
7
3
6
4
5
D
C
TOP VIEW
A2
SIDE VIEW
A
A1
E2
b (8x)
8
7
1
D2
6
3
5
4
e (6x)
K
L (8x)
BOTTOM VIEW
Notes:
COMMON DIMENSIONS
(Unit of Measure = mm)
2
Pin#1 ID
1. This drawing is for general information only. Refer to
Drawing MO-229, for proper dimensions, tolerances,
datums, etc.
2. The Pin #1 ID is a laser-marked feature on Top View.
3. Dimensions b applies to metallized terminal and is
measured between 0.15 mm and 0.30 mm from the
terminal tip. If the terminal has the optional radius on
the other end of the terminal, the dimension should
not be measured in that radius area.
4. The Pin #1 ID on the Bottom View is an orientation
feature on the thermal pad.
SYMBOL
MIN
NOM
MAX
A
0.50
0.55
0.60
A1
0.0
0.02
0.05
A2
-
-
0.55
D
1.90
2.00
2.10
D2
1.40
1.50
1.60
E
2.90
3.00
3.10
E2
1.20
1.30
1.40
b
0.18
0.25
0.30
C
L
3
1.52 REF
0.30
e
K
NOTE
0.35
0.40
0.50 BSC
0.20
-
-
11/26/14
Package Drawing Contact:
[email protected]
19
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
TITLE
8MA2, 8-pad 2 x 3 x 0.6mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No-Lead
Package (UDFN)
GPC
DRAWING NO.
REV.
YNZ
8MA2
G
13.5
8U-8 — 8-ball WLCSP
TOP VIEW
BOTTOM VIEW
A1 CORNER
1
-B-
2
3
4
5
5
4
3
2
A1 CORNER
1
A
B
E2
E
A
E1
C
B
C
-A-
Øb(8X)
D2
D
D1
d 0.015(4X)
j
n 0.015 m C
n 0.05 m C A B
SIDE VIEW
d 0.075 C
A
A2
-C-
A1
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
PIN ASSIGNMENT MATRIX
2
1
A
VCC
4
SDA
5
A0
WP
A1
SCL
B
C
3
A2
VSS
SYMBOL
MIN
TYP
MAX
A
0.456
0.495
0.534
A1
0.16
-
0.22
A2
0.280
0.305
0.330
E
Contact Atmel for details
E1
0.866
E2
0.500
D
Contact Atmel for details
D1
1.000
D2
0.500
b
NOTE
0.240
0.270
0.300
4/11/13
Package Drawing Contact:
[email protected]
20
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
TITLE
8U-8, 8-ball Wafer Level Chip Scale Package
(WLCSP)
GPC
DRAWING NO.
REV.
GRX
8U-8
A
13.6
8U2-1 — 8-ball VFBGA
f 0.10 C
d 0.10
A1 BALL
PAD
CORNER
D
A
(4X)
d 0.08 C
C
A1 BALL PAD CORNER
2
1
Øb
A
j n0.15 m C A B
j n0.08 m C
B
e
E
C
D
(e1)
B
A1
d
A2
(d1)
A
TOP VIEW
BOTTOM VIEW
SIDE VIEW
8 SOLDER BALLS
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
Notes:
1. This drawing is for general
2. Dimension 'b' is measured at the maximum solder ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
A
A1
A2
b
D
E
e
e1
d
d1
MIN
0.81
0.15
0.40
0.25
NOM
0.91
0.20
0.45
0.30
2.35 BSC
3.73 BSC
0.75 BSC
0.74 REF
0.75 BSC
0.80 REF
MAX
NOTE
1.00
0.25
0.50
0.35
6/11/13
TITLE
Package Drawing Contact:
[email protected]
8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch,
Very Thin, Fine-Pitch Ball Grid Array Package
(VFBGA)
GPC
DRAWING NO.
GWW
8U2-1
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
REV.
G
21
14.
Revision History
Doc. Rev.
Date
8720G
09/2015
8720F
01/2015
8720E
08/2013
Comments
Added the AT24C512C-CUMHY-T package option.
Added the UDFN expanded quantity option.
Updated package outline drawings and the ordering information section.
Correct spelling error.
Correct subscript pin names on pinouts.
Update the ICC1 and ICC2 supply currents in the DC Characteristics table.
Added 8U-8 WLCSP package offering.
8720D
03/2013
Update related information throughout document.
Update footers and disclaimer page.
Update part markings.
8720C
07/2012
Update package drawings.
Update template.
22
8720B
12/2010
8720A
09/2010
Replace part markings with single page standard marking.
Remove five ordering code variations.
Initial document release.
AT24C512C [DATASHEET]
Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015
XXXXXX
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© 2015 Atmel Corporation. / Rev.: Atmel-8720G-SEEPROM-AT24C512C-Datasheet_092015.
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