AT86RF232 Features • High Performance RF-CMOS 2.4GHz radio transceiver targeted for ® ® IEEE 802.15.4, ZigBee , RF4CE, 6LoWPAN, and ISM applications • Industry leading link budget: - Receiver sensitivity -100dBm - Programmable output power from -17dBm up to +3dBm • Ultra-low current consumption: - SLEEP = 0.4µA - TRX_OFF = 330µA - RX_ON = 11.8mA (LISTEN) - BUSY_TX = 13.8mA (at max. transmit power) • Ultra-low supply voltage (1.8V to 3.6V) with internal regulator • Support for coin cell operation • Optimized for low BoM cost and ease of production: - Few external components necessary (crystal, capacitors and antenna) • Easy to use interface: - Registers, frame buffer and AES accessible through fast SPI - Only two microcontroller GPIO lines necessary - One interrupt pin from radio transceiver - Clock output • Radio transceiver features: - 128-byte FIFO (SRAM) for data buffering - Fully integrated, fast settling PLL to support Frequency Hopping - Battery monitor - Fast Wake-Up time < 0.4msec ™ • Special IEEE 802.15.4 -2011 hardware support: - FCS computation and Clear Channel Assessment - RSSI measurement, Energy Detection and Link Quality Indication • MAC hardware accelerator: - Automated acknowledgement, CSMA-CA and retransmission - Automatic address filtering - Automated FCS check • Extended feature set hardware support: - AES 128-bit hardware accelerator - Antenna Diversity - True Random Number Generation for security application • Commercial temperature range: - 0°C to +70°C • I/O and packages: - 32-pin low-profile QFN package 5 x 5 x 0.9mm³ - RoHS/Fully Green • Compliant to IEEE 802.15.4-2011, IEEE 802.15.4-2006 and IEEE 802.15.4-2003 • Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-66, RSS-210 Low Power, 2.4GHz Transceiver for ZigBee, IEEE 802.15.4, 6LoWPAN, RF4CE and ISM Applications AT86RF232 PRELIMINARY Rev. 8321A–MCU Wireless–10/11 1 8321A–MCU Wireless–10/11 1 Pin-out Diagram 2 1. XTAL2 XTAL1 AVSS EVDD AVDD AVSS IRQ AVSS 2 23 /SEL AVSS 3 22 MOSI RFP 4 21 DVSS RFN 5 20 MISO AVSS 6 19 SCLK DVSS 7 18 DVSS /RST 8 17 9 10 11 12 13 14 15 16 CLKM AVSS DEVDD DVDD DVDD DVSS SLP_TR DIG2 AT86RF232 DVSS AVSS 32 31 30 29 28 27 26 25 1 24 exposed paddle DIG1 Note: AVSS AVSS Figure 1-1. Atmel AT86RF232 Pin-out Diagram. The exposed paddle is electrically connected to the die inside the package. It shall be soldered to the board to ensure electrical and thermal contact and good mechanical stability. AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 1.1 Pin Descriptions Table 1-1. Atmel AT86RF232 Pin Description. Pins Name Type Description 1 AVSS Ground Analog ground 2 AVSS Ground Analog ground 3 AVSS Ground Ground for RF signals 4 RFP RF I/O Differential RF signal 5 RFN RF I/O Differential RF signal 6 AVSS Ground Ground for RF signals 7 DVSS Ground Digital ground 8 /RST Digital input Chip reset; active low 9 DIG1 Digital output (Ground) 1. Antenna Diversity RF switch control, see Section 11.3 2. If disabled, pull-down enabled (DVSS) 10 DIG2 Digital output (Ground) 1. Antenna Diversity RF switch control (DIG1 inverted), see Section 11.3 2. RX Frame Time Stamping, see Section 11.4 3. TX Frame Time Stamping, see Section 11.4 4. If functions disabled, pull-down enabled (DVSS) 11 SLP_TR Digital input Controls sleep, transmit start, receive states; active high, see Section 6.5 12 DVSS Ground Digital ground 13, 14 DVDD Supply Regulated 1.8V voltage regulator; digital domain, see Section 9.4 15 DEVDD Supply External supply voltage; digital domain 16 DVSS Ground Digital ground 17 CLKM Digital output Master clock signal output; low if disabled, see Section 9.6 18 DVSS Ground Digital ground 19 SCLK Digital input SPI clock 20 MISO Digital output SPI data output (master input slave output) 21 DVSS Ground Digital ground 22 MOSI Digital input SPI data input (master output slave input) 23 /SEL Digital input SPI select, active low 24 IRQ Digital output 1. Interrupt request signal; active high or active low; configurable 2. Frame Buffer Empty Indicator; active high, see Section 11.5 25 XTAL2 Analog input Crystal pin, see Section 9.6 26 XTAL1 Analog input Crystal pin or external clock supply, see Section 9.6 27 AVSS Ground Analog ground 28 EVDD Supply External supply voltage, analog domain 29 AVDD Supply Regulated 1.8V voltage regulator; analog domain, see Section 9.4 30, 31, 32 AVSS Ground Analog ground Paddle AVSS Ground Analog ground; Exposed paddle of QFN package 3 8321A–MCU Wireless–10/11 1.2 Analog and RF Pins 1.2.1 Supply and Ground Pins EVDD, DEVDD ® EVDD and DEVDD are analog and digital supply voltage pins of the Atmel AT86RF232 radio transceiver. AVDD, DVDD AVDD and DVDD are outputs of the internal 1.8V voltage regulators. The voltage regulators can be configured for external supply. For details, refer to Section 9.4. AVSS, DVSS AVSS and DVSS are analog and digital ground pins respectively. The analog and digital power domains should be separated on the PCB. 1.2.2 RF Pins RFN, RFP A differential RF port (RFP/RFN) provides common-mode rejection to suppress the switching noise of the internal digital signal processing blocks. At board-level, the differential RF layout ensures high receiver sensitivity by rejecting any spurious emissions originated from other digital ICs such as a microcontroller. A simplified schematic of the RF front end is shown in Figure 1-2. Figure 1-2. Simplified RF Front-end Schematic. PCB AT86RF232 0.9V M0 LNA RX PA TX CM Feedback RXTX The RF port is designed for a 100 differential load. A DC path between the RF pins is allowed. A DC path to ground or supply voltage is not allowed. The RF port DC values depend on the operating state, see Chapter 7. In TRX_OFF state, when the analog front-end is disabled (see Section 7.1.2.3), the RF pins are pulled to ground, preventing a floating voltage. 4 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 In transmit mode, a control loop provides a common-mode voltage of 0.9V. Transistor M0 is off, allowing the PA to set the common-mode voltage. The common-mode capacitance at each pin to ground shall be < 30pF to ensure the stability of this common-mode feedback loop. In receive mode, the RF port provides a low-impedance path to ground when transistor M0, see Figure 1-2, pulls the inductor center tap to ground. A DC voltage drop of 20mV across the on-chip inductor can be measured at the RF pins. 1.2.3 Crystal Oscillator Pins XTAL1, XTAL2 The pin 26 (XTAL1) of Atmel AT86RF232 is the input of the reference oscillator amplifier (XOSC), the pin 25 (XTAL2) is the output. A detailed description of the crystal oscillator setup and the related XTAL1/XTAL2 pin configuration can be found in Section 9.6. When using an external clock reference signal, XTAL1 shall be used as input pin. For further details, refer to Section 9.6.3. 1.2.4 Analog Pin Summary Table 1-2. Analog Pin Behavior – DC values. Pin Values and Conditions Comments RFP/RFN VDC = 0.9V (BUSY_TX) VDC = 20mV (receive states) VDC = 0mV (otherwise) DC level at pins RFP/RFN for various transceiver states. AC coupling is required if a circuitry with DC path to ground or supply is used. Serial capacitance and capacitance of each pin to ground must be < 30pF. XTAL1/XTAL2 VDC = 0.9V at both pins CPAR = 3pF DC level at pins XTAL1/XTAL2 for various transceiver states. Parasitic capacitance (Cpar) of the pins must be considered as additional load capacitance to the crystal. DVDD VDC = 1.8V (all states, except SLEEP) VDC = 0mV (otherwise) DC level at pin DVDD for various transceiver states. Supply pins (voltage regulator output) for the digital 1.8V voltage domain, recommended bypass capacitor 100nF. AVDD VDC = 1.8V (all states, except P_ON, SLEEP, RESET, and TRX_OFF) VDC = 0mV (otherwise) DC level at pin AVDD for various transceiver states. Supply pin (voltage regulator output) for the analog 1.8V voltage domain, recommended bypass capacitor 100nF. 5 8321A–MCU Wireless–10/11 1.3 Digital Pins The Atmel AT86RF232 provides a digital microcontroller interface. The interface comprises a slave SPI (/SEL, SCLK, MOSI and MISO) and additional control signals (CLKM, IRQ, SLP_TR, /RST and DIG2). The microcontroller interface is described in detail in Chapter 6. Additional digital output signals DIG1 and DIG2 are provided to control external blocks, that is for Antenna Diversity RF switch control, see Section 11.3. 1.3.1 Driver Strength Settings The driver strength of all digital output pins (MISO, IRQ, DIG1, and DIG2) and CLKM pin are fixed. The capacitive load should be as small as possible as, not larger than 50pF. 1.3.2 Pull-up and Pull-down Configuration All digital input pins are internally pulled-up or pulled-down in radio transceiver state P_ON, see Section 7.1.2.1. Table 1-3 summarizes the pull-up and pull-down configuration. Table 1-3. Pull-up / Pull-Down Configuration of Digital Input Pins. Pins H ̂ pull-up, L /RST H /SEL H SCLK L MOSI L SLP_TR L ̂ pull-down In all other radio transceiver states, no pull-up or pull-down circuitry is connected to any of the digital input pins mentioned in Table 1-3. In RESET state, the pull-up or pull-down resistors are not enabled. If the additional digital output signals DIG1or DIG2 are not activated, these pins are pulled-down to digital ground. 6 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 2 Disclaimer Typical values contained in this datasheet are based on simulations and testing. Minimum and maximum values are available when the radio transceiver has been fully characterized. 3 Overview The Atmel AT86RF232 is a low-power 2.4GHz radio transceiver designed for consumer ZigBee/IEEE 802.15.4, RF4CE, 6LoWPAN, and 2.4GHz ISM band applications. The radio transceiver is a true SPI-to-antenna solution. All RF-critical components except the antenna, crystal and de-coupling capacitors are integrated on-chip. Therefore, the AT86RF232 is particularly suitable for applications like: 2.4GHz IEEE 802.15.4 and ZigBee systems RF4CE systems 6LoWPAN systems Wireless sensor networks Residential and commercial automation Health care Consumer electronics PC peripherals ® The AT86RF232 can be operated by using an external microcontroller like Atmel AVR microcontrollers. A comprehensive software programming description can be found in reference [6], AT86RF232 Software Programming Model. 7 8321A–MCU Wireless–10/11 4 General Circuit Description This single-chip radio transceiver provides a complete radio transceiver interface between an antenna and a microcontroller. It comprises the analog radio, digital modulation and demodulation including time and frequency synchronization and data buffering. The number of external components is minimized such that only the antenna, the crystal and decoupling capacitors are required. The bidirectional differential antenna pins (RFP, RFN) are used for transmission and reception, thus no external antenna switch is needed. The Atmel AT86RF232 block diagram is shown in Figure 4-1. PA and Power Control PA XTAL2 XTAL1 Figure 4-1. AT86RF232 Block Diagram. XOSC PLL AVREG TX Data Configuration Registers TX BBP /SEL DVREG SPI (Slave) RFP FTN, BATMON Frame Buffer MISO MOSI SCLK RFN LNA PPF BPF Limiter ADC RX BBP AES IRQ CLKM DIG2 AGC AD DIG1/2 Analog Domain /RST RSSI Control Logic SLP_TR Antenna Diversity Digital Domain The received RF signal at pin 5 (RFN) and pin 6 (RFP) is differentially fed through the low-noise amplifier (LNA) to the RF filter (PPF) to generate a complex signal, driving the integrated channel filter (BPF). The limiting amplifier provides sufficient gain to drive the succeeding analog-to-digital converter (ADC) and generates a digital RSSI signal. The ADC output signal is sampled by the digital base band receiver (RX BBP). The transmit modulation scheme is offset-QPSK (O-QPSK) with half-sine pulse shaping and 32-length block coding (spreading) according to [1] and [2]. The modulation signal is generated in the digital transmitter (TX BBP) and applied to the fractional-N frequency synthesis (PLL), to ensure the coherent phase modulation required for demodulation of O-QPSK signals. The frequency-modulated signal is fed to the power amplifier (PA). 8 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Two on-chip low-dropout voltage regulators (A|DVREG) provide the analog and digital 1.8V supply. An internal 128-byte RAM for RX and TX (Frame Buffer) buffers the data to be transmitted or the received data. The configuration of the Atmel AT86RF232, reading and writing of Frame Buffer is controlled by the SPI interface and additional control lines. The AT86RF232 further contains comprehensive hardware-MAC support (Extended Operating Mode) and a security engine (AES) to improve the overall system power efficiency and timing. The stand-alone 128-bit AES engine can be accessed in parallel to all PHY operational transactions and states using the SPI interface, except during SLEEP state. To improve the reliability of an RF connection the RF performance can further be improved by using Antenna Diversity. Additional features of the Extended Feature Set, see Chapter 11, are provided to simplify the interaction between radio transceiver and microcontroller. 9 8321A–MCU Wireless–10/11 5 Application Circuits 5.1 Basic Application Schematic A basic application schematic of the Atmel AT86RF232 with a single-ended RF connector is shown in Figure 5-1. The 50Ω single-ended RF input is transformed to the 100Ω differential RF port impedance using balun B1. The capacitors C1 and C2 provide AC coupling of the RF input to the RF port, optional capacitor C4 improves matching if required. Figure 5-1. Basic Application Schematic. CB2 CX1 XTAL CX2 VDD CB1 Digital Interface XTAL2 XTAL1 AVSS EVDD MOSI 22 DVSS 21 AT86RF232 MISO 20 SCLK 19 6 AVSS 9 DVSS DEVDD DVDD DVDD 8 /RST DVSS DVSS 18 CLKM 17 DIG2 7 DVSS DIG1 C2 AVDD 3 AVSS 5 RFN C4 AVSS /SEL 23 4 RFP B1 IRQ 24 2 AVSS SLP_TR C1 RF AVSS 1 AVSS AVSS 32 31 30 29 28 27 26 25 R1 C3 10 11 12 13 14 15 16 VDD CB3 CB4 The power supply decoupling capacitors (CB2, CB4) are connected to the external analog supply pin 28 (EVDD) and external digital supply pin 15 (DEVDD). Capacitors CB1 and CB3 are bypass capacitors for the integrated analog and digital voltage regulators to ensure stable operation. All decoupling and bypass capacitors should be placed as close as possible to the pins and should have a low-resistance and lowinductance connection to ground to achieve the best performance. The crystal (XTAL), the two load capacitors (CX1, CX2), and the internal circuitry connected to pins XTAL1 and XTAL2 form the crystal oscillator. To achieve the best accuracy and stability of the reference frequency, large parasitic capacitances should be avoided. Crystal lines should be routed as short as possible and not in proximity of digital I/O signals. 10 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Crosstalk from digital signals on the crystal pins or the RF pins can degrade the system performance. Therefore, a low-pass filter (C3, R1) is placed close to the Atmel AT86RF232 CLKM output pin to reduce the emission of CLKM signal harmonics. This is not needed if the pin 17 (CLKM) is not used as a microcontroller clock source. In that case, the output should be turned off during device initialization. The ground plane of the application board should be separated into four independent fragments, the analog, the digital, the antenna and the XTAL ground plane. The exposed paddle shall act as the reference point of the individual grounds. Table 5-1. Example Bill of Materials (BoM) for Basic Application Schematic. Designator Description Value Manufacturer Part Number Comment B1 SMD balun 2.45GHz Wuerth 748421245 2.45GHz Balun B1 (alternatively) SMD balun / filter 2.45GHz Johanson Technology 2450FB15L0001 2.45GHz Balun / Filter CB1 CB3 LDO VREG bypass capacitor 100nF Generic CB2 CB4 Power supply decoupling 1µF AVX Murata CX1, CX2 Crystal load capacitor 12pF C1, C2 RF coupling capacitor C3 CLKM low-pass filter capacitor C4 (optional) RF matching R1 CLKM low-pass filter resistor XTAL Crystal X7R (0402) 10% 16V 0603YD105KAT2A GRM188R61C105KA12D X5R (0603) 10% 16V AVX Murata 06035A120JA GRM1555C1H120JA01D COG (0402) 5% 50V 22pF Murata Epcos AVX GRM1555C1H220JA01J C0G 5% B37920 (0402 or 0603) 06035A220JAT2A 2.2pF AVX Murata 06035A229DA GRP1886C1H2R0DA01 COG (0603) 0.5pF 50V 50V Designed for fCLKM = 1MHz Value depends on final PCB implementation 680 CX-4025 16MHz SX-4025 16MHz Designed for fCLKM = 1MHz ACAL Taitjen Siward XWBBPL-F-1 A207-011 11 8321A–MCU Wireless–10/11 5.2 Extended Feature Set Application Schematic The Atmel AT86RF232 supports additional features like: Security Module (AES) Section 11.1 Random Number Generator Section 11.2 Antenna Diversity uses pins DIG1(/2) Section 11.3 RX and TX Frame Time Stamping (TX_ARET) Frame Buffer Empty Indicator uses pin DIG2 Section 11.4 uses pin IRQ Section 11.5 Dynamic Frame Buffer Protection Section 11.6 An extended feature set application schematic illustrating the use of the AT86RF232 Extended Feature Set, see Chapter 11, is shown in Figure 5-2 Although this example shows all additional hardware features combined, it is possible to use all features separately or in various combinations. Figure 5-2. Extended Feature Application Schematic. CB2 CX1 XTAL CX2 VDD CB1 MOSI 22 4 RFP DVSS 21 AT86RF232 5 RFN MISO 20 8 /RST CLKM 17 DVSS DVSS 18 DEVDD 7 DVSS DVDD SCLK 19 DVDD 6 AVSS 9 Digital Interface XTAL2 XTAL1 AVSS EVDD AVDD AVSS AVSS 3 AVSS DVSS ANT1 /SEL 23 SLP_TR B1 IRQ 24 2 AVSS DIG1 Balun RFSwitch SW1 1 AVSS DIG2 ANT0 AVSS 32 31 30 29 28 27 26 25 R1 C3 10 11 12 13 14 15 16 VDD CB3 12 CB4 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 In this example, a balun (B1) transforms the differential RF signal at the Atmel AT86RF232 radio transceiver RF pins (RFP/RFN) to a single ended RF signal, similar to the Basic Application Schematic; refer to Figure 5-1. During receive mode the radio transceiver searches for the most reliable RF signal path using the Antenna Diversity algorithm. One antenna is selected (SW2) by the Antenna Diversity RF switch control pin 9 (DIG1), refer to Section 11.3. RX and TX Frame Time stamping is implemented through pin 10 (DIG2), refer to Section 11.4. The security engine (AES) does not require specific circuitry to operate, for details refer to Section 11.1. 13 8321A–MCU Wireless–10/11 6 Microcontroller Interface This section describes the Atmel AT86RF232 to microcontroller interface. The interface comprises a slave SPI and additional control signals; see Figure 6-1. The SPI timing and protocol are described below. Figure 6-1. Microcontroller to AT86RF232 Interface. AT86RF232 /SEL /SEL /SEL MOSI MOSI MOSI MISO MISO MISO SCLK SCLK SCLK GPIO1/CLK CLKM CLKM GPIO2/IRQ IRQ SPI - Master SPI - Slave SPI Microcontroller IRQ SLP_TR GPIO3 SLP_TR GPIO4 /RST /RST GPIO5 DIG2 DIG2 Microcontrollers with a master SPI such as Atmel AVR family interface directly to the AT86RF232. The SPI is used for register, Frame Buffer, SRAM and AES access. The additional control signals are connected to the GPIO/IRQ interface of the microcontroller. Table 6-1 introduces the radio transceiver I/O signals and their functionality. Table 6-1. Signal Description of Microcontroller Interface. 14 Signal Description /SEL SPI select signal, active low MOSI SPI data (master output slave input) signal MISO SPI data (master input slave output) signal SCLK SPI clock signal CLKM Optional, Clock output, refer to Section 9.6.4, usable as: - microcontroller clock source - high precision timing reference IRQ Interrupt request signal, further used as: - Frame Buffer Empty indicator, refer to Section 11.5 SLP_TR Multi purpose control signal (functionality is state dependent, see Section 6.5): - Sleep/Wakeup enable/disable SLEEP state - TX start BUSY_TX_(ARET) state /RST AT86RF232 reset signal, active low DIG2 Optional, - IRQ_2 (RX_START) for RX Frame Time Stamping, see Section 11.4 - Signals frame transmit within TX_ARET mode for TX Time Stamping AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 6.1 SPI Timing Description Pin 17 (CLKM) can be used as a microcontroller master clock source. If the microcontroller derives the SPI master clock (SCLK) directly from CLKM, the SPI operates in synchronous mode, otherwise in asynchronous mode. In asynchronous mode, the maximum SCLK frequency fasync is limited to 7.5MHz. The signal at pin 17 (CLKM) is not required to derive SCLK and may be disabled to reduce power consumption and spurious emissions. Figure 6-2 and Figure 6-3 illustrate the SPI timing and introduces its parameters. The corresponding timing parameter definitions t1 – t9 are defined in Section 12.4. Figure 6-2. SPI Timing, Global Map and Definition of Timing Parameters t5, t6, t8, t9. t8 t9 /SEL SCLK MOSI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 t5 MISO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 t6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Figure 6-3. SPI Timing, Detailed Drawing of Timing Parameters t1 to t4. /SEL SCLK t3 MOSI t4 Bit 7 Bit 6 t1 MISO Bit 5 t2 Bit 7 Bit 6 Bit 5 The SPI is based on a byte-oriented protocol and is always a bidirectional communication between master and slave. The SPI master starts the transfer by asserting /SEL = L. Then the master generates eight SPI clock cycles to transfer one byte to the radio transceiver (via MOSI). At the same time, the slave transmits one byte to the master (via MISO). When the master wants to receive one byte of data from the slave it must also transmit one byte to the slave. All bytes are transferred with MSB first. An SPI transaction is finished by releasing /SEL = H. An SPI register access consists of two bytes, a Frame Buffer or SRAM access of at least two or more bytes as described in Section 6.2. /SEL = L enables the MISO output driver of the Atmel AT86RF232. The MSB of MISO is valid after t1 (see Section 12.4 parameter) and is updated at each falling edge of SCLK. If the driver is disabled, there is no internal pull-up circuitry connected to it. Driving the appropriate signal level must be ensured by the master device or an external pull-up resistor. 15 8321A–MCU Wireless–10/11 Note: 1. When both /SEL and /RST are active, the MISO output driver is also enabled. Referring to Figure 6-2 and Figure 6-3 Atmel AT86RF232 MOSI is sampled at the rising edge of the SCLK signal and the output is set at the falling edge of SCLK. The signal must be stable before and after the rising edge of SCLK as specified by t3 and t4, refer to Section 12.4 parameters. This SPI operational mode is commonly known as “SPI mode 0”. 6.2 SPI Protocol Each SPI sequence starts with transferring a command byte from the SPI master via MOSI (see Table 6-2) with MSB first. This command byte defines the SPI access mode and additional mode-dependent information. Table 6-2. SPI Command Byte Definition. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 1 0 1 1 0 0 1 reserved 0 1 1 reserved 0 0 0 reserved 0 1 0 reserved Bit 1 Bit 0 Register address [5:0] Access Mode Access Type Register access Read access Register address [5:0] Write access Frame Buffer access Read access Write access SRAM access Read access Write access Each SPI transfer returns bytes back to the SPI master on MISO. The content of the first byte (see value “PHY_STATUS“ in Figure 6-4 to Figure 6-14) is set to zero after reset. To transfer status information of the radio transceiver to the microcontroller, the content of the first byte can be configured with register bits SPI_CMD_MODE (register 0x04, TRX_CTRL_1). For details, refer to Section 6.3.1. In Figure 6-4 to Figure 6-14 and the following chapters logic values stated with XX on MOSI are ignored by the radio transceiver, but need to have a valid logic level. Return values on MISO stated as XX shall be ignored by the microcontroller. The different access modes are described within the following sections. 6.2.1 Register Access Mode A register access mode is a two-byte read/write operation initiated by /SEL = L. The first transferred byte on MOSI is the command byte including an identifier bit (bit[7] = 1), a read/write select bit (bit[6]), and a 6-bit register address. On read access, the content of the selected register address is returned in the second byte on MISO (see Figure 6-4). Figure 6-4. Packet Structure - Register Read Access. byte 1 (command byte) MOSI 1 MISO Note: 16 0 ADDRESS[5:0] PHY_STATUS 1. (1) byte 2 (data byte) XX READ DATA[7:0] Each SPI access can be configured to return radio controller status information (PHY_STATUS) on MISO, for details refer to Section 6.3. AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 On write access, the second byte transferred on MOSI contains the write data to the selected address (see Figure 6-5). Figure 6-5. Packet Structure - Register Write Access. byte 1 (command byte) MOSI 1 1 MISO byte 2 (data byte) ADDRESS[5:0] WRITE DATA[7:0] PHY_STATUS XX Each register access must be terminated by setting /SEL = H. Figure 6-6 illustrates a typical SPI sequence for a register access sequence for write and read respectively. Figure 6-6. Example SPI Sequence – Register Access Mode. Register Write Access Register Read Access /SEL SCLK MOSI WRITE COMMAND MISO PHY_STATUS WRITE DATA READ COMMAND XX PHY_STATUS XX READ DATA 6.2.2 Frame Buffer Access Mode The Atmel AT86RF232 128-byte Frame Buffer can hold the PHY service data unit (PSDU) data of one IEEE 802.15.4 compliant RX or one TX frame of maximum length at a time. A detailed description of the Frame Buffer can be found in Section 9.3. An introduction to the IEEE 802.15.4 frame format can be found in Section 8.1. Frame Buffer read and write accesses are used to read or write frame data (PSDU and additional information) from or to the Frame Buffer. Each access starts with /SEL = L followed by a command byte on MOSI. If this byte indicates a frame read or write access, the next byte PHR indicates the frame length followed by the PSDU data, see Figure 6-7 and Figure 6-8. On Frame Buffer read access, PHY header (PHR) and PSDU are transferred via MISO starting with the second byte. After the PSDU data, three more bytes are transferred containing the link quality indication (LQI) value, the energy detection (ED) value, and the status information (RX_STATUS) of the received frame, for LQI details refer to Section 8.6. The Figure 6-7 illustrates the packet structure of a Frame Buffer read access. Figure 6-7. Packet Structure - Frame Read Access. byte 1 (command byte) byte 2 (data byte) byte 3 (data byte) byte n-1 (data byte) byte n (data byte) MOSI 0 0 1 reserved[4:0] XX XX XX XX MISO PHY_STATUS PHR[7:0] PSDU[7:0] ED[7:0] RX_STATUS[7:0] 17 8321A–MCU Wireless–10/11 The structure of RX_STATUS is described in Table 6-3. Table 6-3. Structure of RX_STATUS. Bit 7 6 RX_CRC_VALID 5 4 TRAC_STATUS Read/Write Reset value R 0 R 0 Bit 3 2 RX_STATUS R 0 R 0 1 0 reserved Read/Write Reset value Note: 1. R 0 RX_STATUS R 0 R 0 R 0 More information to RX_CRC_VALID, see Section 8.2.5, and to TRAC_STATUS, see Section 7.2.6. On Frame Buffer write access the second byte transferred on MOSI contains the frame length (PHR field) followed by the payload data (PSDU) as shown by Figure 6-8. Figure 6-8. Packet Structure - Frame Write Access. byte 1 (command byte) byte 2 (data byte) byte 3 (data byte) byte n-1 (data byte) byte n (data byte) MOSI 0 1 1 reserved[4:0] PHR[7:0] PSDU[7:0] PSDU[7:0] PSDU[7:0] MISO PHY_STATUS XX XX XX XX The number of bytes n for one frame access is calculated as follows: Read Access: n = 5 + frame_length [PHY_STATUS, PHR byte, PSDU data, LQI, ED, and RX_STATUS] Write Access: n = 2 + frame_length [command byte, PHR byte, and PSDU data] Each read or write of a data byte automatically increments the address counter of the Frame Buffer until the access is terminated by setting /SEL = H. A Frame Buffer read access may be terminated (/SEL = H) at any time without affecting the Frame Buffer content. Another Frame Buffer read operation starts again at the PHR field. The content of the Atmel AT86RF232 Frame Buffer is overwritten by a new received frame or a Frame Buffer write access. Figure 6-9 and Figure 6-10 illustrate an example SPI sequence of a Frame Buffer access to read a frame with 2-byte PSDU and write a frame with 4-byte PSDU. Figure 6-9. Example SPI Sequence - Frame Buffer Read of a Frame with 2-byte PSDU. /SEL SCLK MOSI COMMAND XX MISO PHY_STATUS PHR 18 XX PSDU 1 XX PSDU 2 XX LQI XX ED XX RX_STATUS AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Figure 6-10. Example SPI Sequence - Frame Buffer Write of a Frame with 4-byte PSDU. /SEL SCLK MOSI COMMAND MISO PHY_STATUS PHR PSDU 1 XX PSDU 2 XX XX PSDU 3 PSDU 4 XX XX Access violations during a Frame Buffer read or write access are indicated by interrupt IRQ_6 (TRX_UR). For further details, refer to Section 9.3. Notes: 1. The Frame Buffer is shared between RX and TX; therefore, the frame data are overwritten by new incoming frames. If the TX frame data are to be retransmitted, it must be ensured that no frame was received in the meanwhile. 2. To avoid overwriting during receive Dynamic Frame Buffer Protection can be enabled, refer to Section 11.6. 3. For exceptions, receiving acknowledgement frames in Extended Operating Mode (TX_ARET) refer to Section 7.2.4. 6.2.3 SRAM Access Mode The SRAM access mode allows accessing dedicated bytes within Atmel AT86RF232 Frame Buffer or AES address space, refer to Section 11.1. the During frame receive after occurrence of interrupt IRQ_2 (RX_START) an SRAM access can be used to upload the PHR field while preserving Dynamic Frame Buffer Protection, see Section 11.6. Each SRAM access starts with /SEL = L. The first transferred byte on MOSI shall be the command byte and must indicate an SRAM access mode according to the definition in Table 6-2. The following byte indicates the start address of the write or read access. SRAM address space: Frame Buffer: 0x00 to 0x7F AES: 0x82 to 0x94 On SRAM read access, one or more bytes of read data are transferred on MISO starting with the third byte of the access sequence (see Figure 6-11). Figure 6-11. Packet Structure – SRAM Read Access. byte 1 (command byte) byte 2 (address) byte 3 (data byte) byte n-1 (data byte) byte n (data byte) MOSI 0 0 0 reserved[4:0] ADDRESS[7:0] XX XX XX MISO PHY_STATUS XX DATA[7:0] DATA[7:0] DATA[7:0] On SRAM write access, one or more bytes of write data are transferred on MOSI starting with the third byte of the access sequence (see Figure 6-12). 19 8321A–MCU Wireless–10/11 Figure 6-12. Packet Structure – SRAM Write Access. byte 1 (command byte) byte 2 (address) byte 3 (data byte) byte n-1 (data byte) byte n (data byte) MOSI 0 1 0 reserved[4:0] ADDRESS[7:0] DATA[7:0] DATA[7:0] DATA[7:0] MISO PHY_STATUS XX XX XX XX As long as /SEL = L, every subsequent byte read or byte write increments the address counter of the Frame Buffer until the SRAM access is terminated by /SEL = H. Figure 6-13 and Figure 6-14 illustrate an example SPI sequence of an Atmel AT86RF232 SRAM access to read and write a data package of five byte length respectively. Figure 6-13. Example SPI Sequence – SRAM Read Access of a 5-byte Data Package. /SEL SCLK MOSI COMMAND MISO PHY_STATUS ADDRESS XX XX DATA 1 XX DATA 2 XX DATA 3 XX XX DATA 4 DATA 5 DATA 4 DATA 5 Figure 6-14. Example SPI Sequence – SRAM Write Access of a 5-byte Data Package. /SEL SCLK MOSI COMMAND MISO PHY_STATUS ADDRESS XX XX Notes: 20 DATA 1 DATA 2 XX DATA 3 XX XX XX 1. The SRAM access mode is not intended to be used as an alternative to the Frame Buffer access modes (see Section 6.2.2). 2. Frame Buffer access violations are not indicated by a TRX_UR interrupt when using the SRAM access mode, for further details refer to Section 9.3.3. AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 6.3 Radio Transceiver Status information Each Atmel AT86RF232 SPI access can be configured to return status information of the radio transceiver (PHY_STATUS) to the microcontroller using the first byte of the data transferred via MISO. The content of the radio transceiver status information can be configured using register bits SPI_CMD_MODE (register 0x04, TRX_CTRL_1). After reset, the content on the first byte send on MISO to the microcontroller is set to zero. 6.3.1 Register Description Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. Figure 6-15. Register TRX_CTRL_1. Bit 0x04 Read/Write Reset value 7 6 5 4 reserved IRQ_2_EXT_EN TX_AUTO_CRC_ ON RX_BL_CTRL R/W 0 R/W 0 R/W 1 R/W 0 3 2 1 0 IRQ_MASK_MODE IRQ_POLARITY R/W 1 R/W 0 Bit 0x04 SPI_CMD_MODE Read/Write Reset value R/W 0 R/W 0 TRX_CTRL_1 TRX_CTRL_1 Bit 3:2 - SPI_CMD_MODE Each SPI transfer returns bytes back to the SPI master. The content of the first byte (PHY_STATUS) can be configured using register bits SPI_CMD_MODE. Table 6-4. SPI_CMD_MODE. Register Bits SPI_CMD_MODE Note: 1. Value Description 0 Default (empty, all bits zero) 1 Monitor TRX_STATUS register 2 Monitor PHY_RSSI register 3 Monitor IRQ_STATUS register More information to register TRX_STATUS, see Section 7.1.5, to register PHY_RSSI, see Section 8.3, and to register IRQ_STATUS, see Section 6.6. 21 8321A–MCU Wireless–10/11 6.4 Radio Transceiver Identification The Atmel AT86RF232 can be identified by four registers. One register contains a unique part number and one register the corresponding version number. Two additional registers contain the JEDEC manufacture ID. 6.4.1 Register Description Register 0x1C (PART_NUM): The register PART_NUM can be used for the radio transceiver identification and includes the device part number. Figure 6-16. Register PART_NUM. Bit 7 6 0x1C Read/Write Reset value R 0 R 0 Bit 3 2 0x1C Read/Write Reset value 5 4 R 0 R 0 1 0 R 1 R 0 PART_NUM PART_NUM PART_NUM R 1 R 0 PART_NUM Bit 7:0 - PART_NUM Table 6-5. PART_NUM. Register Bits Value Description PART_NUM 0x0A AT86RF232 part number Register 0x1D (VERSION_NUM): The register VERSION_NUM can be used for the radio transceiver identification and includes the device version number. Figure 6-17. Register VERSION_NUM. Bit 7 6 5 0x1D Read/Write Reset value R 0 R 0 Bit 3 2 0x1D Read/Write Reset value 4 VERSION_NUM VERSION_NUM R 0 R 0 1 0 R 1 R 0 VERSION_NUM R 0 R 0 VERSION_NUM Bit 7:0 - VERSION_NUM Table 6-6. VERSION_NUM. 22 Register Bits Value Description VERSION_NUM 0x02 Revision A AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Register 0x1E (MAN_ID_0): Part one of the JEDEC manufacturer ID. Figure 6-18. Register MAN_ID_0. Bit 7 6 Read/Write Reset value R 0 R 0 Bit 3 2 0x1E 4 R 0 R 1 1 0 R 1 R 1 MAN_ID_0 0x1E Read/Write Reset value 5 MAN_ID_0 MAN_ID_0 R 1 R 1 MAN_ID_0 Bit 7:0 - MAN_ID_0 Table 6-7. MAN_ID_0. Register Bits Value Description MAN_ID_0 0x1F Atmel JEDEC manufacturer ID, bits[7:0] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_0. Bits [15:8] are stored in register 0x1F (MAN_ID_1). The higher 16 bits of the ID are not stored in registers. Register 0x1F (MAN_ID_1): Part two of the JEDEC manufacturer ID. Figure 6-19. Register MAN_ID_1. Bit 7 6 0x1F Read/Write Reset value R 0 R 0 Bit 3 2 0x1F Read/Write Reset value 5 4 R 0 R 0 1 0 R 0 R 0 MAN_ID_1 MAN_ID_1 MAN_ID_1 R 0 R 0 MAN_ID_1 Bit 7:0 - MAN_ID_1 Table 6-8. MAN_ID_1. Register Bits Value Description MAN_ID_1 0x00 Atmel JEDEC manufacturer ID, bits[15:8] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_1. Bits [7:0] are stored in register 0x1E (MAN_ID_0). The higher 16 bits of the ID are not stored in registers. 23 8321A–MCU Wireless–10/11 6.5 Sleep/Wake-up and Transmit Signal (SLP_TR) Pin 11 (SLP_TR) is a multi-functional pin. Its function relates to the current state of the Atmel AT86RF232 and is summarized in Table 6-9. The radio transceiver states are explained in detail in Chapter 7. Table 6-9. SLP_TR Multi-functional Pin. Transceiver Status Function Transition Description PLL_ON TX start LH Starts frame transmission TX_ARET_ON TX start LH Starts TX_ARET transaction TRX_OFF Sleep LH Takes the radio transceiver into SLEEP state, CLKM disabled SLEEP Wakeup HL Takes the radio transceiver back into TRX_OFF state, level sensitive In states PLL_ON and TX_ARET_ON, pin 11 (SLP_TR) is used as trigger input to initiate a TX transaction. Here SLP_TR is sensitive on rising edge only. After initiating a state change by a rising edge at pin 11 (SLP_TR) in radio transceiver state TRX_OFF, the radio transceiver remains in the new state as long as the pin is logical high and returns to the preceding state with the falling edge. SLEEP state The SLEEP state is used when radio transceiver functionality is not required, and thus the AT86RF232 can be powered down to reduce the overall power consumption. A power-down scenario is shown in Figure 6-20. When the radio transceiver is in TRX_OFF state the microcontroller forces the AT86RF232 to SLEEP by setting SLP_TR = H. If pin 17 (CLKM) provides a clock to the microcontroller this clock is switched off after 35 CLKM cycles. The AT86RF232 awakes when the microcontroller releases pin 11 (SLP_TR). The CLKM clock frequency setting for 62.5kHz are not intended to directly clock the microcontroller. When using these clock rates, CLKM is turned off immediately when entering SLEEP state. Figure 6-20. Sleep and Wake-up Initiated by Asynchronous Microcontroller Timer. SLP_TR tTR1a CLKM tTR3 (35 CLKM clock cycles) CLKM off async timer elapses (microcontroller) Note: 24 1. Timing figures tTR3 and tTR1a refer to Table 7-1. AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 6.6 Interrupt Logic 6.6.1 Overview The Atmel AT86RF232 differentiates between nine interrupt events (eight physical interrupt registers, one shared by two functions). Each interrupt is enabled by setting the corresponding bit in the interrupt mask register 0x0E (IRQ_MASK). Internally, each pending interrupt is stored in a separate bit of the interrupt status register. All interrupt events are OR-combined to a single external interrupt signal (IRQ pin). If an interrupt is issued, pin 24 (IRQ) = H, the microcontroller shall read the interrupt status register 0x0F (IRQ_STATUS) to determine the source of the interrupt. A read access to this register clears the interrupt status register and thus the IRQ pin, too. Interrupts are not cleared automatically when the event that caused them vanishes. Exceptions are IRQ_0 (PLL_LOCK) and IRQ_1 (PLL_UNLOCK) because the occurrence of one clears the other. The supported interrupts for the Basic Operating Mode are summarized in Table 6-10. Table 6-10. Interrupt Description in Basic Operating Mode. IRQ Name Description Section IRQ_7 (BAT_LOW) Indicates a supply voltage below the programmed threshold. 9.5.4 IRQ_6 (TRX_UR) Indicates a Frame Buffer access violation. 9.3.3 IRQ_5 (AMI) Indicates an address match. IRQ_4 (CCA_ED_DONE) Multi-functional interrupt: 1. AWAKE_END: Indicates finished transition to TRX_OFF state from P_ON, SLEEP, or RESET state. 2. CCA_ED_DONE: Indicates the end of a CCA or ED measurement. 7.2.3.4 7.1.2.3 8.4.4 8.5.4 IRQ_3 (TRX_END) RX: Indicates the completion of a frame reception. TX: Indicates the completion of a frame transmission. 7.1.3 7.1.3 IRQ_2 (RX_START) Indicates the start of a PSDU reception. Register bits TRX_STATUS changes to BUSY_RX, the PHR is valid to be read from Frame Buffer. 7.1.3 IRQ_1 (PLL_UNLOCK) Indicates PLL unlock. If the radio transceiver is in BUSY_TX / BUSY_TX_ARET state, the PA is turned off immediately. 9.7.5 IRQ_0 (PLL_LOCK) Indicates PLL lock. 9.7.5 Note: 1. The IRQ_4 (AWAKE_END) interrupt can usually not be seen when the transceiver enters TRX_OFF state after P_ON, or RESET, because register 0x0E (IRQ_MASK) is reset to mask all interrupts. It is recommended to enable IRQ_4 (AWAKE_END) to be notified once the TRX_OFF state is entered. The interrupt handling in Extended Operating Mode is described in Section 7.2.5. 25 8321A–MCU Wireless–10/11 6.6.2 Interrupt Mask Modes and Pin Polarity If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt event can be read from IRQ_STATUS register even if the interrupt itself is masked. However, in that case no timing information for this interrupt is provided. The Table 6-11, Figure 6-21, and Figure 6-22 describes the function. Table 6-11. IRQ Mask Configuration. IRQ_MASK Value IRQ_MASK_MODE Description 0 0 IRQ is suppressed entirely and none of interrupt causes are shown in register IRQ_STATUS. 0 1 IRQ is suppressed entirely but all interrupt causes are shown in register IRQ_STATUS. ≠0 0 All enabled interrupts are signaled on IRQ pin and are also shown in register IRQ_STATUS. ≠0 1 All enabled interrupts are signaled on IRQ pin and all interrupt causes are shown in register IRQ_STATUS. Interrupt Sources Figure 6-21. IRQ_MASK_MODE = 0. . . . IRQ_MASK (register 0x0E) IRQ_STATUS (register 0x0F) OR IRQ Interrupt Sources Figure 6-22. IRQ_MASK_MODE = 1. . . . IRQ_STATUS (register 0x0F) IRQ_MASK OR IRQ (register 0x0E) The Atmel AT86RF232 IRQ pin polarity can be configured with register bit IRQ_POLARITY (register 0x04, TRX_CTRL_1). The default behavior is active high, which means that pin 24 (IRQ) = H issues an interrupt request. If “Frame Buffer Empty Indicator” is enabled during Frame Buffer read access the IRQ pin has an alternative functionality, refer to Section 11.5 for details. 26 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 6.6.3 Register Description Register 0x0E (IRQ_MASK): The IRQ_MASK register controls the interrupt signaling via pin 24 (IRQ). Figure 6-23. Register IRQ_MASK. Bit 7 6 R/W 0 R/W 0 3 2 0x0E 5 4 R/W 0 R/W 0 1 0 R/W 0 R/W 0 IRQ_MASK Read/Write Reset value Bit 0x0E IRQ_MASK IRQ_MASK Read/Write Reset value R/W 0 R/W 0 IRQ_MASK Bit 7:0 - IRQ_MASK Mask register for interrupts. IRQ_MASK[7] correspondents with IRQ_7_BAT_LOW. IRQ_MASK[0] correspondents with IRQ_0_PLL_LOCK. Table 6-12. IRQ_MASK. Register Bits Value Description IRQ_MASK 0x00 The IRQ_MASK register is used to enable or disable individual interrupts. An interrupt is enabled if the corresponding bit is set to one. All interrupts are disabled after power-on sequence (P_ON state) or reset (RESET state). Valid values are [0xFF, 0xFE, …, 0x00]. Note: 1. If an interrupt is enabled it is recommended to read the interrupt status register 0x0F (IRQ_STATUS) first to clear the history. Register 0x0F (IRQ_STATUS): The IRQ_STATUS register contains the status of the pending interrupt requests. Figure 6-24. Register IRQ_STATUS. Bit 0x0F 7 6 5 4 IRQ_7_BAT_LOW IRQ_6_TRX_UR IRQ_5_AMI IRQ_4_CCA_ED_ DONE Read/Write Reset value R 0 R 0 R 0 R 0 Bit 3 2 1 0 IRQ_3_TRX_END IRQ_2_RX_ START IRQ_1_PLL_ UNLOCK IRQ_0_PLL_ LOCK R 0 R 0 R 0 R 0 0x0F Read/Write Reset value IRQ_STATUS IRQ_STATUS For more information to meanings of interrupts, see Table 6-10 Interrupt Description in Basic Operating Mode. 27 8321A–MCU Wireless–10/11 By reading the register after an interrupt is signaled at pin 24 (IRQ) the source of the issued interrupt can be identified. A read access to this register resets all interrupt bits, and so clears the IRQ_STATUS register. Notes: 1. If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt event can be read from IRQ_STATUS register even if the interrupt itself is masked. However in that case no timing information for this interrupt is provided. 2. If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, it is recommended to read the interrupt status register 0x0F (IRQ_STATUS) first to clear the history. Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. Figure 6-25. Register TRX_CTRL_1. Bit 7 0x04 6 5 4 reserved IRQ_2_EXT_EN TX_AUTO_CRC_ ON RX_BL_CTRL R/W 0 R/W 0 R/W 1 R/W 0 3 2 Read/Write Reset value Bit 0x04 SPI_CMD_MODE Read/Write Reset value R/W 0 1 0 IRQ_MASK_MODE IRQ_POLARITY R/W 1 R/W 0 R/W 0 TRX_CTRL_1 TRX_CTRL_1 Bit 6 - IRQ_2_EXT_EN Controls external signaling for time stamping via pin 10 (DIG2). Table 6-13. IRQ_2_EXT_EN. Register Bits IRQ_2_EXT_EN Value Description 0 Time stamping over pin 10 (DIG2) is disabled (1) Time stamping over pin 10 (DIG2) is enabled 1 Notes: 1. The pin 10 (DIG2) is also active even if the corresponding interrupt event IRQ_2 (RX_START) mask bit in register 0x0E (IRQ_MASK) is set to zero. 2. The pin remains at high level until the end of the frame receive or transmit procedure. The timing of a received frame can be determined by a separate pin 10 (DIG2). If register bit IRQ_2_EXT_EN is set to one, the reception of a PHR is directly issued on pin 10 (DIG2), similar to interrupt IRQ_2 (RX_START). For further details refer to Section 11.4. 28 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Bit 1 - IRQ_MASK_MODE The radio transceiver supports polling of interrupt events. Interrupt polling can be enabled by register bit IRQ_MASK_MODE. Table 6-14. IRQ_MASK_MODE. Register Bits Value IRQ_MASK_MODE Description 0 Interrupt polling is disabled Masked off IRQ bits will not appear in IRQ_STATUS register. 1 Interrupt polling is enabled Masked off IRQ bits will appear in IRQ_STATUS register. Even if an interrupt request is masked by the corresponding bit in register 0x0E (IRQ_MASK), the event is indicated in register 0x0F (IRQ_STATUS). Bit 0 - IRQ_POLARITY The register bit IRQ_POLARITY controls the polarity for pin 24 (IRQ). The default polarity of the pin 24 (IRQ) is active high. The polarity can be configured to active low via register bit IRQ_POLARITY. Table 6-15. IRQ_POLARITY. Register Bits IRQ_POLARITY Note: 1. Value Description 0 Pin IRQ is high active 1 Pin IRQ is low active A modification on IRQ_POLARITY bit has no influence to RX_BL_CTRL behavior. This setting does not affect the polarity of the “Frame Buffer Empty Indicator”, refer to Section 11.5. The Frame Buffer Empty Indicator is always active high. 29 8321A–MCU Wireless–10/11 7 Operating Modes 7.1 Basic Operating Mode This section summarizes all states to provide the basic functionality of the Atmel AT86RF232, such as receiving and transmitting frames, the power-on sequence, and sleep. The Basic Operating Mode is designed for IEEE 802.15.4 and general ISM band applications; the corresponding radio transceiver states are shown in Figure 7-1. Figure 7-1. Basic Operating Mode State Diagram (for timing refer to Table 7-1). SLEEP (Sleep State) XOSC=ON Pull=ON XOSC=OFF Pull=OFF FORCE_TRX_OFF TR X_ O FF RX _O N 5 RX_ON (Rx Listen State) ON L_ PL Frame End 8 RESET (all states except P_ON) XOSC=ON Pull=OFF 7 /RST = H 13 FF O X_ TR BUSY_RX (Receive State) /RST = L (Clock State) (all states except SLEEP) SHR Detected (from all states) TRX_OFF 12 6 3 = _TR = _TR SLP L 2 TR X_ OF F SLP 15 H P_ON (Power-on after VDD) 4 11 RX_ON PLL_ON (PLL State) PLL_ON 9 Frame End 10 BUSY_TX (Transmit State) SLP_TR = H or TX_START FORCE_PLL_ON 14 (all states except SLEEP, or P_ON) Legend: Blue: SPI Write to Register TRX_STATE (0x02) Red: Control signals via IC Pin Green: Event Basic Operating Mode States X State transition number, see Table 7-1 for timing 7.1.1 State Control The radio transceiver states are controlled either by writing commands to register bits TRX_CMD (register 0x02, TRX_STATE), or directly by two signal SLP_TR and /RST pins. A successful state change can be verified by reading the radio transceiver status from register bits TRX_STATUS (register 0x01, TRX_STATUS). 30 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 If TRX_STATUS = 0x1F (STATE_TRANSITION_IN_PROGRESS) the Atmel AT86RF232 is within a state transition. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS. Pin 11 (SLP_TR) is a multifunctional pin, refer to Section 6.5. Depending on the radio transceiver state, a rising edge of pin 11 (SLP_TR) causes the following state transitions: TRX_OFF SLEEP PLL_ON BUSY_TX (level sensitive) Whereas the falling edge of pin SLP_TR causes the following state transitions: SLEEP TRX_OFF (level sensitive) A low level on pin 8 (/RST) causes a reset of all registers (register bits CLKM_CTRL are shadowed, for details refer to Section 9.6.4) and forces the radio transceiver into TRX_OFF state. However, if the device was in P_ON state it remains in the P_ON state. For all states except SLEEP, the state change commands FORCE_TRX_OFF or TRX_OFF lead to a transition into TRX_OFF state. If the radio transceiver is in active receive or transmit states (BUSY_*), the command FORCE_TRX_OFF interrupts these active processes, and forces an immediate transition to TRX_OFF. In contrast a TRX_OFF command is stored until an active state (receiving or transmitting) has been finished. After that the transition to TRX_OFF is performed. For a fast transition from any non sleep states to PLL_ON state, the command FORCE_PLL_ON is provided. In contrast to FORCE_TRX_OFF this command does not disable PLL and analog voltage regulator (AVREG). It is not available in states P_ON, SLEEP, or RESET. The completion of each requested state change shall always be confirmed by reading the register bits TRX_STATUS (register 0x01, TRX_STATUS). Note: 1. If FORCE_TRX_OFF and FORCE_PLL_ON commands are used, it is recommended to set pin 11 (SLP_TR) = L before. 7.1.2 Basic Operating Mode Description 7.1.2.1 P_ON – Power-On after VDD When the external supply voltage (VDD) is firstly applied to the AT86RF232, the radio transceiver goes into the P_ON state performing an on-chip reset. The crystal oscillator is activated and the default 1MHz master clock is provided at pin 17 (CLKM) after the crystal oscillator has stabilized. CLKM can be used as a clock source to the microcontroller. The SPI interface and digital voltage regulator (DVREG) are enabled. The on-chip power-on-reset sets all registers to their default values. A dedicated reset signal from the microcontroller at pin 8 (/RST) is not necessary, but recommended for hardware / software synchronization reasons. All digital inputs are pulled-up or pulled-down during P_ON state, refer to Section 1.3.2. This is necessary to support microcontrollers where GPIO signals are floating after power-on or reset. The input pull-up and pull-down circuitry is disabled when the radio transceiver leaves the P_ON state. Output pins DIG1/DIG2 are pulled-down to digital ground, unless their configuration is changed. 31 8321A–MCU Wireless–10/11 Prior to leaving P_ON, the microcontroller must set the Atmel AT86RF232 pins to the default operating values: pin 11 (SLP_TR) = L, pin 8 (/RST) = H and pin 23 (/SEL) = H. All interrupts are disabled by default. Thus, interrupts for state transition control are to be enabled first, for example enable IRQ_4 (AWAKE_END) to indicate a state transition to TRX_OFF state or interrupt IRQ_0 (PLL_LOCK) to signal a locked PLL in PLL_ON state. In P_ON state a first access to the radio transceiver registers is possible after a default 1MHz master clock is provided at pin 17 (CLKM), refer to tTR1 to Table 7-1. Once the supply voltage has stabilized and the crystal oscillator has settled (see parameter tXTAL refer to Table 7-2), a valid SPI write access to register bits TRX_CMD (register 0x02, TRX_STATE) with the command TRX_OFF or FORCE_TRX_OFF initiate a state change from P_ON towards TRX_OFF state, which is then indicated by an interrupt IRQ_4 (AWAKE_END) if enabled. 7.1.2.2 SLEEP – Sleep State In SLEEP state, the entire radio transceiver is disabled. No circuitry is operating beyond the circuitry monitoring pin 11 (SLP_TR) and pin 8 (/RST). This state can only be entered from state TRX_OFF, by setting the SLP_TR = H. If CLKM is enabled with a clock rates higher than 62.5kHz, the SLEEP state is entered 35 CLKM cycles after the rising edge at pin 11 (SLP_TR). At that time CLKM is turned off. If the CLKM output is already turned off (register bits CLKM_CTRL = 0), the SLEEP state is entered immediately. At clock rate 62.5kHz, the main clock at pin 17 (CLKM) is turned off immediately. Setting SLP_TR = L returns the radio transceiver to the TRX_OFF state. During SLEEP state the radio transceiver register contents and the AES register contents remain valid while the contents of the Frame Buffer are destroyed. /RST = L in SLEEP state returns the radio transceiver to TRX_OFF state and thereby sets all registers to their default values. Exceptions are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0). These register bits require a specific treatment, for details see Section 9.6.4. Note: 1. If during SLEEP state a voltage jump on VDD occurs of more than 0.8V within 1ms, the internal Power-On logic detects this as a P_ON reset and the AT86RF232 goes into the P_ON state. 7.1.2.3 TRX_OFF – Clock State In TRX_OFF the crystal oscillator is running and the master clock is available if enabled. The SPI interface and digital voltage regulator are enabled, thus the radio transceiver registers, the Frame Buffer and security engine (AES) are accessible (see Section 9.3 and Section 11.1). In contrast to P_ON state the pull-up and pull-down configuration is disabled. Pin 11 (SLP_TR) and pin 8 (/RST) are available for state control. The analog front-end is disabled during TRX_OFF state. Entering the TRX_OFF state from P_ON, SLEEP or RESET state is indicated by interrupt IRQ_4 (AWAKE_END) if enabled. 7.1.2.4 PLL_ON – PLL State Entering the PLL_ON state from TRX_OFF state enables the analog voltage regulator (AVREG) first. After the voltage regulator has been settled, the PLL frequency 32 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 synthesizer is enabled. When the PLL has been settled at the receive frequency to a channel defined by register bits CHANNEL (register 0x08, PHY_CC_CCA), refer to Section 9.7.2, a successful PLL lock is indicated by issuing an interrupt IRQ_0 (PLL_LOCK). If an RX_ON command is issued in PLL_ON state, the receiver is enabled immediately. If the PLL has not been settled before the state change nevertheless takes place. Even if the register bits TRX_STATUS (register 0x01, TRX_STATUS) indicates RX_ON, actual frame reception can only start once the PLL has locked. The PLL_ON state corresponds to the TX_ON state in IEEE 802.15.4. 7.1.2.5 RX_ON and BUSY_RX – RX Listen and Receive State In RX_ON state the receiver module and the PLL frequency synthesizer are enabled. The Atmel AT86RF232 receive mode is internally separated into RX_ON state and BUSY_RX state. There is no difference between these states with respect to the analog radio transceiver circuitry, which is always turned on. In both states, the receiver and the PLL frequency synthesizer are enabled. During RX_ON state, the receiver listens for incoming frames. After detecting a valid synchronization header (SHR), the AT86RF232 automatically enters the BUSY_RX state. The reception of a valid PHY header (PHR) generates an IRQ_2 (RX_START) and starts the PSDU data demodulation. During PSDU reception, the frame data are stored continuously in the Frame Buffer until the last byte was received. The completion of the frame reception is indicated by an interrupt IRQ_3 (TRX_END) and the radio transceiver reenters the state RX_ON. At the same time the register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is updated with the result of the FCS check (see Section 8.2). Received frames are passed to the frame filtering unit, refer to Section 7.2.3.4. If the content of the MAC addressing fields (refer to [1] IEEE 802.15.4-2006 Section 7.2.1) of a frame matches to the expected addresses, which is further dependent on the addressing mode, an address match interrupt IRQ_5 (AMI) is issued, refer to Section 6.6. The expected address values are to be stored in registers 0x20 – 0x2B (Short address, PAN-ID and IEEE address). Frame filtering is available in Basic Operating Mode and Extended Operating Mode, refer to Section 7.2.3.4. Leaving state RX_ON is possible by writing a state change command to register bits TRX_CMD in register 0x02 (TRX_STATE). 7.1.2.6 BUSY_TX – Transmit State A transmission can be initiated in state PLL_ON. There are two ways to start a transmission: Rising edge of pin 11 (SLP_TR) TX_START command to register bits TRX_CMD (register 0x02, TRX_STATE). Either of these takes the radio transceiver into the BUSY_TX state. During the transition to BUSY_TX state, the PLL frequency shifts to the transmit frequency. The actual transmission of the first data chip of the SHR starts after 16µs to allow PLL settling and PA ramp-up, see Figure 7-6. After transmission of the SHR, the Frame Buffer content is transmitted. In case the PHR indicates a frame length of zero, the transmission is aborted. 33 8321A–MCU Wireless–10/11 After the frame transmission has completed, the Atmel AT86RF232 automatically turns off the power amplifier, generates an IRQ_3 (TRX_END) interrupt and returns into PLL_ON state. 7.1.2.7 RESET State The RESET state is to reset all registers and state machines of the AT86RF232 to their default values, exception are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0). These register bits require a specific treatment, for details see Section 9.6.4. A reset forces the radio transceiver into TRX_OFF state. If the device is still in the P_ON state it remains in the P_ON state though. A reset is initiated with pin 8 (/RST) = L and the state is left after setting /RST = H. The reset pulse should have a minimum length as specified in Section 12.4 see parameter t10. During reset the microcontroller has to set the radio transceiver control SLP_TR and /SEL pins to their default values. An overview about the register reset values is provided in Table 14-2. 34 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 7.1.3 Interrupt Handling All interrupts provided by the Atmel AT86RF232 (see Table 6-10) are supported in Basic Operating Mode. For example, interrupts are provided to observe the status of radio transceiver RX and TX operations. On reception IRQ_2 (RX_START) indicates the detection of a valid PHR first, IRQ_5 (AMI) an address match and IRQ_3 (TRX_END) the completion of the frame reception. On transmission IRQ_3 (TRX_END) indicates the completion of the frame transmission. Figure 7-2 shows an example for a transmit/receive transaction between two devices and the related interrupt events in Basic Operating Mode. Device 1 transmits a frame containing a MAC header (in this example of length seven), payload and valid FCS. The frame is received by Device 2 which generates the interrupts during the processing of the incoming frame. The received frame is stored in the Frame Buffer. The first interrupt IRQ_2 (RX_START) signals the reception of a valid PHR. If the received frame passes the address filter, refer to Section 7.2.3.4, an address match interrupt IRQ_5 (AMI) is issued after the reception of the MAC header (MHR). In Basic Operating Mode the third interrupt IRQ_3 (TRX_END) is issued at the end of the received frame. In Extended Operating Mode, refer to Section 7.2; the interrupt is only issued if the received frame passes the address filter and the FCS is valid. Further exceptions are explained in Section 7.2. Processing delay tIRQ is a typical value, refer to Section 12.4. Figure 7-2. Timing of RX_START, AMI and TRX_END Interrupts in Basic Operating Mode. 160 PLL_ON 192 192+(9+m)*32 BUSY_TX Time [µs] PLL_ON SLP_TR IRQ Number of Octets Frame Content TRX_STATE IRQ Interrupt latency tTR10 4 1 1 7 Preamble SFD PHR MHR RX_ON m 2 MSDU FCS BUSY_RX IRQ_2 (RX_START) tIRQ IRQ_5 (AMI) tIRQ Frame on Air Typ. Processing Delay IRQ_3 (TRX_END) RX_ON TRX_END tIRQ RX (Device 2) TRX_STATE 128 TX (Device1) -16 0 35 8321A–MCU Wireless–10/11 7.1.4 Basic Operating Mode Timing The following paragraphs depict Atmel AT86RF232 state transitions and their timing properties. Timing figures are explained in Table 7-1, Table 7-2, and Section 12.4. 7.1.4.1 Power-on Procedure The power-on procedure to P_ON state is shown in Figure 7-3. Figure 7-3. Power-on Procedure to P_ON State. 0 100 Event VDD on State P_ON Block XOSC, DVREG Time 400 Time [µs] CLKM on tTR1 When the external supply voltage (VDD) is first supplied to the AT86RF232, the radio transceiver enables the crystal oscillator (XOSC) and the internal 1.8V voltage regulator for the digital domain (DVREG). After tTR1 = 330µs (typ.), the master clock signal is available at pin 17 (CLKM) at default rate of 1MHz. As soon as CLKM is available the SPI is enabled and can be used to control the transceiver. As long as no state change towards state TRX_OFF is performed, the radio transceiver remains in P_ON state. 7.1.4.2 Wake-up Procedure The wake-up procedure from SLEEP state is shown in Figure 7-4. Figure 7-4. Wake-up Procedure from SLEEP State. 0 SLP_TR = L Event State Block Time 200 CLKM on Time [μs] IRQ_4 (AWAKE_END) TRX_OFF SLEEP XOSC, DVREG FTN XOSC, DVREG tTR2 The radio transceiver’s SLEEP state is left by releasing SLP_TR pin to logic low. This restarts the XOSC and DVREG. After tTR2 = 210µs (typ.) the radio transceiver enters TRX_OFF state. The internal clock signal is available and provided to pin 17 (CLKM), if CLKM was enabled. This procedure is similar to the Power-on Procedure. However the radio transceiver automatically proceeds to the TRX_OFF state. During this, transition the filter-tuning network (FTN) calibration is performed. Entering TRX_OFF state is signaled by IRQ_4 (AWAKE_END), if this interrupt was enabled by the appropriate mask register bit. 36 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 7.1.4.3 PLL_ON and RX_ON States The transition from TRX_OFF to PLL_ON or RX_ON mode is shown in Figure 7-5. Figure 7-5. Transition from TRX_OFF to PLL_ON or RX_ON state. 0 80 IRQ_0 (PLL_LOCK) Event State PLL_ON TRX_OFF Block AVREG Command PLL_ON Time Notes: Time [µs] RX_ON RX PLL RX_ON tTR4 tTR8 1. If TRX_CMD = RX_ON in TRX_OFF state RX_ON state is entered immediately, even if the PLL has not settled. 2. Timing figures tTR4 and tTR8 refers to Table 7-1. In TRX_OFF state, entering the commands PLL_ON or RX_ON initiates a ramp-up sequence of the internal 1.8V voltage regulator for the analog domain (AVREG). RX_ON state can be entered any time from PLL_ON state regardless whether the PLL has already locked, which is indicated by IRQ_0 (PLL_LOCK). 7.1.4.4 BUSY_TX and RX_ON States The transition from PLL_ON to BUSY_TX state and subsequently to RX_ON state is shown in Figure 7-6. Figure 7-6. PLL_ON to BUSY_TX to RX_ON Timing. 0 Pin State Block Command Time 16 x x + 32 Time [µs] SLP_TR PLL_ON BUSY_TX PLL PA or command TX_START tTR10 RX_ON PA, TX PLL RX RX_ON tTR11 Starting from PLL_ON state it is further assumed that the PLL is already locked. A transmission is initiated either by a rising edge of pin 11 (SLP_TR) or by command TX_START, the Atmel AT86RF232 changes into BUSY_TX state. The PLL settles to the transmit frequency and the PA is enabled. tTR10 = 16µs after initiating the transmission starts the internally generated SHR transmission. After that the PSDU data are transmitted from the Frame Buffer. After completing the frame transmission, indicated by IRQ_3 (TRX_END), the PLL settles back to the receive frequency within tTR11 = 32µs in state PLL_ON. 37 8321A–MCU Wireless–10/11 If during TX_BUSY the radio transmitter is programmed to change to a receive state it automatically proceeds the state change to RX_ON state after finishing the transmission. 7.1.4.5 Reset Procedure The radio transceiver reset procedure is shown in Figure 7-7. Figure 7-7. Reset Procedure. x 0 x + 10 x + 30 Event Time [μs] [IRQ_4 (AWAKE_END)] State various Block TRX_OFF XOSC, DVREG FTN XOSC, DVREG Pin /RST Time Note: >t10 1. >t11 tTR13 Timing figure tTR13 refers to Table 7-1, t10, t11 refers to Section 12.4. /RST = L sets all registers to their default values. Exceptions are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0), refer to Section 9.6.4. After releasing the reset pin 8 (/RST) = H the wake-up sequence including an FTN calibration cycle is performed, refer to Section 9.8. After that the TRX_OFF state is entered. Figure 7-7 illustrates the reset procedure once the P_ON state was left and the radio transceiver was not in SLEEP state. The reset procedure is identical for all originating radio transceiver states except of state P_ON, or SLEEP. Instead, here the procedure described in Section 7.1.2.1 must be followed to enter the TRX_OFF state. If the radio transceiver was in state SLEEP, the XOSC and DVREG are enabled before entering TRX_OFF state. If register bits TRX_STATUS indicates STATE_TRANSITION_IN_PROGRESS during system initialization until the Atmel AT86RF232 reaches TRX_OFF state, do not try to initiate a further state change while the radio transceiver is in this state. Notes: 38 2. The reset impulse should have a minimum length t10 = 625ns as specified in Section 12.4. 3. An access to the device should not occur earlier than t11 ≥ 625ns after releasing the /RST pin; refer to Section 12.4. 4. A reset overrides an SPI command request that might have been queued. AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 7.1.4.6 State Transition Timing Summary The Atmel AT86RF232 transition numbers correspond to Figure 7-1 and do not include SPI access time unless otherwise stated. See measurement setup in Figure 5-1. Table 7-1. State Transition Timing. Symbol Parameter Condition tTR1 P_ONCLKM is available tTR1a Min. Typ. Max. Unit Depends on crystal oscillator setup (CL= 10pF) and external capacitor at DVDD (100nF nom.). 330 1000 µs SLEEPCLKM is available Depends on crystal oscillator setup (CL= 10pF) and external capacitor at DVDD (100nF nom.). 180 1000 µs tTR2 SLEEPTRX_OFF Depends on crystal oscillator setup (CL= 10pF) and external capacitor at DVDD (100nF nom.). 210 1000 µs tTR3 TRX_OFFSLEEP For fCLKM > 62.5kHz. 35 CLKM cycles Otherwise. 0 CLKM cycles Depends on external capacitor at AVDD (100nF nom.). 80 µs 1 µs 80 µs 1 µs tTR4 TRX_OFFPLL_ON tTR5 PLL_ONTRX_OFF tTR6 TRX_OFFRX_ON tTR7 RX_ONTRX_OFF tTR8 PLL_ONRX_ON 1 µs tTR9 RX_ONPLL_ON Transition time is also valid for TX_ARET_ON, RX_AACK_ON. 1 µs tTR10 PLL_ONBUSY_TX When asserting pin 11 (SLP_TR) or TRX_CMD = TX_START first symbol transmission is delayed by one symbol period (PLL settling and PA ramp-up). 16 µs tTR11 BUSY_TXPLL_ON PLL settling time. 32 µs tTR12 Various statesTRX_OFF Using TRX_CMD = FORCE_TRX_OFF; not valid for SLEEP. 1 µs tTR13 RESETTRX_OFF Not valid for P_ON or SLEEP. 26 µs tTR14 Various statesPLL_ON Using TRX_CMD = FORCE_PLL_ON; not valid for P_ON, SLEEP, or RESET. 1 µs tTR15 P_ONTRX_OFF Using TRX_CMD = TRX_OFF directly after CLKM is available. 360 Depends on external capacitor at AVDD (100nF nom.). 1000 µs The state transition timing is calculated based on the timing of the individual blocks shown in Figure 7-3 to Figure 7-7. The worst case values include maximum operating temperature, minimum supply voltage, and device parameter variations. 39 8321A–MCU Wireless–10/11 Table 7-2. Atmel AT86RF232 Block Initialization and Settling Time. Symbol Parameter Condition tXTAL Reference oscillator settling time tFTN FTN calibration time tDVREG Typ. Max. Unit Start XTALclock available at pin 17 (CLKM). Depends on crystal Q factor and load capacitor. 330 1000 µs 25 µs DVREG settling time Depends on external bypass capacitor at DVDD (CB3 = 100nF nom., 10µF worst case). 50 1000 µs tAVREG AVREG settling time Depends on external bypass capacitor at AVDD (CB1 = 100nF nom., 10µF worst case). 50 1000 µs tPLL_INIT Initial PLL settling time PLL settling time TRX_OFFPLL_ON, including 50µs AVREG settling time. 80 250 µs tPLL_SW PLL settling time on channel switch Duration of channel switch within frequency band. 11 100 µs tPLL_CF PLL CF calibration PLL center frequency calibration. 8 24 µs tPLL_DCU PLL DCU calibration PLL DCU calibration. 6 µs tRX_TX RXTX Maximum settling time RXTX. 16 µs tTX_RX TXRX Maximum settling time TXRX. 32 µs tSHR_SYNC SHR, sync SHR synchronization period. 160 µs tRSSI RSSI, update RSSI update period in receive states. tED ED measurement ED measurement period is eight symbols. 135 180 µs tCCA CCA measurement CCA measurement period is eight symbols. 135 180 µs tRND Random value, update Random value update period. tAES AES core cycle time 40 Min. 32 96 2 µs 1 23.4 µs 24 µs AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 7.1.5 Register Description Register 0x01 (TRX_STATUS): The read-only register TRX_STATUS signals the present state of the radio transceiver as well as the status of a CCA operation. Figure 7-8. Register TRX_STATUS. Bit 0x01 7 6 5 4 CCA_DONE CCA_STATUS reserved TRX_STATUS Read/Write Reset value R 0 R 0 R 0 R 0 Bit 3 2 1 0 R 0 R 0 0x01 TRX_STATUS Read/Write Reset value R 0 R 0 TRX_STATUS TRX_STATUS Bit 4:0 - TRX_STATUS The register bits TRX_STATUS signals the current radio transceiver status. Table 7-3. TRX_STATUS. Register Bits Value Description TRX_STATUS 0x00 P_ON 0x01 BUSY_RX 0x02 BUSY_TX 0x06 RX_ON 0x08 TRX_OFF (CLK Mode) 0x09 PLL_ON (TX_ON) (1) SLEEP 0x11 (2) BUSY_RX_AACK 0x12 (2) BUSY_TX_ARET 0x16 (2) RX_AACK_ON 0x19 (2) TX_ARET_ON (3) STATE_TRANSITION_IN_PROGRESS 0x0F 0x1F All other values are reserved Notes: 1. In SLEEP state register not accessible. 2. Extended Operating Mode only. 3. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state. A read access to register bits TRX_STATUS reflects the current radio transceiver state. A state change is initiated by writing a state transition command to register bits TRX_CMD (register 0x02, TRX_STATE). Alternatively, some state transitions can be initiated by the rising edge of pin 11 (SLP_TR) in the appropriate state. These register bits are used for Basic and Extended Operating Mode, see Section 7.2. If the requested state transition is not completed yet, the TRX_STATUS returns STATE_TRANSITION_IN_PROGRESS. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS. State transition timings are defined in Table 7-1. 41 8321A–MCU Wireless–10/11 Register 0x02 (TRX_STATE): The radio transceiver states are controlled via register TRX_STATE using register bits TRX_CMD. The read-only register bits TRAC_STATUS indicate the status or result of an Extended Operating Mode transaction. Figure 7-9. Register TRX_STATE. Bit 7 0x02 6 5 TRAC_STATUS Read/Write Reset value R 0 R 0 Bit 3 2 0x02 4 TRX_CMD R 0 R/W 0 1 0 R/W 0 R/W 0 TRX_CMD Read/Write Reset value R/W 0 R/W 0 TRX_STATE TRX_STATE Bit 4:0 - TRX_CMD A write access to register bits TRX_CMD initiates a radio transceiver state transition. Table 7-4. TRX_CMD. Register Bits TRX_CMD Value Description 0x00 (1) NOP 0x02 (2) TX_START 0x03 0x04 (3) FORCE_TRX_OFF FORCE_PLL_ON 0x06 RX_ON 0x08 TRX_OFF (CLK Mode) 0x09 PLL_ON (TX_ON) 0x16 (4) RX_AACK_ON 0x19 (4) TX_ARET_ON All other values are reserved Notes: 1. TRX_CMD = “0” after power on reset (POR). 2. The frame transmission starts one symbol after TX_START command. 3. FORCE_PLL_ON is not valid for states P_ON, SLEEP, and RESET, as well as STATE_TRANSITION_IN_PROGRESS towards these states. 4. Extended Operating Mode only. A write access to register bits TRX_CMD initiates a radio transceiver state transition towards the new state. These register bits are used for Basic and Extended Operating Mode, see Section 7.2. 42 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 7.2 Extended Operating Mode The Extended Operating Mode is a hardware MAC accelerator and goes beyond the basic radio transceiver functionality provided by the Basic Operating Mode. It handles time critical MAC tasks as requested by the IEEE 802.15.4 standard, by hardware, such as automatic acknowledgement, automatic CSMA-CA and retransmission. This results in a more efficient IEEE 802.15.4 software MAC implementation including reduced code size and may allow the use of a smaller microcontroller or to operate at low clock rates. The Extended Operating Mode is designed to support IEEE 802.15.4-2006 and IEEE 802.15.4-2011 compliant frames; the mode is backward compatible to IEEE 802.15.4-2003 and supports non IEEE 802.15.4 compliant frames. This mode comprises the following procedures: Automatic acknowledgement (RX_AACK) divides into the tasks: Frame reception and automatic FCS check Configurable addressing fields check Interrupt indicating address match Interrupt indicating frame reception, if it passes address filtering and FCS check Automatic ACK frame transmission (if the received frame passed the address filter and FCS check and if an ACK is required by the frame type and ACK request) Support of slotted acknowledgment using SLP_TR pin Automatic CSMA-CA and Retransmission (TX_ARET) divides into the tasks: CSMA-CA including automatic CCA retry and random back-off Frame transmission and automatic FCS field generation Reception of ACK frame (if an ACK was requested) Automatic frame retry if ACK was expected but not received Interrupt signaling with transaction status Automatic FCS check and generation, refer to Section 8.2, is used by the RX_AACK and TX_ARET modes. In RX_AACK mode, an automatic FCS check is always performed for incoming frames. In TX_ARET mode, an ACK, received within the time required by IEEE 802.15.4, is accepted if the FCS is valid, and if the sequence number of the ACK matches the sequence number of the previously transmitted frame. Dependent on the value of the frame pending subfield in the received acknowledgement frame the transaction status is set, see TRAC_STATUS, Section 7.2.7. An Atmel AT86RF232 state diagram including the Extended Operating Mode states is shown in Figure 7-10. Yellow marked states represent the Basic Operating Mode; blue marked states represent the Extended Operating Mode. 43 8321A–MCU Wireless–10/11 Figure 7-10. Extended Operating Mode State Diagram. SLEEP (Sleep State) XOSC=ON Pull=ON XOSC=OFF Pull=OFF 2 5 TR X_ O FF RX_ON RX_ON (Rx Listen State) PLL_ON 4 11 PLL_ON 9 10 BUSY_RX_AACK Transaction Finished PL L_ (all states except SLEEP or P_ON) From / To TRX_OFF SLP_TR=H or TX_START RX_AACK_ON RX_AACK_ON TX_ARET_ON FORCE_PLL_ON TX_ARET_ON TX _A RE T_ TR ON X_ OF F RX _A AC K_ ON PLL_ON 14 N _O ET SHR Detected BUSY_TX (Transmit State) SLP_TR = H or TX_START R _A TX _A F OF X_ ON TR K_ AC RX RX_AACK_ON RX_ON N _O RX From / To TRX_OFF Frame End (PLL State) ON Frame End 8 RESET ON L_ PL RX _O N XOSC=ON Pull=OFF 7 /RST = H (all states except P_ON) FF _O BUSY_RX (Receive State) 13 X TR SHR Detected /RST = L (Clock State) (all states except SLEEP) 6 (from all states) TRX_OFF 12 FORCE_TRX_OFF 3 _TR SLP = _TR SLP TR X_ OF F L 15 =H P_ON (Power-on after VDD) TX_ARET_ON Frame End BUSY_TX_ARET Legend: Blue: SPI Write to Register TRX_STATE (0x02) Red: Control signals via IC Pin Green: Event Basic Operating Mode States Extended Operating Mode States 44 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 7.2.1 State Control The Extended Operating Mode states RX_AACK and TX_ARET are controlled via register bits TRX_CMD (register 0x02, TRX_STATE), which receives the state transition commands. The states are usually entered from TRX_OFF or PLL_ON state as illustrated by Figure 7-10. The completion of each state change command shall always be confirmed by reading the register bits TRX_STATUS (register 0x01, TRX_STATUS). RX_AACK - Receive with Automatic ACK A state transition to RX_AACK_ON is initiated by writing the command RX_AACK_ON to the register bits TRX_CMD. The state change should be confirmed by reading register bits TRX_STATUS (register 0x01, TRX_STATUS). The RX_AACK state is left by writing a new command to the register bits TRX_CMD. If the Atmel AT86RF232 is within a frame receive or acknowledgment procedure (BUSY_RX_AACK), the state change is executed after finishing. Alternatively, the commands FORCE_TRX_OFF or FORCE_PLL_ON can be used to cancel the RX_AACK transaction and change into radio transceiver state TRX_OFF or PLL_ON, respectively. TX_ARET - Transmit with Automatic Frame Retransmission and CSMA-CA Retry A state transition to TX_ARET_ON is initiated by writing command TX_ARET_ON to register bits TRX_CMD. The radio transceiver is in the TX_ARET_ON state after register bits TRX_STATUS (register 0x01, TRX_STATUS) changes to TX_ARET_ON. The TX_ARET transaction is started with a rising edge of pin 11 (SLP_TR) or writing the command TX_START to register bits TRX_CMD. The TX_ARET state is left by writing a new command to the register bits TRX_CMD. If the AT86RF232 is within a CSMA-CA transaction, a frame transmission or an acknowledgment procedure (BUSY_TX_ARET), the state change is executed after finishing. Alternatively, the command FORCE_TRX_OFF or FORCE_PLL_ON can be used to instantly terminate the TX_ARET transaction and change into radio transceiver state TRX_OFF or PLL_ON, respectively. Note: 1. A state change request from TRX_OFF to RX_AACK_ON or TX_ARET_ON internally passes the state PLL_ON. Thus the ability to receive or transmit data is delayed accordingly. It is recommended to use interrupt IRQ_0 (PLL_LOCK) as an indicator. 45 8321A–MCU Wireless–10/11 7.2.2 Configuration The use of the Extended Operating Mode is based on Basic Operating Mode functionality. Only features beyond the basic radio transceiver functionality are described in the following sections. For details on the Basic Operating Mode refer to Section 7.1. When using the RX_AACK or TX_ARET modes, the following registers needs to be configured. RX_AACK configuration steps: Short address, PAN-ID and IEEE address registers 0x20 – 0x2B Configure RX_AACK properties registers 0x2C, 0x2E o Handling of Frame Version Subfield o Handling of Pending Data Indicator o Characterize as PAN coordinator o Handling of Slotted Acknowledgement Additional Frame Filtering Properties registers 0x17, 0x2E o Promiscuous Mode o Enable or disable automatic ACK generation o Handling of reserved frame types The addresses for the address match algorithm are to be stored in the appropriate address registers. Additional control of the RX_AACK mode is done with register 0x17 (XAH_CTRL_1) and register 0x2E (CSMA_SEED_1). As long as a short address has not been set, only broadcast frames and frames matching the IEEE address can be received. Configuration examples for different device operating modes and handling of various frame types can be found in Section 7.2.3.1. TX_ARET configuration steps: Leave register bit TX_AUTO_CRC_ON = 1 register 0x04, TRX_CTRL_1 Configure CSMA-CA o MAX_FRAME_RETRIES register 0x2C, XAH_CTRL_0 o MAX_CSMA_RETRIES register 0x2C, XAH_CTRL_0 o CSMA_SEED registers 0x2D, 0x2E o MAX_BE, MIN_BE register 0x2F, CSMA_BE Configure CCA (see Section 8.5) MAX_FRAME_RETRIES (register 0x2C, XAH_CTRL_0) defines the maximum number of frame retransmissions. The register bits MAX_CSMA_RETRIES (register 0x2C, XAH_CTRL_0) configure the number of CSMA-CA retries after a busy channel is detected. The register bits CSMA_SEED (registers 0x2D, 0x2E) define a random seed for the back-off-time random-number generator in the Atmel AT86RF232. The register bits MAX_BE and MIN_BE (register 0x2F, CSMA_BE) set the maximum and minimum CSMA back-off exponent (see [1]), respectively. 46 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 7.2.3 RX_AACK_ON – Receive with Automatic ACK The general functionality of the RX_AACK procedure is shown in Figure 7-11. The gray shaded area is the standard flow of an RX_AACK transaction for IEEE 802.15.4 compliant frames, refer to Section 7.2.3.2. All other procedures are exceptions for specific operating modes or frame formats, refer to Section 7.2.3.3. The frame filtering operation is described in detail in Section 7.2.3.4. In RX_AACK_ON state, the radio transceiver listens for incoming frames. After detecting a valid PHR, the radio transceiver parses the frame content of the MAC header (MHR), refer to Section 8.1.2. If the content of the MAC addressing fields of the received frame (refer to IEEE 802.15.4 Section 7.2.1) matches one of the configured addresses, dependent on the addressing mode, an address match interrupt IRQ_5 (AMI) is issued, refer to Section 7.2.3.4. The expected address values are to be stored in registers 0x20 – 0x2B (Short address, PAN-ID and IEEE address). Frame filtering as described in Section 7.2.3.4 is also applied in Basic Operating Mode. However, in Basic Operating Mode, the result of frame filtering or FCS check do not affect the generation of an interrupt IRQ_3 (TRX_END). By default, only frames that match the address filter and have a valid FCS generate an interrupt IRQ_3 (TRX_END). An exception applies if promiscuous mode is enabled; see Section 7.2.3.2, in that case an IRQ_3 (TRX_END) interrupt is issued, even if the FCS fails. During reception the Atmel AT86RF232 parses bit[5] (ACK Request) of the frame control field of the received data or MAC command frame to check if an ACK reply is expected. In that case and if the frame passes the third level of filtering, see IEEE 802.15.4-2006, Section 7.5.6.2, the radio transceiver automatically generates and transmits an ACK frame. The sequence number is copied from the received frame. The content of the frame pending subfield of the ACK response is set by register bit AACK_SET_PD (register 0x2E, CSMA_SEED_1) when the ACK frame is sent in response to a data request MAC command frame, otherwise this subfield is set to zero. Optionally, the start of the transmission of the acknowledgement frame can be influenced by register bit AACK_ACK_TIME. Default value (according to standard IEEE 802.15.4) is 12 symbol periods after the reception of the last symbol of a data or MAC command frame. If the register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1) is set, no acknowledgement frame is sent even if an acknowledgment frame was requested. This is useful for operating the MAC hardware accelerator in promiscuous mode, see Section 7.2.3.2. The status of the RX_AACK operation is indicated by register bits TRAC_STATUS (register 0x02, TRAC_STATUS), see Section 7.2.7. During the operations described above, the AT86RF232 remains in BUSY_RX_AACK state. 47 8321A–MCU Wireless–10/11 Figure 7-11. Flow Diagram of RX_AACK. TRX_STATE = RX_AACK_ON N SHR detected Y TRX_STATE = BUSY_RX_AACK Generate IRQ_2 (RX_START) Scanning MHR (see Note 1) Y Reserved Frames N Frame Filtering Note 1: Frame Filtering, Promiscuous Mode and Reserved Frames: - A radio transceiver in Promiscuous Mode, or configured to receive Reserved Frames handles received frames passing the third level of filtering - For details refer to the description of Promiscuous Mode and Reserved Frame Types Promiscuous Mode Frame reception Generate IRQ_5 (AMI) AACK_PROM_MODE == 1 Frame reception N Y N FCS valid N (see Note 2) Note 2: FCS check is omitted for Promiscous Mode Y Y Generate IRQ_3 (TRX_END) N N FCF[2:0] >3 ACK requested AACK_UPLD_RES_FT == 1 (see Note 3) Note 3: Additional conditions: - ACK requested & - AACK_DIS_ACK==0 & - frame_version<=AACK_FVN_MODE Y Y N N Slotted Operation == 0 Y Y AACK_ACK_TIME == 0 FCS valid Generate IRQ_3 (TRX_END) N Generate IRQ_3 (TRX_END) Y Wait 2 symbol periods pin 11 (SLP_TR) rising edge Wait 12 symbol periods Wait 2 symbol periods N Y Transmit ACK TRX_STATE = RX_AACK_ON 48 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 7.2.3.1 Description of RX_AACK Configuration Bits Overview Table 7-5 summarizes all register bits which affect the behavior of an RX_AACK transaction. For address filtering it is further required to setup address registers to match the expected address. Configuration and address bits are to be set in TRX_OFF or PLL_ON state prior to switching to RX_AACK mode. A graphical representation of various operating modes is illustrated in Figure 7-11. Table 7-5. Overview of RX_AACK Configuration Bits. Register Address Register Bits 0x20,0x21 0x22,0x23 0x24 … 0x2B Register Name Description SHORT_ADDR_0/1 PAN_ADDR_0/1 IEEE_ADDR_0 … IEEE_ADDR_7 Set node addresses. 0x0C 7 RX_SAFE_MODE Protect buffer after frame reception. 0x17 1 AACK_PROM_MODE Support promiscuous mode. 0x17 2 AACK_ACK_TIME Change auto acknowledge start time. 0x17 4 AACK_UPLD_RES_FT Enable reserved frame type reception, needed to receive non-standard compliant frames. 0x17 5 AACK_FLTR_RES_FT Filter reserved frame types like data frame type, needed for filtering of non-standard compliant frames. 0x2C 0 SLOTTED_OPERATION If set, acknowledgment transmission has to be triggered by pin 11 (SLP_TR) 0x2E 3 AACK_I_AM_COORD If set, the device is a PAN coordinator, that is responds to a null address. 0x2E 4 AACK_DIS_ACK Disable generation of acknowledgment. 0x2E 5 AACK_SET_PD Set frame pending subfield in Frame Control Field (FCF), refer to Section 8.1.2.2. 0x2E 7:6 AACK_FVN_MODE Controls the ACK behavior, depending on FCF frame version number. The usage of the RX_AACK configuration bits for various operating modes of a node is explained in the following sections. Configuration bits not mentioned in the following two sections should be set to their reset values according to Table 14-2. All registers mentioned in Table 7-5 are described in Section 7.2.6. The general behavior of the “Atmel AT86RF232 Extended Feature Set”, Chapter 11, settings: o ANT_DIV (Antenna Diversity) o RX_PDT_LEVEL (blocking frame reception of lower power signals) are completely independent from RX_AACK mode and can be arbitrarily combined. 49 8321A–MCU Wireless–10/11 7.2.3.2 Configuration of IEEE Scenarios Normal Device Table 7-6 shows a typical Atmel AT86RF232 RX_AACK configuration of an IEEE 802.15.4 device operating as a normal device, rather than a PAN coordinator or router. Table 7-6. Configuration of IEEE 802.15.4 Devices. Register Address Register Bits 0x20,0x21 0x22,0x23 0x24 … 0x2B Register Name Description SHORT_ADDR_0/1 PAN_ADDR_0/1 IEEE_ADDR_0 … IEEE_ADDR_7 Set node addresses. 0x0C 7 RX_SAFE_MODE 0: Disable frame protection. 1: Enable frame protection. 0x2C 0 SLOTTED_OPERATION 0: Slotted acknowledgment transmissions are not to be used. 1: Slotted acknowledgment transmissions are to be used. 0x2E 7:6 AACK_FVN_MODE Controls the ACK behavior, depending on FCF frame version number. 0x00: Acknowledges only frames with version number 0, that is according to IEEE 802.15.4-2003 frames. 0x01: Acknowledges only frames with version number 0 or 1, that is frames according to IEEE 802.15.4-2006. 0x10: Acknowledges only frames with version number 0 or 1 or 2. 0x11: Acknowledges all frames, independent of the FCF frame version number. Notes: 1. If no short address has been configured, only frames directed to either the broadcast address or the IEEE address are received. 2. In IEEE 802.15.4-2003 standard the frame version subfield did not yet exist but was marked as reserved. According to this standard, reserved fields have to be set to zero. On the other hand, IEEE 802.15.4-2003 standard requires ignoring reserved bits upon reception. Thus, there is a contradiction in the standard which can be interpreted in two ways: a. If a network should only allow access to nodes which use the IEEE 802.15.4-2003, then AACK_FVN_MODE should be set to zero. b. If a device should acknowledge all frames independent of its frame version, AACK_FVN_MODE should be set to three. However, this can result in conflicts with co-existing IEEE 802.15.4-2006 standard compliant networks. The same holds for PAN coordinators, see below. 50 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 PAN-Coordinator Table 7-7 shows the Atmel AT86RF232 RX_AACK configuration for a PAN coordinator. Table 7-7. Configuration of a PAN Coordinator. Register Address Register Bits 0x20,0x21 0x22,0x23 0x24 … 0x2B Register Name Description SHORT_ADDR_0/1 PAN_ADDR_0/1 IEEE_ADDR_0 … IEEE_ADDR_7 Set node addresses. 0x0C 7 RX_SAFE_MODE 0: Disable frame protection. 1: Enable frame protection. 0x2C 0 SLOTTED_OPERATION 0: Slotted acknowledgment transmissions are not to be used. 1: Slotted acknowledgment transmissions are to be used. 0x2E 3 AACK_I_AM_COORD 1: Device is PAN coordinator. 0x2E 5 AACK_SET_PD 0: Frame pending subfield is not set in FCF. 1: Frame pending subfield is set in FCF. 0x2E 7:6 AACK_FVN_MODE Controls the ACK behavior, depends on FCF frame version number. 0x00: Acknowledges only frames with version number 0, that is according to IEEE 802.15.4-2003 frames. 0x01: Acknowledges only frames with version number 0 or 1, that is frames according to IEEE 802.15.4-2006. 0x10: Acknowledges only frames with version number 0 or 1 or 2. 0x11: Acknowledges all frames, independent of the FCF frame version number. Promiscuous Mode The promiscuous mode is described in IEEE 802.15.4-2006, Section 7.5.6.5. This mode is further illustrated in Figure 7-11. According to IEEE 802.15.4-2006 when in promiscuous mode, the MAC sub layer shall pass received frames with correct FCS to the next higher layer and shall not process them further. That implies that frames should never be acknowledged. Only second level filter rules as defined by IEEE 802.15.4-2006, Section 7.5.6.2, are applied to the received frame. 51 8321A–MCU Wireless–10/11 Table 7-8 shows the typical configuration of a device operating promiscuous mode. Table 7-8. Configuration of Promiscuous Mode. Register Address Register Bits 0x20,0x21 0x22,0x23 0x24 … 0x2B Register Name Description SHORT_ADDR_0/1 PAN_ADDR_0/1 IEEE_ADDR_0 … IEEE_ADDR_7 Each address shall be set: 0x00. 0x17 1 AACK_PROM_MODE 1: Enable promiscuous mode. 0x2E 4 AACK_DIS_ACK 1: Disable generation of acknowledgment. 0x2E 7:6 AACK_FVN_MODE Controls the ACK behavior, depends on FCF frame version number. 0x00: Acknowledges only frames with version number 0, that is according to IEEE 802.15.4-2003 frames. 0x01: Acknowledges only frames with version number 0 or 1, that is frames according to IEEE 802.15.4-2006. 0x10: Acknowledges only frames with version number 0 or 1 or 2. 0x11: Acknowledges all frames, independent of the FCF frame version number. If the Atmel AT86RF232 radio transceiver is in promiscuous mode, second level of filtering according to IEEE 802.15.4-2006, Section 7.5.6.2, is applied to a received frame. However, an IRQ_3 (TRX_END) is issued even if the FCS is invalid. Thus, it is necessary to read register bit RX_CRC_VALID (register 0x06, PHY_RSSI) after IRQ_3 (TRX_END) in order to verify the reception of a frame with a valid FCS. If a device, operating in promiscuous mode, receives a frame with a valid FCS which further passed the third level of filtering according to IEEE 802.15.4-2006, Section 7.5.6.2, an acknowledgement frame would be transmitted. According to the definition of the promiscuous mode a received frame shall not be acknowledged, even if it is requested. Thus register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1) has to be set to one. In all receive modes an IRQ_5 (AMI) interrupt is issued, when the received frame matches the node’s address according to the filter rules described in Section 7.2.3.4. Alternatively, in Basic Operating Mode RX_ON state, when a valid PHR is detected, an IRQ_2 (RX_START) is generated and the frame is received. The end of the frame reception is signalized with an IRQ_3 (TRX_END). At the same time the register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is updated with the result of the FCS check (see Section 8.2). According to the promiscuous mode definition the register bit RX_CRC_VALID needs to be checked in order to dismiss corrupted frames. 52 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 7.2.3.3 Configuration of non IEEE 802.15.4 Compliant Scenarios Sniffer Table 7-9 shows an Atmel AT86RF232 RX_AACK configuration to setup a sniffer device. Other RX_AACK configuration bits, refer to Table 7-5, should be set to their reset values. All frames received are indicated by an IRQ_2 (RX_START) and IRQ_3 (TRX_END). After frame reception register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is updated with the result of the FCS check (see Section 8.2). The RX_CRC_VALID bit needs to be checked in order to dismiss corrupted frames. Table 7-9. Configuration of a Sniffer Device. Register Address Register Bits Register Name Description 0x17 1 AACK_PROM_MODE 1: Enable promiscuous mode. 0x2E 4 AACK_DIS_ACK 1: Disable generation of acknowledgment. This operating mode is similar to the promiscuous mode. Reception of Reserved Frames In RX_AACK mode, frames with reserved frame types, refer to Section 8.1.2.2, can also be handled. This might be required when implementing proprietary, non-standard compliant, protocols. It is an extension of the address filtering in RX_AACK mode. Received frames are either handled similar to data frames, or may be allowed to completely bypass the address filter. Table 7-10 shows the required configuration for a node to receive reserved frames, Figure 7-11 shows the corresponding flow chart. Table 7-10. RX_AACK Configuration to Receive Reserved Frame Types. Register Address Register Bits 0x20,0x21 0x22,0x23 0x24 … 0x2B Register Name Description SHORT_ADDR_0/1 PAN_ADDR_0/1 IEEE_ADDR_0 … IEEE_ADDR_7 Set node addresses. 0x0C 7 RX_SAFE_MODE 0: Disable frame protection. 1: Enable frame protection. 0x17 4 AACK_UPLD_RES_FT 1: Enable reserved frame type reception. 0x17 5 AACK_FLTR_RES_FT Filter reserved frame types like data frame type, see note below. 0: Disable reserved frame types filtering. 1: Enable reserved frame types filtering. 0x2C 0 SLOTTED_OPERATION 0: Slotted acknowledgment transmissions are not to be used. 1: Slotted acknowledgment transmissions are to be used. 53 8321A–MCU Wireless–10/11 Register Address Register Bits Register Name Description 0x2E 3 AACK_I_AM_COORD 0: Device is not PAN coordinator. 1: Device is PAN coordinator. 0x2E 4 AACK_DIS_ACK 0: Enable generation of acknowledgment. 1: Disable generation of acknowledgment. 0x2E 7:6 AACK_FVN_MODE Controls the ACK behavior, depends on FCF frame version number. 0x00: Acknowledges only frames with version number 0, that is according to IEEE 802.15.4-2003 frames. 0x01: Acknowledges only frames with version number 0 or 1, that is frames according to IEEE 802.15.4-2006. 0x10: Acknowledges only frames with version number 0 or 1 or 2. 0x11: Acknowledges all frames, independent of the FCF frame version number. There are three different options for handling reserved frame types. 1. AACK_UPLD_RES_FT = 1, AACK_FLT_RES_FT = 0: Any non-corrupted frame with a reserved frame type is indicated by an IRQ_3 (TRX_END) interrupt. No further address filtering is applied on those frames. An IRQ_5 (AMI) interrupt is never generated and the acknowledgment subfield is ignored. 2. AACK_UPLD_RES_FT = 1, AACK_FLT_RES_FT = 1: If AACK_FLT_RES_FT = 1 any frame with a reserved frame type is filtered by the address filter similar to a data frame as described in the standard. This implies the generation of the IRQ_5 (AMI) interrupts upon address match. An IRQ_3 (TRX_END) interrupt is only generated if the address matched and the frame was not corrupted. An acknowledgment is only send, when the ACK request subfield was set in the received frame and an IRQ_3 (TRX_END) interrupt occurred. 3. AACK_UPLD_RES_FT = 0: Any received frame with a reserved frame type is discarded. 54 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Short Acknowledgment Frame (ACK) Start Timing Register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1), see Table 7-11, defines the symbol time between frame reception and transmission of an acknowledgment frame. Table 7-11. Overview of RX_AACK Configuration Bits. Register Address Register Bit 0x17 2 Register Name Description AACK_ACK_TIME 0: Standard compliant acknowledgement timing of 12 symbol periods. In slotted acknowledgement operation mode, the acknowledgment frame transmission can be triggered two symbol periods after reception of the frame earliest. 1: Reduced acknowledgment timing of two symbol periods (32µs). This feature can be used in all scenarios, independent of other configurations. 7.2.3.4 Frame Filtering Frame Filtering is an evaluation whether or not a received frame is addressed to this node. To accept a received frame and to generate an address match interrupt IRQ_5 (AMI) a filtering procedure as described in IEEE 802.15.4-2006 Section 7.5.6.2. (Third level of filtering) is applied to the frame. The Atmel AT86RF232 RX_AACK mode accepts only frames that satisfy all of the following requirements (quote from IEEE 802.15.4-2006, Section 7.5.6.2): 1. The Frame Type subfield shall not contain a reserved frame type. 2. The Frame Version subfield shall not contain a reserved value. 3. If a destination PAN identifier is included in the frame, it shall match macPANId or shall be the broadcast PAN identifier (0xFFFF). 4. If a short destination address is included in the frame, it shall match either macShortAddress or the broadcast address (0xFFFF). Otherwise, if an extended destination address is included in the frame, it shall match aExtendedAddress. 5. If the frame type indicates that the frame is a beacon frame, the source PAN identifier shall match macPANId unless macPANId is equal to 0xFFFF, in which case the beacon frame shall be accepted regardless of the source PAN identifier. 6. If only source addressing fields are included in a data or MAC command frame, the frame shall be accepted only if the device is the PAN coordinator and the source PAN identifier matches macPANId. The AT86RF232 requires satisfying two additional rules: 7. The frame type indicates that the frame is not an ACK frame (refer to Table 8-4). 8. At least one address field must be present. Address match, indicated by interrupt IRQ_5 (AMI), is further controlled by the content of subfields of the frame control field of a received frame according to the following rule: If (Destination Addressing Mode = 0 OR 1) AND (Source Addressing Mode = 0) no IRQ_5 (AMI) is generated, refer to Section 8.1.2.2. This effectively causes all 55 8321A–MCU Wireless–10/11 acknowledgement frames not to be announced, which would otherwise always pass the filter, regardless of whether they are intended for this device or not. For backward compatibility to IEEE 802.15.4-2003 third level filter rule two (Frame Version) can be disabled by register bits AACK_FVN_MODE (register 0x2E, CSMA_SEED_1). Frame filtering is available in Extended and Basic Operating Mode, refer to Section 7.1, a frame passing the frame filtering generates an IRQ_5 (AMI), if enabled. Notes: 1. Filter rule one is affected by register bits AACK_FLTR_RES_FT and AACK_UPLD_RES_FT, Section 7.2.7. 2. Filter rule two is affected by register bits AACK_FVN_MODE, Section 7.2.7. 7.2.3.5 RX_AACK Slotted Operation – Slotted Acknowledgement Atmel AT86RF232 supports slotted acknowledgement operation, refer IEEE 802.15.4-2006, Section 7.5.6.4.2, in conjunction with the microcontroller. to In RX_AACK mode with register bit SLOTTED_OPERATION (register 0x2C, XAH_CTRL_0) set, the transmission of an acknowledgement frame has to be controlled by the microcontroller. If an ACK frame has to be transmitted, the radio transceiver expects a rising edge on pin 11 (SLP_TR) to actually start the transmission. This waiting state is signaled two symbol periods after the reception of the last symbol of a data or MAC command frame by register bits TRAC_STATUS (register 0x02, XAH_CTRL_0), which are set to SUCCESS_WAIT_FOR_ACK in that case. In networks using slotted operation the start of the acknowledgment frame, and thus the exact timing, must be provided by the microcontroller. A timing example of an RX_AACK transaction with register bit SLOTTED_OPERATION (register 0x2C, XAH_CTRL_0) set is shown in Figure 7-12. The acknowledgement frame is ready to be transmitted two symbol times after the reception of the last symbol of a data or MAC command frame. The transmission of the acknowledgement frame is initiated by the microcontroller with the rising edge of pin 11 (SLP_TR) and starts tTR10 = 16µs later. The interrupt latency tIRQ is specified in Section 12.4. Figure 7-12. Example Timing of an RX_AACK Transaction for Slotted Operation. 64 Frame Type 512 SFD TRX_STATE Data Frame (Length = 10, ACK=1) BUSY_RX_AACK tIRQ ACK transmission initated by microcontroller 32 μs (2 symbols) SLP_TR waiting period signalled by register bits TRAC_STATUS SLP_TR RX RX/TX TX TX TRX_END Typ. Processing Delay time [μs] RX_AACK_ON RX IRQ 1026 ACK Frame RX_AACK_ON RX/TX 704 Frame on Air 0 tTR10 56 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 7.2.3.6 RX_AACK Mode Timing A timing example of an RX_AACK transaction is shown in Figure 7-13. In this example a data frame of length 10 with an ACK request is received. The Atmel AT86RF232 changes to state BUSY_RX_AACK after SFD detection. The completion of the frame reception is indicated by an IRQ_3 (TRX_END) interrupt. Interrupts IRQ_2 (RX_START) and IRQ_5 (AMI) are disabled in this example. The ACK frame is automatically transmitted after a default wait period of 12 symbols (192µs), register bit AACK_ACK_TIME = 0 (reset value). The interrupt latency tIRQ is specified in Section 12.4. Figure 7-13. Example Timing of an RX_AACK Transaction. Frame Type TRX_STATE 512 SFD Data Frame (Length = 10, ACK=1) 1088 time [µs] ACK Frame RX_AACK_ON RX/TX 704 Frame on Air 64 BUSY_RX_AACK RX RX_AACK_ON TX IRQ TRX_END RX RX/TX 0 tIRQ Typ. Processing Delay 192 µs (12 symbols) Note: 1. If register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1) is set, an acknowledgment frame is sent already two symbol times after the reception of the last symbol of a data or MAC command frame. 57 8321A–MCU Wireless–10/11 7.2.4 TX_ARET_ON – Transmit with Automatic Frame Retransmission and CSMA-CA Retry Figure 7-14. Flow Diagram of TX_ARET. TRX_STATE = TX_ARET_ON frame_rctr = 0 N Start TX Y TRX_STATE = BUSY_TX_ARET TRAC_STATUS = INVALID (see Note 1) N Note 1: If MAX_CSMA_RETRIES = 7 no retry is performed MAX_CSMA_RETRIES <7 Y csma_rctr = 0 Random Back-Off csma_rctr = csma_rctr + 1 CCA N CCA Result Failure csma_rctr > MAX_CSMA_RETRIES Y Success Transmit Frame frame_rctr = frame_rctr + 1 ACK requested N Y N Receive ACK until timeout Y ACK valid Y N N frame_rctr > MAX_FRAME_RETRIES Y TRAC_STATUS = NO_ACK Data Pending N Y TRAC_STATUS = SUCCESS_DATA_PENDING TRAC_STATUS = SUCCESS TRAC_STATUS = CHANNEL_ACCESS_FAILURE Issue IRQ_3 (TRX_END) interrupt TRX_STATE = TX_ARET_ON 58 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Overview The implemented TX_ARET algorithm is shown in Figure 7-14. In TX_ARET mode, the Atmel AT86RF232 first executes the CSMA-CA algorithm, as defined by IEEE 802.15.4–2006, Section 7.5.1.4, initiated by a transmit start event. If the channel is IDLE a frame is transmitted from the Frame Buffer. If the acknowledgement frame is requested the radio transceiver additionally checks for an ACK reply. The completion of the TX_ARET IRQ_3 (TRX_END) interrupt. transmit transaction is indicated by an Description Configuration and address bits are to be set in TRX_OFF or PLL_ON state prior to switching to TX_ARET mode. It is further recommended to transfer the PSDU data to the Frame Buffer in advance. The transaction is started by either using pin 11 (SLP_TR), refer to Section 6.5, or writing a TX_START command to register bits TRX_CMD (register 0x02, TRX_STATE). If the CSMA-CA detects a busy channel, it is retried as specified by the register bits MAX_CSMA_RETRIES (register 0x2C, XAH_CTRL_0). In case that CSMA-CA does not detect a clear channel after MAX_CSMA_RETRIES, it aborts the TX_ARET transaction, issues interrupt IRQ_3 (TRX_END), and set the value of the register bits TRAC_STATUS to CHANNEL_ACCESS_FAILURE. During transmission of a frame the radio transceiver parses bit 5 (ACK Request) of the MAC header (MHR) frame control field of the PSDU data (PSDU octet #1) to be transmitted to check if an ACK reply is expected. If an ACK is expected, the radio transceiver automatically switches into receive mode to wait for a valid ACK reply. After receiving an ACK frame the Frame Pending subfield of that frame is parsed and the status register bits TRAC_STATUS are updated accordingly, refer to Table 7-12. This receive procedure does not overwrite the Frame Buffer content. Transmit data in the Frame Buffer is not changed during the entire TX_ARET transaction. Received frames other than the expected ACK frame are discarded. If no valid ACK is received or after timeout of 54 symbol periods (864µs), the radio transceiver retries the entire transaction, (including CSMA-CA) until the maximum number of retransmissions (as set by the register bits MAX_FRAME_RETRIES (register 0x2C, XAH_CTRL_0)) is exceeded. The current CSMA-CA and frame retransmission counter values of an ongoing TX_ARET transaction can be retrieved by the register bits ARET_FRAME_RETRIES and ARET_CSMA_RETRIES (register 0x19, XAH_CTRL_2). Additionally to the RX Frame Time stamping via pin 10 (DIG2), a TX Frame Time stamping within TX_ARET mode can be activated, if the register bits IRQ_2_EXT_EN (register 0x04, TRX_CTRL_1) and ARET_TX_TS_EN (register 0x17, XAH_CTRL_1) are set to one, see Section 11.4. After that, the microcontroller may read the value of the register bits TRAC_STATUS (register 0x02, TRX_STATE) to verify whether the transaction was successful or not. The register bits are set according to the following cases, additional exit codes are described in Section 7.2.6: 59 8321A–MCU Wireless–10/11 Table 7-12. Interpretation of TRAC_STATUS Register Bits. Value Name Description 0 SUCCESS The transaction was responded by a valid ACK, or, if no ACK is requested, after a successful frame transmission. 1 SUCCESS_DATA_PENDING Equivalent to SUCCESS, indicates pending frame data according to the MHR frame control field of the received ACK response. 3 CHANNEL_ACCESS_FAILURE Channel is still busy after MAX_CSMA_RETRIES of CSMA-CA. 5 NO_ACK No acknowledgement frames were received during all retry attempts. 7 INVALID Transaction not yet finished. If no ACK is expected (according to the content of the received frame in the Frame Buffer), the radio transceiver issues IRQ_3 (TRX_END) directly after the frame transmission has been completed. The value of register bits TRAC_STATUS (register 0x02, TRX_STATE) is set to SUCCESS. A value of MAX_CSMA_RETRIES = 7 initiates an immediate TX_ARET transaction without performing CSMA-CA. This can be used for example to transmit indirect data to a device. Further the value MAX_FRAME_RETRIES is ignored and the TX_ARET transaction is performed only once. A timing example of a TX_ARET transaction is shown in Figure 7-15. Figure 7-15. Example Timing of a TX_ARET Transaction. 128 FrameType TRX_STATE 672 x Data Frame (Length = 10, ACK=1) TX_ARET_ON RX/TX ACK Frame BUSY_TX_ARET TX_ARET_ON RX TX RX/TX CSMA-CA time [µs] x+352 Frame on Air 0 SLP_TR IRQ TRX_END Typ. Processing Delay tCSMA-CA tTR10 Notes: tTR11 1. tCSMA-CA defines the random CSMA-CA backoff time. 2. Timing figure tTR10 and tTR11 refer to Table 7-1. tIRQ Here an example data frame of length 10 with an ACK request is transmitted. After that the Atmel AT86RF232 switches to receive mode and expects an acknowledgement response. During the whole transaction including frame transmit, wait for ACK and ACK receive the radio transceiver status register bits TRX_STATUS (register 0x01, TRX_STATUS) signals BUSY_TX_ARET. A successful reception IRQ_3 (TRX_END). The 60 of the acknowledgment frame is status register bits TRX_STATUS indicated by (register 0x01, AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 TRX_STATUS) changes back to TX_ARET_ON. The register bits TRAC_STATUS (register 0x02, TRX_STATE) change to either TRAC_STATUS = SUCCESS, or TRAC_STATUS = SUCCESS_DATA_PENDING if the frame pending subfield of the received ACK frame was set to one. 7.2.5 Interrupt Handling The Atmel AT86RF232 interrupt handling in the Extended Operating Mode is similar to the Basic Operating Mode, refer to Section 7.1.3. The microcontroller enables interrupts by setting the appropriate bit in register 0x0E (IRQ_MASK). For RX_AACK and TX_ARET modes the following interrupts inform about the status of a frame reception and transmission: Table 7-13. Interrupt Handling in Extended Operating Mode. Mode Interrupt Description RX_AACK IRQ_2 (RX_START) Indicates a PHR reception IRQ_5 (AMI) Issued at address match IRQ_3 (TRX_END) Signals completion of RX_AACK transaction if successful - A received frame must pass the address filter - The FCS is valid TX_ARET IRQ_3 (TRX_END) Signals completion of TX_ARET transaction Both IRQ_0 (PLL_LOCK) Entering RX_AACK_ON or TX_ARET_ON state from TRX_OFF state, the PLL_LOCK interrupt signals that the transaction can be started RX_AACK For RX_AACK mode, it is recommended to enable IRQ_3 (TRX_END). This interrupt is issued only if a frame passes the frame filtering, refer to Section 7.2.3.4, and has a valid FCS. This is in contrast to Basic Operating Mode, refer to Section 7.1.3. The use of the other interrupts is optional. On reception of a valid PHR an IRQ_2 (RX_START) is issued. IRQ_5 (AMI) indicates address match, refer to filter rules in Section 7.2.3.4, and the completion of a frame reception with a valid FCS is indicated by interrupt IRQ_3 (TRX_END). Thus, it can happen that an IRQ_2 (RX_START) and/or IRQ_5 (AMI) are issued, but no IRQ_3 (TRX_END) interrupt. TX_ARET In TX_ARET mode, interrupt IRQ_3 (TRX_END) is only issued after completing the entire TX_ARET transaction. Reception of acknowledgement IRQ_3 (TRX_END) interrupts. frames does not issue IRQ_5 (AMI) or All other interrupts as described in Section 6.6, are also available in Extended Operating Mode. 61 8321A–MCU Wireless–10/11 7.2.6 Register Summary The following Atmel AT86RF232 registers are to be configured to control the Extended Operating Mode: Table 7-14. Register Summary. Reg.-Addr. Register Name Description 0x01 TRX_STATUS Radio transceiver status, CCA result 0x02 TRX_STATE Radio transceiver state control, TX_ARET status 0x04 TRX_CTRL_1 TX_AUTO_CRC_ON 0x08 PHY_CC_CCA CCA mode control, see Section 8.5.6 0x09 CCA_THRES CCA threshold settings, see Section 8.5.6 0x17 XAH_CTRL_1 TX_ARET and RX_AACK control 0x19 XAH_CTRL_2 TX_ARET control 0x20 – 0x2B Address filter configuration - Short address, PAN-ID and IEEE address 0x2C XAH_CTRL_0 TX_ARET control, retries value control 0x2D CSMA_SEED_0 CSMA-CA seed value 0x2E CSMA_SEED_1 CSMA-CA seed value, RX_AACK control 0x2F CSMA_BE CSMA-CA back-off exponent control 7.2.7 Register Description – Control Registers Register 0x01 (TRX_STATUS): The read-only register TRX_STATUS signals the present state of the radio transceiver as well as the status of a CCA operation. Figure 7-16. Register TRX_STATUS. Bit 7 6 5 4 CCA_DONE CCA_STATUS reserved TRX_STATUS Read/Write Reset value R 0 R 0 R 0 R 0 Bit 3 2 1 0 R 0 R 0 0x01 0x01 Read/Write Reset value TRX_STATUS R 0 R 0 TRX_STATUS TRX_STATUS Bit 4:0 - TRX_STATUS The register bits TRX_STATUS signals the current radio transceiver status. Table 7-15. TRX_STATUS. 62 Register Bits Value Description TRX_STATUS 0x00 P_ON 0x01 BUSY_RX 0x02 BUSY_TX 0x06 RX_ON 0x08 TRX_OFF (CLK Mode) AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Register Bits Value Description 0x09 PLL_ON (TX_ON) (1) SLEEP 0x11 (2) BUSY_RX_AACK 0x12 (2) BUSY_TX_ARET 0x16 (2) RX_AACK_ON 0x19 (2) TX_ARET_ON (3) STATE_TRANSITION_IN_PROGRESS 0x0F 0x1F All other values are reserved Notes: 1. In SLEEP state register not accessible. 2. Extended Operating Mode only. 3. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state. A read access to TRX_STATUS register signals the current radio transceiver state. A state change is initiated by writing a state transition command to register bits TRX_CMD (register 0x02, TRX_STATE). Alternatively, some state transitions can be initiated by the rising edge of pin 11 (SLP_TR) in the appropriate state. Register 0x02 (TRX_STATE): The radio transceiver states are controlled via register TRX_STATE using register bits TRX_CMD. The read-only register bits TRAC_STATUS indicate the status or result of an Extended Operating Mode transaction. Figure 7-17. Register TRX_STATE. Bit 7 0x02 6 Read/Write Reset value R 0 R 0 Bit 3 2 0x02 Read/Write Reset value 5 TRAC_STATUS 4 TRX_CMD R 0 R/W 0 1 0 R/W 0 R/W 0 TRX_CMD R/W 0 R/W 0 TRX_STATE TRX_STATE 63 8321A–MCU Wireless–10/11 Bit 7:5 – TRAC_STATUS Table 7-16. TRAC_STATUS. Register Bits Value TRAC_STATUS Description RX_AACK TX_ARET X X (1) SUCCESS 1 SUCCESS_DATA_PENDING 2 SUCCESS_WAIT_FOR_ACK 3 CHANNEL_ACCESS_FAILURE X 5 NO_ACK X (1) INVALID 0 7 X X X X All other values are reserved Note: 1. Even though the reset value for register bits TRAC_STATUS is zero, the RX_AACK and TX_ARET procedures set the register bits to TRAC_STATUS = 7 (INVALID) when they are started. The status of the RX_AACK and TX_ARET procedure is indicated by register bits TRAC_STATUS. Details of the algorithm and a description of the status information are given in Section 7.2.3 and Section 7.2.4. RX_AACK SUCCESS_WAIT_FOR_ACK: Indicates an ACK frame is about to be sent in RX_AACK slotted acknowledgement. Slotted acknowledgement operation must be enabled with register bit SLOTTED_OPERATION (register 0x2C, XAH_XTRL_0). The microcontroller must pulse pin 11 (SLP_TR) at the next back-off slot boundary in order to initiate a transmission of the ACK frame. For details refer to IEEE 802.15.4-2006, Section 7.5.6.4.2. TX_ARET SUCCESS_DATA_PENDING: Indicates a successful reception of an ACK frame with frame pending bit set to one. 64 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Bit 4:0 - TRX_CMD A write access to register bits TRX_CMD initiates a radio transceiver state transition. Table 7-17. TRX_CMD. Register Bits Value TRX_CMD Description 0x00 (1) NOP 0x02 (2) TX_START 0x03 0x04 FORCE_TRX_OFF (3) FORCE_PLL_ON 0x06 RX_ON 0x08 TRX_OFF (CLK Mode) 0x09 PLL_ON (TX_ON) 0x16 (4) RX_AACK_ON 0x19 (4) TX_ARET_ON All other values are reserved Notes: 1. TRX_CMD = “0” after power on reset (POR). 2. The frame transmission starts one symbol after TX_START command. 3. FORCE_PLL_ON is not valid for states P_ON, SLEEP, and RESET, as well as STATE_TRANSITION_IN_PROGRESS towards these states. 4. Extended Operating Mode only. A successful state transition shall be confirmed by reading register bits TRX_STATUS (register 0x01, TRX_STATUS). The register bits TRX_CMD are used for Basic and Extended Operating Modes, refer to Section 7.1. Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. Figure 7-18. Register TRX_CTRL_1. Bit 0x04 Read/Write Reset value Bit 0x04 Read/Write Reset value 7 6 5 4 reserved IRQ_2_EXT_EN TX_AUTO_CRC_ ON RX_BL_CTRL R/W 0 R/W 0 R/W 1 R/W 0 3 2 SPI_CMD_MODE R/W 0 R/W 0 1 0 IRQ_MASK_MODE IRQ_POLARITY R/W 1 R/W 0 TRX_CTRL_1 TRX_CTRL_1 65 8321A–MCU Wireless–10/11 Bit 5 - TX_AUTO_CRC_ON The register bit TX_AUTO_CRC_ON controls the automatic FCS generation for transmit operations. Table 7-18. TX_AUTO_CRC_ON. Register Bits Value TX_AUTO_CRC_ON Note: 1. Description 0 Automatic FCS generation is disabled 1 Automatic FCS generation is enabled The TX_AUTO_CRC_ON function can be used within Basic and Extended Operating Modes. For further details refer to Section 8.2. Register 0x17 (XAH_CTRL_1): The XAH_CTRL_1 register is a multi-purpose control register for Extended Operating Mode. Figure 7-19. Register XAH_CTRL_1. Bit 7 0x17 6 5 ARET_TX_TS_EN reserved R/W 0 R/W 0 3 Read/Write Reset value R/W 0 R/W 0 2 1 0 reserved AACK_ACK_TIME AACK_PROM_ MODE reserved R 0 R/W 0 R/W 0 R/W 0 Bit 0x17 4 AACK_FLTR_RES_ AACK_UPLD_RES_ FT FT Read/Write Reset value XAH_CTRL_1 XAH_CTRL_1 Bit 7 - ARET_TX_TS_EN If register bit ARET_TX_TS_EN = 1, then any frame transmission within TX_ARET mode is signaled via pin 10 (DIG2). Table 7-19. ARET_TX_TS_EN. Register Bits ARET_TX_TS_EN Value 0 TX_ARET time stamping via pin 10 (DIG2) is disabled (1) TX_ARET time stamping via pin 10 (DIG2) is enabled 1 Note: 66 1. Description It is necessary to set register bit IRQ_2_EXT_EN (register 0x04, TRX_CTRL_1). AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Bit 5 - AACK_FLTR_RES_FT Filter reserved frame types like data frame type. The register bit AACK_FLTR_RES_FT shall only be set if register bit AACK_UPLD_RES_FT = 1. Table 7-20. AACK_FLTR_RES_FT. Register Bits AACK_FLTR_RES_FT Value Description 0 (1) Filtering reserved frame types is disabled 1 (2) Filtering reserved frame types is enabled Notes: 1. If AACK_FLTR_RES_FT = 0 the received reserved frame is only checked for a valid FCS. 2. If AACK_FLTR_RES_FT = 1 reserved frame types are filtered similar to data frames as specified in IEEE 802.15.4-2006. Reserved frame types are explained in IEEE 802.15.4, Section 7.2.1.1.1. Bit 4 - AACK_UPLD_RES_FT Upload reserved frame types within RX_AACK mode. Table 7-21. AACK_UPLD_RES_FT. Register Bits AACK_UPLD_RES_FT Value 0 Upload of reserved frame types is disabled (1) Upload of reserved frame types is enabled 1 Note: 1. Description If AACK_UPLD_RES_FT = 1 received frames indicated as a reserved frame are further processed. For those frames, an IRQ_3 (TRX_END) interrupt is generated if the FCS is valid. In conjunction with the configuration bit AACK_FLTR_RES_FT, these frames are handled like IEEE 802.15.4 compliant data frames during RX_AACK transaction. An IRQ_5 (AMI) interrupt is issued, if the addresses in the received frame match the node’s addresses. That means, if a reserved frame passes the third level filter rules, an acknowledgement frame is generated and transmitted if it was requested by the received frame. If this is not wanted register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1) has to be set. Bit 2 - AACK_ACK_TIME The register bit AACK_ACK_TIME controls the acknowledgment frame response time within RX_AACK mode. Table 7-22. AACK_ACK_TIME. Register Bits AACK_ACK_TIME Value Description 0 Acknowledgment time is 12 symbols (aTurnaroundTime) 1 Acknowledgment time is two symbols According to IEEE 802.15.4, Section 7.5.6.4.2 the transmission of an acknowledgment frame shall commence 12 symbols (aTurnaroundTime) after the reception of the last symbol of a data or MAC command frame. This is achieved with the reset value of the register bit AACK_ACK_TIME. Alternatively, if AACK_ACK_TIME = 1 an acknowledgment frame is sent already two symbol periods after the reception of the last symbol of a data or MAC command frame. 67 8321A–MCU Wireless–10/11 Bit 1 - AACK_PROM_MODE The register bit AACK_PROM_MODE enables the promiscuous mode, within the RX_AACK mode. Table 7-23. AACK_PROM_MODE. Register Bits Value AACK_PROM_MODE Description 0 Promiscuous mode is disabled 1 Promiscuous mode is enabled Refer to IEEE 802.15.4-2006, Section 7.5.6.5. If this register bit is set, every incoming frame with a valid PHR finishes with IRQ_3 (TRX_END) interrupt even if the third level filter rules do not match or the FCS is not valid. Register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is set accordingly. In contrast to IEEE 802.15.4-2006, if a frame passes the third level filter rules, an acknowledgement frame is generated and transmitted unless disabled by register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1), or use Basic Operating Mode instead. Register 0x19 (XAH_CTRL_2): The read-only register XAH_CTRL_2 retrieves the current counter values for Extended Operating Mode. Figure 7-20. Register XAH_CTRL_2. Bit 7 6 0x19 5 4 ARET_FRAME_RETRIES Read/Write Reset value R 0 Bit 3 0x19 R 0 R 0 2 1 ARET_CSMA_RETRIES Read/Write Reset value R 0 R 0 XAH_CTRL_2 R 0 0 reserved R 0 XAH_CTRL_2 R 0 Bit 7:4 - ARET_FRAME_RETRIES Retrieves current frame retry counter value. Table 7-24. ARET_FRAME_RETRIES. Register Bits ARET_FRAME_RETRIE S Note: 68 1. Value Description 0x0 Minimum possible frame retry counter value 0xF Maximum possible frame retry counter value A new CCA_BACKOFF cycle or new frame transmit cycle changed these value. AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Bit 3:1 - ARET_CSMA_RETRIES Retrieves current CSMA-CA retry counter value. Table 7-25. ARET_CSMA_RETRIES. Register Bits Value ARET_CSMA_RETRIES Note: 1. Description 0 Minimum possible CSMA-CA retry counter value 5 Maximum possible CSMA-CA retry counter value A new CCA_BACKOFF cycle or new frame transmit cycle changed these value. Register 0x2C (XAH_CTRL_0): The XAH_CTRL_0 register is a control register for Extended Operating Mode. Figure 7-21. Register XAH_CTRL_0. Bit 7 6 R/W 0 R/W 0 R/W 1 3 2 1 0x2C Read/Write Reset value Bit 4 MAX_FRAME_RETRIES 0x2C Read/Write Reset value 5 R/W 0 0 SLOTTED_ OPERATION MAX_CSMA_RETRIES R/W 1 XAH_CTRL_0 R/W 1 R/W 0 XAH_CTRL_0 R/W 0 Bit 7:4 - MAX_FRAME_RETRIES Number of retransmission attempts in TX_ARET mode before the transaction gets cancelled. Table 7-26. MAX_FRAME_RETRIES. Register Bits MAX_FRAME_RETRIES Value 0x3 Description The setting of MAX_FRAME_RETRIES in TX_ARET mode specifies the number of attempts to retransmit a frame, when it was not acknowledged by the recipient, before the transaction gets cancelled. Valid values are [0x7, 0x6, …, 0x0]. 69 8321A–MCU Wireless–10/11 Bit 3:1 - MAX_CSMA_RETRIES Number of retries in TX_ARET mode to repeat the CSMA-CA procedure before the transaction gets cancelled. Table 7-27. MAX_CSMA_RETRIES. Register Bits MAX_CSMA_RETRIES Notes: 1. Value Description 0 (1) no retries 1 (1) One retry 2 (1) Two retries 3 (1) Three retries 4 (1) Four retries 5 (1) Five retries 7 (3) Immediate frame transmission without performing CSMACA MAX_CSMA_RETRIES specifies the number of retries in TX_ARET mode to repeat the CSMA-CA procedure before the transaction gets cancelled. According to IEEE 802.15.4 the valid range of MAX_CSMA_RETRIES is [5, 4, …, 0]. 2. MAX_CSMA_RETRIES = 6 is reserved. 3. A value of MAX_CSMA_RETRIES = 7 initiates an immediate frame transmission without performing CSMA-CA. Bit 0 - SLOTTED_OPERATION For RX_AACK mode, the register bit SLOTTED_OPERATION determines, if the transceiver will require a time base for slotted operation. Table 7-28. SLOTTED_OPERATION. Register Bits SLOTTED_OPERATION Value Description 0 The radio transceiver operates in unslotted mode. An acknowledgment frame is automatically sent if requested. 1 The transmission of an acknowledgement frame has to be controlled by the microcontroller. Using RX_AACK mode in networks operating in beacon or slotted mode, refer to IEEE 802.15.4-2006, Section 5.5.1, register bit SLOTTED_OPERATION indicates that acknowledgement frames are to be sent on back-off slot boundaries (slotted acknowledgement), refer to Section 7.2.3.5. If this register bit is set the acknowledgement frame transmission has to be initiated by the microcontroller using the rising edge of pin 11 (SLP_TR). This waiting state is signaled in register bits TRAC_STATUS (register 0x02, TRX_STATE) with value SUCCESS_WAIT_FOR_ACK. 70 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Register 0x2D (CSMA_SEED_0): The register CSMA_SEED_0 contains the lower 8-bit of CSMA_SEED. Figure 7-22. Register CSMA_SEED_0. Bit 7 6 R/W 1 R/W 1 3 2 0x2D 5 4 R/W 1 R/W 0 1 0 R/W 1 R/W 0 CSMA_SEED_0 Read/Write Reset value Bit 0x2D CSMA_SEED_0 CSMA_SEED_0 Read/Write Reset value R/W 1 R/W 0 CSMA_SEED_0 Bit 7:0 - CSMA_SEED_0 Lower 8-bit of CSMA_SEED, bits[7:0]. Used as seed for random number generation in the CSMA-CA algorithm. Table 7-29. CSMA_SEED_0. Register Bits Value Description CSMA_SEED_0 0xEA This register contains the lower 8-bit of the CSMA_SEED, bits[7:0]. The higher 3-bit are part of register bits CSMA_SEED_1 (register 0x2E, CSMA_SEED_1). CSMA_SEED is the seed for the random number generation that determines the length of the back-off period in the CSMA-CA algorithm. Register 0x2E (CSMA_SEED_1): The CSMA_SEED_1 register is a control register for RX_AACK and contains a part of the CSMA_SEED for the CSMA-CA algorithm. Figure 7-23. Register CSMA_SEED_1. Bit 7 0x2E Read/Write Reset value Bit 0x2E Read/Write Reset value 6 AACK_FVN_MODE 5 4 AACK_SET_PD AACK_DIS_ACK R/W 0 R/W 1 R/W 0 R/W 0 3 2 1 0 AACK_I_AM_ COORD R/W 0 CSMA_SEED_1 R/W 0 R/W 1 CSMA_SEED_1 CSMA_SEED_1 R/W 0 71 8321A–MCU Wireless–10/11 Bit 7:6 - AACK_FVN_MODE Controls the ACK behaviour dependent from FCF frame version number within RX_AACK mode. Table 7-30. AACK_FVN_MODE. Register Bits Value AACK_FVN_MODE Note: 1. Description 0 Accept frames with version number 0 1 Accept frames with version number 0 or 1 2 Accept frames with version number 0 or 1 or 2 3 Accept frames independent of frame version number AACK_FVN_MODE value one indicates frames according to IEEE-802.15.4-2006, a value of three indicates frames according to IEEE-802.15.4-2003 standard. The frame control field of the MAC header (MHR) contains a frame version subfield. The setting of register bits AACK_FVN_MODE specifies the frame filtering behavior of the Atmel AT86RF232. According to the content of these register bits the radio transceiver passes frames with a specific frame version number, number group, or independent of the frame version number. Thus the register bits AACK_FVN_MODE defines the maximum acceptable frame version. Received frames with a higher frame version number than configured do not pass the address filter and are not acknowledged. The frame version field of the acknowledgment frame is set to zero according to IEEE 802.15.4-2006, Section 7.2.2.3.1 Acknowledgment frame MHR fields. Bit 5 - AACK_SET_PD The content of AACK_SET_PD bit is copied into the frame pending subfield of the acknowledgment frame if the ACK is the answer to a data request MAC command frame. Table 7-31. AACK_SET_PD. Register Bits AACK_SET_PD Value Description 0 Pending data bit set to zero 1 Pending data bit set to one In addition, if register bits AACK_FVN_MODE (register 0x2E, CSMA_SEED_1) are configured to accept frames with a frame version other than zero or one, the content of register bit AACK_SET_PD is also copied into the frame pending subfield of the acknowledgment frame for any MAC command frame with a frame version of two or three that have the security enabled subfield set to one. This is done in the assumption that a future version of the standard [1] might change the length or structure of the auxiliary security header. 72 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Bit 4 - AACK_DIS_ACK If this bit is set no acknowledgment frames are transmitted in RX_AACK Extended Operating Mode, even if requested. Table 7-32. AACK_DIS_ACK. Register Bits Value AACK_DIS_ACK Description 0 Acknowledgment frames are transmitted 1 Acknowledgment frames are not transmitted Bit 3 - AACK_I_AM_COORD This register bit has to be set if the node is a PAN coordinator. It is used for frame filtering in RX_AACK. Table 7-33. AACK_I_AM_COORD. Register Bits Value AACK_I_AM_COORD Description 0 PAN coordinator addressing is disabled 1 PAN coordinator addressing is enabled If AACK_I_AM_COORD = 1 and if only source addressing fields are included in a data or MAC command frame, the frame shall be accepted only if the device is the PAN coordinator and the source PAN identifier matches macPANId, for details refer to IEEE 802.15.4, Section 7.5.6.2 (third-level filter rule six). Bit 2:0 - CSMA_SEED_1 Higher 3-bit of CSMA_SEED, bits[10:8]. Seed for random number generation in the CSMA-CA algorithm. Table 7-34. CSMA_SEED_1. Register Bits Value CSMA_SEED_1 Description 2 These register bits are the higher 3-bit of the CSMA_SEED, bits [10:8]. The lower part is in register 0x2D (CSMA_SEED_0), see register CSMA_SEED_0 for details. Register 0x2F (CSMA_BE): The register CSMA_BE contains the back-off exponents for the CSMA-CA algorithm. Figure 7-24. Register CSMA_BE. Bit 7 6 0x2F Read/Write Reset value Bit R/W 0 R/W 1 3 2 0x2F 4 R/W 0 R/W 1 1 0 R/W 1 R/W 1 CSMA_BE MIN_BE Read/Write Reset value Note: 5 MAX_BE 1. R/W 0 R/W 0 CSMA_BE If MIN_BE = 0 and MAX_BE = 0 the CCA backoff period is always set to zero. 73 8321A–MCU Wireless–10/11 Bit 7:4 - MAX_BE Maximum back-off exponent in the CSMA-CA algorithm. Table 7-35. MAX_BE. Register Bits MAX_BE Value 0x5 Description Register bits MAX_BE defines the maximum back-off exponent used in the CSMA-CA algorithm to generate a pseudo random number for CCA back-off. Valid values are [0x8, 0x7, …, 0x0]. For details refer to IEEE 802.15.4-2006, Section 7.5.1.4. Bit 3:0 - MIN_BE Minimum back-off exponent in the CSMA-CA algorithm. Table 7-36. MIN_BE. Register Bits MIN_BE Value 0x3 Description Register bits MIN_BE defines the minimum back-off exponent used in the CSMA-CA algorithm to generate a pseudo random number for CCA back-off. Valid values are [MAX_BE, (MAX_BE – 1), …, 0]. For details refer to IEEE 802.15.4-2006, Section 7.5.1.4. 74 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 7.2.8 Register Description – Address Registers Register 0x20 (SHORT_ADDR_0): This register contains the lower 8-bit of the MAC short address for Frame Filter address recognition, bits[7:0]. Figure 7-25. Register SHORT_ADDR_0. Bit 7 6 5 4 R/W 1 R/W 1 R/W 1 R/W 1 3 2 1 0 R/W 1 R/W 1 0x20 Read/Write Reset value Bit SHORT_ADDR_0 0x20 Read/Write Reset value SHORT_ADDR_0 SHORT_ADDR_0 R/W 1 R/W 1 SHORT_ADDR_0 Register 0x21 (SHORT_ADDR_1): This register contains the higher 8-bit of the MAC short address for Frame Filter address recognition, bits[15:8]. Figure 7-26. Register SHORT_ADDR_1. Bit 7 6 0x21 Read/Write Reset value Bit 4 SHORT_ADDR_1 R/W 1 R/W 1 R/W 1 R/W 1 3 2 1 0 R/W 1 R/W 1 0x21 Read/Write Reset value 5 SHORT_ADDR_1 SHORT_ADDR_1 R/W 1 R/W 1 SHORT_ADDR_1 Register 0x22 (PAN_ID_0): This register contains the lower 8-bit of the MAC PAN ID for Frame Filter address recognition, bits[7:0]. Figure 7-27. Register PAN_ID_0. Bit 7 6 0x22 Read/Write Reset value Bit R/W 1 R/W 1 3 2 0x22 Read/Write Reset value 5 4 R/W 1 R/W 1 1 0 PAN_ID_0 PAN_ID_0 PAN_ID_0 R/W 1 R/W 1 PAN_ID_0 R/W 1 R/W 1 75 8321A–MCU Wireless–10/11 Register 0x23 (PAN_ID_1): This register contains the higher 8-bit of the MAC PAN ID for Frame Filter address recognition, bits[15:8]. Figure 7-28. Register PAN_ID_1. Bit 7 6 R/W 1 R/W 1 3 2 0x23 Read/Write Reset value Bit 4 R/W 1 R/W 1 1 0 R/W 1 R/W 1 PAN_ID_1 0x23 Read/Write Reset value 5 PAN_ID_1 PAN_ID_1 R/W 1 R/W 1 PAN_ID_1 Register 0x24 (IEEE_ADDR_0): This register contains the lower 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[7:0]. Figure 7-29. Register IEEE_ADDR_0. Bit 7 6 0x24 Read/Write Reset value Bit 4 IEEE_ADDR_0 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 0x24 Read/Write Reset value 5 IEEE_ADDR_0 IEEE_ADDR_0 IEEE_ADDR_0 Register 0x25 (IEEE_ADDR_1): This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[15:8]. Figure 7-30. Register IEEE_ADDR_1. Bit 7 6 0x25 Read/Write Reset value Bit R/W 0 R/W 0 3 2 0x25 Read/Write Reset value 76 5 4 R/W 0 R/W 0 1 0 IEEE_ADDR_1 IEEE_ADDR_1 IEEE_ADDR_1 R/W 0 R/W 0 IEEE_ADDR_1 R/W 0 R/W 0 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Register 0x26 (IEEE_ADDR_2): This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[23:16]. Figure 7-31. Register IEEE_ADDR_2. Bit 7 6 R/W 0 R/W 0 3 2 0x26 Read/Write Reset value Bit 4 R/W 0 R/W 0 1 0 R/W 0 R/W 0 IEEE_ADDR_2 0x26 Read/Write Reset value 5 IEEE_ADDR_2 IEEE_ADDR_2 R/W 0 R/W 0 IEEE_ADDR_2 Register 0x27 (IEEE_ADDR_3): This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[31:24]. Figure 7-32. Register IEEE_ADDR_3. Bit 7 6 0x27 Read/Write Reset value Bit 4 IEEE_ADDR_3 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 0x27 Read/Write Reset value 5 IEEE_ADDR_3 IEEE_ADDR_3 IEEE_ADDR_3 Register 0x28 (IEEE_ADDR_4): This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[39:32]. Figure 7-33. Register IEEE_ADDR_4. Bit 7 6 0x28 Read/Write Reset value Bit R/W 0 R/W 0 3 2 0x28 Read/Write Reset value 5 4 R/W 0 R/W 0 1 0 R/W 0 R/W 0 IEEE_ADDR_4 IEEE_ADDR_4 IEEE_ADDR_4 R/W 0 R/W 0 IEEE_ADDR_4 77 8321A–MCU Wireless–10/11 Register 0x29 (IEEE_ADDR_5): This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[47:40]. Figure 7-34. Register IEEE_ADDR_5. Bit 7 6 R/W 0 R/W 0 3 2 0x29 Read/Write Reset value Bit 4 R/W 0 R/W 0 1 0 R/W 0 R/W 0 IEEE_ADDR_5 0x29 Read/Write Reset value 5 IEEE_ADDR_5 IEEE_ADDR_5 R/W 0 R/W 0 IEEE_ADDR_5 Register 0x2A (IEEE_ADDR_6): This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[55:48]. Figure 7-35. Register IEEE_ADDR_6. Bit 7 6 0x2A Read/Write Reset value Bit 4 IEEE_ADDR_6 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 0x2A Read/Write Reset value 5 IEEE_ADDR_6 IEEE_ADDR_6 IEEE_ADDR_6 Register 0x2B (IEEE_ADDR_7): This register contains the higher 8-bit of the MAC IEEE Frame Filter address for address recognition, bits[63:56]. Figure 7-36. Register IEEE_ADDR_7. Bit 7 6 0x2B Read/Write Reset value Bit R/W 0 R/W 0 3 2 0x2B Read/Write Reset value 78 5 4 R/W 0 R/W 0 1 0 R/W 0 R/W 0 IEEE_ADDR_7 IEEE_ADDR_7 IEEE_ADDR_7 R/W 0 R/W 0 IEEE_ADDR_7 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 8 Functional Description 8.1 Introduction – IEEE 802.15.4-2006 Frame Format Figure 8-1 provides an overview of the physical layer (PHY) frame structure as defined by IEEE 802.15.4. Figure 8-2 shows the frame structure of the medium access control (MAC) layer. Figure 8-1. IEEE 802.15.4 Frame Format - PHY-Layer Frame Structure (PPDU). PHY Protocol Data Unit (PPDU) Preamble Sequence SFD Frame Length PHY Payload 5 octets 1 octet Maximum 127 octets Synchronization Header (SHR) (PHR) PHY Service Data Unit (PSDU) MAC Protocol Data Unit (MPDU) 8.1.1 PHY Protocol Layer Data Unit (PPDU) 8.1.1.1 Synchronization Header (SHR) The SHR consists of a four-octet preamble field (all zero), followed by a single byte start-of-frame delimiter (SFD, value 0xA7). During transmission, the SHR is automatically generated by the Atmel AT86RF232, thus the Frame Buffer shall contain PHR and PSDU only. The transmission of the SHR requires 160µs (10 symbols). As the SPI data rate is normally higher than the over-air data rate, this allows the microcontroller to initiate a transmission without having transferred the full frame data already. Instead it is possible to subsequently write the frame content. During frame reception, the SHR is used for synchronization purposes. The matching SFD determines the beginning of the PHR and the following PSDU payload data. 8.1.1.2 PHY Header (PHR) The PHY header is a single octet following the SHR. The least significant seven bits denote the frame length of the following PSDU, while the most significant bit of that octet is reserved, and shall be set to zero for IEEE 802.15.4 compliant frames. On reception, the PHR is returned as the first octet during Frame Buffer read access. While the IEEE 802.15.4-2006 standard declares bit seven of the PHR octet as being reserved, the AT86RF232 preserves this bit upon transmission and reception so it can be used to carry additional information within proprietary networks. Nevertheless, this bit is not considered to be part of the frame length, so only frames between one and 127 octets are possible. For IEEE 802.15.4 compliant operation bit[7] has to be masked by software. The reception of a valid PHR (that is frame length greater than zero) is signaled by an interrupt IRQ_2 (RX_START). On transmission the PHR is to be supplied by the microcontroller during Frame Buffer write access as the first octet. 79 8321A–MCU Wireless–10/11 8.1.1.3 PHY Payload (PHY Service Data Unit, PSDU) The PSDU has a variable length between zero and aMaxPHYPacketSize (127, maximum PSDU size in octets). The length of the PSDU is signaled by the frame length field (PHR), refer to Table 8-1. The PSDU contains the MAC Protocol Layer Data Unit (MPDU). Received frames with a frame length field set to zero (invalid PHR) are not signaled to the microcontroller. Table 8-1 summarizes the type of payload versus the frame length value. Table 8-1. Frame Length Field – PHR. Frame Length Value Payload 0-4 Reserved 5 MPDU (Acknowledgement) 6–8 Reserved 9 - aMaxPHYPacketSize MPDU 8.1.2 MAC Protocol Layer Data Unit (MPDU) Figure 8-2 shows the frame structure of the MAC layer. Figure 8-2. IEEE 802.15.4 Frame Format - MAC-Layer Frame Structure (MPDU). MAC Protocol Data Unit (MPDU) Sequence Number FCF Addressing Fields MAC Payload MAC Header (MHR) Destination PAN ID 0 1 Frame Type 2 MAC Service Data Unit (MSDU) Destination Source address PAN ID 0/4/6/8/10/12/14/16/18/20 octets 3 4 5 Sec. Enabled Frame Pending ACK Request FCS 6 7 Source address 8 PAN ID Reserved Comp. Frame Control Field 2 octets 9 (MFR) Auxiliary Security Header CRC-16 0/5/6/10/14 octets 2 octets 10 11 Destination addressing mode 12 13 Frame Version 14 15 Source addressing mode 8.1.2.1 MAC Header (MHR) Fields The MAC header consists of the Frame Control Field (FCF), a sequence number, and the addressing fields (which are of variable length, and can even be empty in certain situations). 8.1.2.2 Frame Control Field (FCF) The FCF consists of 16 bits, and occupies the first two octets of the MPDU or PSDU, respectively. 80 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Figure 8-3. IEEE 802.15.4-2006 Frame Control Field (FCF). 0 1 2 Frame Type 3 4 5 6 Sec. Enabled Frame Pending ACK Request PAN ID Comp. 7 8 9 Reserved 10 11 Destination addressing mode 12 13 Frame Version 14 15 Source addressing mode Frame Control Field 2 octets Bit [2:0]: describes the frame type. Table 8-2 summarizes frame types defined by IEEE 802.15.4, Section 7.2.1.1.1. Table 8-2. Frame Control Field – Frame Type Subfield. Frame Control Field Bit Assignments Description Frame Type Value b2 b1 b0 Value 000 0 Beacon 001 1 Data 010 2 Acknowledge 011 3 MAC command 100 – 111 4–7 Reserved This subfield is used for address filtering by the third level filter rules. By default, only frame types 0 – 3 pass the third level filter rules, refer to Section 7.2.3.4. Automatic address filtering by the Atmel AT86RF232 is enabled when using the RX_AACK mode, refer to Section 7.2.3. However, a reserved frame (frame type value > 3) can be received if register bit AACK_UPLD_RES_FT (register 0x17, XAH_CTRL_1) is set, for details refer to Section 7.2.3.3. Address filtering is also provided in Basic Operating Mode, refer to Section 7.1. Bit 3: indicates whether security processing applies to this frame. Bit 4: is the “Frame Pending” subfield. This field can be set in an acknowledgment frame (ACK) in response to a data request MAC command frame. This bit indicates that the node, which transmitted the ACK, might have more data to send to the node receiving the ACK. For acknowledgment frames automatically generated by the AT86RF232, this bit is set according to the content of register bit AACK_SET_PD in register 0x2E (CSMA_SEED_1) if the received frame was a data request MAC command frame. Bit 5: forms the “Acknowledgment Request” subfield. If this bit is set within a data or MAC command frame that is not broadcast, the recipient shall acknowledge the reception of the frame within the time specified by IEEE 802.15.4 (that is within 192µs for non beacon-enabled networks). The radio transceiver parses this bit during RX_AACK mode and transmits an acknowledgment frame if necessary. In TX_ARET mode this bit indicates if an acknowledgement frame is expected after transmitting a frame. If this is the case, the receiver waits for the acknowledgment frame, otherwise the TX_ARET transaction is finished. Bit 6: the “PAN ID compression” subfield indicates that in a frame, where both, the destination and source addresses are present, the PAN-ID of the source address field 81 8321A–MCU Wireless–10/11 is omitted. In RX_AACK mode, this bit is evaluated by the address filter logic of the Atmel AT86RF232. This subfield was previously named “Intra-PAN”. Bit [11:10]: the “Destination Addressing Mode” subfield describes the format of the destination address of the frame. The values of the address modes are summarized in Table 8-3, according to IEEE 802.15.4: Table 8-3. Frame Control Field – Destination and Source Addressing Mode. Frame Control Field Bit Assignments Description Addressing Mode b11 b10 b15 b14 Value 00 0 PAN identifier and address fields are not present 01 1 Reserved 10 2 Address field contains a 16-bit short address 11 3 Address field contains a 64-bit extended address If the destination address mode is either two or three (that is if the destination address is present), it always consists of a 16-bit PAN-ID first, followed by either the 16-bit or 64-bit address as described by the mode. Bit [13:12]: the “Frame Version” subfield specifies the version number corresponding to the frame. These register bits are reserved in IEEE 802.15.4-2003. This subfield shall be set to zero to indicate a frame compatible with IEEE 802.15.4-2003 and one to indicate an IEEE 802.15.4-2006 frame. All other subfield values shall be reserved for future use. RX_AACK register bits AACK_FVN_MODE (register 0x2E, CSMA_SEED_1) controls the behavior of frame acknowledgements. This register determines if, depending on the Frame Version Number, a frame is acknowledged or not. This is necessary for backward compatibility to IEEE 802.15.4-2003 and for future use. Even if frame version numbers two and three are reserved, it can be handled by the radio transceiver, for details refer to Section 7.2.7. See IEEE 802.15.4-2006, Section 7.2.3 for details on frame compatibility. Table 8-4. Frame Control Field – Frame Version Subfield. Frame Control Field Bit Assignments Description Frame Version b13 b12 Value 00 0 Frames are compatible with IEEE 802.15.4-2003 01 1 Frames are compatible with IEEE 802.15.4-2006 10 2 Reserved 11 3 Reserved Bit [15:14]: the “Source Addressing Mode” subfield, with similar meaning as “Destination Addressing Mode”, see Table 8-3. The subfields of the FCF (Bits 0–2, 3, 6, 10–15) affect the address filter logic of the AT86RF232 while operating in RX_AACK operation, see Section 7.2.3. 82 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 8.1.2.3 Frame Compatibility between IEEE 802.15.4-2003 and IEEE 802.15.4-2006 All unsecured frames according to IEEE 802.15.4-2006 are compatible with unsecured frames compliant with IEEE 802.15.4-2003 with two exceptions: a coordinator realignment command frame with the “Channel Page” field present (see IEEE 802.15.4-2006, Section 7.3.8) and any frame with a MAC Payload field larger than aMaxMACSafePayloadSize octets. Compatibility for secured frames is shown in Table 8-5, which identifies the security operating modes for IEEE 802.15.4-2006. Table 8-5. Frame Control Field – Security and Frame Version. Frame Control Field Bit Assignments Description Security Enabled b3 Frame Version b13 b12 0 00 No security. Frames are compatible between IEEE 802.15.4-2003 and IEEE 802.15.4-2006. 0 01 No security. Frames are not compatible between IEEE 802.15.4-2003 and IEEE 802.15.4-2006. 1 00 Secured frame formatted according to IEEE 802.15.4-2003. This frame type is not supported in IEEE 802.15.4-2006. 1 01 Secured frame formatted according to IEEE 802.15.4-2006 8.1.2.4 Sequence Number The one-octet sequence number following the FCF identifies a particular frame, so that duplicated frame transmissions can be detected. While operating in RX_AACK mode, the content of this field is copied from the frame to be acknowledged into the acknowledgment frame. 8.1.2.5 Addressing Fields The addressing fields of the MPDU are used by the Atmel AT86RF232 for address matching indication. The destination address (if present) is always first, followed by the source address (if present). Each address field consists of the PAN-ID and a device address. If both addresses are present, and the “PAN ID compression” subfield in the FCF is set to one, the source PAN-ID is omitted. Note that in addition to these general rules, IEEE 802.15.4 further restricts the valid address combinations for the individual possible MAC frame types. For example, the situation where both addresses are omitted (source addressing mode = 0 and destination addressing mode = 0) is only allowed for acknowledgment frames. The address filter in the AT86RF232 has been designed to apply to IEEE 802.15.4 compliant frames. It can be configured to handle other frame formats and exceptions. 8.1.2.6 Auxiliary Security Header Field The Auxiliary Security Header specifies information required for security processing and has a variable length. This field determines how the frame is actually protected (security level) and which keying material from the MAC security PIB is used (see IEEE 802.15.4-2006, Section 7.6.1). This field shall be present only if the Security Enabled subfield b3, see Section 8.1.2.3, is set to one. For details of its structure, see IEEE 802.15.4-2006, Section 7.6.2 Auxiliary security header. 83 8321A–MCU Wireless–10/11 8.1.2.7 MAC Service Data Unit (MSDU) This is the actual MAC payload. It is usually structured according to the individual frame type. A description can be found in IEEE 802.15.4-2006, Section 5.5.3.2. 8.1.2.8 MAC Footer (MFR) Fields The MAC footer consists of a two-octet Frame Checksum (FCS), for details refer to Section 8.2. 8.2 Frame Check Sequence (FCS) The Frame Check Sequence (FCS) is characterized by: Indicate bit errors, based on a cyclic redundancy check (CRC) of length 16-bit Uses International Telecommunication Union (ITU) CRC polynomial Automatically evaluated during reception Can be automatically generated during transmission 8.2.1 Overview The FCS is intended for use at the MAC layer to detect corrupted frames at a first level of filtering. It is computed by applying an ITU CRC polynomial to all transferred bytes following the length field (MHR and MSDU fields). The frame check sequence has a length of 16-bit and is located in the last two bytes of a frame (MAC footer, see Figure 8-2). The Atmel AT86RF232 applies an FCS check on each received frame. The FCS check result is stored in register bit RX_CRC_VALID (register 0x06, PHY_RSSI). On transmission the radio transceiver generates and appends the FCS bytes during the frame transmission. This behavior can be disabled by setting register bit TX_AUTO_CRC_ON = 0 (register 0x04, TRX_CTRL_1). 8.2.2 CRC calculation The CRC polynomial used in IEEE 802.15.4 networks is defined by G16 ( x) x16 x12 x 5 1 The FCS shall be calculated for transmission using the following algorithm: Let M ( x) b0 x k 1 b1 x k 2 bk 2 x bk 1 be the polynomial representing the sequence of bits for which the checksum is to be 16 computed. Multiply M(x) by x , giving the polynomial N ( x) M ( x) x16 Divide N (x) modulo two by the generator polynomial, G16 ( x) , to obtain the remainder polynomial, R( x) r0 x15 r1 x14 ... r14 x r15 The FCS field is given by the coefficients of the remainder polynomial, R(x). Example: Considering a five octet ACK frame. The MHR field consists of 0100 0000 0000 0000 0101 0110. 84 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 The leftmost bit (b0) is transmitted first in time. The FCS is in this case 0010 0111 1001 1110. The leftmost bit (r0) is transmitted first in time. 8.2.3 Automatic FCS generation The automatic FCS generation is activated with register bit TX_AUTO_CRC_ON = 1 (reset value). This allows the Atmel AT86RF232 to compute the FCS autonomously. For a frame with a frame length specified as N (3 ≤ N ≤ 127), the FCS is calculated on the first N-2 octets in the Frame Buffer, and the resulting FCS field is transmitted in place of the last two octets from the Frame Buffer. If the radio transceiver’s automatic FCS generation is enabled, the Frame Buffer write access can be stopped right after MAC payload. There is no need to write FCS dummy bytes. In RX_AACK mode, when a received frame needs to be acknowledged, the FCS of the ACK frame is always automatically generated by the AT86RF232, independent of the TX_AUTO_CRC_ON setting. Example: A frame transmission of length five with TX_AUTO_CRC_ON set, is started with a Frame Buffer write access of five bytes (the last two bytes can be omitted). The first three bytes are used for FCS generation; the last two bytes are replaced by the internally calculated FCS. 8.2.4 Automatic FCS check An automatic FCS check is applied on each received frame with a frame length N ≥ 2. Register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is set if the FCS of a received frame is valid. The register bit is updated when issuing interrupt IRQ_3 (TRX_END) and remains valid until the next TRX_END interrupt caused by a new frame reception. In RX_AACK mode, if FCS of the received frame is not valid, the radio transceiver rejects the frame and the TRX_END interrupt is not issued. In TX_ARET mode, the FCS and the sequence number of an ACK is automatically checked. If one of these is not correct, the ACK is not accepted. 85 8321A–MCU Wireless–10/11 8.2.5 Register Description Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. Figure 8-4. Register TRX_CTRL_1. Bit 0x04 Read/Write Reset value Bit 7 6 5 4 reserved IRQ_2_EXT_EN TX_AUTO_CRC_ ON RX_BL_CTRL R/W 0 R/W 0 R/W 1 R/W 0 3 2 1 0 IRQ_MASK_MODE IRQ_POLARITY R/W 1 R/W 0 0x04 SPI_CMD_MODE Read/Write Reset value R/W 0 R/W 0 TRX_CTRL_1 TRX_CTRL_1 Bit 5 - TX_AUTO_CRC_ON The register bit TX_AUTO_CRC_ON controls the automatic FCS generation for transmit operations. Table 8-6. TX_AUTO_CRC_ON. Register Bits Value TX_AUTO_CRC_ON Note: 1. Description 0 Automatic FCS generation is disabled 1 Automatic FCS generation is enabled The TX_AUTO_CRC_ON function can be used within Basic and Extended Operating Modes. Register 0x06 (PHY_RSSI): The PHY_RSSI register is a multi-purpose register that indicates FCS validity, provides random numbers and shows the actual RSSI value. Figure 8-5. Register PHY_RSSI. Bit 0x06 7 6 RX_CRC_VALID Read/Write Reset value R 0 R 1 Bit 3 2 0x06 Read/Write Reset value 86 5 RND_VALUE 4 RSSI R 1 R 0 1 0 R 0 R 0 RSSI R 0 R 0 PHY_RSSI PHY_RSSI AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Bit 7 - RX_CRC_VALID The register bit RX_CRC_VALID signals the FCS check status for a received frame. Table 8-7. RX_CRC_VALID. Register Bits RX_CRC_VALID Value Description 0 FCS is not valid 1 FCS is valid Reading this register bit indicates whether the last received frame has a valid FCS or not. The register bit is updated when issuing interrupt IRQ_3 (TRX_END) and remains valid until the next TRX_END interrupt is issued, caused by a new frame reception. 87 8321A–MCU Wireless–10/11 8.3 Received Signal Strength Indicator (RSSI) The Atmel AT86RF232 Received Signal Strength Indicator is characterized by: Minimum RSSI level is -91dBm (RSSIBASE_VAL) Dynamic range is 87dB Minimum RSSI value is 0 Maximum RSSI value is 28 8.3.1 Overview The RSSI is a 5-bit value indicating the receive power in the selected channel, in steps of 3dB. No attempt is made to distinguish IEEE 802.15.4 signals from others, only the received signal strength is evaluated. The RSSI provides the basis for an ED measurement, see Section 8.4. 8.3.2 Reading RSSI In Basic Operating Mode the RSSI value is valid in any receive state, and is updated every tRSSI = 2µs to register 0x06 (PHY_RSSI). It is not recommended to read the RSSI value when using the Extended Operating Mode. The automatically generated ED value should be used alternatively, see Section 8.4. 8.3.3 Data Interpretation The RSSI value is a 5-bit value indicating the receive power, in steps of 3dB and with a range of zero to 28. An RSSI value of zero indicates a receiver RF input power of PRF ≤ -91dBm. For an RSSI value in the range of one to 28, the RF input power can be calculated as follows: PRF[dBm] = RSSIBASE_VAL + 3 x RSSI Figure 8-6. Mapping between RSSI Value and Received Input Power. 10 Receiver Input Power PRF [dBm] 0 Measured -10 Ideal -20 -30 -40 -50 -60 -70 -80 -90 -100 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 RSSI 88 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 8.3.4 Register Description Register 0x06 (PHY_RSSI): The PHY_RSSI register is a multi-purpose register that indicates FCS validity, provides random numbers and shows the actual RSSI value. Figure 8-7. Register PHY_RSSI. Bit 0x06 7 6 5 RX_CRC_VALID RND_VALUE Read/Write Reset value R 0 R 1 Bit 3 2 0x06 Read/Write Reset value 4 RSSI R 1 R 0 1 0 R 0 R 0 RSSI R 0 R 0 PHY_RSSI PHY_RSSI Bit 4:0 - RSSI Received signal strength as a linear curve on a logarithmic input power scale with a resolution of 3dB. Table 8-8. RSSI. Register Bits Value Description RSSI 0x00 Minimum RSSI value 0x1C Maximum RSSI value The result of the automated RSSI measurement is stored in register bits RSSI. The value is updated every tRSSI = 2µs in receive states. The read value is a number between zero and 28 indicating the received signal strength as a linear curve on a logarithmic input power scale with a resolution of 3dB. An RSSI value of zero indicates an RF input power of PRF ≤ -91dBm (RSSIBASE_VAL), a value of 28 a power of PRF ≥ -7dBm (see parameter RSSIMAX specified in Section 12.7). 89 8321A–MCU Wireless–10/11 8.4 Energy Detection (ED) The Atmel AT86RF232 Energy Detection (ED) module is characterized by: 84 unique energy levels defined 1dB resolution 8.4.1 Overview The receiver ED measurement is used by the network layer as part of a channel selection algorithm. It is an estimation of the received signal power within the bandwidth of an IEEE 802.15.4 channel. No attempt is made to identify or decode signals on the channel. The ED value is calculated by averaging RSSI values over eight symbols (128µs). 8.4.2 Measurement Description There are two ways to initiate an ED measurement: Manually, by writing an arbitrary value to register 0x07 (PHY_ED_LEVEL), or Automatically, after detection of a valid SHR of an incoming frame. For manually initiated ED measurements the radio transceiver needs to be in one of the states RX_ON or BUSY_RX state. The end of the ED measurement is indicated by an interrupt IRQ_4 (CCA_ED_DONE). An automated ED measurement is started if an SHR is detected. The end of the automated measurement is not signaled by an interrupt. Note: 1. The ED result is not updated during the rest of the frame reception, even by requesting an ED measurement manually. The measurement result is stored after tED = 180µs (max.) (128µs measurement duration and processing delay) in register 0x07 (PHY_ED_LEVEL) ), refer to Table 7-2. Thus by using Basic Operating Mode, a valid ED value from the currently received frame is accessible 108µs after IRQ_2 (RX_START) and remains valid until a new RX_START interrupt is generated by the next incoming frame or until another ED measurement is initiated. When using the Extended Operating Mode, it is recommended to mask IRQ_2 (RX_START), thus the interrupt cannot be used as timing reference. A successful frame reception is signalized by interrupt IRQ_3 (TRX_END). The minimum time span between an IRQ_3 (TRX_END) interrupt and a following SFD detection is tSHR_SYNC = 96µs due to the length of the SHR. Including the ED measurement time, the ED value needs to be read within 224µs after the TRX_END interrupt; otherwise, it could be overwritten by the result of the next measurement cycle. This is important for time critical applications or if interrupt IRQ_2 (RX_START) is not used to indicate the reception of a frame. Note: 90 2. It is not recommended to manually initiate an ED measurement when using the Extended Operating Mode. AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 8.4.3 Data Interpretation The PHY_ED_LEVEL is an 8-bit register. The ED_LEVEL value of the Atmel AT86RF232 has a valid range from 0x00 to 0x53 with a resolution of 1dB. A value of 0xFF indicates the reset value. All other values do not occur. Due to environmental conditions (temperature, voltage, semiconductor parameters, etc.) the calculated ED_LEVEL value has a maximum tolerance of ±5dB, this is to be considered as constant offset over the measurement range. An ED_LEVEL value of zero indicates an RF input power of PRF ≤ -91dBm (see parameter RSSIBASE_VAL, Section 12.7). For an ED_LEVEL value in the range of one to 83, the RF input power can be calculated as follows: PRF[dBm] = RSSIBASE_VAL + ED_LEVEL Figure 8-8. Mapping between Received Input Power and ED Value. 10 Receiver Input Power PRF [dBm] 0 Measured -10 Ideal -20 -30 -40 -50 -60 -70 -80 -90 -100 0 10 20 30 40 50 60 70 80 90 PHY_ED_LEVEL (register 0x07) 8.4.4 Interrupt Handling Interrupt IRQ_4 (CCA_ED_DONE) is issued at the end of a manually initiated ED measurement. Note: 1. An ED request should only be initiated in receive states. Otherwise the radio transceiver generates an IRQ_4 (CCA_ED_DONE); however no ED measurement was performed. 91 8321A–MCU Wireless–10/11 8.4.5 Register Description Register 0x07 (PHY_ED_LEVEL): The PHY_ED_LEVEL register contains the result of an ED measurement. Figure 8-9. Register PHY_ED_LEVEL. Bit 7 6 0x07 Read/Write Reset value R 1 R 1 Bit 3 2 0x07 Read/Write Reset value 5 4 R 1 R 1 1 0 R 1 R 1 ED_LEVEL PHY_ED_LEVEL ED_LEVEL R 1 R 1 PHY_ED_LEVEL Bit 7:0 - ED_LEVEL The register bits ED_LEVEL signals the ED level for current channel. Table 8-9. ED_LEVEL. Register Bits Value Description ED_LEVEL 0x00 Minimum ED level value 0x53 Maximum ED level value 0xFF Reset value The minimum ED value zero indicates receiver power less than or equal RSSIBASE_VAL. The range is 83dB with a resolution of 1dB and an accuracy of ±5dB. A manual ED measurement can be initiated by a write access to the register. A value 0xFF signals that no measurement has been started yet (reset value). The measurement duration is eight symbol periods (128μs) for a data rate of 250kb/s. 92 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 8.5 Clear Channel Assessment (CCA) The main features of the Clear Channel Assessment (CCA) module are: All four modes are available as defined by IEEE 802.15.4-2006 in Section 6.9.9 Adjustable threshold for energy detection algorithm 8.5.1 Overview A CCA measurement is used to detect a clear channel. Four modes are specified by IEEE 802.15.4-2006: Table 8-10. CCA Mode Overview. CCA Mode Description 1 Energy above threshold. CCA shall report a busy medium upon detecting any energy above the ED threshold. 2 Carrier sense only. CCA shall report a busy medium only upon the detection of a signal with the modulation and spreading characteristics of an IEEE 802.15.4 compliant signal. The signal strength may be above or below the ED threshold. 0, 3 Carrier sense with energy above threshold. CCA shall report a busy medium using a logical combination of - Detection of a signal with the modulation and spreading characteristics of this standard and - Energy above the ED threshold. Where the logical operator may be configured as either OR (mode 0) or AND (mode 3). 8.5.2 Configuration and Request The CCA modes are configurable via register 0x08 (PHY_CC_CCA). Using the Basic Operating Mode, a CCA request can be initiated manually by setting CCA_REQUEST = 1 (register 0x08, PHY_CC_CCA), if the Atmel AT86RF232 is in any RX state. The current channel status (CCA_STATUS) and the CCA completion status (CCA_DONE) are accessible in register 0x01 (TRX_STATUS). The CCA evaluation is done over eight symbol periods and the result is accessible tCCA = 180µs (max.) (128µs measurement duration and processing delay) after the request), refer to Table 7-2. The end of a manually initiated CCA measurement is indicated by an interrupt IRQ_4 (CCA_ED_DONE). The register bits CCA_ED_THRES of register 0x09 (CCA_THRES) defines the received power threshold of the “Energy above threshold” algorithm. The threshold is calculated by RSSIBASE_VAL + 2 x CCA_ED_THRES [dB]. Any received power above this level is interpreted as a busy channel. Note: 1. It is not recommended to manually initiate a CCA measurement when using the Extended Operating Mode. 93 8321A–MCU Wireless–10/11 8.5.3 Data Interpretation The Atmel AT86RF232 current channel status (CCA_STATUS) and the CCA completion status (CCA_DONE) are accessible in register 0x01 (TRX_STATUS). Note, register bits CCA_DONE and CCA_STATUS are cleared in response to a CCA_REQUEST. The completion of a measurement cycle is indicated by CCA_DONE = 1. If the radio transceiver detected no signal (idle channel) during the measurement cycle, the CCA_STATUS bit is set to one. When using the “energy above threshold” algorithm, any received power above CCA_ED_THRES level is interpreted as a busy channel. The “carrier sense” algorithm reports a busy channel when detecting an IEEE 802.15.4 signal above the RSSIBASE_VAL (see Section 12.7). The radio transceiver is also able to detect signals below this value, but the detection probability decreases with the signal power. It is almost zero at the radio transceiver’s sensitivity level (see parameter PSENS). 8.5.4 Interrupt Handling Interrupt IRQ_4 (CCA_ED_DONE) is issued at the end of a manually initiated CCA measurement. Notes: 1. A CCA request should only be initiated in Basic Operating Mode receive states. Otherwise the radio transceiver generates an IRQ_4 (CCA_ED_DONE) and sets the register bit CCA_DONE = 1, even though no CCA measurement was performed. 2. Requesting a CCA measurement in BUSY_RX state and during an ED measurement, an IRQ_4 (CCA_ED_DONE) could be issued immediately after the request. If in this case register bit CCA_DONE = 0, an additional interrupt CCA_ED_DONE is issued after finishing the CCA measurement and register bit CCA_DONE is set to one. 8.5.5 Measurement Time The response time for a manually initiated CCA measurement depends on the receiver state. In RX_ON state the CCA measurement is done over eight symbol periods and the result is accessible tCCA = 180µs after the request (see above). 94 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Table 8-11. CCA Measurement Period and Access in BUSY_RX state. CCA Mode 1 Request within ED measurement (1) Request after ED measurement Energy above threshold. CCA result is available after finishing automated ED measurement period. 2 CCA result is immediately available after request. Carrier sense only. CCA result is immediately available after request. 3 Carrier sense with Energy above threshold (AND). CCA result is available after finishing automated ED measurement period. 0 CCA result is immediately available after request. Carrier sense with Energy above threshold (OR). CCA result is available after finishing automated ED measurement period. Note: CCA result is immediately available after request. 1. After receiving the SHR an automated ED measurement is started with a length of eight symbol periods (PSDU rate 250kb/s), refer to Section 8.4. This automated ED measurement must be finished to provide a result for the CCA measurement. Only one automated ED measurement per frame is performed. In BUSY_RX state the CCA measurement duration depends on the CCA Mode and the CCA request relative to the reception of an SHR. The end of the CCA measurement is indicated by an IRQ_4 (CCA_ED_DONE). The variation of a CCA measurement period in BUSY_RX state is described in Table 8-11. It is recommended to perform CCA measurements in Atmel AT86RF232 RX_ON state only. To avoid switching accidentally to BUSY_RX state the SHR detection can be disabled by setting register bit RX_PDT_DIS (register 0x15, RX_SYN), refer to Section 9.1. The receiver remains in RX_ON state to perform a CCA measurement until the register bit RX_PDT_DIS is set back to continue the frame reception. In this case the CCA measurement duration is eight symbol periods. 8.5.6 Register Description Register 0x01 (TRX_STATUS): The read-only register TRX_STATUS signals the present state of the radio transceiver as well as the status of a CCA operation. Figure 8-10. Register TRX_STATUS. Bit 7 6 5 4 CCA_DONE CCA_STATUS reserved TRX_STATUS Read/Write Reset value R 0 R 0 R 0 R 0 Bit 3 2 1 0 R 0 R 0 0x01 0x01 Read/Write Reset value TRX_STATUS R 0 R 0 TRX_STATUS TRX_STATUS 95 8321A–MCU Wireless–10/11 Bit 7 - CCA_DONE Table 8-12. CCA_DONE. Register Bits Value CCA_DONE Description 0 CCA calculation not finished 1 CCA calculation finished The register bit CCA_DONE indicates if a CCA request is completed. This is also indicated by an interrupt IRQ_4 (CCA_ED_DONE). The register bit CCA_DONE is cleared in response to a CCA_REQUEST. Bit 6 - CCA_STATUS Table 8-13. CCA_STATUS. Register Bits Value Description CCA_STATUS 0 Channel indicated as busy 1 Channel indicated as idle After a CCA request is completed the result of the CCA measurement is available in register bit CCA_STATUS. The register bit CCA_STATUS is cleared in response to a CCA_REQUEST. Register 0x08 (PHY_CC_CCA): The PHY_CC_CCA register is a multi-purpose register that controls CCA configuration, CCA measurement, and the IEEE 802.15.4 channel setting. Figure 8-11. Register PHY_CC_CCA. Bit 7 0x08 6 5 CCA_REQUEST Read/Write Reset value Bit CCA_MODE R/W 0 R/W 0 3 2 0x08 4 CHANNEL R/W 1 R/W 0 1 0 R/W 1 R/W 1 CHANNEL Read/Write Reset value R/W 1 R/W 0 PHY_CC_CCA PHY_CC_CCA Bit 7 - CCA_REQUEST The register bit CCA_REQUEST initiates a manual started CCA measurement. Table 8-14. CCA_REQUEST. Register Bits CCA_REQUEST Notes: 1. 2. Value Description 0 Reset value 1 Starts a CCA measurement The read value returns always with zero. If a CCA request is initiated in states others than RX_ON or RX_BUSY the PHY generates an IRQ_4 (CCA_ED_DONE) and sets the register bit CCA_DONE, however no CCA was carried out. A manual CCA measurement is initiated with setting CCA_REQUEST = 1. The end of the CCA measurement is indicated by interrupt IRQ_4 (CCA_ED_DONE). Register bits CCA_DONE and CCA_STATUS (register 0x01, TRX_STATUS) are updated after a 96 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 CCA_REQUEST. The register bit is automatically cleared after requesting a CCA measurement with CCA_REQUEST = 1. Bit 6:5 - CCA_MODE The CCA mode can be selected using register bits CCA_MODE. Table 8-15. CCA_MODE. Register Bits Value Description CCA_MODE 0 Mode 3a, Carrier sense OR energy above threshold 1 Mode 1, Energy above threshold 2 Mode 2, Carrier sense only 3 Mode 3b, Carrier sense AND energy above threshold Register 0x09 (CCA_THRES): The CCA_THRES register sets the ED threshold level for CCA. Figure 8-12. Register CCA_THRES. Bit 7 6 5 0x09 Read/Write Reset value CCA_THRES R/W 1 R/W 1 R/W 0 R/W 0 3 2 1 0 R/W 1 R/W 1 Bit 0x09 Read/Write Reset value 4 reserved CCA_ED_THRES R/W 0 R/W 1 CCA_THRES Bit 3:0 - CCA_ED_THRES An ED value above the threshold signals the channel during a CCA_ED measurement as busy. Table 8-16. CCA_ED_THRES. Register Bits CCA_ED_THRES Value 0x7 Description The CCA Mode 1 request indicates a busy channel if the measured received power is above RSSI_BASE_VAL + 2 x CCA_ED_THRES [dB]. CCA Modes 0 and 3 are logical related to this result. 97 8321A–MCU Wireless–10/11 8.6 Link Quality Indication (LQI) According to IEEE 802.15.4, the LQI measurement is a characterization of the strength and/or quality of a received packet. The measurement may be implemented using receiver ED, a signal-to-noise ratio estimation, or a combination of these methods. The use of the LQI result by the network or application layers is not specified in this standard. LQI values shall be an integer ranging from 0x00 to 0xFF. The minimum and maximum LQI values (0x00 and 0xFF) should be associated with the lowest and highest quality compliant signals, respectively, and LQI values in between should be uniformly distributed between these two limits. 8.6.1 Overview The LQI measurement of the Atmel AT86RF232 is implemented as a measure of the link quality which can be described with the packet error rate (PER) for this link. An LQI value can be associated with an expected packet error rate. The PER is the ratio of erroneous received frames to the total number of received frames. A PER of zero indicates no frame error, whereas at a PER of one no frame was received correctly. The radio transceiver uses correlation results of multiple symbols within a frame to determine the LQI value. This is done for each received frame. The minimum frame length for a valid LQI value is two octets PSDU. LQI values are integers ranging from zero to 255. As an example, Figure 8-13 shows the conditional packet error rate (PER) when receiving a certain LQI value. Figure 8-13. Conditional Packet Error Rate versus LQI. 1 0.9 0.8 0.7 PER 0.6 0.5 0.4 0.3 0.2 0.1 0 0 50 100 150 200 250 LQI That means that a large number of transmission with an identical LQI value results in a packet error rate shown in the Figure 8-13. Lost packets have been discarded since in this case there is no LQI value available. 98 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 If, instead, the mean LQI over a large number of transmissions is computed, and the mean LQI is quantized to an LQI value of the figure, the corresponding frame error rate is not strictly equal to the true error rate. The values are taken from received frames of PSDU length of 20 octets on transmission channels with reasonable low multipath delay spreads. If the transmission channel characteristic has higher multipath delay spread than assumed in the example, the PER is slightly higher for a certain LQI value. Since the packet error rate is a statistical value, the PER shown in Figure 8-13 is based on a huge number of transactions. A reliable estimation of the packet error rate cannot be based on a single or a small number of LQI values. 8.6.2 Request an LQI Measurement The LQI byte can be obtained after a frame has been received by the radio transceiver. One additional byte is automatically attached to the received frame containing the LQI value. This information can also be read via Frame Buffer read access, see Section 6.2.2. The LQI byte can be read after IRQ_3 (TRX_END) interrupt. 8.6.3 Data Interpretation According to IEEE 802.15.4 a low LQI value is associated with low signal strength and/or high signal distortions. Signal distortions are mainly caused by interference signals and/or multipath propagation. High LQI values indicate a sufficient high signal power and low signal distortions. Note: 1. The received signal power as indicated by received signal strength indication (RSSI) value or energy detection (ED) value of the Atmel AT86RF232 do not characterize the signal quality and the ability to decode a signal. As an example, a received signal with an input power of about 6dB above the receiver sensitivity likely results in a LQI value close to 255 for radio channels with very low signal distortions. For higher signal power the LQI value becomes independent of the actual signal strength. This is because the packet error rate for these scenarios tends towards zero and further increased signal strength, that is increasing the transmission power does not decrease the error rate any further. In this case RSSI or ED can be used to evaluate the signal strength and the link margin. ZigBee networks often require the identification of the “best” routing between two nodes. Both, the LQI and the RSSI/ED can be used for this, dependent on the optimization criteria. If a low packet error rate (corresponding to high throughput) is the optimization criteria then the LQI value should be taken into consideration. If a low transmission power or the link margin is the optimization criteria then the RSSI/ED value is also helpful. Combinations of LQI, RSSI and ED are possible for routing decisions. As a rule of thumb RSSI and ED values are useful to differentiate between links with high LQI values. Transmission links with low LQI values should be discarded for routing decisions even if the RSSI/ED values are high. This is because RSSI/ED does not say anything about the possibility to decode a signal. It is only an information about the received signal strength whereas the source can be an interferer. 99 8321A–MCU Wireless–10/11 9 Module Description 9.1 Receiver (RX) 9.1.1 Overview The Atmel AT86RF232 receiver is split into an analog radio front-end and a digital base band processor (RX BBP), see Figure 9-1. Figure 9-1. Receiver Block Diagram. Analog Domain LO Digital Domain Frame Buffer RFP LNA PPF BPF Limiter ADC RX BBP SPI SPI I/F RFN AGC RSSI Control, Registers µC I/F The differential RF signal is amplified by a low noise amplifier (LNA), filtered (PPF) and down converted to an intermediate frequency by a mixer. Channel selectivity is performed using an integrated band pass filter (BPF). A limiting amplifier (Limiter) provides sufficient gain to overcome the DC offset of the succeeding analog-to-digital converter (ADC) and generates a digital RSSI signal. The ADC output signal is sampled and processed further by the digital base band receiver (RX BBP). The RX BBP performs additional signal filtering and signal synchronization. The frequency offset of each frame is calculated by the synchronization unit and is used during the remaining receive process to correct the offset. The receiver is designed to handle frequency and symbol rate deviations fSRD up to ±120ppm, caused by combined receiver and transmitter deviations. For details refer to Section 12.5 parameter fSRD. Finally the signal is demodulated and the data are stored in the Frame Buffer. In Basic Operating Mode, refer to Section 7.1, the reception of a frame is indicated by an interrupt IRQ_2 (RX_START). Accordingly its end is signalized by an interrupt IRQ_3 (TRX_END). Based on the quality of the received signal a link quality indicator (LQI) is calculated and appended to the frame, refer to Section 8.6. Additional signal processing is applied to the frame data to provide further status information like ED value (register 0x07, PHY_ED_LEVEL) and FCS correctness (register 0x06, PHY_RSSI). Beyond these features the Extended Operating Mode of the AT86RF232 supports address filtering and pending data indication. For details refer to Section 7.2. 9.1.2 Frame Receive Procedure The frame receive procedure including the radio transceiver setup for reception and reading PSDU data from the Frame Buffer is described in Section 10.1 Frame Receive Procedure. 9.1.3 Configuration In Basic Operating Mode the receiver is enabled by writing command RX_ON to register bits TRX_CMD (register 0x02, TRX_STATE) in states TRX_OFF or PLL_ON. Similarly in Extended Operating Mode, the receiver is enabled for RX_AACK operation 100 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 from states TRX_OFF or PLL_ON by writing the command RX_AACK_ON. There is no additional configuration required to receive IEEE 802.15.4 compliant frames when using the Basic Operating Mode. However, the frame reception in the Atmel AT86RF232 Extended Operating Mode requires further register configurations, for details refer to Section 7.2. The AT86RF232 receiver has an outstanding sensitivity performance of -100dBm. It may be useful to manually decrease this sensitivity. This is achieved by adjusting the synchronization header detector threshold using register bits RX_PDT_LEVEL (register 0x15, RX_SYN). Received signals with an RSSI value below the threshold do not activate the demodulation process. Furthermore, it may be useful to protect a received frame against overwriting by subsequent received frames. A Dynamic Frame Buffer Protection is enabled with register bit RX_SAFE_MODE (register 0x0C, TRX_CTRL_2) set, see Section 11.6. The receiver remains in RX_ON or RX_AACK_ON state until the whole frame is read by the microcontroller, indicated by pin 23 (/SEL) = H during the SPI Frame Receive Mode. The Frame Buffer content is only protected if the FCS is valid. A Static Frame Buffer Protection is enabled with register bit RX_PDT_DIS (register 0x15, RX_SYN) set. The receiver remains in RX_ON or RX_AACK_ON state and no further SHR is detected until the register bit RX_PDT_DIS is set back. 9.1.4 Register Description Register 0x15 (RX_SYN): The register RX_SYN controls the blocking of receiver path and the sensitivity threshold of the receiver. Figure 9-2. Register RX_SYN. Bit 0x15 7 6 5 RX_PDT_DIS Read/Write Reset value Bit R/W 0 R 0 3 2 0x15 Read/Write Reset value 4 reserved RX_SYN R 0 R 0 1 0 R/W 0 R/W 0 RX_PDT_LEVEL R/W 0 R/W 0 RX_SYN Bit 7 - RX_PDT_DIS The register bit RX_PDT_DIS prevents the reception of a frame during RX phase. Table 9-1. RX_PDT_DIS. Register Bits Value RX_PDT_DIS 0 Description RX path is enabled 1 RX path is disabled RX_PDT_DIS = 1 prevents the reception of a frame even if the radio transceiver is in receive modes. An ongoing frame reception is not affected. This operation mode is independent of the setting of register bits RX_PDT_LEVEL. 101 8321A–MCU Wireless–10/11 Bit 3:0 - RX_PDT_LEVEL The register bits RX_PDT_LEVEL desensitize the receiver in steps of 3dB. Table 9-2. RX_PDT_LEVEL. Register Bits RX_PDT_LEVEL Value Description 0x00 Maximum RX sensitivity 0x0F RX input level > RSSI_BASE_VAL + 3 x 14 These register bits desensitize the receiver such that frames with an RSSI level below the RX_PDT_LEVEL threshold level (if RX_PDT_LEVEL > 0) are not received. For a RX_PDT_LEVEL > 0 value the threshold level can be calculated according to the following formula: PRF[dBm] > RSSIBASE_VAL + 3 x (RX_PDT_LEVEL - 1) Examples for certain register settings are given in Table 9-3. Table 9-3. Receiver Desensitization Threshold Level – RX_PDT_LEVEL. Register Value RX Input Threshold Level Value [dBm] 0x0 disabled, maximum RX sensitivity RSSI value not considered 0x1 > RSSI_BASE_VAL + 3 x 0 > -91 0xE > RSSI_BASE_VAL + 3 x 13 > -52 0xF > RSSI_BASE_VAL + 3 x 14 > -49 … If register bits RX_PDT_LEVEL = 0 (reset value) all frames with a valid SHR and PHR are received, independently of their signal strength. If register bits RX_PDT_LEVEL > 0, the current consumption of the receiver in states RX_ON and RX_AACK_ON is reduced to IRX_ON_L0 = 11.3mA (typ.), refer to Section 12.8. 102 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 9.2 Transmitter (TX) 9.2.1 Overview The Atmel AT86RF232 transmitter consists of a digital base band processor (TX BBP) and an analog radio front end, see Figure 9-3. Figure 9-3. Transmitter Block Diagram. Ext. RF front-end and Output Power Control RFP PA Buf µC I/F Control, Registers TX BBP TX Data PLL – TX Modulation SPI SPI I/F RFN Frame Buffer Analog Domain Digital Domain The TX BBP reads the frame data from the Frame Buffer and performs the bit-tosymbol and symbol-to-chip mapping as specified by IEEE 802.15.4 in Section 6.5.2. The O-QPSK modulation signal is generated and fed into the analog radio front end. The fractional-N frequency synthesizer (PLL) converts the baseband transmit signal to the RF signal, which is amplified by the power amplifier (PA). The PA output is internally connected to bidirectional differential antenna pins (RFP, RFN), so that no external antenna switch is needed. 9.2.2 Frame Transmit Procedure The frame transmit procedure including writing PSDU data in the Frame Buffer and initiating a transmission is described in Section 10.2 Frame Transmit Procedure. 9.2.3 Configuration The maximum output power of the transmitter is typically +3dBm. The output power can be configured via register bits TX_PWR (register 0x05, PHY_TX_PWR). The output power of the transmitter can be controlled over a range of 20dB. A transmission can be started from PLL_ON or TX_ARET_ON state by a rising edge of pin 11 (SLP_TR) or by writing TX_START command to register bits TRX_CMD (register 0x02, TRX_STATE). Figure 9-4. TX Power Ramping for maximum TX Power. 0 TRX_STATE PLL_ON 2 4 6 8 10 12 14 16 18 Length [μs] BUSY_TX SLP_TR PA buffer PA Modulation 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 103 8321A–MCU Wireless–10/11 9.2.4 TX Power Ramping To optimize the output power spectral density (PSD), the PA buffer and PA are enabled sequentially, see in Figure 9-4. In this example the transmission is initiated with the rising edge of pin 11 (SLP_TR). The radio transceiver state changes from PLL_ON to BUSY_TX. The modulation of the frame starts 16µs after SLP_TR rising edge. 9.2.5 Register Description Register 0x05 (PHY_TX_PWR): The PHY_TX_PWR register controls the output power of the transmitter. Figure 9-5. Register PHY_TX_PWR. Bit 7 6 Read/Write Reset value R 0 R/W 0 Bit 3 2 0x05 4 R 0 R 0 1 0 R/W 0 R/W 0 reserved 0x05 Read/Write Reset value 5 PHY_TX_PWR TX_PWR R/W 0 R/W 0 PHY_TX_PWR Bit 3:0 – TX_PWR The register bits TX_PWR determine the TX output power of the radio transceiver. Table 9-4. TX Output Power. Register Bits TX_PWR 104 Value TX Output Power [dBm] 0x0 +3.0 0x1 +2.8 0x2 +2.3 0x3 +1.8 0x4 +1.3 0x5 +0.7 0x6 0.0 0x7 -1 0x8 -2 0x9 -3 0xA -4 0xB -5 0xC -7 0xD -9 0xE -12 0xF -17 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 9.3 Frame Buffer The Atmel AT86RF232 contains a 128 byte dual port SRAM. One port is connected to the SPI interface, the other to the internal transmitter and receiver modules. For data communication, both ports are independent and simultaneously accessible. The Frame Buffer uses the address space 0x00 to 0x7F for RX and TX operation of the radio transceiver and can keep one IEEE 802.15.4 RX or one TX frame of maximum length at a time. Frame Buffer access modes are described in Section 6.2.2. Frame Buffer access conflicts are indicated by an under run interrupt IRQ_6 (TRX_UR). Note: 1. The IRQ_6 (TRX_UR) interrupt also occurs on the attempt to write frames longer than 127 octets to the Frame Buffer. In that case the content of the Frame Buffer cannot be guaranteed. Frame Buffer access is only possible if the digital voltage regulator (DVREG) is turned on. This is valid in all device states except in SLEEP state. An access in P_ON state is possible if pin 17 (CLKM) provides the 1MHz master clock. 9.3.1 Data Management Data in Frame Buffer (received data or data to be transmitted) remains valid as long as: No new frame or other data are written into the buffer over SPI No new frame is received (in any BUSY_RX state) No state change into SLEEP state is made No RESET took place By default there is no protection of the Frame Buffer against overwriting. Therefore, if a frame is received during Frame Buffer read access of a previously received frame, interrupt IRQ_6 (TRX_UR) is issued and the stored data might be overwritten. Even so, the old frame data can be read, if the SPI data rate is higher than the effective over air data rate. For a data rate of 250kb/s a minimum SPI clock rate of 1MHz is recommended. Finally the microcontroller should check the transferred frame data integrity by an FCS check. To protect the Frame Buffer content against being overwritten by newly incoming frames the radio transceiver state should be changed to PLL_ON state after reception. This can be achieved by writing immediately the command PLL_ON to register bits TRX_CMD (register 0x02, TRX_STATE) after receiving the frame, indicated by IRQ_3 (TRX_END). Alternatively, Dynamic Frame Buffer Protection can be used to protect received frames against overwriting, for details refer to Section 11.6. Both procedures do not protect the Frame Buffer from overwriting by the microcontroller. In Extended Operating Mode during TX_ARET operation, see Section 7.2.4, the radio transceiver switches to receive, if an acknowledgement of a previously transmitted frame was requested. During this period received frames are evaluated, but not stored in the Frame Buffer. This allows the radio transceiver to wait for an acknowledgement frame and retry the frame transmission without writing them again. 105 8321A–MCU Wireless–10/11 A radio transceiver state change, except a transition to SLEEP, or RESET state, does not affect the Frame Buffer contents. If the radio transceiver is forced into SLEEP, the Frame Buffer is powered off and the stored data gets lost. 9.3.2 User accessible Frame Content The Atmel AT86RF232 supports an IEEE 802.15.4 compliant frame format as shown in Figure 9-6. Figure 9-6. AT86RF232 Frame Structure. 0 Frame Length [octets] 4 5 Preamble Sequence SFD Duration 4 octets 1 Access SHR not accesible PHY generated 6 PHR n+3 Payload n+5 FCS n+6 LQI(1) n+7 ED(1) n+8 RX_STATUS(1) 3 octets n octets (n <= 128) TX: Frame Buffer content RX: Frame Buffer content Note: 1. Stored into Frame Buffer during frame reception. A frame comprises two sections, the radio transceiver internally generated SHR field and the user accessible part stored in the Frame Buffer. The SHR contains the preamble and the SFD field. The variable frame section contains the PHR and the PSDU including the FCS, see Section 8.2. To access the data follow the procedures described in Section 6.2.2. The frame length information (PHR field) and the PSDU are stored in the Frame Buffer. During frame reception, the link quality indicator (LQI) value, the energy detection (ED) value, and the status information (RX_STATUS) of a received frame are additionally stored, see Section 8.6, Section 8.4, and Section 6.2.2, respectively. The radio transceiver appends these values to the frame data during Frame Buffer read access. If the SRAM read access is used to read an RX frame, the frame length field (PHR) can be accessed at address zero. The SHR cannot be read by the microcontroller. For frame transmission, the PHR and the PSDU needs to be stored in the Frame Buffer. The maximum frame size supported by the radio transceiver is 128 bytes. If the register bit TX_AUTO_CRC_ON is set in register 0x05 (PHY_TX_PWR), the FCS field of the PSDU is replaced by the automatically calculated FCS during frame transmission. There is no need to write the FCS field when using the automatic FCS generation. To manipulate individual bytes of the Frame Buffer a SRAM write access can be used instead. For non IEEE 802.15.4 compliant frames, the minimum frame length supported by the radio transceiver is one byte (Frame Length Field + one byte of data). 9.3.3 Interrupt Handling Access conflicts may occur when reading and writing data simultaneously at the two independent ports of the Frame Buffer, TX/RX BBP and SPI. These ports have their own address counter that points to the Frame Buffer’s current address. Access violations occurs during concurrent Frame Buffer read or write accesses, when the SPI port’s address counter value becomes higher than or equal to that of TX/RX BBP port. 106 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 While receiving a frame, primarily the data needs to be stored in the Atmel AT86RF232 Frame Buffer before reading it. This can be ensured by accessing the Frame Buffer 32µs after IRQ_2 (RX_START) at the earliest. When reading the frame data continuously the SPI data rate shall be lower than 250kb/s to ensure no under run interrupt occurs. To avoid access conflicts and to simplify the Frame Buffer read access Frame Buffer Empty indication may be used, for details refer to Section 11.5. During transmission, an access violation occurs on Frame Buffer write access, when the SPI port’s address counter value becomes less than or equal to that of TX BBP port. Both these access violations may cause data corruption and are indicated by IRQ_6 (TRX_UR) interrupt when using the Frame Buffer access mode. Access violations are not indicated when using the SRAM access mode. Notes: 1. Interrupt IRQ_6 (TRX_UR) is valid 64µs after IRQ_2 (RX_START). The occurrence of the interrupt can be disregarded when reading the first byte of the Frame Buffer between 32µs and 64µs after the RX_START interrupt. 2. If a Frame Buffer read access is not finished until a new frame is received, an IRQ_6 (TRX_UR) interrupt occurs. Nevertheless the old frame data can be read, if the SPI data rate is higher than the effective PHY data rate. A minimum SPI clock rate of 1MHz is recommended in this case. Finally, the microcontroller should check the integrity of the transferred frame data by calculating the FCS. 3. When writing data to the Frame Buffer during frame transmission, the SPI data rate shall be higher than the PHY data rate to ensure no under run interrupt. The first byte of the PSDU data must be available in the Frame Buffer before SFD transmission is complete, which takes 176µs (16µs PA ramp-up + 160µs SHR) from the rising edge of pin 11 (SLP_TR) (see Figure 7-2). 107 8321A–MCU Wireless–10/11 9.4 Voltage Regulators (AVREG, DVREG) The main features of the Voltage Regulator blocks are: Bandgap stabilized 1.8V supply for analog and digital domain Low dropout (LDO) voltage regulator Configurable for usage of external voltage regulator 9.4.1 Overview The internal voltage regulators supply a stabilized voltage to the Atmel AT86RF232. The AVREG provides the regulated 1.8V supply voltage for the analog section and the DVREG supplies the 1.8V supply voltage for the digital section. A simplified schematic of the internal voltage regulator is shown in Figure 9-7. Figure 9-7. Simplified Schematic of AVREG/DVREG. (D)EVDD Bandgap voltage reference 1.25V AVDD, DVDD The voltage regulators require bypass capacitors for stable operation. The value of the bypass capacitors determine the settling time of the voltage regulators. The bypass capacitors shall be placed as close as possible to the pins and shall be connected to ground with the shortest possible traces. 9.4.2 Configuration The voltage regulators can be configured by the register 0x10 (VREG_CTRL). It is recommended to use the internal regulators, but it is also possible to supply the low voltage domains by an external voltage supply. For this configuration, the internal regulators need to be switched off by setting the register bits to the values AVREG_EXT = 1 and DVREG_EXT = 1. A regulated external supply voltage of 1.8V needs to be connected to the pins 13, 14 (DVDD) and pin 29 (AVDD). When turning on the external supply, ensure a sufficiently long stabilization time before interacting with the AT86RF232. 9.4.3 Data Interpretation The status bits AVDD_OK = 1 and DVDD_OK = 1 of register 0x10 (VREG_CTRL) indicate an enabled and stable internal supply voltage. Reading value zero indicates a disabled or internal supply voltage not settled to the final value. 108 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 9.4.4 Register Description Register 0x10 (VREG_CTRL): The VREG_CTRL register controls the use of the voltage regulators and indicates the status of these. Figure 9-8. Register VREG_CTRL. Bit 0x10 Read/Write Reset value Bit 0x10 Read/Write Reset value 7 6 AVREG_EXT AVDD_OK 5 R/W 0 R 0 R 0 1 3 2 DVREG_EXT DVDD_OK R/W 0 R 0 4 reserved VREG_CTRL R 0 0 reserved R 0 VREG_CTRL R 0 Bit 7 - AVREG_EXT If set this register bit disables the internal analog voltage regulator to apply an external regulated 1.8V supply for the analog building blocks. Table 9-5. AVREG_EXT. Register Bits Value AVREG_EXT 0 Description Internal voltage regulator enabled, analog section 1 Internal voltage regulator disabled, use external regulated 1.8V supply voltage for the analog section Bit 6 - AVDD_OK This register bit indicates if the internal 1.8V regulated voltage supply AVDD has settled. The bit is set to logic high, if AVREG_EXT = 1. Table 9-6. AVDD_OK. Register Bits AVDD_OK Value Description 0 Analog voltage regulator is disabled or supply voltage not stable 1 Analog supply voltage has been settled Bit 3 - DVREG_EXT If set this register bit disables the internal digital voltage regulator to apply an external regulated 1.8V supply for the digital building blocks. Table 9-7. DVREG_EXT. Register Bits Value DVREG_EXT 0 Description Internal voltage regulator enabled, digital section 1 Internal voltage regulator disabled, use external regulated 1.8V supply voltage for the digital section 109 8321A–MCU Wireless–10/11 Bit 2 - DVDD_OK This register bit indicates if the internal 1.8V regulated voltage supply DVDD has settled. The bit is set to logic high, if DVREG_EXT = 1. Table 9-8. DVDD_OK. Register Bits DVDD_OK Note: 110 1. Value Description 0 Digital voltage regulator is disabled or supply voltage not stable 1 Digital supply voltage has settled While the reset value of this bit is zero, any practical access to the register is only possible when DVREG is active. So this bit is normally always read out as one. AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 9.5 Battery Monitor (BATMON) The main features of the battery monitor are: Configurable voltage threshold range: 1.7V to 3.675V Generates an interrupt when supply voltage drops below a threshold 9.5.1 Overview The Atmel AT86RF232 battery monitor (BATMON) detects and indicates a low supply voltage of the external supply voltage at pin 28 (EVDD). This is done by comparing the voltage on the external supply pin 28 (EVDD) with a configurable internal threshold voltage. A simplified schematic of the BATMON with the most important input and output signals is shown in Figure 9-9. Figure 9-9. Simplified Schematic of BATMON. EVDD BATMON_HR + DAC 4 BATMON_VTH Threshold Voltage For input-to-output mapping see control register 0x11 (BATMON) BATMON_OK - „1“ clear D Q BATMON_IRQ 9.5.2 Configuration The BATMON can be configured using the register 0x11 (BATMON). Register bits BATMON_VTH sets the threshold voltage. It is configurable with a resolution of 75mV in the upper voltage range (BATMON_HR = 1) and with a resolution of 50mV in the lower voltage range (BATMON_HR = 0), for details refer to register 0x11 (BATMON). 9.5.3 Data Interpretation The signal register bit BATMON_OK of register 0x11 (BATMON) monitors the current value of the battery voltage: If BATMON_OK = 0, the battery voltage is lower than the threshold voltage If BATMON_OK = 1, the battery voltage is higher than the threshold voltage After setting a new threshold, the value BATMON_OK should be read out to verify the current supply voltage value. Note: 1. The battery monitor is inactive during P_ON, and SLEEP states, see register bits TRX_STATUS (register 0x01, TRX_STATUS). 111 8321A–MCU Wireless–10/11 9.5.4 Interrupt Handling A supply voltage drop below the configured threshold value is indicated by an interrupt IRQ_7 (BAT_LOW), see Section 6.6. Note: 1. The Atmel AT86RF232 IRQ_7 (BAT_LOW) BATMON_OK changes from one to zero. interrupt is issued only if No interrupt is generated when: The battery voltage is under the default 1.8V threshold at power-on (BATMON_OK was never one), or A new threshold is set, which is still above the current supply voltage (BATMON_OK remains zero). When the battery voltage is close to the programmed threshold voltage, noise or temporary voltage drops may generate unwanted interrupts. To avoid this: Disable the IRQ_7 (BAT_LOW) in register 0x0E (IRQ_MASK) and treat the battery as empty, or Set a lower threshold value. 9.5.5 Register Description Register 0x11 (BATMON): The BATMON register signals and configures the battery monitor to observe the supply voltage at pin 28 (EVDD). Figure 9-10. Register BATMON. Bit 7 0x11 6 reserved Read/Write Reset value R 0 R/W 0 Bit 3 2 0x11 Read/Write Reset value 5 4 BATMON_OK BATMON_HR R 0 R/W 0 1 0 R/W 1 R/W 0 BATMON_VTH R/W 0 R/W 0 BATMON BATMON Bit 5 - BATMON_OK The register bit BATMON_OK indicates the level of the external supply voltage with respect to the programmed threshold BATMON_VTH. Table 9-9. BATMON_OK. 112 Register Bits Value Description BATMON_OK 0 The battery voltage is below the threshold 1 The battery voltage is above the threshold AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Bit 4 - BATMON_HR The register bit BATMON_HR sets the range and resolution of the battery monitor. Table 9-10. BATMON_HR. Register Bits Value Description BATMON_HR 0 Enables the low range, see BATMON_VTH 1 Enables the high range, see BATMON_VTH Bit 3:0 – BATMON_VTH The threshold values for the battery monitor are set by register bits BATMON_VTH. Table 9-11. Battery Monitor Threshold Voltages. Value BATMON_VTH Voltage [V] BATMON_HR = 1 Voltage [V] BATMON_HR = 0 0x0 2.550 1.70 0x1 2.625 1.75 0x2 2.700 1.80 0x3 2.775 1.85 0x4 2.850 1.90 0x5 2.925 1.95 0x6 3.000 2.00 0x7 3.075 2.05 0x8 3.150 2.10 0x9 3.225 2.15 0xA 3.300 2.20 0xB 3.375 2.25 0xC 3.450 2.30 0xD 3.525 2.35 0xE 3.600 2.40 0xF 3.675 2.45 113 8321A–MCU Wireless–10/11 9.6 Crystal Oscillator (XOSC) The main crystal oscillator features are: 16MHz amplitude controlled crystal oscillator 180µs typical settling time after leaving SLEEP state Configurable trimming capacitance array Configurable clock output (CLKM) 9.6.1 Overview The crystal oscillator generates the reference frequency for the Atmel AT86RF232. All other internally generated frequencies of the radio transceiver are derived from this unique frequency. Therefore, the overall system performance is mainly determined by the accuracy of crystal reference frequency. The external components of the crystal oscillator should be selected carefully and the related board layout should be done with caution (see Chapter 5). The register 0x12 (XOSC_CTRL) provides access to the control signals of the oscillator. Two operating modes are supported. It is recommended to use the integrated oscillator setup as described in Figure 9-11; nevertheless a reference frequency can be fed to the internal circuitry by using an external clock reference as shown in Figure 9-12. 9.6.2 Integrated Oscillator Setup Using the internal oscillator, the oscillation frequency depends on the load capacitance between the crystal pin 26 (XTAL1) and pin 25 (XTAL2). The total load capacitance CL must be equal to the specified load capacitance of the crystal itself. It consists of the external capacitors CX and parasitic capacitances connected to the XTAL nodes. Figure 9-11 shows all parasitic capacitances, such as PCB stray capacitances and the pin input capacitance, summarized to CPAR. Figure 9-11. Simplified XOSC Schematic with External Components. CPAR CX CX CPAR VDD XTAL1 EVDD 16MHz XTAL2 PCB AT86RF232 CTRIM CTRIM XTAL_TRIM[3:0] XTAL_TRIM[3:0] EVDD 114 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Additional internal trimming capacitors CTRIM are available. Any value in the range from 0pF to 4.5pF with a 0.3pF resolution is selectable using XTAL_TRIM of register 0x12 (XOSC_CTRL). To calculate the total load capacitance, the following formula can be used CL [pF] = 0.5 x (CX + CTRIM + CPAR). The Atmel AT86RF232 trimming capacitors provide the possibility of reducing frequency deviations caused by production process variations or by external components tolerances. Note that the oscillation frequency can only be reduced by increasing the trimming capacitance. The frequency deviation caused by one step of CTRIM decreases with increasing crystal load capacitor values. An amplitude control circuit is included to ensure stable operation under different operating conditions and for different crystal types. Enabling the crystal oscillator in P_ON state and after leaving SLEEP state causes a slightly higher current during the amplitude build-up phase to guarantee a short start-up time. At stable operation, the current is reduced to the amount necessary for a robust operation. This also keeps the drive level of the crystal low. Generally, crystals with a higher load capacitance are less sensitive to parasitic pulling effects caused by external component variations or by variations of board and circuit parasitic. On the other hand, a larger crystal load capacitance results in a longer startup time and a higher steady state current consumption. 9.6.3 External Reference Frequency Setup When using an external reference frequency, the signal must be connected to pin 26 (XTAL1) as indicated in Figure 9-12 and the register bits XTAL_MODE (register 0x12, XOSC_CTRL) need to be set to the external oscillator mode for power saving reasons. The oscillation peak-to-peak amplitude shall be between 100mV and 500mV, the optimum range is between 400mV and 500mV. Pin 25 (XTAL2) should not be wired. It is possible, among other waveforms, to use sine and square wave signals. Note: 1. The quality of the external reference (that is phase noise) determines the system performance. Figure 9-12. Setup for Using an External Frequency Reference. 16MHz XTAL1 XTAL2 PCB AT86RF232 9.6.4 Master Clock Signal Output (CLKM) The generated reference clock signal can be fed to a microcontroller using pin 17 (CLKM). The internal 16MHz raw clock can be divided by an internal prescaler. Thus, clock frequencies of 1MHz or 62.5kHz can be supplied by pin 17 (CLKM). The CLKM frequency is configurable using register 0x03 (TRX_CTRL_0). There are two possibilities to change the CLKM frequency. If CLKM_SHA_SEL = 0, changing the register bits CLKM_CTRL (register 0x03, TRX_CTRL_0) immediately affects a glitch 115 8321A–MCU Wireless–10/11 free CLKM clock rate change. Otherwise (CLKM_SHA_SEL = 1) the new clock rate is supplied when leaving the SLEEP state the next time. To reduce power consumption and spurious emissions, it is recommended to turn off the Atmel AT86RF232 CLKM clock when not in use. Note: 1. During reset procedure, see Section 7.1.2.7, register bits CLKM_CTRL are shadowed. Although the clock setting of CLKM remains after reset, a read access to register bits CLKM_CTRL delivers the reset value one. For that reason it is recommended to write the previous configuration (before reset) to register bits CLKM_CTRL to align the radio transceiver behavior and register configuration. Otherwise the CLKM clock rate is set back to the reset value (1MHz) after the next SLEEP cycle. 9.6.5 Register Description Register 0x03 (TRX_CTRL_0): The TRX_CTRL_0 register controls the CLKM clock rate. Figure 9-13. Register TRX_CTRL_0. Bit 7 6 R/W 0 R 0 3 2 0x03 4 R/W 0 R/W 0 1 0 reserved Read/Write Reset value Bit 0x03 5 CLKM_SHA_SEL Read/Write Reset value TRX_CTRL_0 CLKM_CTRL R/W 1 R/W 0 R/W 0 TRX_CTRL_0 R/W 1 Bit 3 - CLKM_SHA_SEL The register bit CLKM_SHA_SEL defines if a new clock rate, defined by CLKM_CTRL, is set immediately or after the next SLEEP cycle. Table 9-12. CLKM_SHA_SEL. Register Bits Value CLKM_SHA_SEL Description 0 CLKM clock rate change appears immediately 1 CLKM clock rate change appears after SLEEP cycle Bit 2:0 - CLKM_CTRL The register bits CLKM_CTRL sets the clock rate of pin 17 (CLKM). Table 9-13. CLKM_CTRL. Register Bits Value Description CLKM_CTRL 0 No clock at pin CLKM, pin set to logic low 1 1MHz 7 62.5kHz (IEEE 802.15.4 symbol rate) All other values are reserved 116 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Register 0x12 (XOSC_CTRL): The XOSC_CTRL register controls the operation of the crystal oscillator. Figure 9-14. Register XOSC_CTRL. Bit 7 6 R/W 1 R/W 1 3 2 0x12 Read/Write Reset value Bit 4 R/W 1 R/W 1 1 0 R/W 0 R/W 0 XTAL_MODE 0x12 Read/Write Reset value 5 XOSC_CTRL XTAL_TRIM R/W 0 R/W 0 XOSC_CTRL Bit 7:4 - XTAL_MODE The register bits XTAL_MODE sets the operating mode of the crystal oscillator. Table 9-14. XTAL_MODE. Register Bits Value Description XTAL_MODE 0x5 Internal crystal oscillator disabled, use external reference frequency 0xF Internal crystal oscillator enabled and XOSC voltage regulator enabled All other values are reserved For normal operation the default value is set to XTAL_MODE = 0xF after reset. Using an external clock source it is recommended to set XTAL_MODE = 0x5. Bit 3:0 - XTAL_TRIM The register bits XTAL_TRIM controls internal capacitance arrays connected to pin 26 (XTAL1) and pin 25 (XTAL2). Table 9-15. XTAL_TRIM. Register Bits XTAL_TRIM Value 0x0 Description A capacitance value in the range from 0pF to 4.5pF is selectable with a resolution of 0.3pF. Valid values are [0xF, 0xE, …, 0x0]. 117 8321A–MCU Wireless–10/11 9.7 Frequency Synthesizer (PLL) The main PLL features are: Generate RX/TX frequencies for all IEEE 802.15.4 – 2.4GHz channels Autonomous calibration loops for stable operation within the operating range Two PLL-interrupts for status indication Fast PLL settling to support frequency hopping 9.7.1 Overview The PLL generates the RF frequencies for the Atmel AT86RF232. During receive operation the frequency synthesizer works as a local oscillator on the radio transceiver receive frequency, during transmit operation the voltage-controlled oscillator (VCO) is directly modulated to generate the RF transmit signal. The frequency synthesizer is implemented as a fractional-N PLL. Two calibration loops ensure correct PLL functionality within the specified operating limits. 9.7.2 RF Channel Selection The PLL is designed to support 16 channels in the 2.4GHz ISM band with channel spacing of 5MHz according to IEEE 802.15.4. The center frequency of these channels is defined as follows: Fc [MHz] = 2405 + 5 x (k – 11), for k = 11, 12, ..., 26 where k is the channel number. The channel k is selected by register bits CHANNEL (register 0x08, PHY_CC_CA). 9.7.3 Frequency Agility When the PLL is enabled during state transition from TRX_OFF to PLL_ON, the settling time is typically tTR4 = 80µs, including settling of the analog voltage regulator (AVREG) and PLL self calibration, refer to Table 7-2 and Figure 13-12. A lock of the PLL is indicated with an interrupt IRQ_0 (PLL_LOCK). Switching between 2.4GHz ISM band channels in PLL_ON or RX_ON states is typically done within tPLL_SW = 11µs. This makes the radio transceiver highly suitable for frequency hopping applications. When starting the transmit procedure the PLL frequency is changed to the transmit frequency within a period of tRX_TX = 16µs before starting the transmission. After the transmission the PLL settles back to the receive frequency within a period of tTX_RX = 32µs. This frequency step does not generate an interrupt IRQ_0 (PLL_LOCK) or IRQ_1 (PLL_UNLOCK) within these periods. 9.7.4 Calibration Loops Due to variation of temperature, supply voltage and part-to-part variations of the radio transceiver the VCO characteristics may vary. To ensure a stable operation, two automated control loops are implemented, center frequency (CF) tuning and delay cell (DCU) calibration. Both calibration loops are initiated automatically when the PLL is enabled during state transition from TRX_OFF to PLL_ON state. Additionally, center frequency calibration is initiated when the PLL changes to a different channel center frequency. 118 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 If the Atmel AT86RF232 PLL operates for a long time on the same channel, for example more than five minutes, or the operating temperature changes significantly, it is recommended to initiate the calibration loops manually. Both calibration loops can be initiated manually by setting PLL_CF_START = 1 (register 0x1A, PLL_CF) and register bit PLL_DCU_START = 1 (register 0x1B, PLL_DCU). To start the calibration the device must be in PLL_ON or RX_ON state. The completion of the center frequency tuning is indicated by a PLL_LOCK interrupt. Both calibration loops may be run simultaneously. 9.7.5 Interrupt Handling Two different interrupts indicate the PLL status (refer to register 0x0F). IRQ_0 (PLL_LOCK) indicates that the PLL has locked. IRQ_1 (PLL_UNLOCK) interrupt indicates an unexpected unlock condition. A PLL_LOCK interrupt clears any preceding PLL_UNLOCK interrupt automatically and vice versa. An IRQ_0 (PLL_LOCK) interrupt is supposed to occur in the following situations: State change from TRX_OFF to PLL_ON / RX_ON / TX_ARET_ON / RX_AACK_ON Channel change in states PLL_ON / RX_ON / TX_ARET_ON / RX_AACK_ON Any other occurrences of PLL interrupts indicate erroneous behavior and require checking of the actual device status. The state transition from BUSY_TX to PLL_ON after successful transmission does not generate an IRQ_0 (PLL_LOCK) within the settling period. 9.7.6 Register Description Register 0x08 (PHY_CC_CCA): The PHY_CC_CCA register is a multi-purpose register that controls CCA configuration, CCA measurement, and the IEEE 802.15.4 channel setting. Figure 9-15. Register PHY_CC_CCA. Bit 0x08 Read/Write Reset value Bit 7 6 CCA_REQUEST R/W 0 R/W 0 3 2 0x08 Read/Write Reset value 5 CCA_MODE 4 CHANNEL R/W 1 R/W 0 1 0 R/W 1 R/W 1 CHANNEL R/W 1 R/W 0 PHY_CC_CCA PHY_CC_CCA 119 8321A–MCU Wireless–10/11 Bit 4:0 – CHANNEL The register bits CHANNEL define the RX/TX channel. The channel assignment is according to IEEE 802.15.4. Table 9-16. Channel Assignment for IEEE 802.15.4 – 2.4GHz Band. Register Bits Value IEEE 802.15.4 Channel Number k Center Frequency [MHz] CHANNEL 0x0B 11 2405 0x0C 12 2410 0x0D 13 2415 0x0E 14 2420 0x0F 15 2425 0x10 16 2430 0x11 17 2435 0x12 18 2440 0x13 19 2445 0x14 20 2450 0x15 21 2455 0x16 22 2460 0x17 23 2465 0x18 24 2470 0x19 25 2475 0x1A 26 2480 All other values are reserved Register 0x1A (PLL_CF): The PLL_CF register controls the operation of the center frequency calibration loop. Figure 9-16. Register PLL_CF. Bit 0x1A Read/Write Reset value Bit 7 6 120 4 reserved R/W 0 R/W 1 3 2 0x1A Read/Write Reset value 5 PLL_CF_START PLL_CF R/W 0 R/W 1 1 0 R/W 1 R/W 1 PLL_CF R/W 0 R/W 1 PLL_CF AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Bit 7 - PLL_CF_START Manual start of center frequency calibration cycle. Table 9-17. PLL_CF_START. Register Bits Value PLL_CF_START Description 0 Center frequency calibration cycle is finished 1 Initiates center frequency calibration cycle PLL_CF_START = 1 initiates the center frequency calibration. The calibration cycle has finished after tPLL_CF = 8µs (typ.). The register bit is cleared immediately after finishing the calibration. Bit 3:0 - PLL_CF VCO center frequency control word. Table 9-18. PLL_CF. Register Bits Value PLL_CF Description 0x7 Initial CF start word Valid values are [0xF, 0xE, …, 0x0] Register 0x1B (PLL_DCU): The PLL_DCU register controls the operation of the delay cell calibration loop. Figure 9-17. Register PLL_DCU. Bit 0x1B 7 6 5 PLL_DCU_START Read/Write Reset value reserved R/W 0 R 0 3 2 Bit 0x1B Read/Write Reset value 4 PLL_DCU R/W 1 R/W 0 1 0 R/W 0 R/W 0 reserved R/W 0 R/W 0 PLL_DCU Bit 7 - PLL_DCU_START Manual start of delay cell calibration cycle. Table 9-19. PLL_DCU_START. Register Bits PLL_DCU_START Value Description 0 Delay cell calibration cycle is finished 1 Initiates delay cell calibration cycle PLL_DCU_START = 1 initiates the delay cell calibration. The calibration cycle has finished after tPLL_DCU = 6µs. The register bit is cleared immediately after finishing the calibration. 121 8321A–MCU Wireless–10/11 9.8 Automatic Filter Tuning (FTN) 9.8.1 Overview The Atmel AT86RF232 FTN is incorporated to compensate device tolerances for temperature, supply voltage variations as well as part-to-part variations of the radio transceiver. The filter-tuning result is used to correct the analog baseband filter transfer function and the PLL loop-filter time constant, refer to Chapter 4. An FTN calibration cycle is initiated automatically when entering the TRX_OFF state from the P_ON, SLEEP, or RESET state. Although receiver and transmitter are very robust against these variations, it is recommended to initiate the FTN manually if the radio transceiver does not use the SLEEP state. If necessary, a calibration cycle is to be initiated in states TRX_OFF, PLL_ON or RX_ON. The recommended calibration interval is five minutes or less. 9.8.2 Register Description Register 0x18 (FTN_CTRL): The FTN_CTRL register controls the operation of the filter tuning network calibration loop. Figure 9-18. Register FTN_CTRL. Bit 0x18 Read/Write Reset value Bit 7 6 5 FTN_START R/W 0 R/W 1 3 2 0x18 Read/Write Reset value 4 reserved FTN_CTRL R/W 0 R/W 1 1 0 R/W 0 R/W 0 reserved R/W 1 R/W 0 FTN_CTRL Bit 7 - FTN_START Manual start of a filter calibration cycle. Table 9-20. FTN_START. Register Bits Value FTN_START 0 Description Filter calibration is finished 1 Initiates filter calibration cycle FTN_START = 1 initiates the filter tuning network calibration. When the calibration cycle has finished after tFTN = 25µs (typ.). The register bit is cleared immediately after finishing the calibration. 122 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 10 Radio Transceiver Usage This section describes basic procedures to receive and transmit frames using the Atmel AT86RF232. For a detailed programming description refer to reference [6]. 10.1 Frame Receive Procedure A frame reception comprises of two actions: The PHY listens for, receives and demodulates the frame to the Frame Buffer and signalizes the reception to the microcontroller. After or while that the microcontroller read the available frame data from the Frame Buffer via the SPI interface. While in state RX_ON or RX_AACK_ON the radio transceiver searches for incoming frames on the selected channel. Assuming the appropriate interrupts are enabled, a detection of an IEEE 802.15.4 compliant frame is indicated by interrupt IRQ_2 (RX_START) first. The frame reception is completed when issuing interrupt IRQ_3 (TRX_END). Different Frame Buffer read access scenarios are recommended for: Non-time critical applications read access starts after IRQ_3 (TRX_END) Time-critical applications read access starts after IRQ_2 (RX_START) Waiting for IRQ_3 (TRX_END) interrupt before starting a Frame Buffer read access is recommended for operations considered to be none time critical. Figure 10-1 illustrates the frame receive procedure using IRQ_3 (TRX_END). Figure 10-1. Transactions between AT86RF232 and Microcontroller during Receive. Read IRQ status, pin 24 (IRQ) deasserted IRQ issued (IRQ_3) Read IRQ status, pin 24 (IRQ) deasserted Microcontroller AT86RF232 IRQ issued (IRQ_2) Read frame data (Frame Buffer access) Critical protocol timing could require starting the Frame Buffer read access after interrupt IRQ_2 (RX_START). The first byte of the frame data can be read 32µs after the IRQ_2 (RX_START) interrupt. The microcontroller must ensure to read slower than the frame is received. Otherwise a Frame Buffer under run occurs, IRQ_6 (TRX_UR) is issued, and the frame data may be not valid. To avoid this, the Frame Buffer read access can be controlled by using a Frame Buffer Empty indicator, refer to Section 11.5. 123 8321A–MCU Wireless–10/11 10.2 Frame Transmit Procedure A frame transmission comprises of two actions, a Frame Buffer write access and the transmission of the Frame Buffer content. Both actions can be run in parallel if required by critical protocol timing. Figure 10-2 illustrates the Atmel AT86RF232 frame transmit procedure, when writing and transmitting the frame consecutively. After a Frame Buffer write access, the frame transmission is initiated by asserting pin 11 (SLP_TR) or writing command TX_START to register bits TRX_CMD (register 0x02, TRX_STATE), while the radio transceiver is in state PLL_ON or TX_ARET_ON. The completion of the transaction is indicated by interrupt IRQ_3 (TRX_END). Figure 10-2. Transaction between AT86RF232 and Microcontroller during Transmit. Write TRX_CMD = TX_START, or assert pin 11 (SLP_TR) IRQ_3 (TRX_END) issued Microcontroller AT86RF232 Write frame data (Frame Buffer access) Read IRQ_STATUS register, pin 24 (IRQ) deasserted Alternatively, a frame transmission can be started first, followed by the Frame Buffer write access (PSDU data); refer to Figure 10-3. This is applicable for time critical applications. Initiating a transmission, either by asserting pin 11 (SLP_TR) or command TX_START to register bits TRX_CMD (register 0x02, TRX_STATE), the radio transceiver starts transmitting the SHR, which is internally generated. This first phase requires 16µs for PLL settling and 160μs for SHR transmission. The PHR must be available in the Frame Buffer before this time elapses. Furthermore the SPI data rate must be higher than the PHY data rate to ensure that no Frame Buffer under run occurs. Figure 10-3. Time Optimized Frame Transmit Procedure. Write frame data (Frame Buffer access) IRQ_3 (TRX_END) issued Microcontroller AT86RF232 Write TRX_CMD = TX_START, or assert pin 11 (SLP_TR) Read IRQ_STATUS register, pin 24 (IRQ) deasserted 124 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 11 AT86RF232 Extended Feature Set 11.1 Security Module (AES) The security module (AES) is characterized by: Hardware accelerated encryption and decryption Compatible with AES-128 standard (128-bit key and data block size) ECB (encryption/decryption) mode and CBC (encryption) mode support Stand-alone operation, independent of other blocks 11.1.1 Overview The security module is based on an AES-128 core according to FIPS197 standard, refer to [5]. The security module works independent of other building blocks of the Atmel AT86RF232, encryption and decryption can be performed in parallel to a frame transmission or reception. Controlling the security block is implemented as an SRAM access to address space 0x82 to 0x94. A Fast SRAM access mode allows simultaneously writing new data and reading data from previously processed data within the same SPI transfer. This access procedure is used to reduce the turnaround time for ECB and CBC modes, see Section 11.1.5. In addition, the security module contains another 128-bit register to store the initial key used for security operations. This initial key is not modified by the security module. 11.1.2 Security Module Preparation The use of the security module requires a configuration of the security engine before starting a security operation. The following steps are required: Table 11-1. AES Engine Configuration Steps. Step Description Description Section 1 Key Setup Write encryption or decryption key to SRAM 11.1.3 2 AES mode Select AES mode: ECB or CBC Select encryption or decryption 11.1.4.1 11.1.4.2 3 Write Data Write plaintext or cipher text to SRAM 11.1.5 4 Start operation Start AES operation 5 Read Data Read cipher text or plaintext from SRAM 11.1.5 Before starting any security operation a key must be written to the security engine, refer to Section 11.1.3. The key set up requires the configuration of the AES engine KEY mode using register bits AES_MODE (SRAM address 0x83, AES_CTRL). The following step selects the AES mode, either electronic code book (ECB) or cipher block chaining (CBC). These modes are explained more in detail in Section 11.1.4. Further, encryption or decryption must be selected with register bit AES_DIR (SRAM address 0x83, AES_CTRL). As next the 128-bit plain text or ciphertext data has to be provided to the AES hardware engine. The data uses the SRAM address range 0x84 – 0x93. 125 8321A–MCU Wireless–10/11 The encryption or decryption is initiated with register bit AES_REQUEST = 1 (SRAM address 0x83, AES_CTRL or the mirrored version with SRAM address 0x94, AES_CTRL_MIRROR). The AES module control registers are only accessible using SRAM read and write accesses on address space 0x82 to 0x94. A configuration of the AES mode, providing the data and the start of the operation can be combined within one SRAM access. Notes: 1. No additional register access is required to operate the security block. 2. Access to the security block is not possible while the radio transceiver is in SLEEP, or RESET state. 3. All configurations of the security module, the SRAM content and keys are reset during RESET state. 11.1.3 Security Key Setup The setup of the key is prepared by setting register bits AES_MODE = 1 (SRAM address 0x83, AES_CTRL). Afterwards the 128-bit key must be written to SRAM addresses 0x84 through 0x93 (registers AES_KEY). It is recommended to combine the setting of control register 0x83 (AES_CTRL) and the 128-bit key transfer using only one SRAM access starting from address 0x83. The address space for the 128-bit key and 128-bit data is identical from programming point of view. However, both use different pages which are selected by register bit AES_MODE before storing the data. A read access to registers AES_KEY (0x84 – 0x93) returns the last round key of the preceding security operation. After an ECB encryption operation, this is the key that is required for the corresponding ECB decryption operation. However, the initial AES key, written to the security module in advance of an AES run, see step one in Table 11-1, is not modified during an AES operation. This initial key is used for the next AES run even it cannot be read from AES_KEY. Note: 1. ECB decryption is not required for IEEE 802.15.4 or ZigBee security processing. The Atmel AT86RF232 provides this functionality as an additional feature. 11.1.4 Security Operation Modes 11.1.4.1 Electronic Code Book (ECB) ECB is the basic operating mode of the security module. After setting up the initial AES key, register bits AES_MODE = 0 (SRAM address 0x83, AES_CTRL) sets up ECB mode. Register bit AES_DIR (SRAM address 0x83, AES_CTRL) selects the direction, either encryption or decryption. The data to be processed has to be written to SRAM addresses 0x84 through 0x93 (registers AES_STATE). An example for a programming sequence is shown in Figure 11-1. This example assumes a suitable key has been loaded before. A security operation can be started within one SRAM access by appending the start command AES_REQUEST = 1 (register 0x94, AES_CTRL_MIRROR) to the SPI sequence. Register AES_CTRL_MIRROR is a mirrored version of register 0x83 (AES_CTRL). 126 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Figure 11-1. ECB Programming SPI Sequence – Encryption. byte 0 (cmd.) byte 1 (address) byte 2 (AES cmd) byte 3 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 SRAM write 0x83 data_0[7:0] …. byte 18 byte 19 (AES cmd) data_15[7:0] 1 0 0 0 0 0 0 0 ECB, encryption AES start Summarizing, the following steps are required to perform a security operation using only one Atmel AT86RF232 SPI access: 1. Configure SPI access a) SRAM write, refer to Section 6.2.3 b) Start address 0x83 2. Configure AES operation address 0x83: select ECB mode, direction 3. Write 128-bit data block addresses 0x84 – 0x93: either plain or ciphertext 4. Start AES operation address 0x94: start AES operation, ECB mode This sequence is recommended because the security operation is configured and started within one SPI transaction. The ECB encryption operation is illustrated in Figure 11-2. Figure 11-3 shows the ECB decryption mode, which is supported in a similar way. Figure 11-2. ECB Mode – Encryption. Plaintext Encryption Key Block Cipher Encryption Plaintext Encryption Key Ciphertext Block Cipher Encryption Ciphertext Figure 11-3. ECB Mode – Decryption. Ciphertext Decryption Key Block Cipher Decryption Plaintext Ciphertext Decryption Key Block Cipher Decryption Plaintext 127 8321A–MCU Wireless–10/11 When decrypting, due to the nature of AES algorithm, the initial key to be used is not the same as the one used for encryption, but rather the last round key instead. This last round key is the content of the key address space stored after running one full encryption cycle, and must be saved for decryption. If the decryption key has not been saved, it has to be recomputed by first running a dummy encryption (of an arbitrary plaintext) using the original encryption key, then fetching the resulting round key from the key memory, and writing it back into the key memory as the decryption key. ECB decryption is not used by either IEEE 802.15.4 or ZigBee frame security. Both of these standards do not directly encrypt the payload, but rather a nonce instead, and protect the payload by applying an XOR operation between the resulting (AES-) cipher text and the original payload. As the nonce is the same for encryption and decryption only ECB encryption is required. Decryption is performed by XORing the received cipher text with its own encryption result respectively, which results in the original plaintext payload upon success. 11.1.4.2 Cipher Block Chaining (CBC) In CBC mode, the result of a previous AES operation is XORed with the new incoming vector, forming the new plaintext to encrypt, see Figure 11-4. This mode is used for the computation of a cryptographic checksum (message integrity code, MIC). Figure 11-4. CBC Mode – Encryption. Plaintext Encryption Key Initialization Vector (IV) Block Cipher Encryption Encryption Key Plaintext Block Cipher Encryption Ciphertext Ciphertext ECB mode CBC mode After preparing the AES key and defining the AES operation direction using Atmel AT86RF232 SRAM register bit AES_DIR, the data has to be provided to the AES engine and the CBC operation can be started. The first CBC run has to be configured as ECB to process the initial data (plaintext XORed with an initialization vector provided by the microcontroller). All succeeding AES runs are to be configured as CBC by setting register bits AES_MODE = 2 (register 0x83, AES_CTRL). Register bit AES_DIR (register 0x83, AES_CTRL) must be set to AES_DIR = 0 to enable AES encryption. The data to be processed has to be transferred to the SRAM starting with address 0x84 to 0x93 (register AES_STATE). Setting register bit AES_REQUEST = 1 (register 0x94, AES_CTRL_MIRROR) as described in Section 11.1.4 starts the first encryption within one SRAM access. This causes the next 128 bits of plaintext data to be XORed with the previous cipher text data, see Figure 11-4. According to IEEE 802.15.4 the input for the very first CBC operation has to be prepared by a XORing a plaintext with an initialization vector (IV). The value of the 128 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 initialization vector is zero. However, for non-compliant usage any other initialization vector can be used. This operation has to be prepared by the microcontroller. 1. The IEEE 802.15.4-2006 standard MIC algorithm requires CBC mode encryption only, as it implements a one-way hash function. Note: 11.1.5 Data Transfer – Fast SRAM Access The ECB and CBC modules including the AES core are clocked with 16MHz. One AES operation takes tAES = 23.4µs to execute, refer to Table 7-2. That means that the processing of the data is usually faster than the transfer of the data via the SPI interface. To reduce the overall processing time the Atmel AT86RF232 provides a Fast SRAM access for the address space 0x82 to 0x94. Figure 11-5. Packet Structure – Fast SRAM Access Mode. AES run #n AES run #0 AES access #0 AES access #1 AES access #n+1 cmd add cfg P0 P1 ... P14 P15 start cmd add cfg P0 P1 ... P14 P15 start cmd add cfg xx MISO stat xx ... stat xx ... C13 C14 C15 stat xx Address xx xx 0x83 xx xx xx ... xx 0x94 xx xx C0 0x83 ... MOSI ... 0x94 byte 0 (cmd) byte 1 (addr.) byte 2 (cfg) byte 3 byte 4 MOSI SRAM write address 0x83 <AES_CTRL> P0[7:0] P1[7:0] MISO PHY_STATUS XX XX XX C0[7:0] 0x83 0x84 0x85 Address Note: xx 0x83 xx xx C0 ... xx xx start ... C13 C14 C15 ... byte 18 byte 19 (start) ... P15[7:0] <AES_CTRL>(1) ... C14[7:0] C15[7:0] 0x93 0x94 0x94 1. Byte 19 is the mirrored version of register AES_CTRL on SRAM address 0x94, see register description AES_CTRL_MIRROR for details. In contrast to a standard SRAM access, refer to Section 6.2.3, the Fast SRAM access allows writing and reading of data simultaneously during one SPI access for consecutive AES operations (AES run). For each byte P0 transferred to pin 22 (MOSI) for example in “AES access #1”, see Figure 11-5 (lower part), the previous content of the respective AES register C0 is clocked out at pin 20 (MISO) with an offset of one byte. In the example shown in Figure 11-5 the initial plaintext P0 – P15 is written to the SRAM within “AES access #0”. The last command on address 0x94 (AES_CTRL_MIRROR) starts the AES operation (“AES run #0”). In the next “AES access #1” new plaintext data P0 – P15 is written to the SRAM for the second AES run, in parallel the ciphertext C0 – C15 from the first AES run is clocked out at pin MISO. To read the ciphertext from the last “AES run #(n)” one dummy “AES access #(n+1)” is needed. Note: 2. The SRAM write access always overwrites the previous processing result. 129 8321A–MCU Wireless–10/11 The Fast SRAM access automatically applies to all write operations to SRAM addresses 0x82 to 0x94. 11.1.6 Start of Security Operation and Status A security operation is started within one Atmel AT86RF232 SRAM access by appending the start command AES_REQUEST = 1 (register 0x94, AES_CTRL_MIRROR) to the SPI sequence. Register AES_CTRL_MIRROR is a mirrored version of register 0x83 (AES_CTRL). The status of the security processing is indicated by register 0x82 (AES_STATUS). After tAES = 24µs (max.) AES processing time register bit AES_DONE changes to 1 (register 0x82, AES_STATUS) indicating that the security operation has finished. 11.1.7 SRAM Register Summary The following registers are required to control the security module: Table 11-2. SRAM Security Module Address Space Overview. SRAM-Addr. Register Name Description 0x82 AES_STATUS AES status 0x83 AES_CTRL Security module control, AES mode 0x84 – 0x93 Depends on AES_MODE setting: AES_MODE = 1: - Contains AES_KEY (key) AES_MODE = 0 | 2: - Contains AES_STATE (128 bit data block) AES_KEY AES_STATE 0x94 AES_CTRL_MIRROR Mirror of register 0x83 (AES_CTRL) These registers are only accessible using SRAM write and read accesses, for details refer to Section 6.2.3. 11.1.8 AES SRAM Configuration Register Register 0x82 (AES_STATUS): The read-only register AES_STATUS signals the status of the security module and operation. Figure 11-6. Register AES_STATUS. Bit 0x82 7 Read/Write Reset value R 0 Bit 3 0x82 Read/Write Reset value 130 6 AES_ER 5 R 0 R 0 2 1 reserved R 0 4 reserved R 0 AES_STATUS R 0 0 AES_DONE R 0 AES_STATUS R 0 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Bit 7 - AES_ER This SRAM register bit indicates an error of the AES module. An error may occur for instance after an access to SRAM register 0x83 (AES_CTRL) while an AES operation is running or after reading less than 128-bits from SRAM register space 0x84 – 0x93 (AES_STATE). Table 11-3. AES_ER. Register Bits Value AES_ER Description 0 No error of the AES module 1 AES module error Bit 0 - AES_DONE The bit AES_DONE signals the status of AES operation. Table 11-4. AES_DONE. Register Bits Value AES_DONE Description 0 AES module is not finished 1 AES module has finished Register 0x83 (AES_CTRL): The AES_CTRL register controls the operation of the security module. Figure 11-7. Register AES_CTRL. Bit 7 0x83 6 5 AES_REQUEST Read/Write Reset value Bit 0x83 AES_MODE W 0 R/W 0 3 2 AES_DIR Read/Write Reset value 4 AES_CTRL R/W 0 R/W 0 1 0 reserved R/W 0 R 0 R 0 AES_CTRL R 0 Notes: 1. Do not access this register during AES operation to read the AES core status. A read or write access during AES operation stops the actual processing. 2. To read the AES status use register bit AES_DONE (register 0x82, AES_STATUS). Bit 7 - AES_REQUEST A write access with AES_REQUEST = 1 initiates the AES operation. Table 11-5. AES_REQUEST. Register Bits AES_REQUEST Value Description 0 Security module, AES core idle 1 A write access starts the AES operation 131 8321A–MCU Wireless–10/11 Bit 6:4 - AES_MODE This register bit sets the AES operation mode. Table 11-6. AES_MODE. Register Bits AES_MODE Value Description 0 ECB mode 1 KEY mode 2 CBC mode All other values are reserved Bit 3 - AES_DIR The register bit AES_DIR sets the AES operation direction, either encryption or decryption. Table 11-7. AES_DIR. Register Bits AES_DIR Value Description 0 AES encryption (ECB, CBC) 1 AES decryption (ECB) Register 0x94 (AES_CTRL_MIRROR): Register 0x94 is a mirrored version of register 0x83 (AES_CTRL), for details refer to register 0x83 (AES_CTRL). This register could be used to start a security operation within a single SRAM access by appending it to the data stream and setting register bit AES_REQUEST = 1. 132 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 11.2 Random Number Generator 11.2.1 Overview The Atmel AT86RF232 incorporates a two bit truly random number generator by observation of noise. This random number can be used to: Generate random seeds for CSMA-CA algorithm see Section 7.2 Generate random values for AES key generation see Section 11.1 The random number is updated every tRND = 1µs in Basic Operation Mode receive states. The values are stored in register bits RND_VALUE (register 0x06, PHY_RSSI). 11.2.2 Register Description Register 0x06 (PHY_RSSI): The PHY_RSSI register is a multi-purpose register that indicates FCS validity, provides random numbers and shows the actual RSSI value. Figure 11-8. Register PHY_RSSI. Bit 7 0x06 6 5 RX_CRC_VALID RND_VALUE Read/Write Reset value R 0 R 1 Bit 3 2 0x06 4 RSSI R 1 R 0 1 0 R 0 R 0 RSSI Read/Write Reset value R 0 R 0 PHY_RSSI PHY_RSSI Bit 6:5 - RND_VALUE The 2-bit random value can be retrieved by reading register bits RND_VALUE. Table 11-8. RND_VALUE. Register Bits Value RND_VALUE 3 Note: 1. Description Deliver two bit noise value within receive state. Valid values are [3, 2, …, 0]. The radio transceiver shall be in Basic Operating Mode receive state. 133 8321A–MCU Wireless–10/11 11.3 Antenna Diversity The Antenna Diversity implementation is characterized by: Improves signal path robustness between nodes Atmel AT86RF232 self-contained antenna diversity algorithm Direct register based antenna selection 11.3.1 Overview Due to multipath propagation effects between network nodes, the receive signal strength may vary and affect the link quality, even for small changes of the antenna location. These fading effects can result in an increased error floor or loss of the connection between devices. To improve the reliability of an RF connection between network nodes Antenna Diversity can be applied to reduce effects of multipath propagation and fading. Antenna Diversity uses two antennas to select the most reliable RF signal path. To ensure highly independent receive signals on both antennas, the antennas should be carefully separated from each other. If a valid IEEE 802.15.4 frame is detected on one antenna, this antenna is selected for reception. Otherwise the search is continued on the other antenna and vice versa. Antenna Diversity can be used in Basic and Extended Operating Modes and can also be combined with other features and operating modes. 11.3.2 Antenna Diversity Application Example A block diagram for an application using an antenna switch is shown in Figure 11-9. Figure 11-9. Antenna Diversity – Block Diagram. ANT0 1 AVSS AT86RF232 2 AVSS 3 AVSS 4 RFP 6 AVSS ... DIG2 5 RFN DIG1 B1 Balun RFSwitch SW1 9 10 ANT1 Generally, if the antenna diversity used the control of an antenna diversity switch must be enabled by register bit ANT_EXT_SW_EN (register 0x0D, ANT_DIV). The internal connection to digital ground of the control pins pin 9 (DIG1) and pin 10 (DIG2) is disabled (refer to Section 1.3), and they feed the antenna switch signal and its inverse to the differential inputs of the RF Switch (SW1). 134 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 If the Atmel AT86RF232 is not in a receive or transmit state, it is recommended to disable register bit ANT_EXT_SW_EN to reduce the power consumption or avoid leakage current of an external RF switch, especially during SLEEP state. If register bit ANT_EXT_SW_EN = 0, output pins DIG1/DIG2 are pulled-down to digital ground. User Defined Antenna Selection A microcontroller defined selection of a certain antenna can be done by disabling the automated Antenna Diversity algorithm (ANT_DIV_EN = 0) and selecting one antenna using register bits ANT_CTRL = 1 / 2. The antenna defined by register bits ANT_CTRL (register 0x0D, ANT_DIV) is used for transmission and reception. Autonomous Antenna Selection The autonomous Antenna Diversity algorithm is enabled with register bits ANT_DIV_EN = 1 and ANT_CTRL = 0 / 3 (register 0x0D, ANT_DIV). It allows the use of Antenna Diversity even if the microcontroller does currently not control the radio transceiver, for instance in Extended Operating Mode. Upon reception of a frame the AT86RF232 selects one antenna. The selected antenna is then indicated by register bit ANT_SEL (register 0x0D, ANT_DIV). If required, it is recommended to read register bit ANT_SEL after IRQ_2 (RX_START). After the frame reception is completed, the antenna selection continues searching for new frames on both antennas. However, the register bit ANT_SEL maintains its previous value (from the last received frame) until a new IEEE 802.15.4 frame has been detected, and the selection algorithm locked into one antenna again. At this time the register bit ANT_SEL is updated again. If a device is in RX_AACK mode, receiving a frame containing an ACK request, the ACK frame is transmitted using the same antenna as used during receive. If a device performs a transaction in TX_ARET mode, it starts to listen for an ACK on the transmit antenna. If no ACK was received, the next transmission attempt is done on the other transmit antenna. This will be repeated with each retry. 11.3.3 Antenna Diversity Sensitivity Control Due to a different receive algorithm used by the Antenna Diversity algorithm, the correlator threshold of the receiver has to be adjusted. It is recommended to set register bits PDT_THRES (register 0x0A, RX_CTRL) to three. 135 8321A–MCU Wireless–10/11 11.3.4 Register Description Register 0x0A (RX_CTRL): The RX_CTRL register controls the sensitivity of the Antenna Diversity mode. Figure 11-10. Register RX_CTRL. Bit 7 6 Read/Write Reset value R 0 R 0 Bit 3 2 0x0A 5 4 R/W 1 R/W 1 1 0 R/W 1 R/W 1 reserved 0x0A RX_CTRL PDT_THRES Read/Write Reset value R/W 0 R/W 1 RX_CTRL Bit 3:0 - PDT_THRES The register bits PDT_THRES controls the sensitivity of the receiver correlation unit. Table 11-9. PDT_THRES. Register Bits Value PDT_THRES 0x3 Description (1) Recommended correlator threshold for Antenna Diversity operation 0x7 To be used if Antenna Diversity algorithm is disabled All other values are reserved Note: 1. If the Antenna Diversity algorithm is enabled (ANT_DIV_EN = 1), the value shall be set to PDT_THRES = 3, otherwise it shall be set back to the reset value. This is not automatically done by the hardware. Register 0x0D (ANT_DIV): The ANT_DIV register controls Antenna Diversity. Figure 11-11. Register ANT_DIV. Bit 0x0D Read/Write Reset value Bit 0x0D Read/Write Reset value 136 7 6 ANT_SEL R 0 5 4 reserved R 0 R 0 1 3 2 ANT_DIV_EN ANT_EXT_SW_EN R/W 0 R/W 0 ANT_DIV R 0 0 ANT_CTRL R/W 0 ANT_DIV R/W 0 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Bit 7 - ANT_SEL Signals selected antenna, related to the last received frame. Table 11-10. ANT_SEL. Register Bits Value ANT_SEL Note: 1. Description 0 Antenna 0 1 Antenna 1 If the autonomous Antenna Diversity algorithm is enabled, the register bit ANT_SEL maintains its previous value (from the last received frame) until a new SHR has been found. This register bit signals the currently selected antenna path. The selection may be based either on the last antenna diversity cycle (ANT_DIV_EN = 1) or on the content of register bits ANT_CTRL, for details refer to Section 11.3.2. Bit 3 - ANT_DIV_EN The register bit ANT_DIV_EN activates the autonomous Antenna Diversity algorithm. Table 11-11. ANT_DIV_EN. Register Bits Value ANT_DIV_EN 0 Antenna Diversity algorithm is disabled 1 Antenna Diversity algorithm is enabled Note: 1. Description If ANT_DIV_EN = 1 register bit ANT_EXT_SW_EN shall be set to one, too. This is not automatically done by the hardware. If register bit ANT_DIV_EN is set the Antenna Diversity algorithm is enabled. On reception of a frame the algorithm selects an antenna autonomously during SHR search. This selection is kept until: A new SHR search starts Leaving receive states Register bits ANT_CTRL are manually programmed Bit 2 - ANT_EXT_SW_EN The register bit ANT_EXT_SW_EN controls the external antenna switch. Table 11-12. ANT_EXT_SW_EN. Register Bits ANT_EXT_SW_EN Value Description 0 Antenna Diversity RF switch control is disabled 1 Antenna Diversity RF switch control is enabled If enabled, pin 9 (DIG1) and pin 10 (DIG2) become output pins and provide a differential control signal for an Antenna Diversity switch. The selection of a specific antenna is done either by the automated Antenna Diversity algorithm (ANT_DIV_EN = 1), or according to register bits ANT_CTRL if Antenna Diversity algorithm is disabled. If the Atmel AT86RF232 is not in a receive or transmit state, it is recommended to disable register bit ANT_EXT_SW_EN to reduce the power consumption or avoid leakage current of an external RF switch, especially during SLEEP state. If register bit ANT_EXT_SW_EN = 0, output pins DIG1 and DIG2 are pulled-down to digital ground. Pin 10 (DIG2) is overloaded with RX and TX Frame Time Stamping, see Section 11.4, if IRQ_2_EXT_EN is set. 137 8321A–MCU Wireless–10/11 Bit 1:0 - ANT_CTRL These register bits provide a static control of an Antenna Diversity switch. Table 11-13. ANT_CTRL. Register Bits ANT_CTRL 138 Value Description 0 Mandatory setting for applications not using Antenna Diversity and if autonomous antenna selection is enabled 1 Antenna 0 DIG1 = L DIG2 = H 2 Antenna 1 DIG1 = H DIG2 = L 3 Same behaviour as value zero AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 11.4 RX and TX Frame Time Stamping (TX_ARET) 11.4.1 Overview An exact timing of received and transmitted frames is signaled by Atmel AT86RF232 pin 10 (DIG2). A valid PHR reception or start of frame transmission is indicated by a DIG2 posedge. The pin remains high during frame reception or transmission. TX Frame Time Stamping is limited to TX_ARET, whereas the RX Frame Time Stamping is available for all receive modes. Exemplary, Figure 11-12 illustrates a frame reception example. Figure 11-12. Timing of RX_START and DIG2 for RX Frame Time Stamping. 128 TRX_STATE 192 192 + m * 32 4 1 1 m < 128 Preamble SFD PHR PSDU (250 kb/s) Number of Octets Frame Content 160 RX_ON Time [µs] Frame on Air 0 BUSY_RX RX_ON RX DIG2 (RX Frame Time Stamp) IRQ IRQ_2 (RX_START) TRX_END tIRQ Interrupt latency Note: 1. tIRQ Timing figures tIRQ refer to Section 12.4. If pin 10 (DIG2) is not used for RX and/or TX Frame Time Stamping, or Antenna Diversity, it is pulled-down to digital ground. 11.4.2 Register Description Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. Figure 11-13. Register TRX_CTRL_1. Bit 0x04 Read/Write Reset value Bit 0x04 Read/Write Reset value 7 6 5 4 reserved IRQ_2_EXT_EN TX_AUTO_CRC_ ON RX_BL_CTRL R/W 0 R/W 0 R/W 1 R/W 0 3 2 SPI_CMD_MODE R/W 0 R/W 0 1 0 IRQ_MASK_MODE IRQ_POLARITY R/W 1 R/W 0 TRX_CTRL_1 TRX_CTRL_1 139 8321A–MCU Wireless–10/11 Bit 6 - IRQ_2_EXT_EN Controls external signaling for time stamping via pin 10 (DIG2). Table 11-14. IRQ_2_EXT_EN. Register Bits Value IRQ_2_EXT_EN Description 0 Time stamping over pin 10 (DIG2) is disabled (1) Time stamping over pin 10 (DIG2) is enabled 1 Notes: 1. The pin 10 (DIG2) is also active even if the corresponding interrupt event IRQ_2 (RX_START) mask bit in register 0x0E (IRQ_MASK) is set to zero. 2. The pin remains at high level until the end of the frame receive or transmit procedure. Register 0x17 (XAH_CTRL_1): The XAH_CTRL_1 register is a multi-purpose control register for Extended Operating Mode. Figure 11-14. Register XAH_CTRL_1. Bit 7 0x17 6 5 ARET_TX_TS_EN reserved R/W 0 R/W 0 3 Read/Write Reset value R/W 0 R/W 0 2 1 0 reserved AACK_ACK_TIME AACK_PROM_ MODE reserved R 0 R/W 0 R/W 0 R/W 0 Bit 0x17 4 AACK_FLTR_RES_ AACK_UPLD_RES_ FT FT Read/Write Reset value XAH_CTRL_1 XAH_CTRL_1 Bit 7 - ARET_TX_TS_EN If register bit ARET_TX_TS_EN = 1, then any frame transmission within TX_ARET mode is signaled via pin 10 (DIG2). Table 11-15. ARET_TX_TS_EN. Register Bits ARET_TX_TS_EN Value 0 TX_ARET time stamping via pin 10 (DIG2) is disabled (1) TX_ARET time stamping via pin 10 (DIG2) is enabled 1 Note: 140 1. Description It is necessary to set register bit IRQ_2_EXT_EN (register 0x04, TRX_CTRL_1). AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 11.5 Frame Buffer Empty Indicator 11.5.1 Overview For time critical applications that want to start reading the frame data as early as possible, the Atmel AT86RF232 Frame Buffer status can be indicated to the microcontroller through a dedicated pin. This pin indicates to the microcontroller if an access to the Frame Buffer is not possible since valid PSDU data are missing. Pin 24 (IRQ) can be configured as a Frame Buffer Empty Indicator during a Frame Buffer read access. This mode is enabled by register bit RX_BL_CTRL (register 0x04, TRX_CTRL_1). The IRQ pin turns into Frame Buffer Empty Indicator after the Frame Buffer read access command, see note (1) in Figure 11-15, has been transferred on the SPI bus until the Frame Buffer read procedure has finished indicated by /SEL = H, see note (4). Figure 11-15. Timing Diagram of Frame Buffer Empty Indicator. /SEL SCLK MOSI MISO IRQ Command XX PHY_STATUS IRQ_STATUS Command XX TRX_STATUS PHR[7:0] XX XX PSDU[7:0] PSDU[7:0] XX PSDU[7:0] XX LQI[7:0] XX ED[7:0] XX Command RX_STATUS XX TRX_STATUS IRQ_STATUS Frame Buffer Empty Indicator IRQ_2 (RX_START) IRQ_3 (TRX_END) t12 Notes (1) Notes: (2) (3) (4) 1. Timing figure t12 refer to Section 12.4. 2. A Frame Buffer read access can proceed as long as pin 24 (IRQ) = L. 3. Pin IRQ = H indicates that the Frame Buffer is currently not ready for another SPI cycle. 4. The Frame Buffer read procedure has finished indicated by /SEL = H. The microcontroller has to observe the IRQ pin during the Frame Buffer read procedure. A Frame Buffer read access can proceed as long as pin 24 (IRQ) = L, see note (2). Pin IRQ = H indicates that the Frame Buffer is currently not ready for another SPI cycle, note (3), and thus the Frame Buffer read procedure has to wait for valid data accordingly. The access indicator pin 24 (IRQ) shows a valid access signal (either access is allowed or denied) not before t12 = 750ns after the rising edge of last SCLK clock of the Frame Buffer read command byte. After finishing the SPI frame receive procedure, and the SPI has been released by /SEL = H, note (4), pending interrupts are indicated immediately by pin 24 (IRQ). During all other SPI accesses, except during a SPI frame receive procedure with RX_BL_CTRL = 1, pin IRQ only indicates interrupts. If a receive error occurs during the Frame Buffer read access the Frame Buffer Empty Indicator locks on 'empty' (pin 24 (IRQ) = H), too. To prevent possible deadlocks, the microcontroller should impose a timeout counter that checks whether the Frame Buffer Empty Indicator remains logic high for more than 64µs. Presuming a PHY data rate of 250kb/s a new byte must have been arrived at the frame buffer during that period. If not, the Frame Buffer read access should be aborted. 141 8321A–MCU Wireless–10/11 11.5.2 Register Description Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. Figure 11-16. Register TRX_CTRL_1. Bit 0x04 Read/Write Reset value Bit 0x04 7 6 5 4 reserved IRQ_2_EXT_EN TX_AUTO_CRC_ ON RX_BL_CTRL R/W 0 R/W 0 R/W 1 R/W 0 3 2 1 0 IRQ_MASK_MODE IRQ_POLARITY R/W 1 R/W 0 SPI_CMD_MODE Read/Write Reset value R/W 0 R/W 0 TRX_CTRL_1 TRX_CTRL_1 Bit 4 - RX_BL_CTRL The register bit RX_BL_CTRL controls the Frame Buffer Empty Indicator. Table 11-16. RX_BL_CTRL. Register Bits Value RX_BL_CTRL 0 Frame Buffer Empty Indicator disabled 1 Frame Buffer Empty Indicator enabled Note: 1. Description A modification on IRQ_POLARITY bit has no influence to RX_BL_CTRL behavior. If this register bit is set the Frame Buffer Empty Indicator is enabled. After sending a Frame Buffer read command, refer to Section 6.2, pin 24 (IRQ) indicates to the microcontroller that an access to the Frame Buffer is not possible as long as valid PSDU data are missing. The pin 24 (IRQ) does not indicate any interrupts during this time. 142 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 11.6 Dynamic Frame Buffer Protection 11.6.1 Overview The Atmel AT86RF232 continues the reception of incoming frames as long as it is in any receive state. When a frame was successfully received and stored into the Frame Buffer, the following frame will overwrite the Frame Buffer content again. To relax the timing requirements for a Frame Buffer read access the Dynamic Frame Buffer Protection prevents that a new valid frame passes to the Frame Buffer until a Frame Buffer read access has ended (indicated by /SEL = H, refer to Section 6.2). A received frame is automatically protected against overwriting: in Basic Operating Mode, if its FCS is valid in Extended Operating Mode, if an IRQ_3 (TRX_END) is generated The Dynamic Frame Buffer Protection is enabled with RX_SAFE_MODE set and applicable transceiver states RX_ON and RX_AACK_ON. Note: 1. The Dynamic Frame Buffer Protection only prevents write accesses from the air interface – not from the SPI interface. 11.6.2 Register Description Register 0x0C (TRX_CTRL_2): The TRX_CTRL_2 register is a multi-purpose control register to control various settings of the radio transceiver. Figure 11-17. Register TRX_CTRL_2. Bit 7 0x0C 6 5 RX_SAFE_MODE Read/Write Reset value reserved R/W 0 R 0 3 2 Bit 4 0x0C TRX_CTRL_2 R/W 1 R 0 1 0 R/W 0 R/W 0 reserved Read/Write Reset value R 0 R/W 0 TRX_CTRL_2 Bit 7 - RX_SAFE_MODE Protect Frame Buffer after frame receive with valid FCF check. Table 11-17. RX_SAFE_MODE. Register Bits RX_SAFE_MODE Value 0 Disable Dynamic Frame Buffer protection (1) Enable Dynamic Frame Buffer protection 1 Note: 1. Description Dynamic Frame Buffer Protection is released with the rising edge of /SEL pin of a Frame Buffer read access, or radio transceiver state changes from RX_ON or RX_AACK_ON to another state. This operation mode is independent of the setting of register bits RX_PDT_LEVEL, (register 0x15, RX_SYN), refer to Section 9.1.3. 143 8321A–MCU Wireless–10/11 12 Electrical Characteristics 12.1 Absolute Maximum Ratings Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter Condition Min. Typ. TSTOR Storage temperature TLEAD Lead temperature T = 10s (soldering profile compliant with IPC/JEDEC J STD 020B) VESD ESD robustness Compl. to [3], 2 kV Compl. to [4] 500 V -50 Max. Unit 150 °C 260 °C PRF Input RF level +10 dBm VDIG Voltage on all pins (except pins 4, 5, 13, 14, 29) -0.3 VDD+0.3 V VANA Voltage on pins 4, 5, 13, 14, 29 -0.3 2.0 V Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage. 12.2 Recommended Operating Range Symbol Parameter Condition TOP Operating temperature range (1) Min. Typ. Max. Unit 0 +25 +70 °C 1.8 3.0 3.6 V 1.7 1.8 1.9 V VDD Supply voltage Voltage on pins 15, 28 VDD1.8 Supply voltage (on pins 13, 14, 29) External voltage supply Notes: 1. Even if an implementation uses the external 1.8V voltage supply V DD1.8 it is required to connect VDD. 2. (2) Register 0x10 (VREG_CTRL) needs to be programmed to disable internal voltage regulators and supply blocks by an external 1.8V supply, refer to Section 9.4. 12.3 Digital Pin Characteristics Test Conditions: TOP = +25°C (unless otherwise stated). Symbol VIH VIL Parameter Condition High level input voltage Low level input voltage (1) High level output voltage VOL Low level output voltage Typ. Max. VDD-0.4 (1) VOH 144 Min. V 0.4 (1) (1) Unit VDD-0.4 V V 0.4 V AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Symbol Parameter CLoad Note: Condition Min. (1) Capacitive load 1. Typ. Max. 50 Unit pF The capacitive load CLoad should not be larger than 50pF for all I/Os. Generally, large load capacitances increase the overall current consumption. 12.4 Digital Interface Timing Characteristics Test Conditions: TOP = +25°C, VDD = 3.0V, CLoad = 50pF (unless otherwise stated). Symbol Parameter Condition fasync SCLK frequency Asynchronous operation t1 /SEL falling edge to MISO active t2 SCLK falling edge to MISO out 25 ns t3 MOSI setup time 10 ns t4 MOSI hold time 10 ns Data hold time Min. t5 LSB last byte to MSB next byte SPI read/write, standard SRAM and frame access modes 250 (1) t5a LSB last byte to MSB next byte Fast SRAM read/write access mode 500 (1) t6 /SEL rising edge to MISO tri state t7 SLP_TR pulse width Typ. Max. Unit 7.5 MHz 180 ns 10 TX start trigger 62.5 Note ns ns ns (2) ns t8 SPI idle time: SEL rising to falling edge SPI read/write, standard SRAM and frame access modes Idle time between consecutive SPI accesses 250 (1) t8a SPI idle time: SEL rising to falling edge Fast SRAM read/write access mode Idle time between consecutive SPI accesses 500 (1) t9 Last SCLK rising edge to /SEL rising edge t10 Reset pulse width ≥ 10 clock cycles at 16MHz 625 ns t11 SPI access latency after reset ≥ 10 clock cycles at 16MHz 625 ns t12 Frame buffer empty indicator latency rising edge of last SCLK clock of the Frame Buffer read command byte to rising edge of IRQ tIRQ IRQ_2, IRQ_3, IRQ_4 latency Relative to the event to be indicated fCLKM Output clock frequency at pin 17 (CLKM) Configurable in register 0x03 Notes: 1. 2. 250 ns ns ns 750 ns 9 µs 0 MHz 1 MHz 62.5 kHz For Fast SRAM read/write accesses on address space 0x82 – 0x94 the time t5(Min.) and t8(Min.) increases to 500ns. Maximum pulse width less than (TX frame length + 16µs). 145 8321A–MCU Wireless–10/11 12.5 General RF Specifications Test Conditions (unless otherwise stated): VDD = 3.0V, fRF = 2445MHz, TOP = +25°C, Measurement setup see Figure 5-1. Symbol Parameter Condition Min. Typ. Max. Unit fRF Frequency range As specified in [1], [2] 2405 2445 2480 MHz fCH Channel spacing As specified in [1], [2] 5 MHz fHDR Header bit rate (SHR, PHR) As specified in [1], [2] 250 kb/s fPSDU PSDU bit rate As specified in [1], [2] 250 kb/s fCHIP Chip rate As specified in [1], [2] 2000 kchip/s fCLK Crystal oscillator frequency Reference oscillator fSRD Symbol rate deviation Reference frequency accuracy for correct functionality PSDU bit rate f20dB Note: 250kb/s 16 -60 (1) 20dB bandwidth 1. MHz +60 2.8 ppm MHz A reference frequency accuracy of ±40ppm is required by [1], [2]. 12.6 Transmitter Characteristics Test Conditions (unless otherwise stated): VDD = 3.0V, fRF = 2445MHz, TOP = +25°C, Measurement setup see Figure 5-1. Symbol Parameter Condition PTX_MAX TX Output power Maximum configurable TX output power value Register bit TX_PWR = 0 +3 dBm PRANGE Output power range 16 steps, configurable in register 0x05 (PHY_TX_PWR) 20 dB PACC Output power tolerance EVM EVM PHARM 2 harmonic rd Note: 146 Spurious Emissions 1. Typ. nd Harmonics PSPUR_TX Min. (1) Max. Unit ±5 dB 30 %rms -40 dBm 3 harmonic -45 dBm 30 – ≤ 1000MHz -36 dBm >1 – 12.75GHz -30 dBm 1.8 – 1.9GHz -47 dBm 5.15 – 5.3GHz -47 dBm Complies with EN 300 328/440, FCC-CFR-47 part 15, ARIB STD-66, RSS-210. AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 12.7 Receiver Characteristics Test Conditions (unless otherwise stated): VDD = 3.0V, fRF = 2445MHz, TOP = +25°C, Measurement setup see Figure 5-1. Symbol Parameter PSENS Receiver sensitivity RLRX RX Return loss NF Noise figure PRX_MAX Maximum RX input level Condition Min. Typ. Max. Unit (1) 250kb/s -100 dBm Antenna Diversity (1) 250kb/s -99 dBm 100Ω differential impedance 10 dB 6 dB (1) 8 dBm (1) 32 dB (1) 35 dB (1) 48 dB (1) 48 dB (1) 54 dB (1) dB 250kb/s PACRN Adjacent channel rejection: -5MHz 250kb/s , PRF= -82dBm PACRP Adjacent channel rejection: +5MHz 250kb/s , PRF= -82dBm PAACRN Adjacent channel rejection: -10MHz 250kb/s , PRF= -82dBm PAACRP Adjacent channel rejection: +10MHz 250kb/s , PRF= -82dBm PAACR2N 2 alternate channel rejection: -15MHz PAACR2P PSPUR_RX nd 250kb/s , PRF= -82dBm 2 alternate channel rejection: +15MHz nd 250kb/s , PRF= -82dBm 54 Spurious emissions LO leakage -70 30 – ≤ 1000MHz >1 – 12.75GHz -300 (2) dBm -57 dBm -47 dBm +300 kHz ±5 dB fCAR_OFFS TX/RX carrier frequency offset Sensitivity loss ≤ 2dB RSSITOL RSSI tolerance Tolerance within gain step RSSIRANGE RSSI dynamic range 87 dB RSSIRES RSSI resolution 3 dB RSSIBASE_V RSSI sensitivity Defined as RSSI_BASE_VAL RSSIMIN Minimum RSSI value PRF≤ RSSI_BASE_VAL 0 RSSIMAX Maximum RSSI value PRF≥ RSSI_BASE_VAL + 84dB 28 Notes: 1. AWGN channel, PER ≤ 1%, PSDU length 20 octets. -91 dBm AL 2. Offset equals ±120ppm. 147 8321A–MCU Wireless–10/11 12.8 Current Consumption Specifications Test Conditions (unless otherwise stated): VDD = 3.0V, fRF = 2445MHz, TOP = +25°C, Measurement setup see Figure 5-1. Symbol Parameter Condition Min. Typ. Max. Unit IBUSY_TX Supply current transmit state PTX= +3dBm 13.8 mA PTX= +0dBm 11.8 mA PTX= -17dBm 7.2 mA IRX_ON Supply current RX_ON state high sensitivity RX_PDT_LEVEL = [0x0] 11.8 mA IRX_ON_L0 Supply current RX_ON state with active receiver desensitize receiver desensitize RX_PDT_LEVEL = [0x1, ..., 0xE, (1) 0xF] 11.3 mA IPLL_ON Supply current PLL_ON state 5.2 mA ITRX_OFF Supply current TRX_OFF state 330 µA ISLEEP Supply current SLEEP state 0.4 µA Notes: 1. Refer to Section 9.1. 2. All power consumption measurements are performed with CLKM disabled. 12.9 Crystal Parameter Requirements Symbol Parameter f0 Crystal frequency CL Load capacitance C0 R1 148 Condition Min. Typ. Max. 16 8 Unit MHz 14 pF Static capacitance 7 pF Series resistance 100 Ω AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 13 Typical Characteristics 13.1 Active Supply Current The following charts showing each a typical behavior of the Atmel AT86RF232. These figures are not tested during manufacturing. All power consumption measurements are performed with pin 17 (CLKM) disabled, unless otherwise stated. The measurement setup used for the measurements is shown in Figure 5-1. The power consumption of the microcontroller, which is required to program the radio transceiver, is not included in the measurement results. The power consumption in SLEEP state is independent from CLKM master clock rate selection. The current consumption depends on several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, and ambient temperature. The dominating factors are operating voltage and ambient temperature. If possible the measurement results are not affected by current drawn from I/O pins. Register, SRAM or Frame Buffer read or write accesses are not performed during current consumption measurements. 13.1.1 P_ON and TRX_OFF states Figure 13-1. Current Consumption in P_ON State. Current Consumption [mA] Current Consumption [mA] 0,4 0.4 0,3 0.3 0,2 0.2 70°C 70°C 0.1 0,1 25°C 25°C 0°C 0°C 0.0 0,0 1.6 1,6 1.8 1,8 2.0 2,0 2.2 2,2 2.4 2,4 2.6 2,6 2.8 2,8 3.0 3,0 3.23,2 3.43,4 3.63,6 3.83,8 EVDD [V] [V] EVDD 149 8321A–MCU Wireless–10/11 Figure 13-2. Current Consumption in TRX_OFF State. Current Consumption [mA] Current Consumption [mA] 0,4 0.4 0.3 0,3 0.2 0,2 70°C 70°C 0.1 0,1 25°C 25°C 0°C 0°C 0.0 0,0 1.6 1,6 1.8 1,8 2.0 2,0 2.2 2,2 2.4 2,4 2.6 2,6 2.8 2,8 3.0 3,0 3.23,2 3.43,4 3.63,6 3.83,8 EVDD EVDD [V] [V] 13.1.2 PLL_ON state Figure 13-3. Current Consumption in PLL_ON State. 6,0 6.0 Current Consumption [mA] Current Consumption [mA] 5,0 5.0 4,0 4.0 3,0 3.0 2,0 2.0 70°C 70°C 25°C 25°C 1.0 1,0 0°C 0°C 0.0 0,0 1,6 1.6 1,8 1.8 2,0 2.0 2,2 2.2 2,4 2.4 2,6 2.6 2,8 2.8 3.03,0 3.23,2 3.43,4 3.6 3,6 3.83,8 EVDD EVDD[V] [V] 150 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 13.1.3 RX_ON state Figure 13-4. Current Consumption in RX_ON State – High Sensitivity. 14,0 14.0 Current Consumption [mA] [mA] Consumption Current 12,0 12.0 10.0 10,0 8.0 8,0 6.0 6,0 70°C 70°C 4.0 4,0 25°C 25°C 2.0 2,0 0°C 0°C 0.0 0,0 1.6 1,6 1.8 1,8 2.0 2,0 2.2 2,2 2.4 2,4 2.6 2,6 2.8 2,8 3.03,0 3.23,2 3.43,4 3.6 3,6 3.83,8 EVDD[V] [V] EVDD Figure 13-5. Current Consumption in RX_ON State – Reduced Sensitivity. 14,0 14.0 Current Consumption [mA] [mA] Consumption Current 12,0 12.0 10,0 10.0 8,0 8.0 6.0 6,0 70°C 70°C 4.0 4,0 25°C 25°C 2.0 2,0 0°C 0°C 0.0 0,0 1.6 1,6 1.8 1,8 2.0 2,0 2.2 2,2 2.4 2,4 2.6 2,6 2.8 2,8 3.0 3,0 3.23,2 3.43,4 3.63,6 3.83,8 EVDD[V] [V] EVDD 151 8321A–MCU Wireless–10/11 13.1.4 TX_BUSY state Figure 13-6. Current Consumption in TX_BUSY State – Minimum Output Power. 9,0 9.0 Current Consumption [mA] Current Consumption [mA] 8,0 8.0 7,0 7.0 6,0 6.0 5,0 5.0 4,0 4.0 3,0 2.0 70°C 70°C 25°C 25°C 2,0 2.0 0°C 0°C 1,0 1.0 0,0 0.0 1,6 1.6 1,8 1.8 2,0 2.0 2,2 2.2 2,4 2.4 2,6 2.6 2,8 2.8 3,0 3.0 3.23,2 3.43,4 3.6 3,6 3.8 3,8 EVDD EVDD[V] [V] Figure 13-7. Current Consumption in TX_BUSY State – Output Power 0dBm. 14,0 14.0 Current Consumption [mA] [mA] Consumption Current 12,0 12.0 10,0 10.0 8,0 8.0 6,0 6.0 70°C 70°C 4,0 4.0 25°C 25°C 2,0 2.0 0°C 0°C 0,0 0.0 1.6 1,6 1.8 1,8 2.0 2,0 2.2 2,2 2.4 2,4 2.6 2,6 2.8 2,8 3.0 3,0 3.23,2 3.43,4 3.63,6 3.83,8 EVDD [V] EVDD [V] 152 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Figure 13-8. Current Consumption in TX_BUSY State – Maximum Output Power. 16,0 16.0 Consumption Current Current Consumption [mA] [mA] 14,0 14.0 12,0 12.0 10.0 10,0 8.0 8,0 6.0 6,0 70°C 70°C 4.0 4,0 25°C 25°C 0°C 0°C 2.0 2,0 0.0 0,0 1.6 1,6 1.8 1,8 2.0 2,0 2.2 2,2 2.4 2,4 2.6 2,6 2.8 2,8 3.0 3,0 3.23,2 3.43,4 3.6 3,6 3.83,8 EVDD [V] EVDD [V] 13.1.5 SLEEP Figure 13-9. Current Consumption in SLEEP. 1,0 1.0 Current Consumption [µA] Current Consumption [µA] 0,9 0.9 0.8 0,8 0,7 0.7 0,6 0.6 0.5 0,5 0,4 0.4 0.3 0,3 70°C 70°C 0.2 0,2 25°C 25°C 0°C 0°C 0.1 0,1 0.0 0,0 1,6 1.6 1,8 1.8 2,0 2.0 2,2 2.2 2,4 2.4 2,6 2.6 2,8 2.8 3,0 3.0 3.23,2 3.43,4 3.63,6 3.83,8 EVDD EVDD[V] [V] 153 8321A–MCU Wireless–10/11 13.2 State Transition Timing Figure 13-10. Transition Time from EVDD to P_ON (CLKM available). 450,0 450.0 State Time [µs] [us] Time Transition StateTransition 400,0 400.0 350,0 350.0 300.0 300,0 250,0 250.0 200,0 200.0 150,0 150.0 100.0 100,0 70°C 70°C 25°C 25°C 0°C 0°C 50.0 50,0 0.0 0,0 1.6 1,6 1.8 1,8 2.0 2,0 2.2 2,2 2.4 2,4 2.6 2,6 2.8 2,8 3.0 3,0 3.23,2 3.43,4 3.63,6 3.83,8 EVDD [V] EVDD Figure 13-11. Transition Time from SLEEP to TRX_OFF (IRQ_4 (AWAKE_END)). 400,0 400.0 State Time [µs][us] Time Transition StateTransition 350,0 350.0 300,0 300.0 70°C 70°C 25°C 25°C 250,0 250.0 0°C 0°C 200,0 200.0 150.0 150,0 100,0 100.0 50.0 50,0 0,0 0.0 1.6 1,6 1.8 1,8 2.0 2,0 2.2 2,2 2.4 2,4 2.6 2,6 2.8 2,8 3.0 3,0 3.2 3,2 3.43,4 3.63,6 3.83,8 EVDD [V] [V] EVDD 154 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Figure 13-12. Transition Time from TRX_OFF to PLL_ON. 100.0 100,0 90.0 90,0 State Transition Time [µs][us] Time Transition State 80.0 80,0 70.0 70,0 60.0 60,0 50.0 50,0 40.0 40,0 70°C 70°C 30.0 30,0 25°C 25°C 0°C 0°C 20.0 20,0 10.0 10,0 0.0 0,0 1.6 1,6 1.8 1,8 2.0 2,0 2.2 2,2 2.4 2,4 2.6 2,6 2.8 2,8 3.0 3,0 3.23,2 3.43,4 3.63,6 3.8 3,8 EVDD [V] 155 8321A–MCU Wireless–10/11 14 Register Reference The Atmel AT86RF232 provides a register space of 64 8-bit registers, used to configure, control and monitor the radio transceiver. Note: All registers not mentioned within the following table are reserved for internal use and must not be overwritten. When writing to a register, any reserved bits shall be overwritten only with their reset value. Table 14-1. Register Summary. Addr Name Bit 7 0x01 TRX_STATUS CCA_DONE 0x02 TRX_STATE 0x03 TRX_CTRL_0 Bit 6 Bit 5 CCA_STATUS reserved Bit 4 Bit 3 Bit 2 reserved TRX_CTRL_1 reserved IRQ_2_EXT_EN 0x05 PHY_TX_PWR reserved reserved 0x06 PHY_RSSI RX_CRC_VALID reserved TX_AUTO_CRC_ON 42, 63 CLKM_SHA_SEL RX_BL_CTRL CLKM_CTRL SPI_CMD_MODE 116 IRQ_MASK_MODE reserved IRQ_POLARITY TX_PWR RND_VALUE PHY_CC_CCA 0x09 CCA_THRES CCA_REQUEST 0x0A RX_CTRL 0x0C TRX_CTRL_2 RX_SAFE_MODE 0x0D ANT_DIV ANT_SEL 0x0E IRQ_MASK 0x0F IRQ_STATUS IRQ_7_BAT_LOW IRQ_6_TRX_UR 0x10 VREG_CTRL AVREG_EXT AVDD_OK 0x11 BATMON reserved reserved 0x12 XOSC_CTRL 0x15 RX_SYN RX_PDT_DIS 0x17 XAH_CTRL_1 ARET_TX_TS_EN reserved 0x18 FTN_CTRL FTN_START reserved 0x19 XAH_CTRL_2 0x1A PLL_CF PLL_CF_START reserved 0x1B PLL_DCU PLL_DCU_START reserved 0x1C PART_NUM 92 CCA_MODE CHANNEL reserved reserved reserved reserved 96, 119 CCA_ED_THRES 97 PDT_THRES 136 reserved reserved reserved reserved reserved ANT_DIV_EN ANT_EXT_SW_EN IRQ_3_TRX_END IRQ_2_RX_START DVREG_EXT DVDD_OK 143 ANT_CTRL 136 IRQ_MASK IRQ_5_AMI IRQ_4_CCA_ED_DONE reserved BATMON_OK 27 BATMON_HR XTAL_MODE reserved AACK_UPLD_RES_FT reserved IRQ_0_PLL_LOCK reserved BATMON_VTH 112 XTAL_TRIM 117 AACK_ACK_TIME 101 AACK_PROM_MODE reserved PLL_CF reserved 66, 140 122 ARET_CSMA_RETRIES reserved 27 109 reserved ARET_FRAME_RETRIES 0x1D VERSION_NUM IRQ_1_PLL_UNLOCK RX_PDT_LEVEL AACK_FLTR_RES_FT 139, 142 86, 89, 133 ED_LEVEL 0x08 21, 28, 65, 86, 104 RSSI 0x07 PHY_ED_LEVEL Page 41, 62, 95 TRX_CMD reserved 0x04 Bit 0 TRX_STATUS TRAC_STATUS reserved Bit 1 reserved 68 120 121 PART_NUM 22 VERSION_NUM 22 0x1E MAN_ID_0 MAN_ID_0 23 0x1F MAN_ID_1 MAN_ID_1 23 0x20 SHORT_ADDR_0 SHORT_ADDR_0 75 0x21 SHORT_ADDR_1 SHORT_ADDR_1 75 0x22 PAN_ID_0 PAN_ID_0 75 0x23 PAN_ID_1 PAN_ID_1 76 0x24 IEEE_ADDR_0 IEEE_ADDR_0 76 0x25 IEEE_ADDR_1 IEEE_ADDR_1 76 0x26 IEEE_ADDR_2 IEEE_ADDR_2 77 0x27 IEEE_ADDR_3 IEEE_ADDR_3 77 0x28 IEEE_ADDR_4 IEEE_ADDR_4 77 0x29 IEEE_ADDR_5 IEEE_ADDR_5 78 0x2A IEEE_ADDR_6 IEEE_ADDR_6 78 0x2B IEEE_ADDR_7 IEEE_ADDR_7 78 156 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Addr Name 0x2C XAH_CTRL_0 Bit 7 Bit 6 Bit 5 Bit 4 MAX_FRAME_RETRIES Bit 1 CSMA_SEED_0 0x2E CSMA_SEED_1 AACK_FVN_MODE CSMA_BE 0x36 TST_CTRL_DIGI Bit 2 MAX_CSMA_RETRIES 0x2D CSMA_SEED_0 0x2F Bit 3 AACK_SET_PD AACK_DIS_ACK MAX_BE reserved reserved reserved reserved Bit 0 Page SLOTTED_OPERATION 69 71 AACK_I_AM_COORD CSMA_SEED_1 71 MIN_BE 73 TST_CTRL_DIG 166 157 8321A–MCU Wireless–10/11 The reset values of the Atmel AT86RF232 registers in state P_ON Table 14-2. Note: (1, 2, 3) are shown in All reset values in Table 14-2 are only valid after a power on reset. After a reset procedure (/RST = L) as described in Section 7.1.4.5 the reset values of selected registers (for example registers 0x01, 0x10, 0x11, 0x30) can differ from that in Table 14-2. Table 14-2. Register Summary – Reset Values. Address Reset Value Address Reset Value Address Reset Value Address Reset Value 0x00 0x00 0x10 0x00 0x20 0xFF 0x30 0x00 0x01 0x00 0x11 0x02 0x21 0xFF 0x31 0x00 0x02 0x00 0x12 0xF0 0x22 0xFF 0x32 0x00 0x03 0x09 0x13 0x00 0x23 0xFF 0x33 0x00 0x04 0x22 0x14 0x00 0x24 0x00 0x34 0x00 0x05 0x00 0x15 0x00 0x25 0x00 0x35 0x00 0x06 0x60 0x16 0xC1 0x26 0x00 0x36 0x00 0x07 0xFF 0x17 0x00 0x27 0x00 0x37 0x00 0x08 0x2B 0x18 0x58 0x28 0x00 0x38 0x00 158 0x09 0xC7 0x19 0x00 0x29 0x00 0x39 0x40 0x0A 0x37 0x1A 0x57 0x2A 0x00 0x3A 0x00 0x0B 0xA7 0x1B 0x20 0x2B 0x00 0x3B 0x00 0x0C 0x20 0x1C 0x0A 0x2C 0x38 0x3C 0x00 0x0D 0x00 0x1D 0x02 0x2D 0xEA 0x3D 0x00 0x0E 0x00 0x1E 0x1F 0x2E 0x42 0x3E 0x00 0x0F 0x00 0x1F 0x00 0x2F 0x53 0x3F 0x00 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 15 Abbreviations AACK - Automatic acknowledgement ACK - Acknowledgement ADC - Analog-to-digital converter AD - Antenna diversity AGC - Automated gain control AES - Advanced encryption standard ARET - Automatic retransmission AVREG - Voltage regulator for analog building blocks AWGN - Additive White Gaussian Noise BATMON - Battery monitor BBP - Base band processor BPF - Band pass filter CBC - Cipher block chaining CRC - Cyclic redundancy check CCA - Clear channel assessment CSMA-CA - Carrier sense multiple access/Collision avoidance CW - Continuous wave DFBP - Dynamic Frame Buffer Protection DVREG - Voltage regulator for digital building blocks ECB - Electronic code book ED - Energy detection ESD - Electrostatic discharge EVM - Error vector magnitude FCF - Frame control field FCS - Frame check sequence FIFO - First in first out FTN - Filter tuning network GPIO - General purpose input output ISM - Industrial, scientific, and medical LDO - Low-drop output LNA - Low-noise amplifier LO - Local oscillator LQI - Link quality indicator LSB - Least significant bit 159 8321A–MCU Wireless–10/11 160 MAC - Medium access control MFR - MAC footer MHR - MAC header MISO - SPI Interface: Master input slave output MOSI - SPI Interface: Master output slave input MSB - Most significant bit MSDU - MAC service data unit MPDU - MAC protocol data unit MSK - Minimum shift keying O-QPSK - Offset - quadrature phase shift keying PA - Power amplifier PAN - Personal area network PCB - Printed circuit board PER - Packet error rate PHR - PHY header PHY - Physical layer PLL - Phase locked loop POR - Power-on reset PPF - Poly-phase filter PRBS - Pseudo random bit sequence PSDU - PHY service data unit PSD - Power spectral mask QFN - Quad flat no-lead package RF - Radio frequency RSSI - Received signal strength indicator RX - Receiver SCLK - SPI Interface: SPI clock /SEL - SPI Interface: SPI select SFD - Start-of-frame delimiter SHR - Synchronization header SPI - Serial peripheral interface SRAM - Static random access memory SSBF - Single side band filter TX - Transmitter VCO - Voltage controlled oscillator VREG - Voltage regulator AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 XOSC - Crystal oscillator 161 8321A–MCU Wireless–10/11 16 Ordering Information Ordering Code Packaging Package Voltage Range AT86RF232-ZX Tray QN 1.8V – 3.6V Commercial (0°C to +70°C) Lead-free/Halogen-free Tape & Reel QN 1.8V – 3.6V Commercial (0°C to +70°C) Lead-free/Halogen-free AT86RF232-ZXR Temperature Range Package Type Description QN 32QN2, 32-lead 5.0 x 5.0mm Body, 0.50mm Pitch, Quad Flat No-lead Package (QFN) Sawn Note: T&R quantity 5,000. Please contact your local Atmel sales office for more detailed ordering information and minimum quantities. 17 Soldering Information Recommended soldering profile is specified in IPC/JEDEC J-STD-.020C. 18 Package Thermal Properties Thermal Resistance 162 Velocity [m/s] Theta ja [K/W] 0 40.9 1 35.7 2.5 32.0 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 19 Package Drawing – 32QN2 SYMBOL MIN. NOM. MAX. NOTE 163 8321A–MCU Wireless–10/11 Appendix A - Continuous Transmission Test Mode A.1 - Overview The Atmel AT86RF232 offers a Continuous Transmission Test Mode to support final application / production tests as well as certification tests. Using this test mode the radio transceiver transmits continuously a previously transferred frame (PRBS mode) or a continuous wave signal (CW mode). In CW mode two different signal frequencies per channel can be transmitted: f1 = Fc + 0.5MHz f2 = Fc - 0.5MHz Here Fc is the channel center frequency, refer to Section 9.7.2. Note: 1. In CW mode it is not possible to transmit a RF signal directly on the channel center frequency. PSDU data in the Frame Buffer must contain at least a valid PHR (see Section 8.1). It is recommended to use a frame of maximum length (127 bytes) and arbitrary PSDU data for the PRBS mode. The SHR and the PHR are not transmitted. The transmission starts with the PSDU data and is repeated continuously. A.2 - Configuration Before enabling Continuous Transmission Test Mode all register configurations shall be done as follow: TX channel setting (optional) TX output power setting (optional) Mode selection (PRBS / CW) A register access to register 0x36 and 0x1C enables the Continuous Transmission Test Mode. The transmission is started by enabling the PLL (TRX_CMD = PLL_ON) and writing the TX_START command to register 0x02. Even for CW signal transmission it is required to write valid PSDU data to the Frame Buffer. For PRBS mode it is recommended to write a frame of maximum length. The detailed programming sequence is shown in Table A-0-1. The column R/W informs about writing (W) or reading (R) a register or the Frame Buffer. Table A-0-1. Continuous Transmission Programming Sequence. 164 Step Action Register R/W Value Description 1 RESET 2 Register Access 0x0E W 0x01 Set IRQ mask register, enable IRQ_0 (PLL_LOCK) 3 Register Access 0x04 W 0x00 Disable TX_AUTO_CRC_ON 4 Register Access 0x02 W 0x03 Set radio transceiver state TRX_OFF 5 Register Access 0x03 W 0x01 Set clock at pin 17 (CLKM) 6 Register Access 0x08 W 0x33 Set IEEE 802.15.4 CHANNEL, for example channel 19 Reset AT86RF232 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Step Action Register R/W Value Description 7 Register Access 0x05 W 0x00 Set TX output power, for example to PTX_MAX 8 Register Access 0x01 R 0x08 Verify TRX_OFF state 9 Register Access 0x36 W 0x0F Enable Continuous Transmission Test Mode – step # 1 10 (1) Register Access 0x0C W 0x03 Enable raw data mode 11 (1) Register Access 0x0A W 0x37 Enable raw data mode 12 (2) Frame Buffer Write Access W Write PSDU data (even for CW mode), refer to Table A-0-2 13 Register Access 0x1C W 0x54 Enable Continuous Transmission Test Mode – step # 2 14 Register Access 0x1C W 0x46 Enable Continuous Transmission Test Mode – step # 3 15 Register Access 0x02 W 0x09 Enable PLL_ON state 16 Interrupt event 0x0F R 0x01 Wait for IRQ_0 (PLL_LOCK) 17 Register Access 0x02 W 0x02 Initiate Transmission, enter BUSY_TX state 18 Measurement 19 Register Access 20 RESET Notes: Perform measurement 0x1C W 0x00 Disable Continuous Transmission Test Mode Reset AT86RF232 1. Only required for CW mode, do not configure for PRBS mode. 2. Frame Buffer content varies for different modulation schemes. The content of the Frame Buffer has to be defined for Continuous Transmission PRBS mode or CW mode. To measure the power spectral density (PSD) mask of the transmitter it is recommended to use a random sequence of maximum length for the PSDU data. To measure CW signals it is necessary to write either 0x00 or 0xFF to the Frame Buffer, for details refer to Table A-0-2. Table A-0-2. Frame Buffer Content for various Continuous Transmission Modulation Schemes. Step Action Frame Content Comment 12 Frame Buffer Access Random Sequence Modulated RF signal 0x00 (each byte of PSDU) Fc – 0.5MHz, CW signal 0xFF (each byte of PSDU) Fc + 0.5MHz, CW signal Note: 1. It is recommended to use a frame of maximum length (127 bytes). 165 8321A–MCU Wireless–10/11 A.3 – Register Description Register 0x36 (TST_CTRL_DIGI): The TST_CTRL_DIG register enables the continuous transmission test mode. Figure 0-1. Register TST_CTRL_DIGI. Bit 7 6 R/W 0 R/W 0 3 2 0x36 Read/Write Reset value Bit 4 R/W 0 R/W 0 1 0 R/W 0 R/W 0 reserved 0x36 Read/Write Reset value 5 TST_CTRL_DIGI TST_CTRL_DIG R/W 0 R/W 0 TST_CTRL_DIGI Bit 3:0 - TST_CTRL_DIG The register bits TST_CTRL_DIG with value 0xF enables continuous transmission. Table 0-3. TST_CTRL_DIG. Register Bits TST_CTRL_DIG Value Description 0x0 No mode is active 0xF Continuous Transmission enabled All other values are reserved 166 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Appendix B - Errata AT86RF232 Rev. A Potential current peak in radio transceiver state SLEEP When leaving active states like receive or transmit immediately towards SLEEP state, a transient current peak of a few µA at DEVDD may occur for a short period of time. Occurance depends on operational parameters as well as load capacitance at pin 29 (AVDD). Problem Fix/Workaround Place an external resistor (for example 220kΩ) between AVDD and AVSS, in parallel to the AVDD load capacitor. Potential long PLL settling duration In very rare cases a PLL_LOCK interrupt is not generated within the specified maximum tPLL_INIT = 250µs PLL lock duration. Problem Fix/Workaround In such a case perform the following action: - read the register bits PLL_CF (register 0x1A, PLL_CF) - invert the LSB bit - write the value back to the PLL_CF register; keep upper four bits as read before - wait a additional typical tPLL_INIT = 80µs duration or until interrupt is generated 167 8321A–MCU Wireless–10/11 References 168 [1] IEEE Std 802.15.4™-2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs) [2] IEEE Std 802.15.4™-2003: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs) [3] ANSI / ESD-STM5.1-2001: ESD Association Standard Test Method for electrostatic discharge sensitivity testing – Human Body Model (HBM). [4] ESD-STM5.3.1-1999: ESD Association Standard Test Method for electrostatic discharge sensitivity testing – Charged Device Model (CDM). [5] NIST FIPS PUB 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/NIST, November 26, 2001 [6] AT86RF232 Software Programming Model [7] IEEE Std 802.15.4™-2011: Low-Rate Wireless Personal Area Networks (WPANs) AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 Data Sheet Revision History Rev. 8321A–MCU Wireless–10/11 1. Initial release 169 8321A–MCU Wireless–10/11 Table of Contents 1 Pin-out Diagram .................................................................................. 2 1.1 Pin Descriptions...................................................................................................... 3 1.2 Analog and RF Pins ............................................................................................... 4 1.2.1 Supply and Ground Pins................................................................................................ 4 1.2.2 RF Pins.......................................................................................................................... 4 1.2.3 Crystal Oscillator Pins ................................................................................................... 5 1.2.4 Analog Pin Summary ..................................................................................................... 5 1.3 Digital Pins .............................................................................................................. 6 1.3.1 Driver Strength Settings ................................................................................................ 6 1.3.2 Pull-up and Pull-down Configuration ............................................................................. 6 2 Disclaimer ............................................................................................ 7 3 Overview .............................................................................................. 7 4 General Circuit Description................................................................ 8 5 Application Circuits .......................................................................... 10 5.1 Basic Application Schematic ................................................................................ 10 5.2 Extended Feature Set Application Schematic ...................................................... 12 6 Microcontroller Interface .................................................................. 14 6.1 SPI Timing Description ......................................................................................... 15 6.2 SPI Protocol.......................................................................................................... 16 6.2.1 Register Access Mode................................................................................................. 16 6.2.2 Frame Buffer Access Mode ......................................................................................... 17 6.2.3 SRAM Access Mode.................................................................................................... 19 6.3 Radio Transceiver Status information .................................................................. 21 6.3.1 Register Description .................................................................................................... 21 6.4 Radio Transceiver Identification ........................................................................... 22 6.4.1 Register Description .................................................................................................... 22 6.5 Sleep/Wake-up and Transmit Signal (SLP_TR) ................................................... 24 6.6 Interrupt Logic....................................................................................................... 25 6.6.1 Overview ..................................................................................................................... 25 6.6.2 Interrupt Mask Modes and Pin Polarity ........................................................................ 26 6.6.3 Register Description .................................................................................................... 27 7 Operating Modes............................................................................... 30 7.1 Basic Operating Mode .......................................................................................... 30 7.1.1 State Control ............................................................................................................... 30 7.1.2 Basic Operating Mode Description .............................................................................. 31 7.1.3 Interrupt Handling ........................................................................................................ 35 7.1.4 Basic Operating Mode Timing ..................................................................................... 36 7.1.5 Register Description .................................................................................................... 41 7.2 Extended Operating Mode ................................................................................... 43 7.2.1 State Control ............................................................................................................... 45 7.2.2 Configuration ............................................................................................................... 46 7.2.3 RX_AACK_ON – Receive with Automatic ACK ........................................................... 47 170 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 7.2.4 TX_ARET_ON – Transmit with Automatic Frame Retransmission and CSMA-CA Retry ............................................................................................................................................. 58 7.2.5 Interrupt Handling ........................................................................................................ 61 7.2.6 Register Summary ....................................................................................................... 62 7.2.7 Register Description – Control Registers..................................................................... 62 7.2.8 Register Description – Address Registers ................................................................... 75 8 Functional Description ..................................................................... 79 8.1 Introduction – IEEE 802.15.4-2006 Frame Format .............................................. 79 8.1.1 PHY Protocol Layer Data Unit (PPDU) ........................................................................ 79 8.1.2 MAC Protocol Layer Data Unit (MPDU)....................................................................... 80 8.2 Frame Check Sequence (FCS) ............................................................................ 84 8.2.1 Overview ..................................................................................................................... 84 8.2.2 CRC calculation ........................................................................................................... 84 8.2.3 Automatic FCS generation .......................................................................................... 85 8.2.4 Automatic FCS check .................................................................................................. 85 8.2.5 Register Description .................................................................................................... 86 8.3 Received Signal Strength Indicator (RSSI) .......................................................... 88 8.3.1 Overview ..................................................................................................................... 88 8.3.2 Reading RSSI.............................................................................................................. 88 8.3.3 Data Interpretation ....................................................................................................... 88 8.3.4 Register Description .................................................................................................... 89 8.4 Energy Detection (ED) ......................................................................................... 90 8.4.1 Overview ..................................................................................................................... 90 8.4.2 Measurement Description............................................................................................ 90 8.4.3 Data Interpretation ....................................................................................................... 91 8.4.4 Interrupt Handling ........................................................................................................ 91 8.4.5 Register Description .................................................................................................... 92 8.5 Clear Channel Assessment (CCA) ....................................................................... 93 8.5.1 Overview ..................................................................................................................... 93 8.5.2 Configuration and Request .......................................................................................... 93 8.5.3 Data Interpretation ....................................................................................................... 94 8.5.4 Interrupt Handling ........................................................................................................ 94 8.5.5 Measurement Time ..................................................................................................... 94 8.5.6 Register Description .................................................................................................... 95 8.6 Link Quality Indication (LQI) ................................................................................. 98 8.6.1 Overview ..................................................................................................................... 98 8.6.2 Request an LQI Measurement .................................................................................... 99 8.6.3 Data Interpretation ....................................................................................................... 99 9 Module Description ......................................................................... 100 9.1 Receiver (RX) ..................................................................................................... 100 9.1.1 Overview ................................................................................................................... 100 9.1.2 Frame Receive Procedure......................................................................................... 100 9.1.3 Configuration ............................................................................................................. 100 9.1.4 Register Description .................................................................................................. 101 9.2 Transmitter (TX) ................................................................................................. 103 9.2.1 Overview ................................................................................................................... 103 9.2.2 Frame Transmit Procedure........................................................................................ 103 9.2.3 Configuration ............................................................................................................. 103 9.2.4 TX Power Ramping ................................................................................................... 104 171 8321A–MCU Wireless–10/11 9.2.5 Register Description .................................................................................................. 104 9.3 Frame Buffer....................................................................................................... 105 9.3.1 Data Management ..................................................................................................... 105 9.3.2 User accessible Frame Content ................................................................................ 106 9.3.3 Interrupt Handling ...................................................................................................... 106 9.4 Voltage Regulators (AVREG, DVREG) .............................................................. 108 9.4.1 Overview ................................................................................................................... 108 9.4.2 Configuration ............................................................................................................. 108 9.4.3 Data Interpretation ..................................................................................................... 108 9.4.4 Register Description .................................................................................................. 109 9.5 Battery Monitor (BATMON) ................................................................................ 111 9.5.1 Overview ................................................................................................................... 111 9.5.2 Configuration ............................................................................................................. 111 9.5.3 Data Interpretation ..................................................................................................... 111 9.5.4 Interrupt Handling ...................................................................................................... 112 9.5.5 Register Description .................................................................................................. 112 9.6 Crystal Oscillator (XOSC) ................................................................................... 114 9.6.1 Overview ................................................................................................................... 114 9.6.2 Integrated Oscillator Setup ........................................................................................ 114 9.6.3 External Reference Frequency Setup ....................................................................... 115 9.6.4 Master Clock Signal Output (CLKM).......................................................................... 115 9.6.5 Register Description .................................................................................................. 116 9.7 Frequency Synthesizer (PLL) ............................................................................. 118 9.7.1 Overview ................................................................................................................... 118 9.7.2 RF Channel Selection................................................................................................ 118 9.7.3 Frequency Agility ....................................................................................................... 118 9.7.4 Calibration Loops ...................................................................................................... 118 9.7.5 Interrupt Handling ...................................................................................................... 119 9.7.6 Register Description .................................................................................................. 119 9.8 Automatic Filter Tuning (FTN) ............................................................................ 122 9.8.1 Overview ................................................................................................................... 122 9.8.2 Register Description .................................................................................................. 122 10 Radio Transceiver Usage ............................................................. 123 10.1 Frame Receive Procedure ............................................................................... 123 10.2 Frame Transmit Procedure .............................................................................. 124 11 AT86RF232 Extended Feature Set ............................................... 125 11.1 Security Module (AES) ..................................................................................... 125 11.1.1 Overview ................................................................................................................. 125 11.1.2 Security Module Preparation ................................................................................... 125 11.1.3 Security Key Setup .................................................................................................. 126 11.1.4 Security Operation Modes ....................................................................................... 126 11.1.5 Data Transfer – Fast SRAM Access ........................................................................ 129 11.1.6 Start of Security Operation and Status .................................................................... 130 11.1.7 SRAM Register Summary ....................................................................................... 130 11.1.8 AES SRAM Configuration Register ......................................................................... 130 11.2 Random Number Generator ............................................................................. 133 11.2.1 Overview ................................................................................................................. 133 11.2.2 Register Description ................................................................................................ 133 172 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 11.3 Antenna Diversity ............................................................................................. 134 11.3.1 Overview ................................................................................................................. 134 11.3.2 Antenna Diversity Application Example ................................................................... 134 11.3.3 Antenna Diversity Sensitivity Control ....................................................................... 135 11.3.4 Register Description ................................................................................................ 136 11.4 RX and TX Frame Time Stamping (TX_ARET) ............................................... 139 11.4.1 Overview ................................................................................................................. 139 11.4.2 Register Description ................................................................................................ 139 11.5 Frame Buffer Empty Indicator .......................................................................... 141 11.5.1 Overview ................................................................................................................. 141 11.5.2 Register Description ................................................................................................ 142 11.6 Dynamic Frame Buffer Protection .................................................................... 143 11.6.1 Overview ................................................................................................................. 143 11.6.2 Register Description ................................................................................................ 143 12 Electrical Characteristics ............................................................. 144 12.1 Absolute Maximum Ratings .............................................................................. 144 12.2 Recommended Operating Range..................................................................... 144 12.3 Digital Pin Characteristics ................................................................................ 144 12.4 Digital Interface Timing Characteristics ............................................................ 145 12.5 General RF Specifications ................................................................................ 146 12.6 Transmitter Characteristics .............................................................................. 146 12.7 Receiver Characteristics .................................................................................. 147 12.8 Current Consumption Specifications ................................................................ 148 12.9 Crystal Parameter Requirements ..................................................................... 148 13 Typical Characteristics ................................................................. 149 13.1 Active Supply Current ....................................................................................... 149 13.1.1 P_ON and TRX_OFF states .................................................................................... 149 13.1.2 PLL_ON state .......................................................................................................... 150 13.1.3 RX_ON state ........................................................................................................... 151 13.1.4 TX_BUSY state ....................................................................................................... 152 13.1.5 SLEEP ..................................................................................................................... 153 13.2 State Transition Timing .................................................................................... 154 14 Register Reference ....................................................................... 156 15 Abbreviations ................................................................................ 159 16 Ordering Information .................................................................... 162 17 Soldering Information ................................................................... 162 18 Package Thermal Properties ........................................................ 162 19 Package Drawing – 32QN2 ........................................................... 163 Appendix A - Continuous Transmission Test Mode ....................... 164 A.1 - Overview .......................................................................................................... 164 A.2 - Configuration.................................................................................................... 164 173 8321A–MCU Wireless–10/11 A.3 – Register Description ........................................................................................ 166 Appendix B - Errata ........................................................................... 167 AT86RF232 Rev. A .................................................................................................. 167 References.......................................................................................... 168 Data Sheet Revision History ............................................................. 169 8321A–MCU Wireless–10/11 ................................................................................... 169 Table of Contents............................................................................... 170 174 AT86RF232 8321A–MCU Wireless–10/11 AT86RF232 © 175 8321A–MCU Wireless–10/11