9202-076 ESCC Detail Specification - Complete

Pages 1 to 34
INTEGRATED CIRCUITS, SILICON MONOLITHIC, CMOS,
GATE ARRAY/EMBEDDED ARRAY
BASED ON TYPE MH1RT
ESCC Detail Specification No. 9202/076
Issue 4
November 2010
Document Custodian: European Space Agency - see https://escies.org
ESCC Detail Specification No. 9202/076
PAGE 2
ISSUE 4
LEGAL DISCLAIMER AND COPYRIGHT
European Space Agency, Copyright © 2010. All rights reserved.
The European Space Agency disclaims any liability or responsibility, to any person or entity, with respect
to any loss or damage caused, or alleged to be caused, directly or indirectly by the use and application
of this ESCC publication.
This publication, without the prior permission of the European Space Agency and provided that it is not
used for a commercial purpose, may be:
–
copied in whole, in any medium, without alteration or modification.
–
copied in part, in any medium, provided that the ESCC document identification, comprising the
ESCC symbol, document number and document issue, is removed.
ESCC Detail Specification No. 9202/076
PAGE 3
ISSUE 4
DOCUMENTATION CHANGE NOTICE
(Refer to https://escies.org for ESCC DCR content)
DCR No. CHANGE DESCRIPTION
615, 633 Specification upissued to incorporate technical and editorial changes per DCRs.
ESCC Detail Specification No. 9202/076
PAGE 4
ISSUE 4
TABLE OF CONTENTS
1.
GENERAL
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.5
1.6
1.7
1.7.1
1.7.2
1.7.3
1.7.4
1.7.5
1.7.6
1.7.7
1.8
1.9
1.10
1.11
Scope
Applicable Documents
Terms, Definitions, Abbreviations, Symbols and Units
The ESCC Component Number and Component Type Variants
The ESCC Component Number
Component Type Variants
Manufacturer Specific ASIC Identification
Maximum Ratings
Handling Precautions
Physical Dimensions and Terminal Identification
Multilayer Quad Flat Package (MQFP-F196) - 196 Flat Leads
Multilayer Quad Flat Package (MQFP-F256) - 256 Flat Leads
Multilayer Quad Flat Package (MQFP-T352) - 352 Tied Leads
Multilayer Column Grid Array (MCGA-349) - 349 Columns
Multilayer Column Grid Array (MCGA-472) - 472 Columns
Land Grid Array (LGA-349) - 349 Pads
Land Grid Array (LGA-472) - 472 Pads
Functional Diagram
Pin Assignment
Instruction Set and Timing Diagrams
Protection Network
5
5
5
5
5
5
11
11
12
13
13
14
15
17
18
20
21
22
22
22
23
2.
REQUIREMENTS
23
2.1
2.1.1
2.1.1.1
2.2
2.3
2.3.1
2.3.1.1
General
Deviations from the Generic Specification
Deviations from Screening Tests
Marking
Electrical Measurements at Room, High and Low Temperatures
Room Temperature Electrical Measurements
Room Temperature Electrical Measurements for Components Specified at Single Supply
Voltage VDD = 2.5V
Room Temperature Electrical Measurements for Components Specified at Single Supply
Voltage VDD = 3V
Room Temperature Electrical Measurements for Components Specified at Single Supply
Voltage VDD = 3.3V
Room Temperature Electrical Measurements for Components Specified for Bi-voltage
Operation at VDD = 2.5V, 3V or 3.3V and VCC = 5V.
Notes to Electrical Measurements Tables
High and Low Temperatures Electrical Measurements
Parameter Drift Values
Intermediate and End-Point Electrical Measurements
Power Burn-in Conditions
Operating Life Conditions
Total Dose Radiation Testing
Bias Conditions and Total Dose Level for Total Dose Radiation Testing
Electrical Measurements for Total Dose Radiation Testing
23
23
23
23
24
24
2.3.1.2
2.3.1.3
2.3.1.4
2.3.2
2.3.3
2.4
2.5
2.6
2.7
2.8
2.8.1
2.8.2
5
24
26
28
29
31
32
32
33
33
33
33
33
33
ESCC Detail Specification No. 9202/076
PAGE 5
ISSUE 4
1.
GENERAL
1.1
SCOPE
This specification details the ratings, physical and electrical characteristics and test and inspection data
for the component type variants and/or the range of components specified below. It supplements the
requirements of, and shall be read in conjunction with, the ESCC Generic Specification listed under
Applicable Documents.
1.2
APPLICABLE DOCUMENTS
The following documents form part of this specification and shall be read in conjunction with it:
(a) ESCC Generic Specification No. 9000.
(b) MIL-STD-883, Test Methods and Procedures for Microelectronics.
1.3
TERMS, DEFINITIONS, ABBREVIATIONS, SYMBOLS AND UNITS
For the purpose of this specification, the terms, definitions, abbreviations, symbols and units specified in
ESCC Basic Specification No. 21300 shall apply.
1.4
THE ESCC COMPONENT NUMBER AND COMPONENT TYPE VARIANTS
1.4.1
The ESCC Component Number
The ESCC Component number shall be constituted as follows:
Example: 920207601RXYZ
•
Detail Specification Reference: 9202076
•
Component Type Variant Number: 01 (as required)
•
Total Dose Radiation Level Letter: R (as required)
•
Manufacturer Specific ASIC Identification: XYZ (as applicable) where:
XYZ : Individual 3 character code allocated by the Manufacturer to a specific ASIC design.
1.4.2
Component Type Variants
The component type variants applicable to this specification are as follows:
Variant
Number
Based on
Type
Circuit
Function
Supply
Voltage
Case
Terminal
Material
and Finish
(Note 5)
Weight
Total Dose
max g Radiation Level
Letter
(Note 6)
Notes
01
TH1099ER
988000 sites
Single
Supply
(3V)
MQFP-T352
D2
27
R
[100kRAD(Si)]
1, 3
02
TH1099ER
988000 sites
Single
Supply
(3V)
MQFP-F256
D2
14
R
[100kRAD(Si)]
1, 3
ESCC Detail Specification No. 9202/076
PAGE 6
ISSUE 4
Variant
Number
Based on
Type
Circuit
Function
Supply
Voltage
Case
Terminal
Material
and Finish
(Note 5)
Weight
Total Dose
max g Radiation Level
Letter
(Note 6)
Notes
03
TH1099ER
988000 sites
Single
Supply
(3V)
MQFP-F196
D2
10
R
[100kRAD(Si)]
1, 3
04
TH1099ER
988000 sites
Single
Supply
(3V)
MCGA-349
R
9
R
[100kRAD(Si)]
1, 3
05
TH1156ER
1558000 sites
Single
Supply
(3V)
MQFP-T352
D2
27
R
[100kRAD(Si)]
1, 3
06
TH1156ER
1558000 sites
Single
Supply
(3V)
MQFP-F256
D2
14
R
[100kRAD(Si)]
1, 3
07
TH1156ER
1558000 sites
Single
Supply
(3V)
MCGA-472
R
12
R
[100kRAD(Si)]
1, 3
08
TH1156ER
1558000 sites
Single
Supply
(3V)
MCGA-349
R
9
R
[100kRAD(Si)]
1, 3
09
TH1242ER
2422000 sites
Single
Supply
(3V)
MQFP-T352
D2
27
R
[100kRAD(Si)]
1, 3
10
TH1242ER
2422000 sites
Single
Supply
(3V)
MQFP-F256
D2
14
R
[100kRAD(Si)]
1, 3
11
TH1242ER
2422000 sites
Single
Supply
(3V)
MCGA-472
R
12
R
[100kRAD(Si)]
1, 3
12
TH1242ER
2422000 sites
Single
Supply
(3V)
MCGA-349
R
9
R
[100kRAD(Si)]
1, 3
13
TH1332ER
3319000 sites
Single
Supply
(3V)
MCGA-472
R
12
R
[100kRAD(Si)]
1, 3
14
TH1099ES
988000 sites
Bi-voltage
Supply
(3V/5V)
MQFP-T352
D2
27
R
[100kRAD(Si)]
2, 3
15
TH1099ES
988000 sites
Bi-voltage
Supply
(3V/5V)
MQFP-F256
D2
14
R
[100kRAD(Si)]
2, 3
16
TH1099ES
988000 sites
Bi-voltage
Supply
(3V/5V)
MQFP-F196
D2
10
R
[100kRAD(Si)]
2, 3
ESCC Detail Specification No. 9202/076
PAGE 7
ISSUE 4
Variant
Number
Based on
Type
Circuit
Function
Supply
Voltage
Case
Terminal
Material
and Finish
(Note 5)
Weight
Total Dose
max g Radiation Level
Letter
(Note 6)
Notes
17
TH1099ES
988000 sites
Bi-voltage
Supply
(3V/5V)
MCGA-349
R
9
R
[100kRAD(Si)]
2, 3
18
TH1156ES
1558000 sites
Bi-voltage
Supply
(3V/5V)
MQFP-T352
D2
27
R
[100kRAD(Si)]
2, 3
19
TH1156ES
1558000 sites
Bi-voltage
Supply
(3V/5V)
MQFP-F256
D2
14
R
[100kRAD(Si)]
2, 3
20
TH1156ES
1558000 sites
Bi-voltage
Supply
(3V/5V)
MCGA-472
R
12
R
[100kRAD(Si)]
2, 3
21
TH1156ES
1558000 sites
Bi-voltage
Supply
(3V/5V)
MCGA-349
R
9
R
[100kRAD(Si)]
2, 3
22
TH1242ES
2422000 sites
Bi-voltage
Supply
(3V/5V)
MQFP-T352
D2
27
R
[100kRAD(Si)]
2, 3
23
TH1242ES
2422000 sites
Bi-voltage
Supply
(3V/5V)
MQFP-F256
D2
14
R
[100kRAD(Si)]
2, 3
24
TH1242ES
2422000 sites
Bi-voltage
Supply
(3V/5V)
MCGA-472
R
12
R
[100kRAD(Si)]
2, 3
25
TH1242ES
2422000 sites
Bi-voltage
Supply
(3V/5V)
MCGA-349
R
9
R
[100kRAD(Si)]
2, 3
26
TH1332ES
3319000 sites
Bi-voltage
Supply
(3V/5V)
MCGA-472
R
12
R
[100kRAD(Si)]
2, 3
27
TH1M099ER
988000 sites
composite
Single
Supply
(3V)
MQFP-T352
D2
27
R
[100kRAD(Si)]
1, 4
28
TH1M099ER
988000 sites
composite
Single
Supply
(3V)
MQFP-F256
D2
14
R
[100kRAD(Si)]
1, 4
29
TH1M099ER
988000 sites
composite
Single
Supply
(3V)
MQFP-F196
D2
10
R
[100kRAD(Si)]
1, 4
30
TH1M099ER
988000 sites
composite
Single
Supply
(3V)
MCGA-349
R
9
R
[100kRAD(Si)]
1, 4
ESCC Detail Specification No. 9202/076
PAGE 8
ISSUE 4
Variant
Number
Based on
Type
Circuit
Function
Supply
Voltage
Case
Terminal
Material
and Finish
(Note 5)
Weight
Total Dose
max g Radiation Level
Letter
(Note 6)
Notes
31
TH1M156ER
1558000 sites
composite
Single
Supply
(3V)
MQFP-T352
D2
27
R
[100kRAD(Si)]
1, 4
32
TH1M156ER
1558000 sites
composite
Single
Supply
(3V)
MQFP-F256
D2
14
R
[100kRAD(Si)]
1, 4
33
TH1M156ER
1558000 sites
composite
Single
Supply
(3V)
MCGA-472
R
12
R
[100kRAD(Si)]
1, 4
34
TH1M156ER
1558000 sites
composite
Single
Supply
(3V)
MCGA-349
R
9
R
[100kRAD(Si)]
1, 4
35
TH1M242ER
2422000 sites
composite
Single
Supply
(3V)
MQFP-T352
D2
27
R
[100kRAD(Si)]
1, 4
36
TH1M242ER
2422000 sites
composite
Single
Supply
(3V)
MQFP-F256
D2
14
R
[100kRAD(Si)]
1, 4
37
TH1M242ER
2422000 sites
composite
Single
Supply
(3V)
MCGA-472
R
12
R
[100kRAD(Si)]
1, 4
38
TH1M242ER
2422000 sites
composite
Single
Supply
(3V)
MCGA-349
R
9
R
[100kRAD(Si)]
1, 4
39
TH1M332ER
3319000 sites
composite
Single
Supply
(3V)
MCGA-472
R
12
R
[100kRAD(Si)]
1, 4
40
TH1M099ES
988000 sites
composite
Bi-voltage
Supply
(3V/5V)
MQFP-T352
D2
27
R
[100kRAD(Si)]
2, 4
41
TH1M099ES
988000 sites
composite
Bi-voltage
Supply
(3V/5V)
MQFP-F256
D2
14
R
[100kRAD(Si)]
2, 4
42
TH1M099ES
988000 sites
composite
Bi-voltage
Supply
(3V/5V)
MQFP-F196
D2
10
R
[100kRAD(Si)]
2, 4
43
TH1M099ES
988000 sites
composite
Bi-voltage
Supply
(3V/5V)
MCGA-349
R
9
R
[100kRAD(Si)]
2, 4
44
TH1M156ES
1558000 sites
composite
Bi-voltage
Supply
(3V/5V)
MQFP-T352
D2
27
R
[100kRAD(Si)]
2, 4
ESCC Detail Specification No. 9202/076
PAGE 9
ISSUE 4
Variant
Number
Based on
Type
Circuit
Function
Supply
Voltage
Case
Terminal
Material
and Finish
(Note 5)
Weight
Total Dose
max g Radiation Level
Letter
(Note 6)
Notes
45
TH1M156ES
1558000 sites
composite
Bi-voltage
Supply
(3V/5V)
MQFP-F256
D2
14
R
[100kRAD(Si)]
2, 4
46
TH1M156ES
1558000 sites
composite
Bi-voltage
Supply
(3V/5V)
MCGA-472
R
12
R
[100kRAD(Si)]
2, 4
47
TH1M156ES
1558000 sites
composite
Bi-voltage
Supply
(3V/5V)
MCGA-349
R
9
R
[100kRAD(Si)]
2, 4
48
TH1M242ES
2422000 sites
composite
Bi-voltage
Supply
(3V/5V)
MQFP-T352
D2
27
R
[100kRAD(Si)]
2, 4
49
TH1M242ES
2422000 sites
composite
Bi-voltage
Supply
(3V/5V)
MQFP-F256
D2
14
R
[100kRAD(Si)]
2, 4
50
TH1M242ES
2422000 sites
composite
Bi-voltage
Supply
(3V/5V)
MCGA-472
R
12
R
[100kRAD(Si)]
2, 4
51
TH1M242ES
2422000 sites
composite
Bi-voltage
Supply
(3V/5V)
MCGA-349
R
9
R
[100kRAD(Si)]
2, 4
52
TH1M332ES
3319000 sites
composite
Bi-voltage
Supply
(3V/5V)
MCGA-472
R
12
R
[100kRAD(Si)]
2, 4
53
TH1099ER
988000 sites
Single
Supply
(3V)
LGA-349
E2
7
R
[100kRAD(Si)]
1, 3
54
TH1156ER
1558000 sites
Single
Supply
(3V)
LGA-472
E2
10
R
[100kRAD(Si)]
1, 3
55
TH1156ER
1558000 sites
Single
Supply
(3V)
LGA-349
E2
7
R
[100kRAD(Si)]
1, 3
56
TH1242ER
2422000 sites
Single
Supply
(3V)
LGA-472
E2
10
R
[100kRAD(Si)]
1, 3
57
TH1242ER
2422000 sites
Single
Supply
(3V)
LGA-349
E2
7
R
[100kRAD(Si)]
1, 3
58
TH1332ER
3319000 sites
Single
Supply
(3V)
LGA-472
E2
10
R
[100kRAD(Si)]
1, 3
ESCC Detail Specification No. 9202/076
PAGE 10
ISSUE 4
Variant
Number
Based on
Type
Circuit
Function
Supply
Voltage
Case
Terminal
Material
and Finish
(Note 5)
Weight
Total Dose
max g Radiation Level
Letter
(Note 6)
Notes
59
TH1099ES
988000 sites
Bi-voltage
Supply
(3V/5V)
LGA-349
E2
7
R
[100kRAD(Si)]
2, 3
60
TH1156ES
1558000 sites
Bi-voltage
Supply
(3V/5V)
LGA-472
E2
10
R
[100kRAD(Si)]
2, 3
61
TH1156ES
1558000 sites
Bi-voltage
Supply
(3V/5V)
LGA-349
E2
7
R
[100kRAD(Si)]
2, 3
62
TH1242ES
2422000 sites
Bi-voltage
Supply
(3V/5V)
LGA-472
E2
10
R
[100kRAD(Si)]
2, 3
63
TH1242ES
2422000 sites
Bi-voltage
Supply
(3V/5V)
LGA-349
E2
7
R
[100kRAD(Si)]
2, 3
64
TH1332ES
3319000 sites
Bi-voltage
Supply
(3V/5V)
LGA-472
E2
10
R
[100kRAD(Si)]
2, 3
65
TH1M099ER
988000 sites
composite
Single
Supply
(3V)
LGA-349
E2
7
R
[100kRAD(Si)]
1, 4
66
TH1M156ER
1558000 sites
composite
Single
Supply
(3V)
LGA-472
E2
10
R
[100kRAD(Si)]
1, 4
67
TH1M156ER
1558000 sites
composite
Single
Supply
(3V)
LGA-349
E2
7
R
[100kRAD(Si)]
1, 4
68
TH1M242ER
2422000 sites
composite
Single
Supply
(3V)
LGA-472
E2
10
R
[100kRAD(Si)]
1, 4
69
TH1M242ER
2422000 sites
composite
Single
Supply
(3V)
LGA-349
E2
7
R
[100kRAD(Si)]
1, 4
70
TH1M332ER
3319000 sites
composite
Single
Supply
(3V)
LGA-472
E2
10
R
[100kRAD(Si)]
1, 4
71
TH1M099ES
988000 sites
composite
Bi-voltage
Supply
(3V/5V)
LGA-349
E2
7
R
[100kRAD(Si)]
2, 4
72
TH1M156ES
1558000 sites
composite
Bi-voltage
Supply
(3V/5V)
LGA-472
E2
10
R
[100kRAD(Si)]
2, 4
PAGE 11
ESCC Detail Specification No. 9202/076
ISSUE 4
Variant
Number
Based on
Type
Circuit
Function
Supply
Voltage
Case
Terminal
Material
and Finish
(Note 5)
Weight
Total Dose
max g Radiation Level
Letter
(Note 6)
Notes
73
TH1M156ES
1558000 sites
composite
Bi-voltage
Supply
(3V/5V)
LGA-349
E2
7
R
[100kRAD(Si)]
2, 4
74
TH1M242ES
2422000 sites
composite
Bi-voltage
Supply
(3V/5V)
LGA-472
E2
10
R
[100kRAD(Si)]
2, 4
75
TH1M242ES
2422000 sites
composite
Bi-voltage
Supply
(3V/5V)
LGA-349
E2
7
R
[100kRAD(Si)]
2, 4
76
TH1M332ES
3319000 sites
composite
Bi-voltage
Supply
(3V/5V)
LGA-472
E2
10
R
[100kRAD(Si)]
2, 4
NOTES:
1. The component is specified for operation at a nominal single supply voltage VDD = 2.5V, 3V or 3.3V.
2. The component is specified for bi-voltage operation at VDD = 2.5V, 3V or 3.3V and inputs and/or
outputs tolerant or compliant to VCC = 5V.
3. The ASIC design will be customised at metal levels.
4. The ASIC design will be customised at base wafer and metal levels.
5. The terminal material and finish shall be in accordance with the requirements of ESCC Basic
Specification No. 23500.
6. The total dose radiation level letter shall be as defined in ESCC Basic Specification No. 22900. If an
alternative radiation test level is specified in the Purchase Order the letter shall be changed
accordingly.
1.4.3
Manufacturer Specific ASIC Identification
An ASIC Sheet shall be produced by the Manufacturer, after negotiation with the Orderer, that, as a
minimum, specifies all the requirements unique to the specific ASIC design that are identified herein as
being specified in the ASIC Sheet. The ASIC Sheet shall be held under configuration control by the
Manufacturer. For identification and traceability purposes the Manufacturer shall allocate a unique
Manufacturer Specific ASIC Identification to the ASIC Sheet and the specific ASIC design as specified
in The ESCC Component Number herein.
1.5
MAXIMUM RATINGS
The maximum ratings shall not be exceeded at any time during use or storage.
Maximum ratings shall only be exceeded during testing to the extent specified in this specification and
when stipulated in Test Methods and Procedures of the ESCC Generic Specification.
Characteristics
Symbols
Maximum Ratings
Units
Remarks
Supply Voltage
VDD
VCC
-0.5 to 4
-0.5 to 6
V
Note 1
Input Voltage
2.5V, 3V, 3.3V Range
5V Compliant
5V Tolerant
VIN
V
Note 1, 2
Input Current
IIN
mA
Each Input pin
-0.5 to VDD +0.5
-0.5 to VCC +0.5
-0.5V ≤ VCC ≤ 6
±60
PAGE 12
ESCC Detail Specification No. 9202/076
ISSUE 4
Characteristics
Symbols
Maximum Ratings
Units
PD
See ASIC Sheet
W
IDDop
See ASIC Sheet
mA
Minimum Guaranteed Operating
Temperature Range
Top
-55 to +125
oC
Storage Temperature Range
Tstg
-65 to +150
oC
Tj
+175
oC
Rth(j-c)
See ASIC Sheet
oC/W
Tsol
+300
oC
Device Power Dissipation
(Continuous)
Supply Current
Junction Temperature
Thermal Resistance
Junction to case
Soldering Temperature
Remarks
Tamb, Note 4
Note 3
NOTES:
1. With reference to VSS = 0V.
2. Applicable to all inputs. Input current limited to IIC = ±10mA.
3. Duration 10 seconds maximum at a distance of not less than 1.6mm from the device body and the
same terminal shall not be resoldered until 3 minutes have elapsed.
4. For an individual ASIC design see ASIC Sheet for the actual maximum operating temperature
range.
1.6
HANDLING PRECAUTIONS
These devices are susceptible to damage by electrostatic discharge. Therefore, suitable precautions
shall be employed for protection during all phases of manufacture, testing, packaging, shipment and any
handling.
These components are categorised as Class 3 per ESCC Basic Specification No. 23800 with a Minimum
Critical Path Failure Voltage of 4000 Volts.
PAGE 13
ESCC Detail Specification No. 9202/076
ISSUE 4
1.7
PHYSICAL DIMENSIONS AND TERMINAL IDENTIFICATION
1.7.1
Multilayer Quad Flat Package (MQFP-F196) - 196 Flat Leads
A
D
D1
A1
N1
98
49
99
E
e
50
E1
N2
f
1
147
148
196
c
A2
L
Index Corner
Note 2
Symbols
Dimensions mm
Min
Max
A
2.13
2.65
A1
1.83
2.24
A2
0.202
0.204
c
0.102
0.203
D/E
46.73
47.94
D1/E1
34.03
34.54
e
Notes
1
0.635 BSC
1
f
0.15
0.25
1
L
6.35
6.7
1
N1/N2
49
Each side
NOTES:
1. Applies to all leads.
2. Terminal identification is specified by reference to the index corner as shown.
PAGE 14
ESCC Detail Specification No. 9202/076
ISSUE 4
1.7.2
Multilayer Quad Flat Package (MQFP-F256) - 256 Flat Leads
D
A
D1
A1
e
N2
E
E1
f
256
1
-D-
Index
Corner
(Note 2)
A2
L
c
N1
Symbols
Dimensions mm
Min
Max
A
2.41
3.18
A1
2.06
2.56
A2
0.05
0.36
c
0.1
0.2
D/E
53.23
55.74
D1/E1
36.83
37.34
e
Notes
1
0.508 BSC
1
f
0.15
0.25
1
L
8.2
9.2
1
N1/N2
64
Each side
NOTES:
1. Applies to all leads.
2. Terminal identification is specified by reference to the index corner as shown.
PAGE 15
ESCC Detail Specification No. 9202/076
ISSUE 4
1.7.3
Multilayer Quad Flat Package (MQFP-T352) - 352 Tied Leads
L (LEAD)
L1 (CERAMIC
L
D1
DETAIL A
1
Index Corner
(Note 2)
m
E1
DETAIL A
b
F
e
J
c
A2
A1
K
Symbols
Dimensions mm
Notes
Min
Max
A1
2.35
3.15
A2
0.05
0.35
b
0.19
0.25
1
c
0.11
0.2
1
D1/E1
47.52
48.48
e
0.50 BSC
1
F
4.5
5.5
G
2.5
2.6
J
0.75
1.05
PAGE 16
ESCC Detail Specification No. 9202/076
ISSUE 4
Symbols
Dimensions mm
Min
Max
K
-
0.5
L
74.85
76.4
L1
74.6
75.4
m
2.5
2.65
N1/N2
88
Notes
1
Each side
NOTES:
1. Applies to all leads.
2. Terminal identification is specified by reference to the index corner as shown.
ESCC Detail Specification No. 9202/076
PAGE 17
ISSUE 4
1.7.4
Multilayer Column Grid Array (MCGA-349) - 349 Columns
BOTTOM VIEW
TOP VIEW
D1
D
W
V
U
T
R
P
N
M
L
K
E
E1
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
b
A
A1
A2
e
SEATING PLANE
0.15 - (.006)
Symbols
Dimensions mm
Min
Max
A
4.3
5.9
A1
1.4
1.85
A2
2.4
3.45
b
0.79
0.99
Notes
1
PAGE 18
ESCC Detail Specification No. 9202/076
ISSUE 4
Dimensions mm
Symbols
D/E
Min
Max
24.8
25.2
D1/E1
22.86
e
1.27 BSC
Notes
1
NOTES:
1. Applies to all columns.
2. Terminal identification is specified by reference to the index corner as shown.
1.7.5
Multilayer Column Grid Array (MCGA-472) - 472 Columns
BOTTOM VIEW
TOP VIEW
D1
D
AB
AA
Y
W
V
U
T
R
P
N
M
E1
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
b
A
A1
A2
e
SEATING PLANE
0.15 - (.006)
E
ESCC Detail Specification No. 9202/076
PAGE 19
ISSUE 4
Symbols
Dimensions mm
Min
Max
A
4.3
5.9
A1
1.4
1.85
A2
2.6
3.45
b
0.79
0.99
D/E
28.77
29.23
D1/E1
26.67
e
1.27 BSC
NOTES:
1. Applies to all columns.
2. Terminal identification is specified by reference to the index corner as shown.
Notes
1
1
PAGE 20
ESCC Detail Specification No. 9202/076
ISSUE 4
1.7.6
Land Grid Array (LGA-349) - 349 Pads
BOTTOM VIEW
TOP VIEW
D1
D
e
W
V
U
T
R
P
N
M
L
K
E
E1
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
Øb
Note 2
Note 1
A
A1
SEATING PLANE
0.05
Symbols
Dimensions mm
Min
Max
A
-
3.24
A1
2.27
2.77
Øb
0.81
0.91
D/E
24.85
25.15
D1/E1
22.86 BSC
Notes
3
PAGE 21
ESCC Detail Specification No. 9202/076
ISSUE 4
Dimensions mm
Symbols
Min
e
Notes
Max
1.27 BSC
3
NOTES:
1. Index corner. Terminal identification is specified by reference to the index corner as shown.
2. A terminal identification mark shall be located at the index corner as shown.
3. Applies to all pads.
1.7.7
Land Grid Array (LGA-472) - 472 Pads
BOTTOM VIEW
TOP VIEW
D1
D
e
AB
AA
Y
W
V
U
T
R
P
N
M
E
E1
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
Note 2
Øb
Note 1
A
A1
SEATING PLANE
0.05
ESCC Detail Specification No. 9202/076
PAGE 22
ISSUE 4
Symbols
Dimensions mm
Min
Max
A
-
3.24
A1
2.27
2.77
Øb
0.81
0.91
D/E
28.85
29.15
D1/E1
26.67 BSC
e
1.27 BSC
Notes
3
3
NOTES:
1. Index corner. Terminal identification is specified by reference to the index corner as shown.
2. A terminal identification mark shall be located at the index corner as shown.
3. Applies to all pads.
1.8
FUNCTIONAL DIAGRAM
See ASIC Sheet.
NOTES:
1. For all packages the lid is internally connected to the ground terminal as specified in the ASIC Sheet.
1.9
PIN ASSIGNMENT
See ASIC Sheet.
1.10
INSTRUCTION SET AND TIMING DIAGRAMS
See ASIC Sheet.
ESCC Detail Specification No. 9202/076
PAGE 23
ISSUE 4
1.11
PROTECTION NETWORK
NWELL resistance
(900 W typical)
Input buffer
(if any)
Pad
Output buffer
(in high impedance state
if unused)
2.
REQUIREMENTS
2.1
GENERAL
The complete requirements for procurement of the components specified herein are as stated in this
specification and the ESCC Generic Specification. Permitted deviations from the Generic Specification,
applicable to this specification only, are listed below.
Permitted deviations from the Generic Specification and this Detail Specification, formally agreed with
specific Manufacturers on the basis that the alternative requirements are equivalent to the ESCC
requirement and do not affect the component’s reliability, are listed in the appendices attached to this
specification.
2.1.1
Deviations from the Generic Specification
2.1.1.1
Deviations from Screening Tests
High Temperature Reverse Bias Burn-in shall not be performed.
2.2
MARKING
The marking shall be in accordance with the requirements of ESCC Basic Specification No. 21700 and
PAGE 24
ESCC Detail Specification No. 9202/076
ISSUE 4
as follows.
As a minimum the information to be marked on the component shall be:
(a) The ESCC qualified components symbol (for ESCC qualified components only).
(b) The ESCC Component Number.
(c) Traceability information.
The complete marking shall be as specified in the ASIC Sheet.
2.3
ELECTRICAL MEASUREMENTS AT ROOM, HIGH AND LOW TEMPERATURES
Electrical measurements shall be performed at room, high and low temperatures. Consolidated notes are
given after the tables.
2.3.1
Room Temperature Electrical Measurements
The measurements shall be performed at Tamb = +22 ± 3oC.
2.3.1.1
Room Temperature Electrical Measurements for Components Specified at Single Supply
Voltage VDD = 2.5V
Characteristics
Symbols
MIL-STD-883
Test Method
Test Conditions
Note 1
(VDD = 2.5 ± 0.2V)
Limits
Units
Min
Max
Functional Test 1
-
3014
See ASIC Sheet
VDD=2.3V
-
-
-
Functional Test 2
-
3014
See ASIC Sheet
VDD=2.5V
-
-
-
Functional Test 3
-
3014
See ASIC Sheet
VDD=2.7V
-
-
-
Supply Current,
Stand-by
IDDSB
3005
See ASIC Sheet
mA
Supply Current,
Operating
IDDOP
3005
See ASIC Sheet
mA
Low Level Input
Current
IIL
3009
VIN=VSS,
CMOS Buffers
-
-1
μA
Low Level Input
Current, Pull-up
Resistor PRU1
IILPU
3009
VIN=VSS,
CMOS Buffers
Note 2
70
230
μA
Low Level Input
Current, Pull-down
Resistor PRD1
IILPD
3009
VIN=VSS,
CMOS Buffers
Note 2
-
±5
μA
High Level Input
Current
IIH
3010
VIN=VDD,
CMOS Buffers
-
1
μA
High Level Input
Current, Pull-up
Resistor PRU1
IIHPU
3010
VIN=VDD,
CMOS Buffers
Note 2
-
±5
μA
PAGE 25
ESCC Detail Specification No. 9202/076
ISSUE 4
Characteristics
Symbols
MIL-STD-883
Test Method
Test Conditions
Note 1
(VDD = 2.5 ± 0.2V)
Limits
Units
Min
Max
IIHPD
3010
VIN=VDD,
CMOS Buffers
Note 2
70
540
μA
Low Level Input
Voltage
VIL
-
CMOS Buffers
VDD=2.3V,
-
690
mV
High Level Input
Voltage
VIH
-
CMOS Buffers
VDD=2.7V
1.89
-
V
Positive Trigger
Threshold Voltage
VTP
-
Note 5
1.06
1.61
V
Negative Trigger
Threshold Voltage
VTN
-
Note 5
0.78
1.25
V
Hysteresis Voltage
VH
-
Note 5
250
-
mV
Output Leakage
Current Third
State, Low Level
Applied
IOZL
3020
VOUT=0V, All Buffers
VDD=2.7V
-
-1
μA
Output Leakage
Current Third
State, High Level
Applied
IOZH
3021
VOUT=0V, All Buffers
VDD=2.7V
-
1
μA
Input Current, Cold
Sparing
IICS
-
VIN=0V to 2.7V,
PICZ Buffers
VDD=VSS=0V
-
±2
μA
Output Current,
Cold Sparing
IOCS
-
VOUT=0V to 2.7V,
PO11Z Buffers
VDD=VSS=0V
-
±2
μA
Low Level Output
Voltage
VOL
3007
VDD=2.3V, IOL=800μA
PO11 Buffers
Note 3
-
400
mV
High Level Output
Voltage
VOH
3006
VDD=2.3V,
IOH=-600μA
PO11 Buffers
Note 4
2
-
V
Output Short
Circuit Current, to
VDD
IOSN
-
PO11 output at High
Level shorted to VDD
Note 5
-
15
mA
Output Short
Circuit Current, to
VSS
IOSP
-
PO11 output at High
Level shorted to VSS
Note 5
-
8
mA
Input Capacitance
CIN
3012
Note 5
-
2.4
pF
COUT
3012
Note 5
-
5.6
pF
High Level Input
Current, Pull-down
Resistor PRD1
Output
Capacitance
PAGE 26
ESCC Detail Specification No. 9202/076
ISSUE 4
Characteristics
Input/Output
Capacitance
Timings
2.3.1.2
Symbols
MIL-STD-883
Test Method
CI/O
3012
-
3003
Test Conditions
Note 1
(VDD = 2.5 ± 0.2V)
Note 5
Limits
Units
Min
Max
-
6.6
See ASIC Sheet
pF
ns
Room Temperature Electrical Measurements for Components Specified at Single Supply
Voltage VDD = 3V
Characteristics
Symbols
MIL-STD-883
Test Method
Test Conditions
Note 1
(VDD = 3 ± 0.3V)
Limits
Units
Min
Max
Functional Test 1
-
3014
See ASIC Sheet
VDD=2.7V
-
-
-
Functional Test 2
-
3014
See ASIC Sheet
VDD=3V
-
-
-
Functional Test 3
-
3014
See ASIC Sheet
VDD=3.3V
-
-
-
Supply Current,
Stand-by
IDDSB
3005
See ASIC Sheet
mA
Supply Current,
Operating
IDDOP
3005
See ASIC Sheet
mA
Low Level Input
Current
IIL
3009
VIN=VSS,
CMOS Buffers
-
-1
μA
Low Level Input
Current, Pull-up
Resistor PRU1
IILPU
3009
VIN=VSS,
CMOS Buffers
Note 2
108
330
μA
Low Level Input
Current, Pull-down
Resistor PRD1
IILPD
3009
VIN=VSS,
CMOS Buffers
Note 2
-
±5
μA
High Level Input
Current
IIH
3010
VIN=VDD,
CMOS Buffers
-
1
μA
High Level Input
Current, Pull-up
Resistor PRU1
IIHPU
3010
VIN=VDD,
CMOS Buffers
Note 2
-
±5
μA
High Level Input
Current, Pull-down
Resistor PRD1
IIHPD
3010
VIN=VDD,
CMOS Buffers
Note 2
108
825
μA
Low Level Input
Voltage
VIL
-
CMOS Buffers
VDD=2.7V,
-
800
mV
High Level Input
Voltage
VIH
-
CMOS Buffers
VDD=3.3V
2
-
V
Positive Trigger
Threshold Voltage
VTP
-
Note 5
1.25
1.93
V
PAGE 27
ESCC Detail Specification No. 9202/076
ISSUE 4
Characteristics
Symbols
MIL-STD-883
Test Method
Test Conditions
Note 1
(VDD = 3 ± 0.3V)
Limits
Units
Min
Max
Negative Trigger
Threshold Voltage
VTN
-
Note 5
0.9
1.42
V
Hysteresis Voltage
VH
-
Note 5
310
-
mV
Output Leakage
Current Third
State, Low Level
Applied
IOZL
3020
VOUT=0V, All Buffers
VDD=3.3V
-
-1
μA
Output Leakage
Current Third
State, High Level
Applied
IOZH
3021
VOUT=0V, All Buffers
VDD=3.3V
-
1
μA
Input Current, Cold
Sparing
IICS
-
VIN=0V to 3.3V,
PICZ Buffers
VDD=VSS=0V
-
±2
μA
Output Current,
Cold Sparing
IOCS
-
VOUT=0V to 3.3V,
PO11X Buffers
VDD=VSS=0V
-
±2
μA
Low Level Output
Voltage
VOL
3007
VDD=2.7V, IOL=1mA
PO11 Buffers
Note 3
-
400
mV
High Level Output
Voltage
VOH
3006
VDD=2.7V,
IOH=-800μA
PO11 Buffers
Note 4
2.4
-
V
Output Short
Circuit Current, to
VDD
IOSN
-
PO11 output at High
Level shorted to VDD
Note 5
-
21
mA
Output Short
Circuit Current, to
VSS
IOSP
-
PO11 output at High
Level shorted to VSS
Note 5
-
12
mA
Input Capacitance
CIN
3012
Note 5
-
2.4
pF
Output
Capacitance
COUT
3012
Note 5
-
5.6
pF
Input/Output
Capacitance
CI/O
3012
Note 5
-
6.6
pF
-
3003
Timings
See ASIC Sheet
ns
PAGE 28
ESCC Detail Specification No. 9202/076
ISSUE 4
2.3.1.3
Room Temperature Electrical Measurements for Components Specified at Single Supply
Voltage VDD = 3.3V
Characteristics
Symbols
MIL-STD-883
Test Method
Test Conditions
Note 1
(VDD = 3.3 ± 0.3V)
Limits
Units
Min
Max
Functional Test 1
-
3014
See ASIC Sheet
VDD=3V
-
-
-
Functional Test 2
-
3014
See ASIC Sheet
VDD=3.3V
-
-
-
Functional Test 3
-
3014
See ASIC Sheet
VDD=3.6V
-
-
-
Supply Current,
Stand-by
IDDSB
3005
See ASIC Sheet
mA
Supply Current,
Operating
IDDOP
3005
See ASIC Sheet
mA
Low Level Input
Current
IIL
3009
VIN=VSS,
CMOS Buffers
-
-1
μA
Low Level Input
Current, Pull-up
Resistor PRU1
IILPU
3009
VIN=VSS,
CMOS Buffers
Note 2
120
400
μA
Low Level Input
Current, Pull-down
Resistor PRD1
IILPD
3009
VIN=VSS,
CMOS Buffers
Note 2
-
±5
μA
High Level Input
Current
IIH
3010
VIN=VDD,
CMOS Buffers
-
1
μA
High Level Input
Current, Pull-up
Resistor PRU1
IIHPU
3010
VIN=VDD,
CMOS Buffers
Note 2
-
±5
μA
High Level Input
Current, Pull-down
Resistor PRD1
IIHPD
3010
VIN=VDD,
CMOS Buffers
Note 2
150
900
μA
Low Level Input
Voltage
VIL
-
CMOS Buffers
VDD=3V
-
800
mV
High Level Input
Voltage
VIH
-
CMOS Buffers
VDD=3.6V
2
-
V
Positive Trigger
Threshold Voltage
VTP
-
Note 5
1.4
2.08
V
Negative Trigger
Threshold Voltage
VTN
-
Note 5
0.99
1.51
V
Hysteresis Voltage
VH
-
Note 5
370
-
mV
Output Leakage
Current Third
State, Low Level
Applied
IOZL
3020
-
-1
μA
VOUT=0V, All Buffers
VDD=3.6V
PAGE 29
ESCC Detail Specification No. 9202/076
ISSUE 4
Characteristics
MIL-STD-883
Test Method
Test Conditions
Note 1
(VDD = 3.3 ± 0.3V)
Limits
Units
Min
Max
VOUT=0V, All Buffers
VDD=3.6V
-
1
μA
Output Leakage
Current Third
State, High Level
Applied
IOZH
3021
Input Current, Cold
Sparing
IICS
-
VIN=0V to 3.6V,
PICZ Buffers
VDD=VSS=0V
-
±2
μA
Output Current,
Cold Sparing
IOCS
-
VOUT=0V to 3.6V,
PO11Z Buffers
VDD=VSS=0V
-
±2
μA
Low Level Output
Voltage
VOL
3007
VDD=3V
IOL=2mA
PO11 Buffers
Note 3
-
400
mV
High Level Output
Voltage
VOH
3006
VDD=3V
IOL=-1.8mA
PO11 Buffers
Note 4
2.4
-
V
Output Short
Circuit Current, to
VDD
IOSN
-
PO11 output at High
Level shorted to VDD
Note 5
-
23
mA
Output Short
Circuit Current, to
VSS
IOSP
-
PO11 output at High
Level shorted to VSS
Note 5
-
13
mA
Input Capacitance
CIN
3012
Note 5
-
2.4
pF
Output
Capacitance
COUT
3012
Note 5
-
5.6
pF
Input/Output
Capacitance
CI/O
3012
Note 5
-
6.6
pF
-
3003
Timings
2.3.1.4
Symbols
See ASIC Sheet
ns
Room Temperature Electrical Measurements for Components Specified for Bi-voltage
Operation at VDD = 2.5V, 3V or 3.3V and VCC = 5V.
Characteristics
Symbols
MIL-STD-883
Test Method
Test Conditions
Note 1
[VDD = 2.5 ± 0.2V, 3 ±
0.3V, 3.3 ± 0.3V (Note 6)
VCC=5 ± 0.5V (Note 7)]
Limits
Units
Min
Max
Functional Test 1
-
3014
See ASIC Sheet
VCC=4.5V, VDD=3V
-
-
-
Functional Test 2
-
3014
See ASIC Sheet
VCC=5V, VDD=3.3V
-
-
-
PAGE 30
ESCC Detail Specification No. 9202/076
ISSUE 4
Characteristics
Functional Test 3
Symbols
MIL-STD-883
Test Method
Test Conditions
Note 1
[VDD = 2.5 ± 0.2V, 3 ±
0.3V, 3.3 ± 0.3V (Note 6)
VCC=5 ± 0.5V (Note 7)]
See ASIC Sheet
VCC=5.5V, VDD=3.6V
Limits
Units
Min
Max
-
-
-
3014
-
Supply Current,
Stand-by
IDDSB
3005
See ASIC Sheet
mA
Supply Current,
Operating
IDDOP
3005
See ASIC Sheet
mA
Low Level Input
Current
IIL
3009
VIN=VSS,
CMOS Buffers
-
-1
μA
Low Level Input
Current, Pull-up
Resistor PRU1
IILPU
3009
VIN=VSS,
CMOS Buffers
Note 2
180
690
μA
Low Level Input
Current, Pull-down
Resistor PRD1
IILPD
3009
VIN=VSS,
CMOS Buffers
Note 2
-
±5
μA
High Level Input
Current
IIH
3010
VIN=VDD,
CMOS Buffers
-
1
μA
High Level Input
Current, Pull-up
Resistor PRU1
IIHPU
3010
VIN=VDD,
CMOS Buffers
Note 2
-
±5
μA
High Level Input
Current, Pull-down
Resistor PRD1
IIHPD
3010
VIN=VDD,
CMOS Buffers
Note 2
30
400
μA
Low Level Input
Voltage
VIL
-
PICV, PICV5 Buffers
VDD=VDDmin
-
800
mV
High Level Input
Voltage
VIH
-
PICV, PICV5 Buffers
VDD=VDDmax
2
-
V
Positive Trigger
Threshold Voltage
VTP
-
Note 5
1.4
2.08
V
Negative Trigger
Threshold Voltage
VTN
-
Note 5
0.99
1.51
V
Hysteresis Voltage
VH
-
Note 5
370
-
mV
Output Leakage
Current Third
State, Low Level
Applied
IOZL
3020
VOUT=0V, All Buffers
VDD=3.6V
-
-1
μA
Output Leakage
Current Third
State, High Level
Applied
IOZH
3021
VOUT=0V, All Buffers
VDD=3.6V
-
1
μA
PAGE 31
ESCC Detail Specification No. 9202/076
ISSUE 4
Characteristics
Symbols
MIL-STD-883
Test Method
Test Conditions
Note 1
[VDD = 2.5 ± 0.2V, 3 ±
0.3V, 3.3 ± 0.3V (Note 6)
VCC=5 ± 0.5V (Note 7)]
Units
Min
Max
Input Current, Cold
Sparing
IICS
-
VIN=0V to 3.6V,
PICZ Buffers
VDD=VSS=0V
-
±2
μA
Output Current,
Cold Sparing
IOCS
-
VOUT=0V to 3.6V,
PO11Z Buffers
VDD=VSS=0V
-
±2
μA
Low Level Output
Voltage
VOL
3007
VDD=VDDmin,
VCC=4.5V
-
400
mV
High Level Output
Voltage
VOH
3006
VDD=VDDmin(2.5V),
VCC=4.5V
2
-
V
2.4
-
V
VDD=VDDmin(3V, 3.3V),
VCC=4.5V
Output Short
Circuit Current, to
VDD
IOSN
-
PO11 output at High
Level shorted to VDD
Note 5
-
28
mA
Output Short
Circuit Current, to
VSS
IOSP
-
PO11 output at High
Level shorted to VSS
Note 5
-
17
mA
Input Capacitance
CIN
3012
Note 5
-
2.4
pF
Output
Capacitance
COUT
3012
Note 5
-
5.6
pF
Input/Output
Capacitance
CI/O
3012
Note 5
-
6.6
pF
-
3003
Timing
2.3.2
Limits
See ASIC Sheet
ns
Notes to Electrical Measurements Tables
1. Unless otherwise specified: all inputs and outputs shall be tested for each characteristic; Inputs not
under test shall be VIN = VSS, VCC or VDD and outputs not under test shall be open; VSS = 0V.
2.
Standard pull-ups: PRU# where # = [1-31] index for Ron:
Ron = # x R0 = 19kΩ typical (12 to 30kΩ) in 2.5V range.
Ron = # x R0 = 15kΩ typical (10 to 25kΩ) in 3V range.
Ron = # x R0 = 14kΩ typical (9 to 25kΩ) in 3.3V range.
5V tolerant/compliant pull-ups: PRU# where # = [1-31] index for Ron:
Ron = # x R0 = 14kΩ typical (8 to 25kΩ) in each range.
Standard pull-downs: PRD# where # = [1-31] index for Ron:
Ron = # x R0 = 11kΩ typical (5 to 30kΩ) in 2.5V range.
Ron = # x R0 = 9kΩ typical (4 to 25kΩ) in 3V range.
Ron = # x R0 = 8kΩ typical (4 to 20kΩ) in 3.3V range.
5V tolerant/compliant pull-downs: PRD# where # = [1-31] index for Ron:
Ron = # x R0 = 36kΩ typical (17 to 80kΩ) in 2.5V range.
Ron = # x R0 = 23kΩ typical (11 to 55kΩ) in 3V range.
Ron = # x R0 = 19kΩ typical (9 to 45kΩ) in 3.3V range.
ESCC Detail Specification No. 9202/076
PAGE 32
ISSUE 4
3.
Output buffers: PO$# where
$ = [1-12] quantity of output driving capability of p-channels.
#=[1-12] quantity of output driving capability of n-channels.
Standard buffers (including cold sparing)
IO = 1.6, 1.8, 2mA measured at VOL = 400, 400, 400mV in 2.5, 3, 3.3V range respectively.
Tolerance buffers (including cold sparing)
IO = 1, 1.3, 1.4mA measured at VOL = 400, 400, 400mV in 2.5, 3, 3.3V range respectively.
Compliant buffers (VCC = 4.5V)
IO = 1.1, 1.4, 1.6mA measured at VOL = 400, 400, 400mV in 2.5, 3, 3.3V range respectively.
4.
Output buffers: PO$# where
$ = [1-12] quantity of output driving capability of p-channels.
#=[1-12] quantity of output driving capability of n-channels.
Standard buffers (including cold sparing)
IO = -1.6, -1.8, -2mA measured at VOL = 2, 2.4, 2.4V in 2.5, 3, 3.3V range respectively.
Tolerance buffers (including cold sparing)
IO = -1, -1.3, -1.4mA measured at VOL = 2, 2.4, 2.4V in 2.5, 3, 3.3V range respectively.
Compliant buffers (VCC = 4.5V)
IO = -1.1, -1.4, -1.6mA measured at VOL = 2, 2.4, 2.4V in 2.5, 3, 3.3V range respectively.
5.
Guaranteed but not tested.
6.
5V tolerant buffers.
7.
5V compliant buffers.
2.3.3
High and Low Temperatures Electrical Measurements
Unless otherwise specified the measurements shall be performed at Tamb = +125 (+0 -5)oC and Tamb =
-55 (+5 - 0)oC. Unless otherwise specified the characteristics, test methods, conditions and limits shall
be the same as specified for Room Temperature Electrical Measurements.
2.4
PARAMETER DRIFT VALUES
Unless otherwise specified, the measurements shall be performed at Tamb = +22 ± 3oC.
The test methods and test conditions shall be as per the corresponding test defined in Room
Temperature Electrical Measurements.
The drift values (Δ) shall not be exceeded for each characteristic specified. The corresponding absolute
limit values for each characteristic shall not be exceeded.
PAGE 33
ESCC Detail Specification No. 9202/076
ISSUE 4
Characteristics
Symbols
Limits
Drift
Value
Δ
Supply Current, Stand-by
IDDSB
Units
Absolute
Min
Max
See ASIC Sheet
mA
Low Level Input Current
IIL
±0.1
-
-1
μA
High Level Input Current
IIH
±0.1
-
1
μA
Output Leakage Current Third State,
Low Level Applied
IOZL
±0.1
-
-1
μA
Output Leakage Current Third State,
High Level Applied
IOZH
±0.1
-
1
μA
Low Level Output Voltage
VOL
±100
-
400
mV
High Level Output Voltage
VOH
±0.1
2.4 or 2
-
V
NOTES:
1. Unless otherwise specified all inputs and outputs shall be tested for each characteristic.
2.5
INTERMEDIATE AND END-POINT ELECTRICAL MEASUREMENTS
Unless otherwise specified, the measurements shall be performed at Tamb = +22 ± 3oC. Unless
otherwise specified the characteristics, test methods, conditions and limits shall be the same as specified
for Room Temperature Electrical Measurements.
2.6
POWER BURN-IN CONDITIONS
See ASIC Sheet.
2.7
OPERATING LIFE CONDITIONS
Unless otherwise specified the conditions shall be as specified for Power Burn-in.
2.8
TOTAL DOSE RADIATION TESTING
2.8.1
Bias Conditions and Total Dose Level for Total Dose Radiation Testing
Continuous bias shall be applied during irradiation testing as specified in the ASIC Sheet.
The total dose level applied shall be as specified in the component type variant information herein, in the
ASIC Sheet or in the Purchase Order.
2.8.2
Electrical Measurements for Total Dose Radiation Testing
Prior to irradiation testing the devices shall have successfully met Room Temperature Electrical
Measurements specified herein.
Unless otherwise stated the measurements shall be performed at Tamb = +22 ± 3oC.
The test methods and test conditions shall be as per the corresponding test defined in Room
Temperature Electrical Measurements.
ESCC Detail Specification No. 9202/076
PAGE 34
ISSUE 4
The parameters to be measured during and on completion of irradiation testing are specified in the ASIC
Sheet.
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