ATWILC1000-MR110PB - Complete

ATWILC1000-MR110PB DATASHEET
IEEE 802.11 b/g/n Link Controller SoC
Datasheet
Description
The ATWILC1000-MR110PB is a low-power consumption 802.11 b/g/n IoT
(Internet of Things) module which is specifically optimized for low power IoT
applications. The highly integrated module features small form factor (21.5mm x
14.5mm x 2.1mm) while fully integrating Power Amplifier, LNA, Switch, Power
Management, and PCB antenna. With seamless roaming capabilities and
advanced security, it could be interoperable with various vendors’ 802.11b/g/n
Access Points in wireless LAN. The module provides SPI and SDIO to interface
to host controller.
Features
 IEEE® 802.11 b/g/n 20MHz (1x1) solution
 Single spatial stream in 2.4GHz ISM band
 Integrated PA and T/R Switch
 Superior Sensitivity and Range via advanced PHY signal processing
 Advanced Equalization and Channel Estimation
 Advanced Carrier and Timing Synchronization
 Wi-Fi Direct and Soft-AP support
 Supports IEEE 802.11 WEP, WPA, WPA2 Security
 Supports China WAPI security
 Superior MAC throughput via hardware accelerated two-level A-MSDU/AMPDU frame aggregation and block acknowledgement
 On-chip memory management engine to reduce host load
 SPI, SDIO, UART, and I2C host interfaces
 2/3 wire Bluetooth® coexistence interface
 Operating temperature range of -40°C to +85°C
 Power save modes:
– <1µA Power Down mode typical @3.3V I/O
– 380µA Doze mode with chip settings preserved (used for beacon monitoring)
– On-chip low power sleep oscillator
– Fast host wake-up from Doze mode by a pin or host I/O transaction
Atmel-42503B-WILC1000-MR110PB-SmartConnect_Datasheet_05/2016
Ta bl e of Conte nts
1
Ordering Information and Module Marking ................................................................ 4
2
Block Diagram ............................................................................................................. 5
3
Pin-out and Package Information ............................................................................... 6
3.1
3.2
4
Electrical Specifications ........................................................................................... 10
4.1
4.2
5
6.2
6.3
7.2
7.3
7.4
7.5
2
.............................................................................................................................................. 12
Features ................................................................................................................................. 12
Description.............................................................................................................................. 12
.............................................................................................................................................. 13
Features ................................................................................................................................. 13
Description.............................................................................................................................. 13
.............................................................................................................................................. 13
Receiver Performance ............................................................................................................ 14
Transmitter Performance ........................................................................................................ 15
SPI Interface ....................................................................................................................................... 17
7.1.1 Overview................................................................................................................................. 17
7.1.2 SPI Timing .............................................................................................................................. 17
UART Interface ................................................................................................................................... 19
SDIO Interface .................................................................................................................................... 19
7.3.1 Overview................................................................................................................................. 19
7.3.2 Features ................................................................................................................................. 20
7.3.3 SDIO Timing ........................................................................................................................... 20
I2C Interface ........................................................................................................................................ 21
7.4.1 Overview................................................................................................................................. 21
7.4.2 I2C Timing ............................................................................................................................... 21
Wi-Fi/Bluetooth Coexistence ............................................................................................................... 22
Power Consumption .................................................................................................. 24
8.1
8.2
8.3
8.4
8.5
9
MAC
6.1.1
6.1.2
PHY
6.2.1
6.2.2
Radio
6.3.2
6.3.3
External Interfaces .................................................................................................... 17
7.1
8
Processor ............................................................................................................................................ 11
Memory Subsystem............................................................................................................................. 11
Non-volatile Memory (eFuse) .............................................................................................................. 11
WLAN Subsystem ...................................................................................................... 12
6.1
7
Absolute Ratings ................................................................................................................................. 10
Recommended Operating Ratings ...................................................................................................... 10
CPU and Memory Subsystems ................................................................................. 11
5.1
5.2
5.3
6
Pin Description ...................................................................................................................................... 6
Module Outline Drawings ...................................................................................................................... 8
Description of Device States ............................................................................................................... 24
Current Consumption in Various Device States .................................................................................. 24
Restrictions for Power States .............................................................................................................. 25
Power-up/down Sequence .................................................................................................................. 25
Digital I/O Pin Behavior during Power-up Sequences ......................................................................... 27
Notes on Interfacing to the ATWILC1000-MR110PB ............................................... 28
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9.1
Programmable Pull-up Resistors ......................................................................................................... 28
10 Recommended Footprint (Unit: mm) ........................................................................ 29
11 RF Performance Placement Guidelines ................................................................... 30
12 Reflow Profile Information ........................................................................................ 31
12.1 Storage Condition................................................................................................................................ 31
12.1.1 Moisture Barrier Bag Before Opened ..................................................................................... 31
12.1.2 Moisture Barrier Bag Open ..................................................................................................... 31
12.2 Stencil Design ..................................................................................................................................... 31
12.3 Baking Conditions ............................................................................................................................... 31
12.4 Soldering and Reflow Condition .......................................................................................................... 31
12.4.1 Reflow Oven ........................................................................................................................... 31
13 Application Reference Design .................................................................................. 33
14 Reference Documentation and Support................................................................... 35
14.1 Reference Documents......................................................................................................................... 35
15 Revision History ........................................................................................................ 36
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1
Ordering Information and Module Marking
Table 1-1.
Ordering Code
Package
Description
ATWILC1000-MR110PB
22x15mm
Certified module with ATWILC1000B-Mu chip and PCB antenna
ATWILC1000-MR110UB
22x15mm
Certified module with ATWILC1000B-Mu chip and uFL connector
Figure 1-2.
4
Ordering Details
Marking Information
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Block Diagram
Figure 2-1.
Block Diagram
Printed 2.4GHz
Antenna
VBAT
VDDIO
GPIO3
I2C
RX/TX
SPI_CFG
BALUN
SPI
ATWILC1000B
802.11 B,G,N SOC
GPIO4
GPIO5
GPIO6
IRQN
Chip_EN
WAKE
26 Mhz Crystal
RESET
GND
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3
Pin-out and Package Information
3.1
Pin Description
Figure 3-1.
Pin Assignment
Table 3-1.
Pin Description
NO
Name
1
GPIO_6
2
3
6
I2C_SCL
I2C_SDA
Type
Description
I/O
General purpose I/O
I/O
I2C Slave Clock. Can be configured as either master or slave. I2C interface is only used for test purposes. This pin should be brought to a test point
only. Do not add a pull-up resistor.
I/O
I2C Slave Data. Can be configured as either master
or slave. I2C interface is only used for test purposes. This pin should be brought to a test point
only. Do not add a pull-up resistor.
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Programmable
pull-up resistor
Yes
NO
Name
Type
Description
Programmable
pull-up resistor
Yes
4
RESET_N
I
Active-Low Hard Reset. When asserted to a low
level, the module will be placed in a reset state.
When asserted to a high level, the module will run
normally. Connect to a host output that defaults low
at power up. If the output floats, add a 1M ohm
pull-down resistor if necessary to ensure a low
level at power up.
5
NC
-
No connect
Yes
6
NC
-
No connect
No
7
NC
-
No connect
8
NC
-
No connect
9
GND_1
-
GND
10
SDIO~_SPI_CFG
I
Tie to VDDIO through a 1M ohm resistor to enable
the SPI interface. Connect to ground to enable
SDIO interface.
No
11
WAKE
I
Host Wake control. Can be used to wake up the
module from Doze mode. Connect to a host GPIO.
No
12
GND_2
-
GND
13
IRQN
O
ATWINC1500 Device Interrupt
No
SD_DAT3/UART_TXD
SDIO=I/O
UART=O
SDIO Data Line 3 from ATWILC1000-MR110PB
when module is configured for SDIO. UART Transmit Output from ATWILC1000 when module is configured for SPI.
Yes
SD_DAT2/SPI_RXD
SDIO=I/O
SPI=I
SDIO Data Line 2 signal from ATWILC1000MR110PB when module is configured for SDIO.
SPI MOSI (Master Out Slave In) pin when module
is configured for SPI.
Yes
SD_DAT1/SPI_SSN
SDIO=I/O
SPI=I
SDIO Data Line 1 from ATWILC1000-MR110PB
when module is configured for SDIO. Active Low
SPI Slave Select from ATWILC1000 when module
is configured for SPI.
Yes
SD_DAT0/SPI_TXD
SDIO=I/O
SPI=O
SDIO Data Line 0 from ATWILC1000-MR110PB
when module is configured for SDIO. SPI MISO
(Master In Slave Out) pin from ATWILC1000 when
module is configured for SPI.
Yes
SD_CMD/SPI_CLK
SDIO=I/O
SPI=I
SDIO CMD Line from ATWILC1000-MR110PB
when module is configured for SDIO. SPI Clock
from ATWILC1000 when module is configured for
SPI.
Yes
SDIO Clock Line from ATWILC1000-MR110PB
when module is configured for SDIO. UART Receive input to ATWILC1000 when module is configured for SPI.
Yes
14
15
16
17
18
SDIO=I
UART=I
19
SD_CLK/UART_RXD
20
VBATT
-
Battery power supply
Yes
21
GPIO_1
I
General Purpose I/O
Yes
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NO
3.2
Name
Type
Description
Programmable
pull-up resistor
No
22
CHIP_EN
I
Module enable. High level enables module, low
level places module in Power Down mode. Connect to a host Output that defaults low at power up.
If the output floats, add a 1MΩ pull-down resistor if
necessary to ensure a low level at power up.
23
VDDIO
-
I/O Power Supply. Must match host I/O voltage.
24
1P3V_TP
-
1.3V VDD Core Test Point
25
GPIO_3
-
General purpose I/O
Yes
26
GPIO_4
I/O
General purpose I/O
Yes
27
GPIO_5
I/O
General purpose I/O
Yes
28
GND_3
-
GND
Module Outline Drawings
Figure 3-2.
Module Drawings – ATWILC1000-MR110PB - Top and Bottom Views (Unit = mm)
NOTE: THIS PAD MUST BE
SOLDERED TO GND.
Drawing not to scale.
Untoleranced dimensions.
8
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Atmel-42503B-WILC1000-MR110PB-SmartConnect_Datasheet_05/2016
Figure 3-3.
Module Drawings – ATWILC1000-MR110UB - Top and Bottom Views (Unit = mm)
NOTE: THIS PAD MUST BE
SOLDERED TO GND.
Drawing not to scale.
Untoleranced dimensions.
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4
Electrical Specifications
4.1
Absolute Ratings
Table 4-1.
4.2
Voltages
Symbol
Description
Min.
Max.
Unit
VBATT
Input supply Voltage
-0.3
5.5
V
VDDIO
SPI, SDIO, and GPIO Voltage
-0.3
3.6
V
Recommended Operating Ratings
Table 4-2.
Pin Recommended Operating Ratings
Test conditions: -40ºC - +85ºC
Symbol
Min.
Typ.
Max.
Unit
VBATT 1
3.0
3.6
4.2
V
VDDIO 2
1.8
3.3
3.6
V
Notes: 1.
2.
10
VBATT should be equal to or greater than VDDIO.
The voltage of VDDIO is dependent on system I/O voltage.
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5
CPU and Memory Subsystems
5.1
Processor
ATWILC1000B has a Cortus APS3 32-bit processor. This processor performs many of the MAC functions,
including but not limited to association, authentication, power management, security key management, and
MSDU aggregation/de-aggregation. In addition, the processor provides flexibility for various modes of
operation, such as STA and AP modes.
5.2
Memory Subsystem
The APS3 core uses a 128KB instruction/boot ROM along with a 160KB instruction RAM and a 64KB data
RAM. In addition, the device uses a 128KB shared RAM, accessible by the processor and MAC, which allows
the APS3 core to perform various data management tasks on the TX and RX data packets.
Non-volatile Memory (eFuse)
ATWILC1000B has 768 bits of non-volatile eFuse memory that can be read by the CPU after device reset. This
non-volatile one-time-programmable (OTP) memory can be used to store customer-specific parameters, such
as MAC address; various calibration information, such as TX power, crystal frequency offset, etc.; and other
software-specific configuration parameters. The eFuse is partitioned into six 128-bit banks. Each bank has the
same bit map, which is shown in Figure 5-1. The purpose of the first 80 bits in each bank is fixed, and the
remaining 48 bits are general-purpose software dependent bits, or reserved for future use. Since each bank
can be programmed independently, this allows for several updates of the device parameters following the initial
programming, e.g. updating MAC address. Refer to Wi-Fi eFuse Programming Guide for the eFuse
programming instructions.
Flags
8
Bank 0
F
48
MAC ADDR
8
G
1
15
Freq.
Offset
7
Used
1
TX
Gain
Correc
tion
1
Used
4
MAC ADDR
Used
3
Reserved
1
Invalid
1
eFuse Bit Map
Version
Figure 5-1.
Used
5.3
16
FO
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
128 Bits
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1
6
WLAN Subsystem
The WLAN subsystem is composed of the Media Access Controller (MAC) and the Physical Layer (PHY). The
following two subsections describe the MAC and PHY in detail.
6.1
MAC
6.1.1
Features
The ATWILC1000B IEEE802.11 MAC supports the following functions:

IEEE 802.11b/g/n

IEEE 802.11e WMM QoS EDCA/PCF multiple access categories traffic scheduling

Advanced IEEE 802.11n features:

6.1.2
–
Transmission and reception of aggregated MPDUs (A-MPDU)
–
Transmission and reception of aggregated MSDUs (A-MSDU)
–
Immediate Block Acknowledgement
–
Reduced Interframe Spacing (RIFS)
Support for IEEE802.11i and WFA security with key management:
–
WEP 64/128
–
WPA-TKIP
–
128-bit WPA2 CCMP (AES)

Support for WAPI security

Advanced power management
–
Standard 802.11 Power Save Mode
–
Wi-Fi Alliance WMM-PS (U-APSD)

RTS-CTS and CTS-self support

Supports either STA or AP mode in the infrastructure basic service set mode

Supports independent basic service set (IBSS)
Description
The ATWILC1000B MAC is designed to operate at low power while providing high data throughput. The IEEE
802.11 MAC functions are implemented with a combination of dedicated datapath engines, hardwired control
logic, and a low-power, high-efficiency microprocessor. The combination of dedicated logic with a
programmable processor provides optimal power efficiency and real-time response while providing the
flexibility to accommodate evolving standards and future feature enhancements.
Dedicated datapath engines are used to implement data path functions with heavy computational. For
example, an FCS engine checks the CRC of the transmitting and receiving packets, and a cipher engine
performs all the required encryption and decryption operations for the WEP, WPA-TKIP, WPA2 CCMP-AES,
and WAPI security requirements.
Control functions which have real-time requirements are implemented using hardwired control logic modules.
These logic modules offer real-time response while maintaining configurability via the processor. Examples of
hardwired control logic modules are the channel access control module (implements EDCA/HCCA, Beacon TX
control, interframe spacing, etc.), protocol timer module (responsible for the Network Access Vector, back-off
timing, timing synchronization function, and slot management), MPDU handling module, aggregation/deaggregation module, block ACK controller (implements the protocol requirements for burst block
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communication), and TX/RX control FSMs (coordinate data movement between PHY-MAC interface, cipher
engine, and the DMA interface to the TX/RX FIFOs).
The MAC functions implemented solely in software on the microprocessor have the following characteristics:

Functions with high memory requirements or complex data structures. Examples are association table
management and power save queuing

Functions with low computational load or without critical real-time requirements. Examples are
authentication and association

Functions which need flexibility and upgradeability. Examples are beacon frame processing and QoS
scheduling
6.2
PHY
6.2.1
Features
The ATWILC1000B IEEE802.11 PHY supports the following functions:
6.2.2

Single antenna 1x1 stream in 20MHz channels

Supports IEEE 802.11b DSSS-CCK modulation: 1, 2, 5.5, 11Mbps

Supports IEEE 802.11g OFDM modulation: 6, 9, 12, 18, 24, 36, 48, 54Mbps

Supports IEEE 802.11n HT modulations MCS0-7, 20MHz, 800, and 400ns guard interval: 6.5, 7.2, 13.0,
14.4, 19.5, 21.7, 26.0, 28.9, 39.0, 43.3, 52.0, 57.8, 58.5, 65.0, 72.2Mbps

IEEE 802.11n mixed mode operation

Per packet TX power control

Advanced channel estimation/equalization, automatic gain control, CCA, carrier/symbol recovery, and
frame detection
Description
The ATWILC1000B WLAN PHY is designed to achieve reliable and power-efficient physical layer
communication specified by IEEE 802.11 b/g/n in single stream mode with 20MHz bandwidth. Advanced
algorithms have been employed to achieve maximum throughput in a real world communication environment
with impairments and interference. The PHY implements all the required functions such as FFT, filtering, FEC
(Viterbi decoder), frequency and timing acquisition and tracking, channel estimation and equalization, carrier
sensing and clear channel assessment, as well as the automatic gain control.
6.3
Radio
Table 6-1.
Radio Performance under Typical Conditions: VBATT=3.6V; VDDIO=3.3V; Temp.: 25ºC
Feature
Description
Module Part Number
ATWILC1000-MR110PB
WLAN Standard
IEEE 802.11b/g/n, Wi-Fi compliant
Host Interface
SPI, SDIO
Dimension
L x W x H: 21.5 x 14.5 x 1.5 (typical) mm
Frequency Range
2.412GHz ~ 2.4835GHz (2.4GHz ISM Band)
Number of Channels
11 for North America, 13 for Europe, and 14 for Japan
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3
Feature
Description
Modulation
802.11b: DQPSK, DBPSK, CCK
802.11g/n: OFDM/64-QAM,16-QAM, QPSK, BPSK
802.11b: 1, 2, 5.5, 11Mbps
Data Rate
802.11g: 6, 9, 12, 18, 24, 36, 48, 54Mbps
6.3.2
Data Rate
(20MHz, short GI, 400ns)
802.11n: 7.2, 14.4, 21.7, 28.9, 43.3, 57.8, 65, 72.2Mbps
Operating temperature
-40°C to 85°C
Storage temperature
-40°C to 85°C
Humidity
Operating Humidity 10% to 95% Non-Condensing
Storage Humidity 5% to 95% Non-Condensing
Receiver Performance
Radio Performance under Typical Conditions: VBATT=3.6V; VDDIO=3.3V; temp.: 25°C
Table 6-2: Receiver Performance
Parameter
Description
Frequency
Sensitivity
802.11b
Sensitivity
802.11g
Sensitivity
802.11n
(BW=20MHz)
14
Min.
Typ.
2,412
Max.
Unit
2,484
MHz
1Mbps DSS
-98
dBm
2Mbps DSS
-94
dBm
5.5Mbps DSS
-92
dBm
11Mbps DSS
-88
dBm
6Mbps OFDM
-90
dBm
9Mbps OFDM
-89
dBm
12Mbps OFDM
-88
dBm
18Mbps OFDM
-85
dBm
24Mbps OFDM
-83
dBm
36Mbps OFDM
-80
dBm
48Mbps OFDM
-76
dBm
54Mbps OFDM
-74
dBm
MCS 0
-89
dBm
MCS 1
-87
dBm
MCS 2
-85
dBm
MCS 3
-82
dBm
MCS 4
-77
dBm
MCS 5
-74
dBm
MCS 6
-72
dBm
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Parameter
Description
Min.
MCS 7
Maximum Receive Signal
Level
Adjacent Channel Rejection
Cellular Blocker Immunity
6.3.3
Typ.
Max.
Unit
-70.5
dBm
1-11Mbps DSS
-10
0
dBm
6-54Mbps OFDM
-10
0
dBm
MCS 0 – 7
-10
0
dBm
1Mbps DSS (30MHz offset)
50
dB
11Mbps DSS (25MHz offset)
43
dB
6Mbps OFDM (25MHz offset)
40
dB
54Mbps OFDM (25MHz offset)
25
dB
MCS 0 – 20MHz BW (25MHz offset)
40
dB
MCS 7 – 20MHz BW (25MHz offset)
20
dB
776-794MHz CDMA
-14
dBm
824-849MHz GSM
-10
dBm
880-915MHz GSM
-10
dBm
1710-1785MHz GSM
-15
dBm
1850-1910MHz GSM
-15
dBm
1850-1910MHz WCDMA
-24
dBm
1920-1980MHz WCDMA
-24
dBm
Transmitter Performance
Radio Performance under Typical Conditions: VBATT=3.6V; VDDIO=3.3V; temp.: 25°C.
Table 6-3: Transmitter Performance
Parameter
Description
Frequency
Output Power,
ON_Transmit_High_Power Mode
Output Power,
ON_Transmit_Low_Power Mode
TX Power Accuracy
Min.
Typ.
2,412
Max.
Unit
2,484
MHz
802.11b 1Mbps
18.5
dBm
802.11b 11Mbps
19.5
dBm
802.11g 6Mbps
18.5
dBm
802.11g 54Mbps
16.5
dBm
802.11n MCS 0
17.0
dBm
802.11n MCS 7
14.5
dBm
802.11b 1Mbps
17.0
dBm
802.11b 11Mbps
17.5
dBm
802.11g 6-18Mbps
16.0
dBm
802.11g >18Mbps
N/A
dBm
802.11n MCS 0-3
14.5
dBm
802.11n >MCS 3
N/A
dBm
±1.5
dB
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5
Parameter
Description
Carrier Suppression
Min.
Typ.
Max.
Unit
30.0
dBc
76-108
-125
dBm/Hz
776-794
-125
dBm/Hz
869-960
-125
dBm/Hz
925-960
-125
dBm/Hz
1570-1580
-125
dBm/Hz
1805-1880
-125
dBm/Hz
1930-1990
-125
dBm/Hz
2110-2170
-125
dBm/Hz
2nd
-33
dBm/MH
z
3rd
-38
dBm/MH
z
Out of Band Transmit Power
Harmonic Output Power
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7
External Interfaces
7.1
SPI Interface
7.1.1
Overview
When the module is configured for SPI mode by connecting the SDIO~_SPI_CFG pin to VDDIO, the
ATWILC1000-MR110PB has a Serial Peripheral Interface (SPI) that operates as a SPI slave. The SPI interface
can be used for control and for serial I/O of 802.11 data. The SPI pins are mapped as shown in Table 7-1. The
SPI is a full-duplex slave-synchronous serial interface that is available immediately following reset when pin 10
(SPI_CFG) is tied to VDDIO.
Table 7-1.
SPI Interface Pin Mapping
Pin #
SPI function
10
CFG: Must be tied to VDDIO
16
SSN: Active Low Slave Select
15
MOSI: Serial Data Receive
18
SCK: Serial Clock
17
MISO: Serial Data Transmit
When the SPI is not selected, i.e., when SSN is high, the SPI interface will not interfere with data transfers
between the serial-master and other serial-slave devices. When the serial slave is not selected, its transmitted
data output is buffered, resulting in a high impedance drive onto the MISO line.
The SPI interface responds to a protocol that allows an external host to read or write any register in the chip as
well as initiate DMA transfers.
The SPI SSN, MOSI, MISO and SCK pins of the ATWILC1000-MR110PB have internal programmable pull-up
resistors (see Section 8.1). These resistors should be programmed to be disabled. Otherwise, if any of the SPI
pins are driven to a low level while the ATWILC1000-MR110PB is in the low power sleep state, current will flow
from the VDDIO supply through the pull-up resistors, increasing the current consumption of the module.
7.1.2
SPI Timing
The SPI timing is provided in Figure 7-1 and Table 7-2.
ATWILC1000-MR110PB [DATASHEET]
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Figure 7-1.
SPI Timing Diagram (SPI Mode CPOL=0, CPHA=0)
Table 7-2.
SPI Slave Timing Parameters (1)
Parameter
Min.
Max.
Unit
48
MHz
Clock Input Frequency (2)
fSCK
Clock Low Pulse Width
tWL
4
Clock High Pulse Width
tWH
5
Clock Rise Time
tLH
0
7
Clock Fall Time
tHL
0
7
TXD Output Delay (3)
tODLY
4
RXD Input Setup Time
tISU
1
RXD Input Hold Time
tIHD
5
SSN Input Setup Time
tSUSSN
3
SSN Input Hold Time
tHDSSN
5.5
Notes:
1.
2.
3.
18
Symbol
9 from SCK fall
12.5 from SCK rise
ns
Timing is applicable to all SPI modes.
Maximum clock frequency specified is limited by the SPI Slave interface internal design, actual maximum
clock frequency can be lower and depends on the specific PCB layout.
Timing based on 15pF output loading.
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7.2
UART Interface
When the module is configured for SPI mode by connecting the SDIO~_SPI_CFG pin to VDDIO, the
ATWILC1000-MR110PB has a Universal Asynchronous Receiver/Transmitter (UART) interface available on
pins J14 and J19. It can be used for control or data transfer if the baud rate is sufficient for a given application.
The UART is compatible with the RS-232 standard, where NMC1000 operates as Data Terminal Equipment
(DTE). It has a two-pin RXD/TXD interface.
The UART features programmable baud rate generation with fractional clock division, which allows
transmission and reception at a wide variety of standard and non-standard baud rates. The UART input clock is
selectable between 10MHz, 5MHz, 2.5MHz, and 1.25MHz. The clock divider value is programmable as 13
integer bits and three fractional bits (with 8.0 being the smallest recommended value for normal operation).
This results in the maximum supported baud rate of 10MHz/8.0 = 1.25MBd.
The UART can be configured for seven or eight bit operation, with or without parity, with four different parity
types (odd, even, mark, or space), and with one or two stop bits. It also has RX and TX FIFOs, which ensure
reliable high speed reception and low software overhead transmission. FIFO size is 4x8 for both RX and TX
direction. The UART also has status registers showing the number of received characters available in the FIFO
and various error conditions, as well the ability to generate interrupts based on these status bits.
An example of UART receiving or transmitting a single packet is shown in Figure 7-2. This example shows 7-bit
data (0x45), odd parity, and two stop bits.
See the Atmel Wi-Fi eFuse Programming Guide for information on configuring the UART.
Figure 7-2.
Example of UART RX or TX Packet
7.3
SDIO Interface
7.3.1
Overview
When the module is configured for SDIO mode by connecting the SDIO~_SPI_CFG pin to Ground, the
ATWILC1000-MR110PB has a SDIO interface. The SDIO interface can be used for control and for serial I/O of
802.11 data. The SDIO pins are mapped as shown in Table 7-3. The SDIO interface is available immediately
following reset when pin 10 (SPI_CFG) is tied to ground.
The ATWILC1000-MR110PB SDIO is a full speed interface. The interface supports the 1-bit/4-bit SD transfer
mode at the clock range of 0-50MHz. The Host can use this interface to read and write from any register within
the chip as well as configure the ATWILC1000-MR110PB for data DMA.
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Table 7-3.
ATWILC1000 SDIO Interface Pin Mapping
Pin #
SDIO Function
10
CFG: Must be tied to ground
14
DAT3: Data 3
15
DAT2: Data 2
16
DAT1: Data 1
17
DAT0: Data 0
18
CMD: Command
19
CLK: Clock
When the SDIO card is inserted into an SDIO aware host, the detection of the card will be via the means
described in SDIO specification. During the normal initialization and interrogation of the card by the host, the
card will identify itself as an SDIO device. The host software will obtain the card information in a tuple (linked
list) format and determine if that card’s I/O function(s) are acceptable to activate. If the card is acceptable, it will
be allowed to power up fully and start the I/O function(s) built into it.
The SD memory card communication is based on an advanced 9-pin interface (Clock, Command, 4 Data and 3
Power lines) designed to operate at maximum operating frequency of 50MHz.
7.3.2
7.3.3
Features

Meets SDIO card specification version 2.0

Host clock rate variable between 0 and 50MHz

1 bit/4-bit SD bus modes supported

Allows card to interrupt host

Responds to Direct read/write (IO52) and Extended read/write (IO53) transactions

Supports Suspend/Resume operation
SDIO Timing
Figure 7-3.
SDIO Timing Diagram
fpp
tWL
SD_CLK
tHL
tWH
tLH
tISU
tIH
Inputs
tODLY(MAX)
Outputs
20
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tODLY(MIN)
Table 7-4.
SDIO Timing Parameters
Parameter
Symbol
Clock Input Frequency
(1)
Min.
Max.
fPP
Unit
50
MHz
Clock Low Pulse Width
tWL
9
ns
Clock High Pulse Width
tWH
4.5
ns
Clock Rise Time
tLH
0
5
ns
Clock Fall Time
tHL
0
5
ns
Input Setup Time
tISU
6
ns
Input Hold Time
tIH
4
ns
Output Delay (2)
tODLY
3
Notes:
1.
2.
11
ns
Maximum clock frequency specified is limited by the SDIO Slave interface internal design, actual maximum
clock frequency can be lower and depends on the specific PCB layout.
Timing based on 15pF output loading.
7.4
I2C Interface
7.4.1
Overview
ATWILC1000-MR110PB provides an I2C bus slave that allows the host processor to read or write any register
in the chip. ATWILC1000-MR110PB supports I2C bus Version 2.1 – 2000.
The I2C interface, used primarily for debug, is a two-wire serial interface consisting of a serial data line (SDA,
Pin 17) and a serial clock (SCL, Pin 18). It responds to the seven bit address value 0x60. The ATWILC1000MR110PB I2C interface can operate in standard mode (with data rates up to 100Kb/s) and fast mode (with data
rates up to 400Kb/s).
The I2C is a synchronous serial interface. The SDA line is a bidirectional signal and changes only while the
SCL line is low, except for STOP, START, and RESTART conditions. The output drivers are open-drain to
perform wire-AND functions on the bus. The maximum number of devices on the bus is limited by only the
maximum capacitance specification of 400pF. Data is transmitted in byte packages.
For specific information, refer to the Philips Specification entitled “The I2C -Bus Specification, Version 2.1”.
7.4.2
I2C Timing
The I2C timing is provided in Figure 7-4 and Table 7-5.
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Figure 7-4.
I2C Timing Diagram
tPR
tSUDAT
tHDDAT
tBUF
tSUSTO
SDA
tHL
tLH
tWL
SCL
tLH
tHDSTA
tHL
tWH
tPR
fSCL
Table 7-5.
7.5
tPR
tSUSTA
I2C Timing Parameters
Parameter
Symbol
Min.
Max.
Unit
SCL Clock Frequency
fSCL
0
400
kHz
SCL Low Pulse Width
tWL
1.3
µs
SCL High Pulse Width
tWH
0.6
µs
SCL, SDA Fall Time
tHL
300
ns
SCL, SDA Rise Time
tLH
300
ns
START Setup Time
tSUSTA
0.6
µs
START Hold Time
tHDSTA
0.6
µs
SDA Setup Time
tSUDAT
100
ns
SDA Hold Time
tHDDAT
0
40
ns
ns
STOP Setup time
tSUSTO
0.6
µs
Bus Free Time Between
STOP and START
tBUF
1.3
µs
Glitch Pulse Reject
tPR
0
50
Remarks
This is dictated by external
components
Slave and Master Default
Master Programming Option
ns
Wi-Fi/Bluetooth Coexistence
ATWILC1000B-MR110PB supports 2-wire and 3-wire Wi-Fi/Bluetooth Coexistence signaling conforming to the
IEEE 802.15.2-2003 standard, Part 15.2. The type of coexistence interface used (2- or 3-wire) is chosen to be
compatible with the specific Bluetooth device used in a given application. Coexistence interface can be
enabled on the following pins: GPIO_1, GPIO_3, GPIO_4, GPIO_5, GPIO_6, I2C_SCL, I2C_SDA – each of
these pins can be configured for any function of the coexistence interface. Table 7-6 shows a usage example
of the 2-wire interface using the GPIO_3 and GPIO_4 pins; 3-wire interface using the GPIO_3, GPIO_4, and
GPIO_5 pins; for more specific instructions on configuring Coexistence refer to Atmel Wi-Fi eFuse
Programming Guide.
22
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Table 7-6.
Coexistence Pin Assignment Example
Pin name
Pin #
Function
Target
2-wire
3-wire
GPIO_3
25
BT_Req
BT is requesting to access the medium to transmit or receive. Goes high on TX or RX slot.
Used
Used
GPIO_4
26
WL_Act
Device response to the BT request. High BT_req is denied and BT slot blocked.
Used
Used
GPIO_5
27
BT_Pri
Priority of the BT packets in the requested slot.
High to indicate high priority and low for normal.
Not Used
Used
GPIO_6
1
Ant_SW
Direct control on Antenna (coex bypass)
Optional
Optional
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8
Power Consumption
8.1
Description of Device States
ATWILC1000B has several Devices States:

ON_Transmit_High_Power – Device is actively transmitting an 802.11 signal. Highest output power and
nominal current consumption.

ON_Transmit_Low_Power – Device is actively transmitting an 802.11 signal. Reduced output power and
reduced current consumption.

ON_Receive_High_Power – Device is actively receiving an 802.11 signal. Lowest sensitivity and nominal
current consumption.

ON_Receive_Low_Power – Device is actively receiving an 802.11 signal. Degraded sensitivity and
reduced current consumption.

ON_Doze – Device is on but is neither transmitting nor receiving

Power_Down – Device core supply off (Leakage)
The following pins are used to switch between the ON and Power_Down states:

CHIP_EN – Device pin (pin #22) used to enable DC/DC Converter

VDDIO – I/O supply voltage from external supply
In the ON states, VDDIO is on and CHIP_EN is high (at VDDIO voltage level). To switch between the ON
states and Power_Down state CHIP_EN has to change between high and low (GND) voltage. When VDDIO is
off and CHIP_EN is low, the chip is powered off with no leakage (see Section 8.3).
8.2
Current Consumption in Various Device States
Table 8-1.
Current Consumption
Current consumption (1)
Device state
Code rate
Output power [dBm]
IVBATT
IVDDIO
802.11b 1Mbps
19.5
294mA
22mA
802.11b 11Mbps
20.5
290mA
22mA
802.11g 6Mbps
19.5
292mA
22mA
802.11g 54Mbps
17.5
250mA
22mA
802.11n MCS 0
18.0
289mA
22mA
802.11n MCS 7
15.5
244mA
22mA
802.11b 1Mbps
18.0
233mA
2mA
802.11b 11Mbps
18.5
231mA
2mA
802.11g 6-18Mbps
17.0
146mA
2mA
802.11g >18Mbps
N/A
N/A
N/A
802.11n MCS 0-3
15.5
132mA
2mA
802.11n >MCS 3
N/A
N/A
N/A
802.11b 1Mbps
N/A
52.5mA
22mA
802.11b 11Mbps
N/A
52.5mA
22mA
ON_Transmit_High_Power
ON_Transmit_Low_Power
ON_Receive_High_Power
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Current consumption (1)
Device state
Code rate
Output power [dBm]
IVBATT
IVDDIO
802.11g 6Mbps
N/A
55.0mA
22mA
802.11g 54Mbps
N/A
57.5mA
22mA
802.11n MCS 0
N/A
54.0mA
22mA
802.11n MCS 7
N/A
58.5mA
22mA
802.11b 1Mbps
N/A
63.5mA
2.4mA
802.11b 11Mbps
N/A
64.2mA
2.4mA
802.11g 6Mbps
N/A
65.4mA
2.4mA
802.11g 54Mbps
N/A
65.4mA
2.4mA
802.11n MCS 0
N/A
65.6mA
2.4mA
802.11n MCS 7
N/A
70.1mA
2.4mA
ON_Doze
N/A
N/A
380µA
<10µA
Power_Down
N/A
N/A
<0.5µA
<0.2µA
ON_Receive_Low_Power
Note:
8.3
1.
Conditions: VBATT @ 3.6v, [email protected] 3.3V, temp. 25°C.
Restrictions for Power States
When no power supplied to the device, i.e., the DC/DC Converter output and VDDIO are both off (at ground
potential). In this case, a voltage cannot be applied to the device pins because each pin contains an ESD
diode from the pin to supply. This diode will turn on when voltage higher than one diode-drop is supplied to the
pin.
If a voltage must be applied to the signal pads while the chip is in a low power state, the VDDIO supply must
be on, so the SLEEP or Power_Down state must be used.
Similarly, to prevent the pin-to-ground diode from turning on, do not apply a voltage that is more than one
diode-drop below ground to any pin.
8.4
Power-up/down Sequence
The power-up/down sequence for ATWILC1000B is shown in Figure 8-1. The timing parameters are provided
in Table 8-2.
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Figure 8-1.
Power-up/down Sequence
VBATT
tA
t A'
VDDIO
tB
t B'
CHIP_EN
tC
t C'
RESETN
XO Clock
Table 8-2.
Parameter
26
Power-up/down Sequence Timing
Min.
Max.
Unit
Description
Notes
tA
0
ms
VBATT rise to VDDIO rise
VBATT and VDDIO can rise simultaneously
or can be tied together. VDDIO must not rise
before VBATT.
tB
0
ms
VDDIO rise to CHIP_EN rise
CHIP_EN must not rise before VDDIO.
CHIP_EN must be driven high or low, not left
floating.
tC
5
ms
CHIP_EN rise to RESETN
rise
This delay is needed because XO clock must
stabilize before RESETN removal. RESETN
must be driven high or low, not left floating.
tA’
0
ms
VDDIO fall to VBATT fall
VBATT and VDDIO can fall simultaneously or
can be tied together. VBATT must not fall before VDDIO.
tB’
0
ms
CHIP_EN fall to VDDIO fall
VDDIO must not fall before CHIP_EN.
CHIP_EN and RESETN can fall simultaneously.
tC’
0
ms
RESETN fall to VDDIO fall
VDDIO must not fall before RESETN. RESETN and CHIP_EN can fall simultaneously.
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8.5
Digital I/O Pin Behavior during Power-up Sequences
Table 8-3 represents digital I/O pin states corresponding to device power modes.
Table 8-3.
Digital I/O Pin Behavior in Different Device States
Device state
VDDIO
CHIP_EN
RESETN
Output driver
Input
driver
Pull-up/down
resistor (96Ω)
Power_Down:
core supply off
High
Low
Low
Disabled (Hi-Z)
Disabled
Disabled
Power-On Reset:
core supply on, hard reset
on
High
High
Low
Disabled (Hi-Z)
Disabled
Enabled
Power-On Default:
core supply on, device out of
reset but not programmed
yet
High
High
High
Disabled (Hi-Z)
Disabled
Enabled
High
Programmed by
firmware for
each pin:
Enabled or Disabled
Opposite
of Output
Driver
state
Programmed by
firmware for
each pin:
Enabled or Disabled
On_Doze/
On_Transmit/
On_Receive:
core supply on, device
programmed by firmware
High
High
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9
Notes on Interfacing to the ATWILC1000-MR110PB
9.1
Programmable Pull-up Resistors
The ATWILC1000-MR110PB provides programmable pull-up resistors on various pins. The purpose of these
resistors is to keep any unused input pins from floating which can cause excess current to flow through the
input buffer from the VDDIO supply. Any unused module pin on the ATWILC1000-MR110PB should leave
these pull-up resistors enabled so the pin will not float. The default state at power up is for the pull-up resistor
to be enabled. However, any pin which is used should have the pull-up resistor disabled. The reason for this is
that if any pins are driven to a low level while the ATWILC1000-MR110PB is in the low power sleep state,
current will flow from the VDDIO supply through the pull-up resistors, increasing the current consumption of the
module. Since the value of the pull-up resistor is approximately 100KΩ, the current through any pull-up resistor
that is being driven low will be VDDIO/100K. For VDDIO = 3.3V, the current through each pull-up resistor that
is driven low would be approximately 3.3V/100K = 33µA. Pins which are used and have had the programmable
pull-up resistor disabled should always be actively driven to either a high or low level and not be allowed to
float.
See the Atmel Wi-Fi eFuse Programming Guide for information on enabling/disabling the programmable pullup resistors.
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10
Recommended Footprint (Unit: mm)
Figure 10-1.
Footprint Drawing
14.73
1.9
NOTE: THIS PAD MUST BE
SOLDERED TO GND.
0.8
1.016 Pitch
2.032
21.72
Drawing not to scale.
Untoleranced dimensions.
1.016 Pitch
4.064
3.70
1.016 Pitch
3.70
3.68
1.9
6.00
4.42
2.67
2.67
3.048
1.016 Pitch
SOLDER PAD FOOTPRINT
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11
RF Performance Placement Guidelines
It is critical to follow the recommendations listed below to achieve the best RF performance:
Module must be placed on main board - printed antenna area must overlap with the carrier board. The portion
of the module containing the antenna should not stick out over the edge of the main board. The antenna is
designed to work properly when it is sitting directly on top of a 1.5mm thick printed circuit board.
If the module is placed at the edge of the main board, a minimum 22mm by 5mm area directly under the
antenna must be clear of all metal on all layers of the board. “In-land” placement is acceptable; however
deepness of keep-out area must grove to: module edge to main board edge plus 5mm. DO NOT PLACE
MODULE IN THE MIDDLE OF THE MAIN BOARD OR FAR AWAY FROM THE MAIN BOARD EDGE.
Keep away from antenna, as far as possible, large metal objects to avoid electromagnetic field blocking.
Do not enclose the antenna within a metal shield.
Keep any components which may radiate noise or signals within the 2.4GHz – 2.5GHz frequency band far
away from the antenna or better yet, shield those components. Any noise radiated from the main board in this
frequency band will degrade the sensitivity of the module.
Contact Atmel for assistance if any other placement is required.
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12
Reflow Profile Information
This chapter provides guidelines for reflow processes in getting the Atmel module soldered to the customer’s
design.
12.1
Storage Condition
12.1.1 Moisture Barrier Bag Before Opened
A moisture barrier bag must be stored in a temperature of less than 30°C with humidity under 85% RH.
The calculated shelf life for the dry-packed product shall be 12 months from the date the bag is sealed.
12.1.2 Moisture Barrier Bag Open
Humidity indicator cards must be blue, <30%.
12.2
Stencil Design
The recommended stencil is laser-cut, stainless-steel type with thickness of 100µm to 130µm and
approximately a 1:1 ratio of stencil opening to pad dimension. To improve paste release, a positive taper with
bottom opening 25µm larger than the top can be utilized. Local manufacturing experience may find other
combinations of stencil thickness and aperture size to get good results.
12.3
Baking Conditions
This module is rated at MSL level 3. After sealed bag is opened, no baking is required within 168 hours so long
as the devices are held at <= 30°C/60% RH or stored at <10% RH.
The module will require baking before mounting if:
12.4
1.
The sealed bag has been open for > 168 hours.
2.
Humidity Indicator Card reads >10%.
3.
SIPs need to be baked for 8 hours at 125°C.
Soldering and Reflow Condition
12.4.1 Reflow Oven
It is strongly recommended that a reflow oven equipped with more heating zones and Nitrogen atmosphere be
used for lead-free assembly. Nitrogen atmosphere has shown to improve the wet-ability and reduce
temperature gradient across the board. It can also enhance the appearance of the solder joints by reducing the
effects of oxidation.
The following items should also be observed in the reflow process:
1.
Some recommended pastes include NC-SMQ® 230 flux and Indalloy® 241 solder paste made up of 95.5
Sn/3.8 Ag/0.7 Cu or SENJU N705-GRN3360-K2-V Type 3, no clean paste.
2.
Allowable reflow soldering iterations: Three times based on the following reflow soldering profile (as
shown in Figure 12-1).
3.
Temperature profile: Reflow soldering shall be done according to the following temperature profile (as
shown in Figure 12-1).
4.
Peak temperature: 250°C.
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Figure 12-1.
Solder Reflow Profile
Slope: 1~2oC/sec max.
(217oC to peak)
(Peak: 250oC)
Ramp down rate:
Max. 2.5oC/sec.
o
217 C
Preheat:150 ~ 200oC
60 ~ 120 sec.
25oC
32
Ramp up rate:
Max. 2.5oC/sec.
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40 ~ 70 sec.
Time (sec)
13
Application Reference Design
The ATWILC1000-MR110PB reference design schematic is shown in Figure 13-1.
Figure 13-1.
ATWILC1000-MR110PB SDIO
ATWILC1000-MR110PB [DATASHEET]
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Figure 13-2.
34
ATWILC1000-MR110PB SPI
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14
Reference Documentation and Support
14.1
Reference Documents
Atmel offers a set of collateral documentation to ease integration and device ramp.
The following list of documents available on Atmel web or integrated into development tools.
To enable fast development contact your local FAE or visit the http://www.atmel.com/.
Title
Content
Datasheet
This Document
Design Files
Package
User Guide, Schematic, PCB layout, Gerber, BOM, and System notes on: RF/Radio Full Test Report, radiation pattern, design guidelines, temperature performance, ESD.
Platform Getting
Started Guide
How to use package: Out of the Box starting guide, HW limitations and notes, SW Quick start
guidelines.
HW Design
Guide
Best practices and recommendations to design a board with the product, including: Antenna Design
for Wi-Fi (layout recommendations, types of antennas, impedance matching, using a power amplifier, etc.), SPI/UART protocol between Wi-Fi SoC and the Host MCU.
SW Design
Guide
Integration guide with clear description of: High level Arch, overview on how to write a networking
application, list all API, parameters, and structures.
Features of the device, SPI/handshake protocol between device and host MCU, with flow/sequence/state diagram, timing.
SW Programmer Guide
Explain in details the flow chart and how to use each API to implement all generic use cases (e.g.
start AP, start STA, provisioning, UDP, TCP, http, TLS, p2p, errors management, connection/transfer recovery mechanism/state diagram) - usage and sample App note
For a complete listing of development-support tools and documentation, visit http://www.atmel.com/, or contact
the nearest Atmel field representative.
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Revision History
Doc Rev.
42503
42503A
36
Date
Comments
5/2016
1. Revised POD drawings in Section 3.2.
2. Revised Footprint drawing in Section 10.
3. Removed Module schematics and BOM’s.
4. Added Reflow profile Chapter 12.
5. Updated SDIO timing content in Table 7-4.
6. Added footnotes to recommended operating ratings in Table 4-2.
7. Updated SPI timing content in Table 7-2.
08/2015
Updated due to changes from ATWILC100A(42380D) to ATWILC1000B:
1. Updated power numbers and description, added high-power and low-power modes.
2. Updated radio performance numbers.
3. Fixed typos in SPI interface timing.
4. Added hardware accelerators in feature list (security and checksum).
5. Increased instruction RAM size from 128KB to 160KB.
6. Improved and corrected description of Coexistence interface.
7. Miscellaneous minor updates and corrections.
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