AT28C17 - Mature

Features
• Fast Read Access Time - 150 ns
• Fast Byte Write - 200 µs or 1 ms
• Self-Timed Byte Write Cycle
•
•
•
•
•
•
•
– Internal Address and Data Latches
– Internal Control Timer
– Automatic Clear Before Write
Direct Microprocessor Control
– DATA POLLING
– READY/BUSY Open Drain Output
Low Power
– 30 mA Active Current
– 100 µa CMOS Standby Current
High Reliability
– Endurance: 104 or 105 Cycles
– Data Retention: 10 Years
5V ± 10% Supply
CMOS & TTL Compatible Inputs and Outputs
JEDEC Approved Byte Wide Pinout
Commercial and Industrial Temperature Ranges
16K (2K x 8)
Parallel
EEPROMs
AT28C17
Description
The AT28C17 is a low-power, high-performance Electrically Erasable and Programmable Read Only Memory with easy to use features. The AT28C17 is a 16K memory
organized as 2,048 words by 8 bits. The device is manufactured with Atmel’s reliable
(continued)
nonvolatile CMOS technology.
Pin Configurations
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
RDY/BUSY
Ready/Busy Output
NC
No Connect
DC
Don’t Connect
PLCC
Top View
A7
NC
RDY/BUSY
DC
VCC
WE
NC
A0 - A10
PDIP, SOIC
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
NC
A8
A9
NC
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A8
A9
NC
NC
OE
A10
CE
I/O7
I/O6
I/O1
I/O2
GND
DC
I/O3
I/O4
I/O5
RDY/BUSY
NC
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
4
3
2
1
32
31
30
Function
14
15
16
17
18
19
20
Pin Name
Note:
PLCC package pins 1 and 17 are
DON’T CONNECT.
Rev. 0541B–10/98
1
The AT28C17 is accessed like a static RAM for the read or
write cycles without the need of external components. During a byte write, the address and data are latched internally, freeing the microprocessor address and data bus for
other operations. Following the initiation of a write cycle,
the device will go to a busy state and automatically clear
and write the latched data using an internal control timer.
The device includes two methods for detecting the end of a
write cycle, level detection of RDY/BUSY and DATA POLLING of I/O 7 . Once the end of a write cycle has been
detected, a new access for a read or a write can begin.
The CMOS technology offers fast access times of 150 ns at
low power dissipation. When the chip is deselected the
standby current is less than 100 µA.
Atmel’s 28C17 has additional features to ensure high quality and manufacturability. The device utilizes error correction internally for extended endurance and for improved
data retention characteristics. An extra 32 bytes of
EEPROM are available for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
2
AT28C17
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
AT28C17
Device Operation
READ: The AT28C17 is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in a high
impedance state whenever CE or OE is high. This dual line
control gives designers increased flexibility in preventing
bus contention.
BYTE WRITE: Writing data into the AT28C17 is similar to
writing into a Static RAM. A low pulse on the WE or CE
input with OE high and CE or WE low (respectively) initiates a byte write. The address location is latched on the
last falling edge of WE (or CE); the new data is latched on
the first rising edge. Internally, the device performs a selfclear before write. Once a byte write has been started, it
will automatically time itself to completion. Once a programming operation has been initiated and for the duration
of tWC, a read operation will effectively be a polling operation.
FAST BYTE WRITE: The AT28C17E offers a byte write
time of 200 µs maximum. This feature allows the entire
device to be rewritten in 0.4 seconds.
READY/BUSY: Pin 1 is an open drain READY/BUSY output that can be used to detect the end of a write cycle.
RDY/BUSY is actively pulled low during the write cycle and
is released at the completion of the write. The open drain
connection allows for OR-tying of several devices to the
same RDY/BUSY line.
DATA POLLING: The AT28C17 provides DATA POLLING
to signal the completion of a write cycle. During a write
cycle, an attempted read of the data being written results in
the complement of that data for I/O7 (the other outputs are
indeterminate). When the write cycle is finished, true data
appears on all outputs.
WRITE PROTECTION: Inadvertent writes to the device
are protected against in the following ways: (a) V C C
sense—if VCC is below 3.8V (typical) the write function is
inhibited; (b) V CC power on delay once VCC has reached
3.8V the device will automatically time out 5 ms (typical)
before allowing a byte write; and (c) write inhibit—holding
any one of OE low, CE high or WE high inhibits byte write
cycles.
CHIP CLEAR: The contents of the entire memory of the
AT28C17 may be set to the high state by the CHIP CLEAR
operation. By setting CE low and OE to 12 volts, the chip is
cleared when a 10 msec low pulse is applied to WE.
D E V I C E I DE NT I F I C A T I O N : A n e x t r a 3 2 b y t e s o f
EEPROM memory are available to the user for device identification. By raising A9 to 12 ± 0.5V and using address
locations 7E0H to 7FFH the additional bytes may be written
to or read from in the same manner as the regular memory
array.
3
DC and AC Operating Range
AT28C17-15
Operating
Temperature (Case)
Com.
0°C - 70°C
Ind.
-40°C - 85°C
5V ± 10%
VCC Power Supply
Operating Modes
Mode
CE
OE
WE
I/O
Read
VIL
VIL
VIH
DOUT
VIL
VIH
VIL
DIN
High Z
Write
(2)
Standby/Write Inhibit
(1)
VIH
X
X
Write Inhibit
X
X
VIH
Write Inhibit
X
VIL
X
Output Disable
X
VIH
X
High Z
VIL
High Z
Chip Erase
Notes:
VIL
VH
(3)
1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC + 1V
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC + 1.0V
100
µA
Com.
2
mA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC + 1.0V
Ind.
3
mA
30
mA
VCC Active Current AC
f = 5 MHz; IOUT = 0 mA
CE = VIL
Com.
ICC
Ind.
45
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
= 4.0 for RDY/BUSY
VOH
Output High Voltage
IOH = -400 µA
4
Min
2.0
AT28C17
V
.4
2.4
V
V
AT28C17
AC Read Characteristics
AT28C17-15
Symbol
Parameter
tACC
Min
Max
Units
Address to Output Delay
150
ns
(1)
CE to Output Delay
150
ns
(2)
OE to Output Delay
10
70
ns
tDF(3)(4)
CE or OE High to Output Float
0
50
ns
tOH
Output Hold from OE, CE or Address, whichever occurred first
0
tCE
tOE
ns
AC Read Waveforms(1)(2)(3)(4)
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 20 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
5
AC Write Characteristics
Symbol
Parameter
Min
tAS, tOES
Address, OE Set-up Time
10
ns
tAH
Address Hold Time
50
ns
tWP
Write Pulse Width (WE or CE)
100
tDS
Data Set-up Time
50
ns
tDH, tOEH
Data, OE Hold Time
10
ns
tCS, tCH
CE to WE and WE to CE Set-up and Hold Time
0
ns
tDB
Time to Device Busy
tWC
Write Cycle Time
AC Write Waveforms
WE Controlled
CE Controlled
6
AT28C17
Typ
Max
1000
Units
ns
50
ns
AT28C17
0.5
1.0
ms
AT28C17E
100
200
µs
AT28C17
Data Polling Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
Min
OE to Output Delay
tWR
Write Recovery Time
Notes:
Max
Units
10
ns
10
ns
(2)
tOE
Typ
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Data Polling Waveforms
Chip Erase Waveforms
tS = tH = 1 µsec (min.)
tW = 10 msec (min.)
VH = 12.0 ± 0.5V
7
8
AT28C17
AT28C17
Ordering Information(1)
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
150
30
0.1
AT28C17(E)-15JC
AT28C17(E)-15PC
AT28C17(E)-15SC
32J
28P6
28S
Commercial
(0°C to 70°C)
45
0.1
AT28C17(E)-15JI
AT28C17(E)-15PI
AT28C17(E)-15SI
32J
28P6
28S
Industrial
(-40°C to 85°C)
Notes:
Operation Range
1. See Valid Part Numbers table below.
2. The 28C17 200 ns and 250 ns speed selections have been removed from valid selections table and are replaced by the
faster 150 ns TAA offering.
3. The 28C17 ceramic and LCC package offerings have been removed. New designs should utilize the 28C256 ceramic offerings.
Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers
Speed
Package and Temperature Combinations
AT28C17
15
JC, JI, PC, PI, SC, SI
AT28C17E
15
JC, JI, PC, PI, SC, SI
AT28C17
-
W
Die Products
Reference Section: Parallel EEPROM Die Products
Package Type
32J
32-Lead, Plastic J-Leaded Chip Carrier (PLCC)
28P6
28-Lead, 0.600" Wide, Plastic Dull Inline Package (PDIP)
28S
28-Lead, 0.300" Wide, Plastic Gull Wing, Small Outline (SOIC)
W
Die
Options
Blank
Standard Device: Endurance = 10K Write Cycles; Write Time = 1 ms
E
High Endurance Option: Endurance = 100K Write Cycles; Write Time = 200 µs
9
Packaging Information
32J, 32-Lead, Plastic J-Leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AA
28P6, 28-Lead, 0.600" Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AB
.045(1.14) X 45°
PIN NO. 1
IDENTIFY
.025(.635) X 30° - 45°
.012(.305)
.008(.203)
.553(14.0)
.547(13.9)
.595(15.1)
.585(14.9)
.032(.813)
.026(.660)
.050(1.27) TYP
.300(7.62) REF
.430(10.9)
.390(9.90)
AT CONTACT
POINTS
.566(14.4)
.530(13.5)
.021(.533)
.013(.330)
.030(.762)
.015(3.81)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
.453(11.5)
.447(11.4)
.495(12.6)
.485(12.3)
28S, 24-Lead, 0.300" Wide, Plastic Gull Wing Small
Outline (SOIC)
Dimensions in Inches and (Millimeters)
.090(2.29)
MAX
1.300(33.02) REF
.220(5.59)
MAX
.005(.127)
MIN
SEATING
PLANE
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
.161(4.09)
.125(3.18)
.110(2.79)
.090(2.29)
.012(.305)
.008(.203)
AT28C17
PIN
1
.530(13.5)
.490(12.4)
.022(.559) X 45° MAX (3X)
10
1.47(37.3)
1.44(36.6)
.065(1.65)
.041(1.04)
.630(16.0)
.590(15.0)
0 REF
15
.690(17.5)
.610(15.5)
AT28C17
11
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© Atmel Corporation 1998.
Atmel Cor poration makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s website. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
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®
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Printed on recycled paper.
0541B–10/98/xM
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