AT25128A/256A - Mature

Features
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Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Data Sheet Describes Mode 0 Operation
Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
20 MHz Clock Rate (5V)
64-byte Page Mode and Byte Write Operation
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
Self-timed Write Cycle (5 ms Max)
High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: >100 Years
8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-ball dBGA2 and 8lead Ultra Thin SAP Packages
Lead-free/Halogen-free
Available in Automotive
Die Sales: Wafer Form, Waffle Pack, and Bumped Die
Description
The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits
each. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available
in space saving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP,
8-ball dBGA2 and 8-lead SAP packages. In addition, the entire family is available in
2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
SPI Serial
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
AT25128A
AT25256A
Not
Recommended
for New Design
The AT25128A/256A is enabled through the Chip Select pin (CS) and accessed via a
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no separate Erase cycle is required before Write.
8-lead SOIC
8-lead PDIP
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
WP
GND
1
2
3
4
8
7
6
5
8-lead Ultra Thin SAP
VCC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
Bottom View
CS
SO
WP
GND
8-lead TSSOP
CS
VCC
SO
HOLD
WP
SCK
GND
SI
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
8-ball dBGA2
VCC
8
1
CS
HOLD
SCK
SI
7
2
6
3
5
4
SO
WP
GND
Bottom View
3368J–SEEPR–06/07
Table 0-1.
Pin Configurations
Pin Name
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
NC
No Connect
Block Write protection is enabled by programming the status register with top ¼, top ½ or entire
array of write protection. Separate Program Enable and Program Disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to
protect against inadvertent write attempts to the status register. The HOLD pin may be used to
suspend any serial communication without resetting the serial sequence.
1. Absolute Maximum Ratings*
Operating Temperature  55C to +125C
Storage Temperature 65C to +150C
Voltage on Any Pin
with Respect to Ground  1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
*NOTICE:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
DC Output Current........................................................ 5.0 mA
2
AT25128A_256A
3368J–SEEPR–06/07
AT25128A_256A
Figure 1-1.
Block Diagram
16384/32768 x 8
Table 1-1.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol
Test Conditions
COUT
CIN
Note:
Max
Units
Conditions
Output Capacitance (SO)
8
pF
VOUT = 0V
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
VIN = 0V
1. This parameter is characterized and is not 100% tested.
3
3368J–SEEPR–06/07
Table 1-2.
DC Characteristics
Applicable over recommended operating range from TAI = 40°C to +85°C, VCC = +1.8V to +5.5V,
TAE = 40C to +125C, VCC = +1.8V to +5.5V(unless otherwise noted)
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Max
Units
1.8
5.5
V
Supply Voltage
2.7
5.5
V
VCC3
Supply Voltage
4.5
5.5
V
ICC1
Supply Current
VCC = 5.0V at 20 MHz, SO = Open,
Read
9.0
10.0
mA
ICC2
Supply Current
VCC = 5.0V at 10 MHz,
SO = Open, Read, Write
5.0
7.0
mA
ICC3
Supply Current
VCC = 5.0V at 1 MHz,
SO = Open, Read, Write
2.2
3.5
mA
ISB1
Standby Current
VCC = 1.8V, CS = VCC
0.2
3.0
µA
ISB2
Standby Current
VCC = 2.7V, CS = VCC
0.5
3.0
µA
ISB3
Standby Current
VCC = 5.0V, CS = VCC
2.0
5.0
µA
IIL
Input Leakage
VIN = 0V to VCC
3.0
3.0
µA
Output Leakage
VIN = 0V to VCC, TAC = 0C to 70C
3.0
3.0
µA
IOL
Test Condition
Min
Typ
(1)
Input Low-voltage
1.0
VCC x 0.3
V
VIH
(1)
Input High-voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low-voltage
0.4
V
VOH1
Output High-voltage
VOL2
Output Low-voltage
VOH2
Output High-voltage
VIL
Note:
4
3.6  VCC  5.5V
1.8V  VCC  3.6V
IOL = 3.0 mA
IOH = 1.6 mA
VCC 0.8
IOL = 0.15 mA
IOH = 100 µA
V
0.2
VCC 0.2
V
V
1. VIL min and VIH max are reference only and are not tested.
AT25128A_256A
3368J–SEEPR–06/07
AT25128A_256A
Table 1-3.
AC Characteristics
Applicable over recommended operating range from TAI = 40C to + 85C, TAE = 40C to +125C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min
Max
Units
fSCK
SCK Clock Frequency
4.55.5
2.75.5
1.85.5
0
0
0
20
10
5
MHz
tRI
Input Rise Time
4.55.5
2.75.5
1.85.5
2
2
2
µs
tFI
Input Fall Time
4.55.5
2.75.5
1.85.5
2
2
2
µs
tWH
SCK High Time
4.55.5
2.75.5
1.85.5
20
40
80
ns
tWL
SCK Low Time
4.55.5
2.75.5
1.85.5
20
40
80
ns
tCS
CS High Time
4.55.5
2.75.5
1.85.5
100
100
200
ns
tCSS
CS Setup Time
4.55.5
2.75.5
1.85.5
100
100
200
ns
tCSH
CS Hold Time
4.55.5
2.75.5
1.85.5
100
100
200
ns
tSU
Data In Setup Time
4.55.5
2.75.5
1.85.5
5
10
20
ns
tH
Data In Hold Time
4.55.5
2.75.5
1.85.5
5
10
20
ns
tHD
Hold Setup Time
4.55.5
2.75.5
1.85.5
5
10
20
ns
tCD
Hold Hold Time
4.55.5
2.75.5
1.85.5
5
10
20
ns
tV
Output Valid
4.55.5
2.75.5
1.85.5
0
0
0
tHO
Output Hold Time
4.55.5
2.75.5
1.85.5
0
0
0
tLZ
Hold to Output Low Z
4.55.5
2.75.5
1.85.5
0
0
0
20
40
80
ns
ns
25
50
100
ns
5
3368J–SEEPR–06/07
Table 1-3.
AC Characteristics (Continued)
Applicable over recommended operating range from TAI = 40C to + 85C, TAE = 40C to +125C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol
Parameter
Voltage
tHZ
Hold to Output High Z
tDIS
tWC
Endurance(1)
Notes:
6
Max
Units
4.55.5
2.75.5
1.85.5
25
50
100
ns
Output Disable Time
4.55.5
2.75.5
1.85.5
25
50
100
ns
Write Cycle Time
4.55.5
2.75.5
1.85.5
5
5
5
ms
5.0V, 25C, Page Mode
Min
1M
Write Cycles
1. This parameter is characterized and is not 100% tested. Contact Atmel for further information.
AT25128A_256A
3368J–SEEPR–06/07
AT25128A_256A
2. Serial Interface Description
MASTER:
The device that generates the serial clock.
SLAVE: Because the serial clock pin (SCK) is always an input, the AT25128A/256A always
operates as a slave.
TRANSMITTER/RECEIVER: The AT25128A/256A has separate pins designated for data
transmission (SO) and reception (SI).
MSB:
The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25128A/256A, and the serial output pin (SO) will remain in a high impedance state until the
falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25128A/256A is selected when the CS pin is low. When the device is not
selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a
high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25128A/256A.
When the device is selected and a serial sequence is underway, HOLD can be used to pause
the serial communication with the master device without resetting the serial sequence. To
pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during
HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held
high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If
the internal write cycle has already been initiated, WP going low will have no effect on any write
operation to the status register. The WP pin function is blocked when the WPEN bit in the status
register is “0”. This will allow the user to install the AT25128A/256A in a system with the WP pin
tied to ground and still be able to write to the status register. All WP pin functions are enabled
when the WPEN bit is set to “1”.
7
3368J–SEEPR–06/07
Figure 2-1.
SPI Serial Interface
AT25128A/256A
8
AT25128A_256A
3368J–SEEPR–06/07
AT25128A_256A
3. Functional Description
The AT25128A/256A is designed to interface directly with the synchronous serial peripheral
interface (SPI) of the 6800 type series of microcontrollers.
The AT25128A/256A utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in see Table 4-3. All instructions, addresses, and data are transferred
with the MSB first and start with a high-to-low CS transition.
Table 3-1.
Instruction Set for the AT25128A/256A
Instruction Name
Instruction Format
Operation
WREN
0000 X110
Set Write Enable Latch
WRDI
0000 X100
Reset Write Enable Latch
RDSR
0000 X101
Read Status Register
WRSR
0000 X001
Write Status Register
READ
0000 X011
Read Data from Memory Array
WRITE
0000 X010
Write Data to Memory Array
WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC is
applied. All programming instructions must therefore be preceded by a Write Enable instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable
instruction disables all programming modes. The WRDI instruction is independent of the status
of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to
the status register. The Ready/Busy and Write Enable status of the device can be determined by
the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection
employed. These bits are set by using the WRSR instruction.
Table 3-2.
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
Table 3-3.
Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = “0” (RDY) indicates the device is ready.
Bit 0 = “1” indicates the write cycle is in progress.
Bit 1 (WEN)
Bit 1 = 0 indicates the device is not write enabled. Bit 1 = “1” indicates
the device is write enabled.
Bit 2 (BP0)
See Table 3-4 on page 10.
Bit 3 (BP1)
See Table 3-4 on page 10.
Bits 4  6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN)
See Table 3-5 on page 10.
Bits 0  7 are “1”s during an internal write cycle.
9
3368J–SEEPR–06/07
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of
four levels of protection. The AT25128A/256A is divided into four array segments. Top quarter
(1/4), top half (1/2), or all of the memory segments can be protected. Any of the data within any
selected segment will therefore be read only. The block write protection levels and corresponding status register control bits are shown in Table 3-4.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and
functions as the regular memory cells (e.g. WREN, tWC, RDSR).
Table 3-4.
Block Write Protect Bits
Status Register Bits
Array Addresses Protected
Level
BP1
BP0
AT25128A
AT25256A
0
0
0
None
None
1(1/4)
0
1
3000 – 3FFF
6000 – 7FFF
2(1/2)
1
0
2000 – 3FFF
4000 – 7FFF
3(All)
1
1
0000 – 3FFF
0000 – 7FFF
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin
through the use of the write protect enable (WPEN) bit. Hardware write protection is enabled
when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when
either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected,
writes to the Status Register, including the Block Protect bits and the WPEN bit, and the blockprotected sections in the memory array are disabled. Writes are only allowed to sections of the
memory which are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as
long as the WP pin is held low.
Table 3-5.
WPEN Operation
WPEN
WP
WEN
Protected
Blocks
Unprotected
Blocks
Status
Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
READ SEQUENCE (READ): Reading the AT25128A/256A via the SO pin requires the following sequence. After the CS line is pulled low to select a device, the Read op-code is transmitted
via the SI line followed by the byte address to be read (see Table 3-6 on page 11). Upon completion, any data on the SI line will be ignored. The data (D7 - D0) at the specified address is
then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high
after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is
10
AT25128A_256A
3368J–SEEPR–06/07
AT25128A_256A
reached, the address counter will roll over to the lowest address allowing the entire memory to
be read in one continuous read cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25128A/256A, two separate instructions must be executed. First, the device must be write enabled via the Write Enable (WREN)
Instruction. Then a Write instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the
Block Write Protection Level. During an internal write cycle, all commands will be ignored except
the RDSR instruction.
A Write Instruction requires the following sequence. After the CS line is pulled low to select the
device, the Write op-code is transmitted via the SI line followed by the byte address and the data
(D7 - D0) to be programmed (see Table 3-6). Programming will start after the CS pin is brought
high. (The Low-to-High transition of the CS pin must occur during the SCK low time immediately
after clocking in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a Read Status Register
(RDSR) Instruction. If Bit 0 = 1, the Write cycle is still in progress. If Bit 0 = 0, the Write cycle has
ended. Only the Read Status Register instruction is enabled during the Write programming
cycle.
The AT25128A/256A is capable of a 64-byte Page Write operation. After each byte of data is
received, the six low order address bits are internally incremented by one; the high order bits of
the address will remain constant. If more than 64 bytes of data are transmitted, the address
counter will roll over and the previously written data will be overwritten. The AT25128A/256A is
automatically returned to the write disable state at the completion of a Write cycle.
NOTE: If the device is not write enabled (WREN), the device will ignore the Write instruction
and will return to the standby state, when CS is brought high. A new CS falling edge is required
to re-initiate the serial communication.
Table 3-6.
Address Key
Address
AT25128A
AT25256A
AN
A13  A0
A14  A0
Don’t Care Bits
A15  A14
A15
11
3368J–SEEPR–06/07
4. Timing Diagrams (for SPI Mode 0 (0, 0))
Figure 4-1.
Synchronous Data Timing
tCS
VIH
CS
VIL
tCSH
tCSS
VIH
tWH
SCK
tWL
VIL
tH
tSU
VIH
SI
VALID IN
VIL
tV
VOH
SO
HI-Z
tHO
tDIS
HI-Z
VOL
Figure 4-2.
12
WREN Timing
AT25128A_256A
3368J–SEEPR–06/07
AT25128A_256A
Figure 4-3.
WRDI Timing
Figure 4-4.
RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
7
6
5
11
12
13
14
15
2
1
0
SCK
INSTRUCTION
SI
SO
HIGH IMPEDANCE
DATA OUT
4
3
MSB
Figure 4-5.
WRSR Timing
13
3368J–SEEPR–06/07
Figure 4-6.
READ Timing
Figure 4-7.
WRITE Timing
Figure 4-8.
HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
SO
tLZ
14
AT25128A_256A
3368J–SEEPR–06/07
AT25128A_256A
5. AT25128A Ordering Information(1)
Ordering Code
(2)
AT25128A-10PU-2.7
AT25128A-10PU-1.8(2)
AT25128AN-10SU-2.7(2)
AT25128AN-10SU-1.8(2)
AT25128AW-10SU-2.7(2)
AT25128AW-10SU-1.8(2)
AT25128A-10TU-2.7(2)
AT25128A-10TU-1.8(2)
AT25128AU2-10UU-1.8(2)
AT25128AY7-10YH-1.8(2)
AT25128A-W1.8-11(3)
Notes:
Package
Operation Range
8P3
8P3
8S1
8S1
8S2
8S2
8A2
8A2
8U2-1
8Y7
Lead-free/Halogen-free/
Industrial Temperature
(40C to 85C)
Die Sale
Industrial Temperature
(40C to 85C)
1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics
tables.
2. “U” designates Green package + RoHS compliant.
3. Available in waffle pack and wafer form; order as SL788 for wafer form. Bumped die available upon request. Please Contact
Serial Interface Marketing.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8S2
8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8U2-1
8-ball, die Ball Grid Array Package (dBGA2)
8A2
8-lead, 4.4 mm Body, Thin Shrink Small Outline Package (TSSOP)
8Y7
8-lead, 6.00 mm x 4.90 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP)
Options
2.7
Low-voltage (2.7V to 5.5V)
1.8
Low-voltage (1.8V to 5.5V)
15
3368J–SEEPR–06/07
AT25256A Ordering Information(1)
Ordering Code
Package
(2)
Operation Range
AT25256A-10PU-2.7
AT25256A-10PU-1.8(2)
AT25256AN-10SU-2.7(2)
AT25256AN-10SU-1.8(2)
AT25256AW-10SU-2.7(2)
AT25256AW-10SU-1.8(2)
AT25256A-10TU-2.7(2)
AT25256A-10TU-1.8(2)
AT25256AU2-10UU-1.8(2)
AT25256AY7-10YH-1.8(2)
8P3
8P3
8S1
8S1
8S2
8S2
8A2
8A2
8U2-1
8Y7
Lead-free/Halogen-free/
Industrial Temperature
(40C to 85C)
AT25256A-W1.8-11(3)
Die Sale
Industrial Temperature
(40C to 85C)
Notes:
1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics
tables.
2. “U” designates Green package + RoHS compliant.
3. Available in waffle pack and wafer form; order as SL788 for wafer form. Bumped die available upon request. Please contact
Serial Interface Marketing.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8S2
8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8U2-1
8-ball, die Ball Grid Array Package (dBGA2)
8A2
8-lead, 4.4 mm Body, Thin Shrink Small Outline Package (TSSOP)
8Y7
8-lead, 6.00 mm x 4.90 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP)
Options
2.7
Low-voltage (2.7V to 5.5V)
1.8
Low-voltage (1.8V to 5.5V)
16
AT25128A_256A
3368J–SEEPR–06/07
AT25128A_256A
6. Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
b2
b3
b
4 PLCS
Side View
L
SYMBOL
NOM
MAX
NOTE
2
A
–
–
0.210
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
3
D1
0.005
–
–
3
E
0.300
0.310
0.325
4
E1
0.240
0.250
0.280
3
e
0.100 BSC
eA
0.300 BSC
L
Notes:
MIN
0.115
0.130
4
0.150
2
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
17
3368J–SEEPR–06/07
8S1 – JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
SYMBOL
MIN
NOM
MAX
A
1.35
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
θ
0˚
–
8˚
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
3/17/05
R
18
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
REV.
8S1
C
AT25128A_256A
3368J–SEEPR–06/07
AT25128A_256A
8S2 – EIAJ SOIC
C
1
E
E1
L
N
Top View
∅
End View
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
A1
D
Side View
NOM
MAX
NOTE
1.70
2.16
A1
0.05
0.25
b
0.35
0.48
5
C
0.15
0.35
5
D
5.13
5.35
E1
5.18
5.40
E
7.70
8.26
L
0.51
0.85
∅
0°
e
Notes: 1.
2.
3.
4.
5.
MIN
A
2, 3
8°
1.27 BSC
4
This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
Mismatch of the upper and lower dies and resin burrs are not included.
It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
Determines the true geometric position.
Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.
10/7/03
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
DRAWING NO.
8S2
REV.
C
19
3368J–SEEPR–06/07
8U2-1 – dBGA2
D
A1 BALL PAD CORNER
1.
b
E
A1
A2
Top View
A
A1 BALL PAD CORNER
Side View
1
2
A
B
e
C
D
(e1)
d
(d1)
COMMON DIMENSIONS
(Unit of Measure = mm)
Bottom View
SYMBOL
MIN
NOM
MAX
8 Solder Balls
A
0.81
0.91
1.00
A1
0.15
0.20
0.25
A2
0.40
0.45
0.50
b
0.25
0.30
0.35
D
2.35 BSC
1. Dimension 'b' is measured at the maximum solder ball diameter.
E
3.73 BSC
This drawing is for general information only.
e
0.75 BSC
e1
0.74 REF
d
0.75 BSC
d1
0.80 REF
NOTE
1
6/24/03
R
20
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch,
Small Die Ball Grid Array Package (dBGA2)
DRAWING NO.
PO8U2-1
REV.
A
AT25128A_256A
3368J–SEEPR–06/07
AT25128A_256A
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
b
D
MIN
NOM
MAX
NOTE
2.90
3.00
3.10
2, 5
4.50
3, 5
E
E1
e
D
A2
6.40 BSC
4.30
A
–
–
1.20
A2
0.80
1.00
1.05
b
0.19
–
0.30
e
Side View
L
4
0.65 BSC
0.45
L1
Notes:
4.40
0.60
0.75
1.00 REF
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
8A2
REV.
B
21
3368J–SEEPR–06/07
8Y7 – UTSAP
PIN 1 INDEX AREA
A
D1
PIN 1 ID
D
E1
L
A1
E
e
b
e1
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
A
–
–
0.60
A1
0.00
–
0.05
D
5.80
6.00
6.20
E
4.70
4.90
5.10
D1
3.30
3.40
3.50
E1
3.90
4.00
4.10
b
0.35
0.40
0.45
e
1.27 TYP
e1
L
NOTE
3.81 REF
0.50
0.60
0.70
10/13/05
R
22
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8Y7, 8-lead (6.00 x 4.90 mm Body) Ultra-Thin SOIC Array
Package (UTSAP) Y7
DRAWING NO.
REV.
8Y7
B
AT25128A_256A
3368J–SEEPR–06/07
AT25128A_256A
Revision History
Doc. Rev.
Date
Comments
3368J
6/2007
Changed 8Y4 to 8Y7 package
3368I
3/2007
Revision history implemented
Removed Pb product offering
23
3368J–SEEPR–06/07
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3368J–SEEPR–06/07
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