AT73C239 - Mature

Features
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Main Supply 3.0V to 3.6V
Independent 2.5V to 3.6V Auxiliary Supply for Backup Section
Internal State Machine for Startup
25 mA/1.8V-2.75V Linear Low Drop Out Regulator with High PSRR and Low Noise
(LDO1)
30 mA/1.5V-1.8V Linear Low Drop Out Regulator with High PSRR and Low Noise
(LDO2)
60 mA/1.23V-1.5V-1.8V Linear Low Drop Out Regulator with High PSRR (LDO3)
2 mA/1.2V-1.5V-1.8V Linear Low Drop Out Regulator with Very Low Quiescent Current
(LDO4)
HPBG Economic High Performance Voltage Reference for LDO Supply to RF Sections
LPBG Low Power Voltage Reference to LDO4 During Backup Battery Operation
Internal Oscillator Generates Internal Master Clock
Internal Reset Generator for Main Supply
Additional External Reset Input
Two Wire Interface (TWI) for Independent Activation and Output Voltage Programming
for Each LDO
Available in 3 x 3 x 0.9 mm 16-pin QFN Package
Applications: GPS Modules, WLAN Devices, Wireless Modules
1. Description
The AT73C239 is a four-channel Power Supply Power Management Unit (PMU) available in a QFN 3 x 3 mm package. It is a fully integrated, low cost, combined Power
Management device for wireless modules, GPS and WLAN devices. It integrates four
Linear Low Drop Out (LDO) Regulators, three of which provide high-accuracy RF performance and one (LDO4) with very low quiescent current that is supplied by an
external backup battery. A Low Power Bandgap (LPBG) requiring no external capacitor for decoupling, is used as reference voltage for LDO4 and starts when VBAT is
present. LDO4 regulates output voltage with extremely low quiescent current, maximizing the lifetime of the backup battery. An Internal State Machine manages the
startup of the other LDOs in the order of LDO3 then LDO1 then LDO2. An economic
High Power Bandgap (HPBG) provides highly accurate, low noise voltage reference
to LDOs 1, 2, 3. HPBG operates in switching mode thereby decreasing its current consumption and becomes inactive when not directly supplied by VIN current. When the
RF LDOs are in idle mode, quiescent current is decreased to a minimum.
Power
Management
and Analog
Companions
(PMAAC)
AT73C239
4-channel
Power
Management for
Wireless
Modules
The AT73C239 features a Two-wire Interface (TWI) to increase the efficiency of the
system by disabling LDOs when not needed.
6201C–PMAAC–31-Jul-07
2. Block Diagram
Figure 2-1.
AT73C239 Functional Block Diagram
VDD1
LDO1
VBG
HPBG
VDD
3.0V-3.6V
VOUT
1.8V or 2.75V
GNDA/AVSS
ILOAD 25 mA
VO1
Internal Oscillator
XRESIN
Reset Generator
TWCK
TWI
TWD
VDD2
LDO2
XRESO
State Machine
GNDD
VDD
3.0V-3.6V
VOUT
1.5V or 1.8V
ILOAD 30 mA
Fuse1
VO2
Fuse2
VZAP
VMON
POR1
VBAT
VO4
POR1
VDD3
LDO4
LDO3
VDD
2.5V-3.6V
VDD
3.0V-3.6V
VOUT
1.2V or 1.5V or 1.8V
VOUT
1.23V or 1.5V or 1.8V
ILOAD 2 mA
ILOAD 60 mA
VO3
LPBG
2
AT73C239
6201C–PMAAC–31-Jul-07
AT73C239
3. Pin Description
Table 3-1.
Pin Description
Pin Name
I/O
Pin Number
Type
Function
XRESIN
Input
1
Digital
Reset in pin
VO3
Output
2
Analog
LDO3 output voltage
VDD3
Input
3
Power
LDO3 input voltage
XRESO
Output
4
Digital
Reset out pin
VO4
Output
5
Analog
LDO4 output voltage
GNDD
GND
6
Power
Digital ground
VBAT
Input
7
Power
LDO4 input voltage
input
8
Digital
Reserved for manufacturing purposes.
VDD2
Input
9
Power
LDO2 input voltage
VO2
Output
10
Analog
LDO2 output voltage
Input
11
Digital
TWI input
Input/Output
12
Digital
TWI input/output
VDD1
Input
13
Power
LDO1 input voltage
VO1
Output
14
Analog
LDO1 output voltage
GNDA/AVSS
GND/Input
15
Analog
Analog ground and ESD ground
VBG
Output
16
Analog
Voltage reference for analog cells
(1)
VZAP
(2)
TWICK
(3)
TWID
Notes:
1. Connected to ground.
2. Connected to VDD1, 2, 3 if TWI is not used.
3. Connected to VDD1, 2, 3 if TWI is not used.
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6201C–PMAAC–31-Jul-07
4. Package
4.1
16-pin QFN Package Outline
Figure 4-1 shows the orientation of the 16-pin QFN package.
Figure 4-1.
16-pin QFN Package - Bottom View
13
15 16
12
1
11
2
10
3
9
4
8
4
14
7
6
5
AT73C239
6201C–PMAAC–31-Jul-07
AT73C239
5. Application Block Diagram
Figure 5-1.
AT73C239 Application Block Diagram
CF
VBG
AT73C239
LDO1
HPBG
VDD
3.0V-3.6V
VDD1
VIN
GPS
Antenna
CIN1
VOUT
1.8V or 2.7V
GNDA/AVSS
VO1
Internal Oscillator
COUT1
XRESIN
XRESO
Baseband
TCXO
ILOAD 25 mA
LDO2
VDD2
VIN
LNA
Reset Generator
TWCK
RF
VDD
3.0V-3.6V
TWI
TWD
VOUT
1.5V or 1.8V
SM
GNDD
VO2
ILOAD 30 mA
3.0V I/O
Supply
Fuse1
VIN
Fuse2
COUT2
VZAP
VMON
3.0V Backup Battery (coin cell)
to other regulators
POR1
VBAT
3.0V I/O
Backup Supply
CIN4
(1µF)
VBAT
POR1
LDO4
LDO3
VDD
2.5V-3.6V
VDD
3.0V-3.6V
VOUT
1.2V or 1.5V or 1.8V
VOUT
1.2V or 1.5V or 1.8V
ILOAD 2 mA
ILOAD 60 mA
COUT4
LPBG
CIN3
(1µF)
VIN 3.3V
Main Supply
COUT3
1.8 V Core
Table 5-1.
VIN
VO3
VO4
1.8V
Backup Core
VDD3
Application Schematic Reference and Pin Description
Schematic Reference
Pin
CIN1
VDD1
CIN2
VDD2
CIN3
VDD3
CIN4
VBAT
COUT1
VO1
COUT2
VO2
COUT3
VO3
COUT4
VO4
CF
VBG
Description
1 µF ± 20% Ceramic Capacitor, X5R
100 nF, ± 20% Ceramic Capacitor
5
6201C–PMAAC–31-Jul-07
6. Functional Description
The AT73C239 integrates the power supply channels described in this section.
6.1
LDO1
LDO1 is a 25 mA/1.8V-2.75V linear low drop out regulator with RF performance. LDO1 operates
with supply from 3.0V to 3.6V and requires at least 300 mV of minimum drop-out. LDO1 supplies
the RF section of wireless devices, showing high PSRR up to 100 kHz, and very low noise on
wide frequency bandwidth. LDO1 requires a 1 µF output capacitor.
Figure 6-1.
LDO1 Functional Diagram
VDD1
VIN
current
reference
VBG
VO1
COUT1
sel1
overcurrent
detection
GNDA
onldo1
AVSS
GNDA
6
AT73C239
6201C–PMAAC–31-Jul-07
AT73C239
6.2
LDO2
LDO2 is a 30 mA/1.5V-1.8V linear low drop out regulator with RF performance. LDO2 operates
with supply from 3.0V to 3.6V and needs at least 300 mV of minimum drop-out. LDO2supplies
the RF section of wireless devices, showing high PSRR up to 100 kHz and very low noise on
wide frequency bandwidth. LDO2 requires a 1 µF output capacitor.
Figure 6-2.
LDO2 Functional Diagram
VDD2
VIN
current
reference
VBG
VO2
COUT2
sel2
overcurrent
detection
GNDA
onldo2
AVSS
GNDA
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6201C–PMAAC–31-Jul-07
6.3
LDO3
LDO3 is a 60 mA/1.2V or 1.5V or 1.8V linear low drop out regulator with RF performance. LDO3
operates with supply from 3.0V to 3.6V and needs at least 300 mV of minimum drop-out. LDO3
supplies the RF section of wireless devices, showing high PSRR up to 100 kHz and low noise on
wide frequency bandwidth. LDO3 requires a 1 µF output capacitor.
Figure 6-3.
LDO3 Functional Diagram
VDD3
VIN
current
reference
VBG
VO3
COUT3
sel3[1:0]
overcurrent
detection
GNDA
onldo3
AVSS
GNDD
8
AT73C239
6201C–PMAAC–31-Jul-07
AT73C239
6.4
LD04
LDO4 is a 2 mA/1.2V or 1.5V or 1.8V low drop out voltage regulator with very low quiescent current. LDO4 operates with supply from 2.5V to 3.6V and needs at least 300 mV of minimum dropout. LDO4 supplies the very low power section of the wireless baseband. It is usually supplied by
the external backup battery and regulates voltage with very low quiescent current, maximizing
the lifetime of the backup battery. LDO4 requires a 1 µF output capacitor or 470 nF if the load is
less than 250 µA. LDO4 is always on once the battery is plugged in. The regulator is activated
when POR1 is released.
Figure 6-4.
LDO4 Functional Diagram
VBATC
VBAT
VBG
VO4
COUT4
sel4[1:0]
GNDD
trcore[1:0]
onldo4
AVSS
GNDDC
6.5
GNDA
High Performance Bandgap (HPBG)
HPBG provides highly accurate, low noise voltage reference to LDOs that supply RF sections.
HPBG operates in switching mode, thus decreasing its current consumption. The economic High
Performance Bandgap is particularly efficient when RF LDOs are in idle mode (output voltage
provided with very low output current e.g. < 1 mA), as the RF section is not active and quiescent
current must be decreased as much as possible.
HPBG requires an external 100 nF ceramic capacitor to achieve very low noise high-accuracy
voltage reference.
6.6
Low Power Bandgap (LPBG)
LPBG is used as reference voltage for LDO4. LPBG starts up as soon as the VBAT pin is active
and does not require an external capacitor for decoupling.
6.7
Reset Generator
The reset generator produces output reset (XRSTOUT) at least 100 ms after input reset state is
activated. Input reset state can be produced the following:
• External manual reset connected to the XRESIN pin
• Internal POR2 monitoring VIN (on VDD3 pin). POR2 is designed with a maximum threshold at
1.81V.
XRESO pin can be generated only if VIN is present.
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6201C–PMAAC–31-Jul-07
6.8
Internal State Machine
The internal state machine manages the start up of the regulators connected to VDD1, VDD2
and VDD3 pins. The startup configuration is in the following order:
1. LDO3
2. LDO1
3. LDO2
6.9
Power on Reset on VBAT (POR1)
POR1 monitors the VBAT pin and generates an internal signal (VPOR1) to enable a fuse read
operation for LDO4 output voltage programming and LDO4 startup. VPOR1 is released when
VBAT is higher than 1.5V ± 300 mV.
6.10
Power on Reset on VDD3 (POR2)
POR2 monitors the VDD3 pin and generates an internal signal (VPOR2) to reset the internal
State Machine and startup the Two-wire Interface (TWI). VPOR2 also enables the fuse read
operation for LDO1, LDO2, LDO3 output voltage programming, reference voltage and internal
oscillator trimming. VPOR2 is released when VIN is higher than 1.5V ± 300 mV.
6.11
Internal Oscillator
The internal oscillator generates the internal master clock to synchronize the state machine that
monitors start up of the LDOs and controls HPBG.
6.12
Voltage Supply Monitor on VDD3 (VMON)
VMON monitors the VDD3 pin and generates an internal signal to enable the state machine to
start up the LDOs and to generate the XRESO signal. Threshold is set to 2.7V at rising and 2.6V
at shut down.
6.13
Two-wire Interface (TWI)
The TWI can be used to activate, disable and set the output voltage of the LDO1, 2, 3, 4 regulators. (VDD3 must be present in order for TWI to be used with LDO4.)
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AT73C239
6201C–PMAAC–31-Jul-07
AT73C239
7. Startup Procedure
At VBAT Rising:
• LPBG automatically starts up.
• POR1 starts up LDO4.
At VDD3 Rising:
• POR2 enables the following:
– Supply Monitor with shutdown threshold setup at 2.7V in order to prevent corruption
in the baseband chip, when the core is still supplied
– Internal State machine that enables the other circuits according to the diagram
shown in Figure 7-1 on page 12.
– Two Wire Interface
At VDD3 Falling:
• The Supply Monitor generates a shut-down control signal when VDD3 reaches 2.6V.
• The State Machine, upon receiving the shut-down control signal, generates the XRESO
signal to set the baseband chip in reset mode.
• The State Machine switches off LDO1, LDO2 and LDO3. HPBG is kept on in order to provide
a fast startup of the LDOs in case of glitches on VDD3.
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6201C–PMAAC–31-Jul-07
7.1
Startup Diagram
Figure 7-1.
Startup Diagram
Start
Wait 0.3 ms
Start VDD3 Comparator
No
VIN > 2.7V ?
Yes
Start LDO3
Start LDO2
Start LDO1
No
VIN < 2.6 V ?
Yes
Wait 220 ms
XRESO = 1
Wait 1 ms
WRESO = XRESIN
XRESO = 0
Wait 1 ms
Stop LDO1, 2, 3
POR2, supplied by VDD3, resets the startup state machine. After 0.3 ms, the VDD3 comparator is
started. If VDD3 is greater than 2.7V, LDO regulators are started in the following order: LDO3,
LDO2, LDO1. During LDO regulator VDD startup, voltage is not checked.
Then XRESO is kept grounded for 220 ms, tied high for 1 ms, before following XRESIN. During
that state, VDD3 voltage is monitored and if it is lower than 2.6V, LDO regulators 1, 2 and 3 are
stopped and XRESO is grounded.
Both XRESIN and VDD3 comparator output are debounced at rising and falling edges for two 10
kHz clock cycles. Debounce time is typically between 100 µs and 200 µs. Timings are defined
± 40%.
12
AT73C239
6201C–PMAAC–31-Jul-07
AT73C239
8. Normal Procedure
The State Machine monitors the XRESIN pin and provides the proper XRESO pin signal when
reset occurs.
Through the Two-wire Interface (TWI), the user can control and change the output voltage delivered by LDO1, LDO2, LDO3 and LDO4.
9. Two-wire Interface (TWI) Protocol
The two-wire interface interconnects components on a unique two-wire bus, made up of one
clock line and one data line with speeds up to 400 Kbits per second, based on a byte oriented
transfer format. The TWI is slave only and has single byte access.
The TWI adds flexibility to the power supply solution, enabling LDO regulators to be controlled
depending on the instantaneous application requirements.
The AT73C239 has the following 7-bit address: 1001000.
Attempting to read data from register addresses not listed in this section results in 0xFF being
read out.
• TWCK is an input pin for the clock
• TWD is an open-drain pin driving or receiving the serial data
The data put on TWD line must be 8 bits long. Data is transferred MSB first. Each byte must be
followed by an acknowledgement.
Each transfer begins with a START condition and terminates with a STOP condition.
• A high-to-low transition on TWD while TWCK is high defines a START condition.
• A low-to-high transition on TWD while TWCK is high defines a STOP condition.
Figure 9-1.
START and STOP Conditions
TWD
TWCK
Start
Figure 9-2.
Stop
Transfer Format
TWD
TWCK
Start
Address
R/W
Ack
Data
Ack
Data
Ack
Stop
After the host initiates a START condition, it sends the 7-bit slave address defined above to
notify the slave device. A read/write bit follows (read = 1, write = 0).
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6201C–PMAAC–31-Jul-07
The device acknowledges each received byte. The first byte sent after the device address and
the R/W bit, is the address of the device register the host wants to read or write.
For a write operation the data follows the internal address. For a read operation a repeated
START condition needs to be generated followed by a read on the device.
Figure 9-3.
S
TWD
Figure 9-4.
TWD
S
Write Operation
ADDR
W
A
IADDR
DATA
A
A
P
Read Operation
ADDR
W
A
IADDR
A
S
ADDR
R
A
DATA
N
P
• S = Start
• P = Stop
• W = Write
• R = Read
• A = Acknowledge
• N = Not Acknowledge
• DADR= Device Address
• IADR = Internal Address
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AT73C239
6201C–PMAAC–31-Jul-07
AT73C239
10. Normal Modes and Quiescent Current
Table 10-1.
Normal Modes and Quiescent Current
Quiescent [µA]
Modes
Conditions
Backup
Battery
VBAT present, VDD3 not present
LDO4 on
typ
max
10
30
VBAT present, VDD3 present
Normal
LDO4 on
LDO1 on
LDO2 on
LDO3 on
800
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6201C–PMAAC–31-Jul-07
11. Electrical Characteristics
11.1
Absolute Maximum Ratings
Table 11-1.
Absolute Maximum Ratings
Operating Temperature (Industrial).............. -40° C to +85° C
*NOTICE:
Storage Temperature .................................. -55°C to +150°C
Power Supply Input on VBAT .......................... -0.3V to + 3.6V
Power Supply Input on VDD1,VDD2,VDD3 ....... -0.3V to + 3.6V
Digital IO Input Voltage ................................. -0.3V to + 3.6V
Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at these or other conditions beyond those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
TWI IO Input Voltage .................................... -0.3V to + 5.5V
All Other Pins................................................ -0.3V to + 3.6V
11.2
Recommended Operating Conditions
Table 11-2.
Recommended Operating Conditions
Parameter
Condition
Min
Max
Unit
-40
85
°C
VDD1, VDD2, VDD3
3.0
3.6
V
VBAT
2.5
3.6
Operating Temperature
Power Supply Input
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AT73C239
6201C–PMAAC–31-Jul-07
AT73C239
12. Timing Diagram
Figure 12-1.
AT73C239 Timings
VBAT 1.5V
POR1
tSTART1
LDO4
VIN
1.5V
2.6V
2.7V
POR2
VMON
tDELAY
XRESIN
tRESGEN
XRESO
tSTARTHPBG
HPBG
0.3 ms
tSTART2
LDO3
tSTART2
LDO2
tSTART2
LDO1
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6201C–PMAAC–31-Jul-07
At VDD3 startup XRESIN is taken into account only if it occurs after tDELAY.
Table 12-1.
Timing Parameters
Parameter
Signal
Constraint
Min
Max
Unit
tSTART1
VO4
LDO4 Startup time
10
100
µsec
tSTART2
VO1,VO2, VO3
LDO1,2,3 Startup time
10
100
µsec
tSTARTHPBG
VBG
HPBG startup time
2
ms
tRESGEN
XRESOUT
Delay to XRESOUT active
500
ms
1
ms
tDELAY
18
100
AT73C239
6201C–PMAAC–31-Jul-07
AT73C239
13. Electrical Specification
13.1
LD01
Table 13-1.
LDO1 Parametric Table
Symbol
Parameter
Comments
Min
Typ
Max
Units
VDD1
Operating supply voltage
Switching Regulated
3.0
3.3
3.6
V
VO1
Output voltage
Factory programmed
2.70
2.75
2.80
V
Programmable
1.75
1.8
1.85
V
I1
Load current
25
mA
IQC
Quiescent current
300
µA
ISC
Shutdown current
1
µA
ISH
Short circuit current
tR
Startup time
∆VDC
Line regulation static
∆VDC
Load regulation static
∆VTRAN
∆VTRAN
PSRR
HiZ output
200
mA
100
µs
From 3.0V to 3.6V
2
From 10% to 100% I1
2
From 0 to 100% I1
7
Line regulation dynamic
From 3.1V to 3.6V
tR = tF = 5 µs, I1 = 5 mA
2
mV
Load regulation dynamic
From 10% to 100%
I1, tR = tF = 5 µs,
2.5
mV
Sine Wave, 100 kHz frequency,
3.3V mean 200 m vPP
48
dB
Sine Wave, 10 kHz frequency,
3.3V mean, 200 m VPP
55
dB
Sine Wave, 1 kHz frequency,
3.3V mean 200 m VPP
60
dB
Power Supply Rejection Ratio
mV
mV
∆VOUT
StartUp Overshoot
40
mV
VN
Output Noise
10 Hz - 100 kHz
45
µVRMS
VNT
Total Output Noise
10 Hz - 100 kHz
55
µVRMS
Table 13-2.
LDO1 External Components
Schematic Reference
Description
COUT1
X5R 1 µF ± 20% ceramic capacitor
Table 13-3.
Control Modes
onldo1
sel1
VO1
0
0
HiZ
1
0
2.75V
1
1
1.8V
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6201C–PMAAC–31-Jul-07
13.2
LDO2
Table 13-4.
LDO2 Parametric Table
Symbol
Parameter
Comments
Min
Typ
Max
Units
VDD2
Operating supply voltage
Switching Regulated
3.0
3.3
3.6
V
V02
Output voltage
Factory programmed
1.75
1.8
1.85
V
Programmable
1.45
1.5
1.55
V
I2
Load current
30
mA
IQC
Quiescent current
300
µA
ISC
Shutdown current
1
µA
ISH
Short circuit current
tR
Startup time
∆VDC
Line regulation static
∆VDC
Load regulation static
∆VTRAN
∆VTRAN
PSRR
HiZ output
200
mA
100
µs
From 3.0V to 3.6V
2
From 10% to 100% I2
2
From 0 to 100% I2
3
Line regulation dynamic
From 3.1V to 3.6V
tR = tF = 5 µs, I2 = 30 mA
2
mV
Load regulation dynamic
From 10% to 100%
I1, tR = tF = 5 µs,
3
mV
Sine Wave, 100 kHz frequency,
3.3V mean 200 m VPP
40
dB
Sine Wave, 10 kHz frequency,
3.3V mean, 200 m VPP
50
dB
Sine Wave, 1 kHz frequency,
3.3V mean 200 m VPP
70
dB
30
mV
Power Supply Rejection Ratio
mV
mV
∆VOUT
Startup Overshoot
VN
Output Noise
10 Hz - 100 kHz
35
µVRMS
VNT
Total Output Noise
10 Hz - 100 kHz
45
µVRMS
Table 13-5.
External Components
Schematic Reference
Description
COUT2
X5R 1 µF ± 20% ceramic capacitor
Table 13-6.
Control Modes
on2ldo
sel2
VO2
0
X
HiZ
1
0
1.8V
1
1
1.5V
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6201C–PMAAC–31-Jul-07
AT73C239
13.3
LDO3
Table 13-7.
LDO3 Parametric Table
Symbol
Parameter
Comments
Min
Typ
Max
Units
VDD3
Operating supply voltage
Switching Regulated
3.0
3.3
3.6
V
Factory programmed
1.75
1.8
1.85
V
Programmable
1.45
1.5
1.55
V
Programmable
1.18
1.23
VO3
Output voltage
1.28
V
I3
Load current
60
mA
IQC
Quiescent current
300
µA
ISC
Shutdown current
1
µA
ISH
Short circuit current
tR
Startup time
∆VDC
Line regulation static
∆VDC
Load regulation static
∆VTRAN
∆VTRAN
PSRR
HiZ output
200
mA
100
µs
From 3.0V to 3.6V
2
From 10% to 100% I3
2
From 0 to 100% I3
3
Line regulation dynamic
From 3.1V to 3.6V
tR = tF = 5 µs, I3 = 60 mA
2
mV
Load regulation dynamic
From 10% to 100%
I1, tR = tF = 5 µs,
3
mV
Sine Wave, 100 kHz frequency,
3.3V mean 200 m VPP
40
dB
Sine Wave, 10 kHz frequency,
3.3V mean, 200 m VPP
50
dB
Sine Wave, 1 kHz frequency,
3.3V mean 200 m VPP
70
dB
30
mV
Power Supply Rejection Ratio
mV
mV
∆VOUT
Startup Overshoot
VN
Output Noise
10 Hz - 100 kHz, without VBG
35
µVRMS
VNT
Total Output Noise
10 Hz - 100 kHz
45
µVRMS
Table 13-8.
External Components
Schematic Reference
Description
COUT3
X5R 1 µF ± 20% ceramic capacitor
Table 13-9.
Control Modes
onldo3
sel3[0]
sel3[1]
VO3
0
X
X
HiZ
1
0
0
1.8V
1
1
0
1.5V
1
0
1
1.23V
21
6201C–PMAAC–31-Jul-07
13.4
LDO4
LDO4 generates 1.2V, 1.5V or 1.8V voltage from VBAT supply. Max DC load is 2 mA. The regulator is activated when POR1 is released.
Table 13-10. LDO4 Parametric Table
Symbol
Parameter
Conditions
Min
VBAT
Operating supply voltage
Backup Battery or Supercap
2.5
Factory programmed
1.7
Programmable
Programmable
Output voltage
VO4
Typ
Max
Unit
3.6
V
1.8
1.9
V
1.4
1.5
1.6
V
1.1
1.2
1.3
V
2
mA
5
µA
I4
Load current
DC load current
IQC
Quiescent current
ISC
Shutdown current
0.5
µA
tS
Startup time
200
µs
∆VDC
Line regulation static
2.5V < VBAT < 3.6V
100
mV
∆VDC
Load regulation static
0 < I4 < 2 mA
100
mV
3
Table 13-11. LDO4 External Components
Schematic Reference
Description
COUT4
X5R 1 µF ± 20% capacitor
Table 13-12. onldo4 sel4[1:0] Control Modes
onldo4
sel4<1>
sel4<0>
VO4
0
X
X
HiZ
1
0
0
1.8V
1
0
1
1.5V
1
1
0
1.2V
Table 13-13. trcore[1:0] Control Modes
trcore<1>
trcore<0>
VO4
0
0
typ
0
1
+ 8 0mV
1
0
- 80 mV
1
1
22
AT73C239
6201C–PMAAC–31-Jul-07
AT73C239
13.5
High Performance Bandgap (HPBG)
Table 13-14. HPBG Parametric Table
Symbol
Parameter
Conditions
VBG
Output voltage
Factory trimmed
Min
Typ
Max
ISC
Shutdown current
encore = en = 0, dcrun = 0 (1)
IQC
Quiescent current
tS
Startup time
CF= 100 nF
1
VN
Output noise
BW 10 Hz to 100 kHz
7
µVRMS
PSRR
Power Supply Rejection Ratio
F = 100 Hz
65
dB
1.231
1
Units
V
6
µA
30
µA
2
ms
Table 13-15. External Components
Schematic Reference
Description
CF
X5R 100 nF ± 20% ceramic capacitor minimum
13.6
Low Power Bandgap (LPBG)
Table 13-16. LPBG Parametric Table
Symbol
Parameter
Conditions
Min
VBAT
Operating supply voltage
Backup Battery or Supercap
2.5
IQC
Quiescent current
tS
Startup time
VLPBG
Bandgap Voltage
13.7
Typ
4
Max
Unit
3.6
V
7.5
µA
100
µs
1.15
1.2
1.25
V
Typ
Max
Unit
3.6
V
Power On Reset on VBAT (POR1)
Table 13-17. POR1 Parametric Table
Symbol
Parameter
Conditions
Min
VBAT
Operating supply voltage
Backup Battery or Supercap
2.5
IQC
Quiescent current
VPON
VPOFF
13.8
3
µA
POR1 on threshold
1.45
V
POR1 off threshold
1.5
V
Power On Reset on VDD3 (POR2)
Table 13-18. POR2 Parametric Table
Symbol
Parameter
Conditions
VDD3
Operating supply voltage
Switching regulated
IQC
Quiescent current
VPON
VPOFF
Min
Typ
0
Max
Unit
3.6
V
3
µA
POR2 on threshold
1.45
V
POR1 off threshold
1.5
V
23
6201C–PMAAC–31-Jul-07
13.9
Voltage Monitor
Table 13-19. Voltage Monitor Parametric Table
Symbol
Parameter
IQC
Quiescent current
Conditions
VPON
POR2 on threshold
on VDD3
VPOFF
POR1 off threshold
Min
Typ
Max
Unit
20
µA
2.7
2.72
V
on VDD3
2.6
2.60
V
Conditions
Min
driven by CPU GPIO
1.8
13.10 XRESIN
Table 13-20. XRESIN Parametric Table
Symbol
Parameter
VI
Input supply voltage range
Typ
Max
Unit
3.3
V
driven by CPU open drain output
Hiz
V
connected to VDD3 when not used
VDD3
V
13.11 XRESO
Table 13-21. XRESO Parametric Table
Symbol
Parameter
VI
Input supply voltage range
Conditions
Min
Typ
1.8
Max
Unit
3.3
V
Max
Unit
5.5
V
13.12 TWICK
Table 13-22. TWICK Parametric Table
Symbol
Parameter
VI
Input supply voltage range
Conditions
Min
Typ
1.8
13.13 TWID
Table 13-23. TWID Parametric Table
Symbol
Parameter
VI
Input supply voltage range
24
Conditions
Min
1.8
Typ
Max
Unit
5.5
V
AT73C239
6201C–PMAAC–31-Jul-07
AT73C239
14. AT73C239 User Interface
Table 14-1.
AT73C239 Register Mapping
Offset
Register
Register Description
Access
Reset Value
0×00
LDO_CTRL
LDO Control
Read/Write
0x0F
0×08
LDO_TRIM1
LDO 1,2,3 Trim
Read/Write
0x00
0×0A
LDO_TRIM4
LDO4 Trim
Read/Write
0x00
25
6201C–PMAAC–31-Jul-07
14.1
LDO Control Register
Register Name:
LDO_CTRL
Reset State:
0X0F
Access:
Read/Write
7
6
5
4
3
2
1
0
–
–
–
–
Onldo4
Onldo3
Onldo2
Onldo1
2
1
0
• Onldo1:
LDO1 enable (active high) reset value = 1.
• Onldo2:
LDO2 enable (active high) reset value = 1.
• Onldo3:
LDO3 enable (active high) reset value = 1.
• Onldo4:
LDO4 enable (active high) reset value = 1.
14.2
LDO 1, 2, 3 Trim Register
Register Name:
LDO_TRIM1
Reset State:
0X08
Access:
Read/Write
7
6
5
4
3
–
–
–
Sel1
Sel2
Sel3
–
• Sel3
LDO3 output voltage select, reset = 00
• Sel2
LDO2 output voltage select, reset = 0
• Sel1
LDO1 output voltage select, reset = 0
26
Sel1
VO1
Sel2
VO2
Sel3
VO3
0
2.75V
0
1.8V
00
1.8V
1
1.8V
1
1.5V
01
1.5V
10
1.23V
11
1.8V
AT73C239
6201C–PMAAC–31-Jul-07
AT73C239
14.3
LDO 4 Trim Register
Register Name:
LDO_TRIM4
Reset State:
0X0A
Access:
Read/Write
7
6
5
4
–
–
–
–
3
2
Sel4
1
0
–
–
• Sel4
LDO4 output voltage select, reset = 00
Sel4
VO4
00
1.8V
01
1.5V
10
1.2V
11
1.2V
27
6201C–PMAAC–31-Jul-07
15. Package Information
Figure 15-1. Mechanical Package Drawing for 16-lead Quad Flat No Lead Package
Note:
28
All dimensions are in mm.
AT73C239
6201C–PMAAC–31-Jul-07
AT73C239
16. Ordering Information
Table 16-1.
Ordering Information
Ordering Code
Package
Package Type
Temperature Operating Range
AT73C239
QFN3x3 mm
Green
0°C to +70°C
29
6201C–PMAAC–31-Jul-07
Revision History
Doc. Rev
Date
Comments
6201A
01-Sep-05
11-Oct-05
First issue
Unqualified on Intranet
Change Request Ref.
Changed HPBG minimum requirement information in
6201B
03-Mar-06
Section 6.5 ”High Performance Bandgap
(HPBG)” on page 9.
Updated Figure 7-1 on page 12 with new values.
Updated Figure 12-1 on page 17 with new
2472
information for LDO2 and LDO3 signals.
Updated Table 13-14, “HPBG Parametric
Table,” on page 23 with max value for startup time
and changed condition.
6201C
30
09-Jul-07
Added Section 4. ”Package” on page 4.
4591
AT73C239
6201C–PMAAC–31-Jul-07
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6201C–PMAAC–31-Jul-07
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