SAM G55G / SAM G55J Atmel | SMART ARM-based Flash MCU SUMMARY DATASHEET Description The Atmel® | SMART SAM G55 is a series of Flash microcontrollers based on the high-performance 32-bit ARM® Cortex®-M4 RISC processor with FPU (Floating Point Unit). It operates at a maximum speed of 120 MHz and features 512 Kbytes of Flash and up to 176 Kbytes of SRAM. The peripheral set includes eight flexible communication units comprising USARTs, SPIs and I2C-bus interfaces (TWIs), two three-channel general-purpose 16-bit timers, two I2S controllers, one-channel pulse density modulation, one 8-channel 12-bit ADC, one real-time timer (RTT) and one real-time clock (RTC), both located in the ultra low-power backup area. The Atmel | SMART SAM G55 devices have three software-selectable low-power modes: Sleep, Wait and Backup. In Sleep mode, the processor is stopped while all other functions can be kept running. In Wait mode, all clocks and functions are stopped but some peripherals can be configured to wake up the system based on events, including partial asynchronous wake-up (SleepWalking™). In Backup mode, RTT, RTC and wakeup logic are running. For power consumption optimization, the flexible clock system offers the capability of having different clock frequencies for some peripherals. Moreover, the processor and bus clock frequency can be modified without affecting the peripheral processing. The real-time event management allows peripherals to receive, react to and send events in Active and Sleep modes without processor intervention. The SAM G55 devices are general-purpose low-power microcontrollers that offer high performance, processing power and small package options combined with a rich and flexible peripheral set. With this unique combination of features, the SAM G55 series is suitable for a wide range of applications including consumer, industrial control and PC peripherals. The device operates from 1.62V to 3.6V and is available in three packages: 49-pin WLCSP, 64-pin QFN and 64-pin LQFP. Atmel-11289DS-ATARM-SAM-G55G-SAM-G55J-Datasheet_01-Dec-15 Features Core ̶ ARM Cortex-M4 with up to 16 Kbytes SRAM on I/D bus providing 0 wait state execution at up to 120 MHz (1) ̶ Memory Protection Unit (MPU) ̶ DSP Instructions ̶ Floating Point Unit (FPU) ̶ Thumb®-2 instruction set 1. 120 MHz with VDDCorext120 or with VDDCore trimmed by regulator. Note: Memories ̶ Up to 512 Kbytes embedded Flash ̶ Up to 176 Kbytes embedded SRAM ̶ 8 Kbytes ROM with embedded boot loader, single-cycle access at full speed System ̶ Embedded voltage regulator for single-supply operation ̶ Power-on reset (POR) and Watchdog for safe operation ̶ Quartz or ceramic resonator oscillators: 3 to 20 MHz with clock failure detection and 32.768 kHz for RTT or system clock ̶ High-precision 8/16/24 MHz factory-trimmed internal RC oscillator. In-application trimming access for frequency adjustment ̶ Slow clock internal RC oscillator as permanent low-power mode device clock ̶ PLL range from 48 MHz to 120 MHz for device clock ̶ PLL range from 24 MHz to 48 MHz for USB device and USB OHCI ̶ Up to 30 peripheral DMA (PDC) channels ̶ 256-bit General-Purpose Backup Registers (GPBR) ̶ 16 external interrupt lines Peripherals ̶ 8 flexible communication units supporting: USART SPI Two-wire Interface (TWI) featuring TWI masters and high-speed TWI slaves ̶ ̶ ̶ ̶ ̶ ̶ ̶ 2 USB 2.0 Device and USB Host OHCI with On-chip Transceiver 2 Inter-IC Sound Controllers (I2S) 1 Pulse Density Modulation Interface (PDMIC) (supports up to two microphones) 2 three-channel 16-bit Timer/Counters (TC) with capture, waveform, compare and PWM modes 1 48-bit Real-Time Timer (RTT) with 16-bit prescaler and 32-bit counter 1 RTC with calendar and alarm features 1 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU) I/O ̶ Up to 48 I/O lines with external interrupt capability (edge or level), debouncing, glitch filtering and on-die series resistor termination. Individually programmable open-drain, pull-up and pull-down resistor and synchronous output ̶ Two PIO Controllers provide control of up to 48 I/O lines Analog ̶ One 8-channel ADC, resolution up to 12 bits, sampling rate up to 500 kSps SAMG55 [DATASHEET] Atmel-11289DS-ATARM-SAM-G55G-SAM-G55J-Datasheet_01-Dec-15 Package ̶ 49-lead WLCSP ̶ 64-lead LQFP ̶ 64-lead QFN Temperature operating range ̶ Industrial (-40° C to +85° C) SAMG55 [DATASHEET] Atmel-11289DS-ATARM-SAM-G55G-SAM-G55J-Datasheet_01-Dec-15 3 1. Configuration Summary Table 1-1 summarizes the SAM G55 device configurations. Table 1-2. Configuration Summary Feature SAM G55G19 SAM G55J19 Flash 512 Kbytes 512 Kbytes Cache (CMCC) up to 8 Kbytes up to 8 Kbytes 160 Kbytes 160 Kbytes SRAM +Up to 16KBytes (Cache +I/D RAM) + Up to 16KBytes (Cache +I/D RAM) Package WLCSP49 QFN64, LQFP64 Number of PIOs 38 48 Event System Yes Yes External Interrupt 16 16 8 channels 8 channels Performance: Performance: 500 kSps 500 kSps 6 channels 6 channels 16-bit Timer (3 external channels) (3 external channels) I2SC/PDM 2 / 1-channel 2-way 2 / 1channel 2-way PDC Channels 28 30 7 8 USB Full Speed/OHCI Full Speed / OHCI CRCCU 1 1 RTT 1 (backup area) 1 (backup area) RTC 1 (backup area) 1 (backup area) 12-bit ADC USART SPI TWI TWIHS 4 SAMG55 [DATASHEET] Atmel-11289DS-ATARM-SAM-G55G-SAM-G55J-Datasheet_01-Dec-15 Block Diagram Power Management Controller IO JTAG and Serial Wire RC OSC 8/16/24 MHz In-Circuit Emulator Cortex-M4 Processor fMAX 120 MHz ERASE Backup area Supply Controller WKUP[15:0] DSP XIN32 XOUT32 XIN XOUT MPU 32K OSC 256-bit General-purpose Backup Registers Real-time Clock Real-time Timer Watchdog Timer Flash Unique Identifier D SRAM CMCC 2/4/8 KB Cache Up to 16 Kbytes S Flash S 512 Kbytes 4-layer AHB Bus Matrix fMAX 120 MHz S 160 Kbytes S Supply Monitor User Signature M M Reset Controller NRST FPU I 32K RC Power-on Reset 24-bit SysTick Counter NVIC Tamper Detection M M SRAM ROM M S 8 Kbytes CRCCU PIOA/PIOB AHB/APB Bridge PDC DMA System Controller MUX USB OHCI 2668 bytes FIFO PDMIC_DAT PDMIC_CLK DP DM USB 2.0 Full-speed PDC PDMIC0 PDMIC1 I2SCK0...1 I2SWS0...1 I2SDI0...1 I2SDO0...1 I2SMCK0...1 Transceiver PLLA VUSB (64pins ONLY) DO Voltage Regulator PLLUSB VDDCORE VD VD D TST PCK[2:0] VDDIO UT SAM G55 Block Diagram PDC PDC 2 x I2SC FLEXCOM SCK_SPCK0...7 TXD_MOSI_TWD0...7 RXD_MISO_TWCK0...7 RTS_NPCS1_0...7 CTS_NPCS0NSS_0...7 PDC 8x USART, SPI, TWI Timer Counter A TC[0..2] TCLK[2:0] TIOA[2:0] TIOB[2:0] Timer Counter B AD[7:0] ADTRG PDC 12-bit ADC Event System Figure 2-1. TD I TD O TM S TC /SW K/ D SW IO JT CL AG K SE L 2. TC[3..5] SAMG55 [DATASHEET] Atmel-11289DS-ATARM-SAM-G55G-SAM-G55J-Datasheet_01-Dec-15 5 3. Signal Description Table 3-1 gives details on the signal names classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Voltage Reference Comments Power Supplies VDDIO Peripheral I/O Lines, Voltage Regulator, ADC Power Supply Power – – 1.62V to 3.6V VDDOUT Voltage Regulator Output Power – – 1.08V to 1.32V VDDCORE Core Chip Power Supply Power – – Connected externally to VDDOUT or VVDDCOREXT100 or VVDDCOREXT120 VUSB USB Power Supply Power – – Only available on 64-pin package GND Ground Ground – – Input – VDDIO Reset state: Output – – - PIO input Input – VDDIO - Internal pull-up disabled Output – – - Schmitt Trigger enabled – Clocks, Oscillators and PLLs XIN Main Oscillator Input XOUT Main Oscillator Output XIN32 Slow Clock Oscillator Input XOUT32 Slow Clock Oscillator Output Reset state: - PIO input PCK0–PCK2 Programmable Clock Output Output – – - Internal pull-up enabled - Schmitt Trigger enabled ICE and JTAG TCK Test Clock Input – VDDIO No pull-up resistor TDI Test Data In Input – VDDIO No pull-up resistor TDO Test Data Out Output – VDDIO – TRACESWO Trace Asynchronous Data Out Output – VDDIO – SWDIO Serial Wire Input/Output I/O – VDDIO – SWCLK Serial Wire Clock Input – VDDIO – TMS Test Mode Select Input – VDDIO No pull-up resistor JTAGSEL JTAG Selection Input High VDDIO Pull-down resistor High VDDIO Pull-down (15 kΩ) resistor Flash Memory ERASE 6 Flash and NVM Configuration Bits Erase Command SAMG55 [DATASHEET] Atmel-11289DS-ATARM-SAM-G55G-SAM-G55J-Datasheet_01-Dec-15 Input Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Voltage Reference I/O Low VDDIO Pull-up resistor Input – VDDIO Pull-down resistor Comments Reset/Test NRST Microcontroller Reset TST Test Mode Select PIO Controller - PIOA - PIOB PA0–PA31 Parallel I/O Controller A I/O – VDDIO Pulled-up input at reset. No pull-down for PA3/PA4/PA14. PB0–PB15(1) Parallel I/O Controller B I/O – VDDIO Pulled-up input at reset I/O – VDDIO Wake-up pins are used also as External Interrupt Wake-up Pins WKUP0–15 Wake-up Pin / External Interrupt Serial Peripheral Interface - SPIx MISOx Master In Slave Out I/O – – – MOSIx Master Out Slave In I/O – – – SPCKx SPI Serial Clock I/O – – NPCS0x SPI Peripheral Chip Select 0 I/O Low – – NPCS1x SPI Peripheral Chip Select Output Low – – High Speed Pad Two-Wire Interface - TWIx TWDx TWIx Two-wire Serial Data I/O – – High Speed Pad for TWD0 TWCKx TWIx Two-wire Serial Clock I/O – – High Speed Pad for TWDCK0 Universal Synchronous Asynchronous Receiver Transmitter USARTx SCKx USART Serial Clock I/O – – – TXDx USART Transmit Data I/O – – – RXDx USART Receive Data Input – – – RTSx USART Request To Send Output – – – CTSx USART Clear To Send Input – – – Input – – – Timer/Counter - TCx TCLKx TC Channel x External Clock Input TIOAx TC Channel x I/O Line A I/O – – – TIOBx TC Channel x I/O Line B I/O – – – 12-bit Analog-to-Digital Converter - ADCC AD0–AD7 Analog Inputs Analog – – – ADTRG ADC Trigger Input – – – ADVREF ADC Voltage Reference Input – – Only available on 64-pin package SAMG55 [DATASHEET] Atmel-11289DS-ATARM-SAM-G55G-SAM-G55J-Datasheet_01-Dec-15 7 Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Voltage Reference Comments Inter-IC Sound Controller - I2SCx I2SMCKx Master Clock Output – – – I2SCKx Serial Clock I/O – – – 2 I2SWSx I S Word Select I/O – – – I2SDIx Serial Data Input Input – – – I2SDOx Serial Data Output Output – – – PDMIC_CLK Pulse Density Modulation Clock Output – – – PDMIC_DAT Pulse Density Modulation Data Input – – – USB OHCI/FS/IC - USB DM WLCSP49: VDDIO USB Data Analog, Digital DP Note: 8 USB Data + 1. Pull-up disabled on PB8/PB9. SAMG55 [DATASHEET] Atmel-11289DS-ATARM-SAM-G55G-SAM-G55J-Datasheet_01-Dec-15 – 64-pin Package: VDDUSB DM and DP in PIO configuration 4. Package and Pinout Table 4-1. SAM G55 Packages Device Package SAM G55G19 WLCSP49 QFN64 SAM G55J19 4.1 LQFP64 49-ball WLCSP Pinout Table 4-2. SAM G55G19 49-ball WLCSP Pinout A1 PA9 B6 NRST D4 PB10 F2 PA19/AD2 A2 GND B7 PB12 D5 PA1 F3 PA17/AD0 A3 PA24 C1 VDDCORE D6 PA5 F4 PA21 A4 PB8/XOUT C2 PA11 D7 VDDCORE F5 PA23 A5 PB9/XIN C3 PA12 E1 PB2/AD6 F6 PA16 A6 PB4 C4 PB6 E2 PB0/AD4 F7 PA8/XOUT32 A7 VDDIO C5 PA4 E3 PA18/AD1 G1 VDDIO B1 PB11 C6 PA3 E4 PA14 G2 VDDOUT B2 PB5 C7 PA0 E5 PA10 G3 GND B3 PB7 D1 PA13 E6 TST G4 VDDIO B4 PA2 D2 PB3/AD7 E7 PA7/XIN32 G5 PA22 B5 JTAGSEL D3 PB1/AD5 F1 PA20/AD3 G6 PA15 G7 PA6 SAMG55 [DATASHEET] Atmel-11289DS-ATARM-SAM-G55G-SAM-G55J-Datasheet_01-Dec-15 9 4.2 64-lead QFN/LQFP Pinout 4.2.1 64-lead QFN / LQFP Pinout Table 4-3. 1 VDDIO 17 PA6 33 PA17 49 PA9 2 NRST 18 PA16 34 PA18 50 PB5 3 PB12 19 PA30 35 PA19 51 PA27 4 PA4 20 PA29 36 PA20 52 PA26 5 PA3 21 PA28 37 PB0 53 GND 6 PA0 22 PA15 38 PB1 54 PB6 7 PA1 23 PA23 39 PB2 55 PB7 8 PA5 24 PA22 40 PB3 56 PA25 9 VDDCORE 25 PA21 41 PA14 57 PB13 10 TEST 26 VDDUSB 42 PA13 58 PA24 11 PA7 27 VDDIO 43 PA12 59 PB8/XOUT 12 PA8 28 ADVREF 44 PA11 60 PB9/XIN 13 GND 29 GND 45 VDDCORE 61 PA2 14 PB15 30 VDDOUT 46 PB10 62 PB4 15 PB14 31 VDDIO 47 PB11 63 JTAGSEL 16 PA31 32 VDDIO 48 PA10 64 VDDIO Note: 10 SAM G55J19 64-pin LQFP and QFN pinout The bottom pad of the QFN package must be tied to ground. SAMG55 [DATASHEET] Atmel-11289DS-ATARM-SAM-G55G-SAM-G55J-Datasheet_01-Dec-15 5. Mechanical Characteristics 5.1 49-lead WLCSP Package 49-lead WLCSP Package Mechanical Drawing Backside coating : 0.025 min 0.040 max Figure 5-1. SAMG55 [DATASHEET] Atmel-11289DS-ATARM-SAM-G55G-SAM-G55J-Datasheet_01-Dec-15 11 5.2 64-lead QFN Package Figure 5-2. 12 64-lead QFN Package Mechanical Drawing SAMG55 [DATASHEET] Atmel-11289DS-ATARM-SAM-G55G-SAM-G55J-Datasheet_01-Dec-15 5.3 64-lead LQFP Package Figure 5-3. 64-lead LQFP Package Mechanical Drawing CONTROL DIMENSIONS ARE IN MILLIMETERS Millimeter Inch Symbol Min. Nom. Max. Symbol Min. Nom. Max. Millimeter Inch Min. Nom. Max. Min. Nom. Max. Tolerances of form and position Drawing No.: Rev.: Date: Jedec Code: R-LQ064_N A 11/22/2013 MS-026 SAMG55 [DATASHEET] Atmel-11289DS-ATARM-SAM-G55G-SAM-G55J-Datasheet_01-Dec-15 13 6. SAMG55 Ordering Information Table 6-1. SAMG55 Ordering Information Ordering Code Package Carrier Type ATSAMG55G19A-UUT WLCSP49 Reel ATSAMG55J19A-MU ATSAMG55J19A-MUT ATSAMG55J19A-AU ATSAMG55J19A-AUT 14 QFN64 LQFP64 SAMG55 [DATASHEET] Atmel-11289DS-ATARM-SAM-G55G-SAM-G55J-Datasheet_01-Dec-15 Temperature Operating Range Industrial -40°C to 85°C Tray Industrial Reel -40°C to 85°C Tray Industrial Reel -40°C to 85°C 7. Revision History In the tables that follow, the most recent version of the document appears first. Table 7-1. Issue Date SAM G55 Summary Datasheet Rev. 11289DS Revision History Changes Updated “Description” Modified “Features” (Note in “Core” section & “Up to 48 I/O lines” instead of “Up to 32 I/O lines” in “I/O “section) 01-Dec-15 Updated Figure 2-1 “SAM G55 Block Diagram” Table 3-1 “Signal Description List”: - modified comments on VDDCORE, DM and DP - PDMCLK0 changed to PDMIC_CLK; PDMDAT0 changed to PDMIC_DAT Table 7-2. Issue Date SAM G55 Summary Datasheet Rev. 11289CS Revision History Changes Removed “Preliminary Status” marking. Modified Section “Description” 16-Jun-15 Updated Figure 2-1 “SAM G55 Block Diagram”(GPBR) Added note to PB0/PB15 in Table 3-1 “Signal Description List” Added note to Section 4.2.1 “64-lead QFN / LQFP Pinout” Replaced ATSAMG55J19-A-AUT with ATSAMG55J19A-AUT in Table 6-1 “SAMG55 Ordering Information” Table 7-3. SAM G55 Summary Datasheet Rev. 11289BS Revision History Issue Date Changes 14-Jan-15 Added “Preliminary Status” marking. Table 7-4. SAM G55 Summary Datasheet Rev. 11289AS Revision History Issue Date Changes 19-Dec-14 First issue. SAMG55 [DATASHEET] Atmel-11289DS-ATARM-SAM-G55G-SAM-G55J-Datasheet_01-Dec-15 15 ARM Connected Logo XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2015 Atmel Corporation. / Rev.: Atmel-11289DS-ATARM-SAM-G55G-SAM-G55J-Datasheet_01-Dec-15. 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