ATMX150RHA - Advance Information

ATMX150RHA
Rad-Hard 150nm SOI CMOS Cell-based ASIC
for Space Use
Advanced Information
Description
ATMX150RHA is a mixed-signal ASIC offer providing high-performance and
high-density solutions for space applications. With a set of pre-qualified analog
IP’s, such as DACs, ADCs, PLL, regulators…, ATMX150RHA will ease the
design of mixed-signal ASIC’s.
The ATMX150RHA covers the digital ATC18RHA ASIC offer domain and
extends it up to 22 ASIC Mgates. The availability of a 5V to 1.8V regulator and
the 5V tolerant IO permits to easily retarget 5V core supply ASIC generation. In
addition, the availability of the Physical Design Kit (PDK) gives the possibility to
customers to develop their own analog blocks and use Atmel SMPW foundry
services.
ATMX150RHA is manufactured on a 150nm, five-metal-layers SOI CMOS
process intended for use with a supply voltage of 1.8V for core and 2.5/3.3/5V
for periphery. This ASIC platform is supported by a combination of state-of-art
third-party and proprietary design tools from: Synopsys, Mentor and Cadence.
The tools from these suppliers collectively form the reference tool flows for
both the front and back end.
ATMX150RHA ASIC’s will be available in several quality assurance grades,
such as Mil-Prf 38535 QML-Q and QML-V and ESCC 9000.
Targeted Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Comprehensive Library of Standard Logic and I/O Cells
Up to 22 usable Mgates equivalent NAND2
Operating voltage 1.8+/-0.15V for the core and 5V +/-0.5V, 3.3+/-0.3V, 2.5+/0.2V for the periphery
High Voltage I/O’s 25-45-65V
Memory Cells Compiled (ROM, SRAM, DPRAM, Register file memory cells)
or synthesized to the Requirements of the Design
32kBytes NVM memory blocks
Cold Sparing Buffers
High Speed LVDS Buffers 655Mbps - PCI Buffers
Set of analog blocks
No single event latch-up below a LET threshold of 75 MeV/mg/cm² at 125°C
SEU hardened flip-flops
TID test up to 300kRads (Si) for 1.8V and 3.3V devices and 150kRads (Si) for
5V and HV I/OS according to Mil-Std 883 TM1019
CCGA, CLGA & CQFP qualified Packages Catalog
Table of Contents
1. Overview............................................................................................................................... 1
2. Periphery .............................................................................................................................. 1
2.1 Buffers description ....................................................................................................................................1
2.2 I/O Clusters ...............................................................................................................................................1
2.3 Double Pad Ring .......................................................................................................................................2
3. Core ...................................................................................................................................... 2
3.1
3.2
3.3
3.4
Standard cell library ..................................................................................................................................2
Memory Hard Blocks.................................................................................................................................2
Analog Blocks ...........................................................................................................................................2
Array Organization ....................................................................................................................................3
4. Advanced Packaging ............................................................................................................ 3
5. Space Multi Project Wafer..................................................................................................... 4
6. Testability Techniques .......................................................................................................... 4
7. Radiation Hardness .............................................................................................................. 4
8. Electrical characteristics ....................................................................................................... 5
8.1 Absolute Maximum Ratings ......................................................................................................................5
8.2 Recommended Operating Conditions .......................................................................................................5
8.3 Consumption .............................................................................................................................................5
8.4 IO DC at 2.5V characteristics ....................................................................................................................5
8.5 IO DC at 3.3V characteristics ....................................................................................................................7
8.6 IO DC at 5V characteristics .......................................................................................................................8
8.7 PCI Characteristics ...................................................................................................................................9
8.8 LVPECL Receiver characteristics .............................................................................................................9
8.9 LVDS reference Characteristics ................................................................................................................9
8.10 LVDS Transmitter Characteristics ...........................................................................................................10
8.11 LVDS Receiver Characteristics ...............................................................................................................10
9. Revision History .................................................................................................................. 11
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1.
Overview
The ASIC “ATMX150RHA Design Manual” presents all the required information and flows to design a mixedsignal ASIC for space applications, allowing users to be trained on Atmel specific or standard commercial
tool kits and methodological details for actual implementations.
This offering is a CMOS technology based, specified with a 5/3.3/2.5V and a HV 25-45-65V ranges for the
periphery, core is supplied at 1.8V.
The technology parameters and some extra features are described here after.
2.
Periphery
2.1
Buffers description
The peripheral I/O buffer is the electrical interface between the external signals (voltage range from 2.3 to
3.6V and from 4.5 to 5.5V) and the internal core signals (from 1.65 to 1.95V).
IO libraries are:
• IO5V0
IO Powered at 5V - 10V tolerant
• IO3V3
IO Powered at 3.3V – both not tolerant and 5V tolerant
• IO2V5
IO Powered at 2.5V, - 3.3V tolerant
All I/O buffers are Cold Sparing, they contains:
• Bidirectional I/O buffers
• Tristate Output I/O buffers
• Output Only I/O buffers
• Input Only I/O buffers (Inverting,Non-Inverting,Schmitt Trigger)
Furthermore the Bidirectional, Tristate Ouputs and Input Only I/O buffers are available with or without PullUp or Pull-Down structures.
Specific I/O buffers have been developed in 3.3V and 2.5V:
• LVDS transmitter and Receiver differential I/O buffers. Cold sparing and tolerant only when they are
disabled (ien=’1’ or oen=’1’)
• LVPECL Receiver differential I/O buffers
And, in 3.3V
• Cold sparing PCI Bidirectional, Tristate Output and Output Only I/O buffers
2.2
I/O Clusters
The periphery of the chip (pad ring) can be split into several I/O segments (I/O clusters), some clusters can
be unpowered while others are active.
A specific Power control line is distributed inside the cluster to be able to force all the I/Os of the cluster in
tristate mode whatever their initial state is (ie: an output only buffer will also be turned to HiZ mode).
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2.3
Double Pad Ring
In order to increase the number of programmable I/O’s, Atmel proposes the double pad ring configuration.
The number of pads on the inner ring will be tailored to the actual need of each design. Core supplies are
automatically routed to the inner ring.
3.
Core
3.1
Standard cell library
The Atmel Standard Cell Library contains a comprehensive set of a combination of logic and storage cells,
including cells that belong to the following categories:
• Buffers and Gates
• Standard and SEU Hardened Flip-flops
• Standard and SEU Hardened Scan Flip-flops
• Latches
• Mux, Adders, Subtractors
3.2
Memory Hard Blocks
The ATMX150RHA memory libraries are developed from Virage memory compilers. All these memories are
synchronous. Four types of memories can be generated on request
•
Single-port synchronous SRAM
•
Dual-port memory with 2 ports read/write synchronous SRAM
•
Two-Port synchronous register-file with one port read and one port write
•
ROM with metal-programming
NVM memory blocks are also proposed.
For maximum block sizes, see the design manual.
3.3
Analog Blocks
Atmel proposes a catalog of pre-qualified IP’s, advanced information for each IP is available under request.
A preliminary list is given below (table 1).
IP block
Features
PLL
40-450 MHz programmable VCO
ADC
12-bit 2 MHz conversion rate @32MHz
ADC
24-bit sampling up to 96 kSa/s
DAC
10-bit 15 MHz
DAC
24-bit sampling up to 2 MSa/s
MUX
8 channels, analog bandwidth 10 MHz
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OSC
10 MHz trimmable, accuracy +/-5%
Xtal OSC
20 MHz
COMP
VHyst [email protected]
BG
Output 1.21/1.23/1.26V, temp.coef 50 ppm/°C
REG
5.5V down to 2.7V to 1.8V, LDO 700mV, 50 mA
DC-DC
5V/2.5V
POR
1.8V/Vth0.9V
Table 1. Catalog of Analog Blocks
A PDK (Physical Design Kit), with a full set of elementary devices is also available to design custom analog
blocks.
3.4
Array Organization
With the ATMX150RHA, the die size and the package are optimized for each mixed-signal ASIC.
However, for some digital designs, pre-defined matrix sizes and pad frames are proposed to ease the
assembly of each individual ASIC design by sticking to available package cavity sizes and layouts.
Double Pad Ring
Single Pad Ring
NAME
AREA (mm2)
Typical Usable
gates(*)
Outer Ring
Pads
Inner Ring
Pads
Typical Usable
gates(*)
ATMX150RHA_216(D)
38
1M
216
88
0.8M
ATMX150RHA_324(D)
77
2.2M
324
140
1.7M
ATMX150RHA_404(D)
114
3.5M
404
180
2.8M
ATMX150RHA_504(D)
170
5.5M
504
232
4.4M
ATMX150RHA_544(D)
199
6.5M
544
252
5.4M
ATMX150RHA_604(D)
237
7.6M
604
284
6.7M
ATMX150RHA_644 (D)
267
8.7M
644
304
7.7M
ATMX150RHA_704(D)
316
10.4M
704
332
9.4M
Table 2. Standard arrays dimensions
(*): based on NAND2 equivalent, without memories
4.
Advanced Packaging
Atmel proposes advanced multi-layers low-noise CQFP and CCGA packages, with isolated power and
ground planes.
CQFP are available with up to 352 leads and CLGA/CCGA up to 896 lands/columns. In addition to the
packages listed in table 3, Atmel offers custom packages development.
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Package
Leads/Columns
CQFP
Up to 352
CLGA/CCGA
349-472-625-896
Table 3. Packages
5.
Space Multi Project Wafer
Atmel proposes a Multi Projects Wafer service, so called SMPW, in order to decrease the cost of reticules
and silicon by sharing them over several designs. Specific milestones have been created to coordinate the
activities and guarantee that there will be no interaction between customer designs.
Any questions related to SMPW service can be addressed to your Atmel technical center.
6.
Testability Techniques
For complex designs, involving blocks of memory and/or cores, careful attention must be given to design-fortest techniques. The chip size of complex designs and the number of functional vectors that would need to
be created to exercise them fully, strongly suggests the use of more efficient techniques. Combinations of
SCAN technic, multiplexed access to memory and/or core blocks, and built-in-self-test logic must be
employed, in addition to functional test patterns, to provide both the user and Atmel the ability to test the
finished product. Test at speed and Transition Delay Fault patterns are also needed to achieve a good
sorting of the dice.
For further information, see the ‘ATMX150RHA TOS manual’.
7.
Radiation Hardness
The ATMX150RHA standard cell library encompasses all the specific functions and buffers necessary for
space designs, such as LVDS transmitters and receivers, PCI buffers, SEU hardened DFFs and cold
sparing buffers. Key radiation-tolerance parameters are controlled and monitored. Reports are available
under request to your Atmel technical center.
Parameter
TID
(1)
Total Ionizing Dose
SEU
Radiation Hardness Assurance
100 kRads(Si) with 2.5V to 3.3V I/Os
50 kRads(Si) with 5V & HV I/Os
(2)
-11
< 4e10
errors/bit-day
Single Event Upset
(3)
SEL
Standard results: LETth > 75 MeV.cm²/mg
Single Event Latch-up
With Deep Trench isolation LETth > 95 MeV.cm²/mg
Table 5. Radiation Hardness
Notes:
(1) Co-60 testing, in compliance with Mil-Std 883 TM 1019.5: Tested at 25°C, with a total dose rate of 300 rad/h and a
total dose up to 300 krad(Si).
(2) Based on hardened DFF, at 1.65V for core, 3V or 5V for I/O’s and 25°C.
(3) In worst case conditions: 1.95V for core, 3.6V or 5.5V for I/O’s @ 125°C
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8.
Electrical characteristics
8.1
Absolute Maximum Ratings
Core Supply Voltage VDD…………….…..………-0.3V to +2V
NOTICE: This absolute maximum ratings voltage is
the maximum voltage that guarantees that the device
will not be burned if those maximum voltages are
applied during a very limited period of time. This is not
a guarantee of functionality or reliability. The users
must be warned that if a voltage exceeding the
maximum voltage (nominal +10%) and below this
absolute maximum rating voltages, is applied to their
devices, the reliability of their devices will be affected.
2.5V IO Supply Voltage VCC……………...………-0.3V to 3V
3.3V IO Supply Voltage VCC………….…………..-0.3V to 4V
5V IO Supply Voltage VCC………….……………..-0.3V to 6V
Storage temperature……….…………………...-65°C to 150°C
ESD………………………………………………………2000V
8.2
8.3
Recommended Operating Conditions
Core Supply Voltage VDD
1.65V to 1.95V
2.5V IO Supply Voltage VCC
2.3V to 2.7V
3.3V IO Supply Voltage VCC
3.0V to 3.6V
5V IO Supply Voltage VCC
4.5V to 5.5V
IO input buffer
0V to VDDIO
Consumption
Symbol
8.4
Parameter
Min
Typ
Max
Unit
Test conditions
TA
Operating Temperature
-55
25
125
°C
VDD
Supply Voltage
1.65
1.8
1.95
V
ICCSBA
Leakage current per gate
0.145
5.5
nA
ICCOPA
Dynamic Current per
Gate
8.8
nA/MHz
Duty cycle = 20%
IO DC at 2.5V characteristics
Symbol
Parameter
Min
VCC
Buffer Supply Voltage
2.3
IIL
Low level Input Current
-1
With pull-up resistor
60
With Pull-down resistor
IIH
IOZ
Typ
Unit
Test conditions
2.7
V
IOs
1
µA
Vin=Vss
260
µA
-5
5
µA
High level Input Current
-1
1
µA
With pull-up resistor
-5
5
µA
With Pull-down resistor
High Impedance State
75
360
µA
1
µA
output Current
-1
2.5
Max
130
180
Vin=Vcc
Vin=Vcc or Vss
no pull resistor
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VIL
Low Level Input Voltage
-0.3
0.7
V
VIH
High Level Input Voltage
2
Vcc+0.3
V
VT+
Schmitt Trigger Threshold
1.31
V
VT-
Schmitt Trigger Threshold
0.94
V
Vhyst
Schmitt Trigger Hysteresis
0.35
V
IICS
Cold Sparing
-1
1
µA
leakage input current
IOCS
Cold Sparing
Vcc=Vss=0V
Vin=0 to Vcc
-1
1
µA
leakage output current
Vcc=Vss=0V
Vout=0 to Vcc
VCSth
Supply threshold of cold
sparing Buffers
0.5
V
IICS < 4µA
VOL
Low level output voltage
0.4V
V
IOL=1.5,3,6,9,12mA
VOH
High level output voltage
V
IOH=1.5,3,6,9,12mA
IOS (1)
Output Short circuit current
Fmax
VCC-0.4
IOSN (nn=1)
14
mA
Vout=Vcc
IOSP (nn=1)
14
mA
Vout=Vss
13
MHz
1 mA
Maximum frequency
-
-
50
4 mA
80
8 mA
(1) Supplied as a design limit but not guaranteed or tested. No more than one output may be shorted at a
time for a maximum duration of 10 seconds.
IOSmax = 14,28,56,84,112 mA for nn=1,2,4 ,6,8
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8.5
IO DC at 3.3V characteristics
Symbol
Parameter
Min
VCC
Buffer Supply Voltage
3.0
IIL
Low level Input Current
-1
With pull-up resistor
110
With Pull-down resistor
IIH
IOZ
Typ
3.3
Max
Unit
3.6
V
IOs
1
µA
Vin=Vss
400
µA
-5
5
µA
High level Input Current
-1
1
µA
With pull-up resistor
-5
5
µA
With Pull-down resistor
140
600
µA
High Impedance State
-1
1
µA
220
320
VIL
Low Level Input Voltage
-0.3
0.8
V
VIH
High Level Input Voltage
2
Vcc+0.3
V
VT+
Schmitt Trigger Threshold
1.63
V
VT-
Schmitt Trigger Threshold
1.23
V
Vhyst
Schmitt Trigger Hysteresis
Cold Sparing
0.4
V
-1
1
µA
leakage input current
IOCS
Cold Sparing
Vin=Vcc
Vin=Vcc or Vss
no pull resistor
output Current
IICS
Test conditions
Vcc=Vss=0V
Vin=0 to Vcc
-1
1
µA
leakage output current
Vcc=Vss=0V
Vout=0 to Vcc
VCSth
Supply threshold of cold
sparing Buffers
0.5
V
IICS < 4µA
VOL
Low level output voltage
0.4V
V
IOL=2,4,8,12,16mA
VOH
High level output voltage
V
IOH=2,4,8,12,16mA
IOS (1)
Output Short circuit current
Fmax
VCC-0.4
IOSN (nn=1)
23
mA
Vout=Vcc
IOSP (nn=1)
23
mA
Vout=Vss
15
MHz
1 mA
Maximum frequency
-
-
70
4 mA
105
8 mA
(1) Supplied as a design limit but not guaranteed or tested. No more than one output may be shorted at a
time for a maximum duration of 10 seconds.
IOSmax = 23,46,92,138,184 mA for nn=1,2,4 ,6,8
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8.6
IO DC at 5V characteristics
Symbol
Parameter
Min
VCC
Buffer Supply Voltage
4.5
IIL
Low level Input Current
-1
With pull-up resistor
180
With Pull-down resistor
IIH
IOZ
Typ
5.0
Max
Unit
Test conditions
5.5
V
IOs
1
µA
Vin=Vss
590
µA
-5
5
µA
High level Input Current
-1
1
µA
With pull-up resistor
-5
5
µA
With Pull-down resistor
High Impedance State
230
1000
µA
1
µA
340
490
-1
Vin=Vcc
Vin=Vcc or Vss
no pull resistor
output Current
VIL (TTL)
Low Level Input Voltage
-0.3
0.8
V
For TTL inputs
VIH (TTL)
High Level Input Voltage
2
Vcc+0.3
V
For TTL inputs
VIL
(CMOS)
Low Level Input Voltage
-0.3
0.3*Vcc
V
For CMOS inputs
VIH
(CMOS)
High Level Input Voltage
0.3*Vcc
Vcc+0.3
V
For CMOS inputs
VT+
Schmitt Trigger Threshold
3.16
V
VT-
Schmitt Trigger Threshold
2.20
V
Vhyst
Schmitt Trigger Hysteresis
Cold Sparing
0.96
V
IICS
-1
1
µA
leakage input current
IOCS
Cold Sparing
Vcc=Vss=0V
Vin=0 to Vcc
-1
1
µA
leakage output current
Vcc=Vss=0V
Vout=0 to Vcc
VCSth
Supply threshold of cold
sparing Buffers
0.5
V
IICS < 4µA
VOL
Low level output voltage
0.4V
V
IOL=2,4,8,12,16mA
VOH
High level output voltage
V
IOH=2,4,8,12,16mA
IOS (1)
Output Short circuit current
Fmax
VCC-0.4
IOSN (nn=1)
35
mA
Vout=Vcc
IOSP (nn=1)
35
mA
Vout=Vss
11
MHz
1 mA
Maximum frequency
-
-
43
4 mA
68
8 mA
(1) Supplied as a design limit but not guaranteed or tested. No more than one output may be shorted at a
time for a maximum duration of 10 seconds.
IOSmax = 35,70,140,210,420 mA for nn=1,2,4 ,6,8
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8.7
PCI Characteristics
Symbol
8.8
Parameter
Min
Typ
Max
3.3
Unit
Test conditions
3.6
V
IOs
VCC
Buffer Supply Voltage
3.0
VIH
High Level Input Voltage
0.5 Vcc
Vcc + 0.3
V
VIL
Low Level Input Voltage
-0.3
0.3 VCC
V
IOH
High Level Current
16
32
mA
VOH=Vcc - 0.4V
IOL
Low Level Current
16
32
mA
VOL=0.4V
IOS(1)
Output Short Current
184
mA
VOH=0 VOL=Vcc
VCSTH
Supply threshold of cold sparing buffers
0.5
V
IICS < 4µA
112
LVPECL Receiver characteristics
DC specifications
Applicable over recommended operating temperature and voltage range unless otherwise noted.
Symbol
8.9
Parameter
Min
Typ
Max
Unit
Test conditions
VCC
Buffer Supply Voltage
3.0
3.3
3.6
V
VCC
Buffer Supply Voltage
2.3
2.5
2.7
V
IIN
Input Leakage
-10
10
µA
ICCstat
Static Consumption(ien=0)
4
mA
VCC=3.3+/-0.3V
ICCstdby
Static Consumption(ien=1)
10
µA
VCC=3.3+/-0.3V
ICCstat
Static Consumption(ien=0)
2.3
mA
VCC=2.5+/-0.25V
ICCstdby
Static Consumption(ien=1)
5.8
µA
VCC=2.5+/-0.25V
2.5
1.5
LVDS reference Characteristics
DC specifications
Applicable over recommended operating temperature and voltage range unless otherwise noted.
Symbol
Parameter
Min
Typ
Max
Unit
Test conditions
VCC
Buffer Supply Voltage
3.0
3.3
3.6
V
VCC
Buffer Supply Voltage
2.3
2.5
2.7
V
Vref
Input Voltage
1.25 5%
1.25
1.25
+ 5%
V
Rpd
Pull Down resistance
140
200
260
kOhm
VIN=1.25V
ICCstat
Static Consumption(ien=0)
260
320
µA
VCC=3.3+/-0.3V
ICCstdby
Static Consumption(ien=1)
2
µA
VCC=3.3+/-0.3V
ICCstat
Static Consumption(ien=0)
184
µA
VCC=2.5+/-0.25V
ICCstdby
Static Consumption(ien=1)
1.2
µA
VCC=2.5+/-0.25V
150
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8.10
LVDS Transmitter Characteristics
DC specifications
Applicable over recommended operating temperature and voltage range unless otherwise noted.
Symbol
Min
Typ
Max
Unit
Test conditions
VCC
Buffer Supply Voltage
3.0
3.3
3.6
V
VCC
Buffer Supply Voltage
2.3
2.5
2.7
V
VOD|
Output Differential Voltage
247
350
454
mV
Rload = 100 ohms
VOS
Output offset Voltage
1.125
1.25
1.375
V
Rload = 100 ohms
|DVOD| (1)
Change in |VOD|
50
|DVOS| (1)
Change in VOS - steady state
50
mV
Change in VOS - dynamic state
150
mV
7
24
mA
Drivers shorten to ground or VCC
4.5
12
mA
Drivers shorten together
4
6
mA
VCC=3.3+/-0.3V
10
µA
VCC=3.3+/-0.3V
3.5
mA
VCC=2.5+/-0.25V
5.8
µA
VCC=2.5+/-0.25V
IOS
8.11
Parameter
Output short current
ICCstat
Static Consumption(ien=0)
ICCstdby
Static Consumption(ien=1)
ICCstat
Static Consumption(ien=0)
ICCstdby
Static Consumption(ien=1)
2.3
Rload = 100 ohms
Rload = 100 ohms
LVDS Receiver Characteristics
DC specifications
Applicable over recommended operating temperature and voltage range unless otherwise noted.
Symbol
Parameter
Min
Typ
Max
Unit
Test conditions
VCC
Buffer Supply Voltage
3.0
3.3
3.6
V
VCC
Buffer Supply Voltage
2.3
2.5
2.7
V
VID
Input Differential Voltage
200
600
mV
VCM
Common Mode Input Voltage
0.05
2.35
V
IIN
Input Leakage
-10
10
µA
ICCstat
Static Consumption(ien=0)
6
mA
VCC=3.3+/-0.3V
ICCstdby
Static Consumption(ien=1)
10
µA
VCC=3.3+/-0.3V
ICCstat
Static Consumption(ien=0)
3.5
mA
VCC=2.5+/-0.25V
ICCstdby
Static Consumption(ien=1)
5.8
µA
VCC=2.5+/-0.25V
3.5
2
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9.
Revision History
Doc. Rev.
Date
Comments
1.0
2015/01/30
Creation
ATMX150RHA Advanced Information
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