AT17LV65A/128A/256A/512A/010A/002A - Complete

AT17LV65A (1), AT17LV128A (1), AT17LV256A (1)
AT17LV512A, AT17LV010A, AT17LV002A
Note 1.
AT17LV65A, AT17LV128A,
and AT17LV256A are
Not Recommended for New
Designs (NRND) and are
Replaced by AT17LV512A.
FPGA Configuration EEPROM Memory
3.3V and 5V System Support
DATASHEET
Features
 EE Programmable Serial Memories Designed to Store Configuration Programs for
Altera® FLEX® and APEX™ Field Programmable Gate Arrays (FPGA)
̶ 1,048,576 x 1-bit
̶ 65,536 x 1-bit(1)
̶ 262,144 x 1-bit(1)
(1)
̶ 131,072 x 1-bit
̶ 524,288 x 1-bit
̶ 2,097,152 x 1-bit
 Supports both 3.3V and 5.0V Operating Voltage Applications
 In-System Programmable (ISP) via 2-wire Bus
 Simple Interface to SRAM FPGAs
 Compatible with the Atmel® AT6000, AT40K and AT94K Devices, Altera FLEX,








APEX Devices, ORCA® FPGAs, Xilinx® XC3000, XC4000, XC5200, Spartan®,
Virtex™ FPGAs, Motorola MPA1000 FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Very Low-power CMOS EEPROM Process
Programmable Reset Polarity
8-lead PDIP and 20-lead PLCC Packages (Pin-compatible Across Product Family)
Emulation of the Atmel AT24C Serial EEPROMs
Low-power Standby Mode
High-reliability
̶ Endurance: 100,000 Write Cycles
̶ Data Retention: 90 Years for Industrial Parts (at 85C)
Green (Pb/Halide-free/RoHS Compliant) Package Options Available
Description
The Atmel® AT17LVxxxA FPGA configuration EEPROMs (Configurators) provide an
easy-to-use, cost-effective configuration memory solution for FPGAs. The
AT17LVxxxA are packaged in 8-lead PDIP and 20-lead PLCC options. The
AT17LVxxxA configurator uses a simple serial-access procedure to configure one or
more FPGA devices. The user can select the polarity of the reset function by
programming four EEPROM bytes. These devices support a write protection
mechanism within its programming mode.
The AT17LVxxxA configurators can be programmed with industry-standard
programmers, the Atmel ATDH2200E Programming Kit, or the Atmel ATDH2225 ISP
Cable.
Table 1.
AT17LVxxxA Packages
Package
AT17LV512A
AT17LV010A
AT17LV002A
8-lead PDIP
Yes
Yes
–
20-lead PLCC
Yes
Yes
Yes
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014
1.
Pin Configuration and Descriptions
Table 1-1.
2
Pin Descriptions
Pin
Description
DATA
Three-state DATA Output for Configuration. Open-collector bi-directional pin for programming.
DCLK
Clock Output or Clock Input. Rising edges on DCLK increment the internal address counter and present
the next bit of data to the DATA pin. The counter is incremented only if the RESET/OE input is held High,
the nCS input is held Low, and all configuration data has not been transferred to the target device
(otherwise, as the master device, the DCLK pin drives Low).
WP1
Write Protect (1). This pin is used to protect portions of memory during programming, and it is disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading operations.
This pin is only available on the AT17LV512A/010A/002A.
RESET/OE
RESET (Active Low) / Output Enable (Active High) when SER_EN is High. A Low logic level resets the
address counter. A High logic level (with nCS Low) enables DATA and permits the address counter to
count. In the mode, if this pin is Low (reset), the internal oscillator becomes inactive and DCLK drives Low.
The logic polarity of this input is programmable and must be programmed active High (RESET active Low)
by the user during programming for Altera applications.
WP
Write Protect Input (when nCS is Low) during programming only (SER_EN Low). When WP is Low, the
entire memory can be written. When WP is enabled (High), the lowest block of the memory cannot be
written. This pin is only available on AT17LV65A/128A/256A devices.
nCS
Chip Select Input (Active Low). A Low input (with OE High) allows DCLK to increment the address
counter and enables DATA to drive out. If the AT17LVxxxA is reset with nCS Low, the device initializes as
the first (and master) device in a daisy-chain. If the AT17LVxxxA is reset with nCS High, the device
initializes as a subsequent AT17LVxxxA in the chain.
GND
Ground. A 0.2μF decoupling capacitor between VCC and GND is recommended.
nCASC
Cascade Select Output (Active Low). This output goes Low when the address counter has reached its
maximum value. In a daisy-chain of AT17LVxxxA devices, the nCASC pin of one device is usually
connected to the nCS input pin of the next device in the chain, which permits DCLK from the master
configurator to clock data from a subsequent AT17LVxxxA device in the chain. This feature is not available
on the AT17LV65A (NRND).
A2
Device Selection Input, A2. This is used to enable (or select) the device during programming (i.e., when
SER_EN is Low). A2 has an internal pull-down resistor.
READY
Open Collector Reset State Indicator. Driven Low during power-on reset cycle, released when powerup is complete. (recommended 4.7k pull-up on this pin if used).
SER_EN
Serial Enable must be held High during FPGA loading operations. Bringing SER_EN Low enables the 2wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC.
VCC
Power Supply. 3.3V (±10%) and 5.0V (±10%) power supply pin.
AT17LV65A/128A/256A/512A/002A [DATASHEET]
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014
Table 1-2.
Pin Configurations
AT17LV65A/128A/256A(2)
AT17LV512A/010A
AT17LV002A
Name
I/O
20-lead PLCC
8-lead PDIP
20-lead PLCC
20-lead PLCC
DATA
I/O
2
1
2
2
DCLK
I
4
2
4
4
WP1
I
–
–
5
5
RESET/OE
I
8
3
8
8
nCS
I
9
4
9
9
10
5
10
10
12
6
12
12
GND
nCASC(1)
O
A2
I
READY
O
–
–
15
15
SER_EN
I
18
7
18
18
20
8
20
20
VCC
The nCASC feature is not available on the AT17LV65A (NRND) device.
The AT17LV65A, AT17LV128A, and AT17LV256A are not recommended for new designs.
Pinouts(1)
20-lead PLCC
8-lead PDIP
Notes:
1.
2.
3.
4.
GND
NC
VCC
NC
20
19
SER_EN
17
NC
NC
6
16
NC
NC
7
15
NC (READY(3))
(WP(2)) RESET/OE
8
14
NC
NC
5
18
5
13
4
4
(A2) nCASC
nCS
DCLK
WP1(3)
12
nCASC(4) (A2)
(4)
6
DATA
3
1
(WP(2)) RESET/OE
11
SER_EN
NC
VCC
7
NC
8
2
2
1
10
DATA
DCLK
3
(Top View)
(Top View)
9
Figure 1-1.
nCS
1.
2.
GND
Notes:
Drawings are not to scale.
This pin is only available on the AT17LV65A/128A/256A (NRND).
This pin is only available on the AT17LV512A/010A/002A.
The nCASC feature is not available on the AT17LV65A (NRND).
AT17LV65A/128A/256A/512A/002A [DATASHEET]
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014
3
2.
Block Diagram
Figure 2-1.
Block Diagram
SER_EN
WP1(2)
Oscillator
Controll
Programming
Data Shift
Register
Programming
Mode Logic
Oscillator
Row
Address
Counter
Power On
Reset
Row
Decoder
Bit
Counter
DCLK READY(2)
Notes:
4
1.
2.
3.
RESET/OE
(WP(1))
Column
Decoder
nCS
nCASC
This pin is only available on AT17LV65A/128A/256A (NRND).
This pin is only available on AT17LV512A/010A/002A.
The nCASC feature is not available on the AT17LV65A (NRND).
AT17LV65A/128A/256A/512A/002A [DATASHEET]
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014
EEPROM
Cell
Matrix
3.
Device Description
The control signals for the configuration EEPROM (nCS, RESET/OE and DCLK) interface directly with the
FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data
from the configuration EEPROM without requiring an external controller.
The configuration EEPROM’s RESET/OE and nCS pins control the tri-state buffer on the DATA output pin and
enable the address counter and the oscillator. When RESET/OE is driven Low, the configuration EEPROM
resets its address counter and tri-states its DATA pin. The nCS pin also controls the output of the AT17LVxxxA
configurator. If nCS is held High after the RESET/OE pulse, the counter is disabled and the DATA output pin is
tri-stated. When nCS is driven subsequently Low, the counter and the DATA output pin are enabled. When
RESET/OE is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regardless of
the state of the nCS.
When the configurator has driven out all of its data and nCASC is driven Low, the device tri-states the DATA pin
to avoid contention with other configurators. Upon power-up, the address counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High, this document
will describe RESET/OE.
4.
FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The
program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA
mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory.
The AT17LVxxxA Serial Configuration EEPROM has been designed for compatibility with the Master Serial
mode.
This document discusses the Altera FLEX FPGA device interfaces.
5.
Control of Configuration
Most connections between the FPGA device and the AT17LVxxxA Serial EEPROM are simple and selfexplanatory.




The DATA output of the AT17LVxxxA configurator drives DIN of the FPGA devices.
The master FPGA DCLK output or external clock source drives the DCLK input of the AT17LVxxxA
configurator.
The nCASC output of any AT17LVxxxA configurator drives the nCS input of the next configurator in a
cascaded chain of EEPROMs.
SER_EN must be connected to VCC (except during ISP).
AT17LV65A/128A/256A/512A/002A [DATASHEET]
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014
5
6.
Cascading Serial Configuration EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories,
cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the next clock signal to the configurator asserts its nCASC
output low and disables its DATA line driver. The second configurator recognizes the low level on its nCS input
and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE
on each configurator is driven to a Low level.
If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to a High
level.
The AT17LV65A (NRND) does not have the nCASC feature to perform cascaded configurations.
7.
AT17LVxxxA Reset Polarity
The AT17LVxxxA configurator allows the user to program the polarity of the RESET/OE pin as either
RESET/OE or RESET/OE. This feature is supported by industry-standard programmer algorithms.
8.
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the
2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated
inside the chip.
9.
Standby Mode
The AT17LVxxxA enters a low-power standby mode whenever nCS is asserted High. In this mode,
the configurator consumes less than 150μA of current at 3.3V. The output remains in a high-impedance state
regardless of the state of the RESET/OE input.
6
AT17LV65A/128A/256A/512A/002A [DATASHEET]
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014
10.
Electrical Specifications
10.1
Absolute Maximum Ratings*
*Notice: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under
operating conditions is not implied. Exposure to
Absolute Maximum Rating conditions for extended
periods of time may affect device reliability.
Operating Temperature . . . . . . . . . . . .-40C to +85C
Storage Temperature . . . . . . . . . . . . .-65C to +150C
Voltage on Any Pin
with Respect to Ground . . . . . . . . . -0.1V to VCC +0.5V
Supply Voltage (VCC) . . . . . . . . . . . . . . -0.5V to +7.0V
Maximum Soldering Temp. (10s @ 1/16 in.) . . . 260C
ESD (RZAP = 1.5K, CZAP = 100 pF)2000V
10.2
Operating Conditions
Table 10-1.
Operating Conditions
3.3V
10.3
Symbol
Description
VCC
Industrial
5.0V
Min
Max
Min
Max
Units
3.0
3.6
4.5
5.5
V
Supply voltage relative to GND
-40C to +85C
DC Characteristics
Table 10-2.
DC Characteristics for VCC = 3.3V ± 10%
AT17LV65A/128A/256A(1)
AT17LV512A/010A
AT17LV002A
Symbol
Description
Min
Max
Min
Max
Min
Max
Units
VIH
High-level Input Voltage
2.0
VCC
2.0
VCC
2.0
VCC
V
VIL
Low-level Input Voltage
0
0.8
0
0.8
0
0.8
V
VOH
High-level Output Voltage
(IOH = -2mA)
VOL
Low-level Output Voltage
(IOL = +3mA)
ICCA
Supply Current, Active Mode
IL
Input or Output Leakage Current
(VIN = VCC or GND)
ICCS
Supply Current, Standby Mode
Note:
1.
2.4
-10
2.4
2.4
V
0.4
0.4
0.4
V
5
5
5
mA
10
μA
150
μA
10
100
-10
10
-10
100
The AT17LV65A, AT17LV128A, and AT17LV256A are not recommended for new designs.
AT17LV65A/128A/256A/512A/002A [DATASHEET]
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014
7
Table 10-3.
DC Characteristics for VCC = 5.0V ± 10%
AT17LV65A/128A/256A(1)
Description
Min
Max
Min
Max
Min
Max
Units
VIH
High-level Input Voltage
2.0
VCC
2.0
VCC
2.0
VCC
V
VIL
Low-level Input Voltage
0
0.8
0
0.8
0
0.8
V
VOH
High-level Output Voltage
(IOH = -2mA)
VOL
Low-level Output Voltage
(IOL = +3mA)
ICCA
Supply Current, Active Mode
IL
Input or Output Leakage Current
(VIN = VCC or GND)
ICCS1
Supply Current, Standby Mode
1.
3.6
3.76
-10
3.76
V
0.37
0.37
0.37
V
10
10
10
mA
10
μA
350
μA
10
-10
150
10
-10
200
The AT17LV65A, AT17LV128A, and AT17LV256A are not recommended for new designs.
AC Characteristics
Table 10-4.
AC Characteristics for VCC = 3.3V ± 10%
AT17LV65A/128A/256A(3)
Symbol
Description
TOE(1)
OE to Data Delay
TCE(1)
Units
55
55
ns
CE to Data Delay
60
60
ns
TCAC(1)
CLK to Data Delay
80
60
ns
TOH
Data Hold from CE, OE, or CLK
TDF(2)
CE or OE to Data Float Delay
TLC
CLK Low Time
25
25
ns
THC
CLK High Time
25
25
ns
TSCE
CE Setup Time to CLK
(to guarantee proper counting)
60
35
ns
THCE
CE Hold Time from CLK
(to guarantee proper counting)
0
0
ns
THOE
OE High Time
(guarantees counter is reset)
25
25
ns
FMAX
Maximum Input Clock Frequency
10
10
MHz
1.
2.
3.
Min
Max
AT17LV512A/010A/002A
Max
Notes:
8
AT17LV002A
Symbol
Note:
10.4
AT17LV512A/010A
0
Min
0
55
ns
50
ns
AC test lead = 50pF.
Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.
The AT17LV65A, AT17LV128A, and AT17LV256A are not recommended for new designs.
AT17LV65A/128A/256A/512A/002A [DATASHEET]
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014
Table 10-5.
AC Characteristics when Cascading for VCC = 3.3V ± 10%
AT17LV65A/128A/256A(3)
Symbol
TCDF
(2)
Description
Min
Max
AT17LV512A/010A/002A
Min
Max
Units
CLK to Data Float Delay
60
50
ns
TOCK(1)
CLK to CEO Delay
60
55
ns
TOCE(1)
CE to CEO Delay
60
40
ns
TOOE(1)
RESET/OE to CEO Delay
45
35
ns
FMAX
Maximum Input Clock Frequency
Notes:
1.
2.
3.
Table 10-6.
8
10
MHz
AC test lead = 50pF.
Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.
The AT17LV65A, AT17LV128A, and AT17LV256A are not recommended for new designs.
AC Characteristics for VCC = 5.0V ± 10%
AT17LV65A/128A/256A(3)
Symbol
Description
TOE(1)
OE to Data Delay
TCE(1)
Max
Units
35
35
ns
CE to Data Delay
45
45
ns
TCAC(1)
CLK to Data Delay
55
50
ns
TOH
Data Hold from CE, OE, or CLK
TDF(2)
CE or OE to Data Float Delay
TLC
CLK Low Time
20
20
ns
THC
CLK High Time
20
20
ns
TSCE
CE Setup Time to CLK
(to guarantee proper counting)
40
25
ns
THCE
CE Hold Time from CLK
(to guarantee proper counting)
0
0
ns
THOE
OE High Time
(guarantees counter is reset)
20
20
ns
FMAX
Maximum Input Clock Frequency
12.5
15
MHz
Notes:
1.
2.
3.
Min
Max
AT17LV512A/010A/002A
0
Min
0
50
ns
50
ns
AC test lead = 50pF.
Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.
The AT17LV65A, AT17LV128A, and AT17LV256A are not recommended for new designs.
AT17LV65A/128A/256A/512A/002A [DATASHEET]
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014
9
Table 10-7.
AC Characteristics when Cascading for VCC = 5.0V ± 10%
AT17LV65A/128A/256A(3)
Symbol
TCDF
(2)
Description
Min
Max
AT17LV512A/010A/002A
Min
Max
Units
CLK to Data Float Delay
50
50
ns
TOCK(1)
CLK to CEO Delay
40
40
ns
TOCE(1)
CE to CEO Delay
35
35
ns
TOOE(1)
RESET/OE to CEO Delay
35
30
ns
FMAX
Maximum Input Clock Frequency
Notes:
1.
2.
3.
Figure 10-1.
10
12.5
MHz
AC test lead = 50pF.
Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.
The AT17LV65A, AT17LV128A, and AT17LV256A are not recommended for new designs.
AC Waveforms
nCS
TSCE
TSCE
THCE
RESET/OE
TLC
THOE
THC
DCLK
TOE
TOH
TCAC
TDF
TCE
DATA
TOH
Figure 10-2.
AC Waveforms when Cascading
RESET/OE
nCS
DCLK
TCDF
DATA
FIRST BIT
LAST BIT
TOCK
TOCE
TOOE
nCASL
TOCE
10
AT17LV65A/128A/256A/512A/002A [DATASHEET]
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014
10.5
Thermal Resistance Coefficients
Table 10-8.
Thermal Resistance Coefficients
AT17LV65A/128A/256A(2)
Package Type
8P3
Plastic Dual Inline
Package (PDIP)
20J
Plastic Leaded Chip
Carrier (PLCC)
Notes:
1.
2.
AT17LV512A/010A
JC [C/W]
37
JA [C/W](1)
107
AT17LV002A
JC [C/W]
35
35
35
JA [C/W](1)
90
90
90
Airflow = 0ft/min.
The AT17LV65A, AT17LV128A, and AT17LV256A are not recommended for new designs.
AT17LV65A/128A/256A/512A/002A [DATASHEET]
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014
11
11.
Ordering Information
11.1
Ordering Code Detail
AT 1 7 LV 5 1 2 A - 1 0 P U
Package Device Grade
Atmel Designator
U
Product Family
17LV = FPGA EEPROM
Configuration Memory
= Green, Industrial
Temperature Range
(-40°C to +85°C)
Package Option
P
J
Device Density
65 = 65 kilobit
128 = 128 kilobit
256 = 256 kilobit
512 = 512 kilobit
010 = 1 Mbit
002 = 2 Mbit
= 8P3, 8-lead PDIP
= 20J, 20-lead PLCC
Product Variation
10 = Default Value
Special Pinouts
A = Altera
Blank = Xilinx/Atmel/Other
11.2
Ordering Information
Memory Size
512-Kbit(1)(4)
Atmel Ordering Code
AT17LV512A-10JU
AT17LV512A-10PU
1-Mbit(2)(4)
AT17LV010A-10JU
AT17LV010A-10PU
2-Mbit(1)(4)
Notes:
1.
2.
3.
4.
AT17LV002A-10JU
Lead Finish
Sn
(Lead-free/Halogen-free)
Sn
(Lead-free/Halogen-free)
Package
Operation Range
3.0V to 5.5V
Industrial
(-40C to 85C)
3.0V to 5.5V
Industrial
(-40C to 85C)
3.0V to 5.5V
Industrial
(-40C to 85C)
20J
8P3
20J
8P3
Sn
(Lead-free/Halogen-free)
20J
Use 512-Kbit density parts to replace Altera EPC1441.
Use 1-Mbit density parts to replace Altera EPC1
Use 2-Mbit density parts to replace Altera EPC2.
The AT17LVxxxA do not support JTAG programming. They use a 2-wire serial interface for in-system
programming.
Package Type
12
Voltage
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20J
20-lead, Plastic J-leaded Chip Carrier (PLCC)
AT17LV65A/128A/256A/512A/002A [DATASHEET]
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014
12.
Packaging Information
12.1
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
MIN
NOM
MAX
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
D1
0.005
E
0.300
E1
0.240
SYMBOL
A
b2
b3
b
4 PLCS
Side View
L
e
2
3
3
0.310
0.325
4
0.250
0.280
3
0.150
2
0.100 BSC
eA
L
Notes:
0.210
NOTE
0.300 BSC
0.115
0.130
4
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
06/21/11
Package Drawing Contact:
[email protected]
TITLE
GPC
DRAWING NO.
8P3, 8-lead, 0.300” Wide Body, Plastic Dual
In-line Package (PDIP)
PTC
8P3
AT17LV65A/128A/256A/512A/002A [DATASHEET]
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014
REV.
D
13
12.2
20J – PLCC
PIN NO. 1
1.14(0.045) X 45°
1.14(0.045) X 45°
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
e
E1
E
D2/E2
B1
B
A2
D1
A1
D
A
0.51(0.020)MAX
45° MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102mm) maximum
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
9.779
–
10.033
D1
8.890
–
9.042
E
9.779
–
10.033
E1
8.890
–
9.042
D2/E2
7.366
–
8.382
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
Package Drawing Contact:
[email protected]
14
TITLE
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
AT17LV65A/128A/256A/512A/002A [DATASHEET]
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014
DRAWING NO. REV.
20J
B
13.
Revision History
Rev. No.
Date
History
The AT17LV65A, AT17LV128A, and AT17LV256A are not recommended for new designs.
2322I
10/2014
Removed the commercial and TQFP options.
Updated the 8P3 package outline drawing, ordering code details, ordering code table,
document’s template, Atmel logos, disclaimer page.
AT17LV65A/128A/256A/512A/002A [DATASHEET]
Atmel-2322I-FPGA-AT17LV65A-128A-256A-512A-002A-Datasheet_102014
15
XXXXXX
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