AT83C5134/35/36 - Complete

Features
• 80C52X2 Core (6 Clocks per Instruction)
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– Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode
– Dual Data Pointer
– Full-duplex Enhanced UART (EUART), TxD and Rxd are 5 Volt Tolerant
– Three 16-bit Timer/Counters: T0, T1 and T2
– 256 Bytes of Scratchpad RAM
8/16/32-Kbyte On-chip ROM
512 byte or 32-Kbyte EEPROM(1)
On-chip Expanded RAM (ERAM): 1024 Bytes
Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
USB 2.0 Full Speed Compliant Module with Interrupt on Transfer Completion (12Mbps)
– Endpoint 0 for Control Transfers: 32-byte FIFO
– 6 Programmable Endpoints with In or Out Directions and with Bulk, Interrupt or
Isochronous Transfers
• Endpoint 1, 2, 3: 32-byte FIFO
• Endpoint 4, 5: 2 x 64-byte FIFO with Double Buffering (Ping-pong Mode)
– Suspend/Resume Interrupts
– Power-on Reset and USB Bus Reset
– 48 MHz DPLL for Full-speed Bus Operation
– USB Bus Disconnection on Microcontroller Request
5 Channels Programmable Counter Array (PCA) with 16-bit Counter, High-speed
Output, Compare/Capture, PWM and Watchdog Timer Capabilities
Programmable Hardware Watchdog Timer (One-time Enabled with Reset-out): 50 ms to
6s at 4 MHz
Keyboard Interrupt Interface on Port P1 (8 Bits)
TWI (Two Wire Interface) 400Kbit/s
SPI Interface (Master/Slave Mode) MISO,MOSI,SCK and SS are 5 Volt Tolerant
34 I/O Pins
4 Direct-drive LED Outputs with Programmable Current Sources: 2-6-10 mA Typical
4-level Priority Interrupt System (11 sources)
Idle and Power-down Modes
0 to 32 MHz On-chip Oscillator with Analog PLL for 48 MHz Synthesis
Industrial Temperature Range
Low Voltage Range Supply: 2.7V to 3.6V
Packages: Die SO28, QFN32, MLF48, TQFP64
Notes:
1. EEPROM only available on MLF48
1. Description
AT83C5134/35/36 are high performance ROM versions
of the 80C51 single-chip 8-bit microcontrollers with full
speed USB functions.
AT83C5134/35 is pin compatible with AT89C5130A 16Kbytes In-System Programmable Flash microcontrollers.
8-bit
Microcontroller
with Full Speed
USB Device
AT83C5134
AT83C5135
AT83C5136
This allows to use AT89C5130A for development, pre-production and flexibility, while using
AT83C5134/35 for cost reduction in mass production. Similarly AT83C5136 is pin compatible
with AT89C5131A 32-Kbytes Flash microcontroller.
AT83C5134/35/36 features a full-speed USB module compatible with the USB specifications
Version 2.0. This module integrates the USB transceivers and the Serial Interface Engine (SIE)
with Digital Phase Locked Loop and 48 MHz clock recovery. USB Event detection logic (Reset
and Suspend/Resume) and FIFO buffers supporting the mandatory control Endpoint (EP0) and
5 versatile Endpoints (EP1/EP2/EP3/EP4/EP5) with minimum software overhead are also part of
the USB module.
AT83C5134/35/36 retains the features of the Atmel 80C52 with extended ROM cpacity (8/16/32
Kbytes), 256 bytes of internal RAM, a 4-level interrupt system, two 16-bit timer/counters (T0/T1),
a full duplex enhanced UART (EUART) and an on-chip oscillator.
In addition, AT83C5134/35/36 has an on-chip expanded RAM of 1024 bytes (ERAM), a dualdata pointer, a 16-bit up/down Timer (T2), a Programmable Counter Array (PCA), up to 4 programmable LED current sources, a programmable hardware watchdog and a power-on reset.
AT83C5134/35/36 has two software-selectable modes of reduced activity for further reduction in
power consumption. In the idle mode the CPU is frozen while the timers, the serial ports and the
interrupt system are still operating. In the power-down mode the RAM is saved, the peripheral
clock is frozen, but the device has full wake-up capability through USB events or external
interrupts.
2
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
XTAL1
XTAL2
EUART
+
BRG
ALE
32Kx8 ROM
SCK
SDA
MISO
MOSI
(1) (1) (1) (1)
(1) (1)
EEPROM*
ERAM
RAM
256x8
SCL
T2
T2EX
CEX
ECI
VDD
VSS
TxD
(1) (1)
(2) (2)
SS
RxD
3. Block Diagram
1Kx8
PCA
1Kx8
Timer2
TWI
SPI
TWI interface
C51
CORE
PSEN
CPU
EA
Parallel I/O Ports & Ext. Bus
Key Watch USB
Board Dog
D+
D-
KIN
P4
P3
P2
P1
INT1
(2) (2)
P0
Port 0 Port 1 Port 2 Port 3 Port 4
(2) (2)
T1
(2)
INT
Ctrl
INT0
Timer 0
Timer 1
RST
WR
(2)
T0
RD
* EEPROM only available in MLF48
Notes:
1. Alternate function of Port 1
2. Alternate function of Port 3
3. Alternate function of Port 4
3
7683C–USB–11/07
4. Pinout Description
Pinout
NC
P1.0/T2/KIN0
P1.1/T2EX/KIN1/SS
P1.2/ECI/KIN2
P1.3/CEX0/KIN3
P0.0/AD0
P1.4/CEX1/KIN4
P2.1/A9
P2.0/A8
P2.2/A10
P1.5/CEX2/KIN5/MISO
P1.6/CEX3/KIN6/SCK
AT83C5134/35/36 64-pin VQFP Pinout
NC
Figure 4-1.
P4.1/SDA
P4.0/SCL
P1.7/CEX4/KIN7/MOSI
4.1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
NC
P2.3/A11
1
2
48
47
P2.4/A12
3
46
NC
P0.1/AD1
P2.5/A13
XTAL2
XTAL1
4
45
P0.2/AD2
5
6
44
43
RST
P0.3/AD3
VSS
P2.6/A14
7
42
P2.7/A15
VDD
AVDD
8
9
41
40
VQFP64
10
39
NC
11
AVSS 12
NC 13
38
P3.0/RxD
36
35
NC
NC
37
14
15
16
NC
NC
P0.4/AD4
P3.7/RD/LED3
P0.5/AD5
P0.6/AD6
P0.7/AD7
P3.6/WR/LED2
34 NC
33 NC
4
P3.4/T0
P3.5/T1/LED1
NC
P3.2/INT0
P3.3/INT1/LED0
P3.1/TxD
ALE
PSEN
EA
VREF
NC
D-
D+
PLLF
NC
NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 3132
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
P4.1/SDA
P2.3/A11
P2.4/A12
P1.1/T2EX/KIN1/SS
P1.3/CEX0/KIN3
P1.2/ECI/KIN2
P0.0/AD0
P1.4/CEX1/KIN4
P2.0/A8
P1.5/CEX2/KIN5/MISO
P2.2/A10
P2.1/A9
P1.6/CEX3/KIN6/SCK
P1.7/CEX4/KIN7/MOSI
AT83C5134/35/36 48-pin MLF Pinout
P4.0/SCL
Figure 4-2.
48 47 46 45 44 43 42 41 40 39 38 37
36
2
35
3
34
1
P2.5/A13
4
33
XTAL2
XTAL1
5
32
RST
P0.3/AD3
6
31
VSS
P2.6/A14
P2.7/A15
7
30
P0.4/AD4
9
29
28
P3.7/RD/LED3
VDD
AVDD
10
27
P0.6/AD6
MLF48
8
P0.5/AD5
P0.7/AD7
P3.6/WR/LED2
P3.5/T1/LED1
P3.4/T0
P3.3/INT1/LED0
P3.2/INT0
ALE
PSEN
P3.1/TxD
VREF
EA
D+
D-
PLLF
AVSS 11
26
P3.0/RxD 12
25
13 14 15 16 17 18 19 20 21 22 23 24
Figure 4-3.
P1.0/T2/KIN0
P0.1/AD1
P0.2/AD2
AT83C5134/35/36 28-pin SO Pinout
P1.5/CEX2/KIN5/MISO 1
28
P1.4/CEX1/KIN4
P1.6/CEX3/KIN6/SCK 2
P1.7/CEX4/KIN7/MOSI 3
27
26
P1.3/CEX0/KIN3
P4.0/SCL 4
25
P1.1/T2EX/KIN1/SS
24
23
P1.0/T2/KIN0
P4.1/SDA 5
XTAL2 6
XTAL1 7
VDD 8
AVSS 9
P3.0/RxD 10
11
PLLF
D- 12
D+
VREF
13
14
SO28
P1.2/ECI/KIN2
RST
22
VSS
21
20
P3.7/RD/LED3
P3.6/WR/LED2
19
18
P3.4/T0
P3.5/T1/LED1
17
P3.3/INT1/LED0
16
P3.2/INT0
15
P3.1/TxD
5
7683C–USB–11/07
Figure 4-4.
P1.2/ECI/KIN2
P1.1/T2EX/KIN1/SS
P1.3/CEX0/KIN3
P1.5/CEX2/KIN5/MISO
P1.4/CEX1/KIN4
P1.7/CEX4/KIN7/MOSI
P1.6/CEX3/KIN6/SCK
P4.0/SCL
AT83C5134/35/36 32-pin QFN Pinout
32 31 30 29 28 27 26 25
P4.1/SDA
1
24
P1.0/T2/KIN0
XTAL2
2
23
RST
XTAL1
3
22
NC
VDD
4
21
VSS
AVDD
5
20
VSS
AVSS
6
19
P3.7/RD/LED3
P3.0/RxD
7
18
P3.6/WR/LED2
PLLF
8
17
P3.5/T1/LED1
QFN32
P3.4/T0
P3.2/INT0
P3.3/INT1/LED0
UVSS
P3.1/TxD
VREF
D-
D+
9 10 11 12 13 14 15 16
Note : The metal plate can be connected to Vss
4.2
Signals
All the AT83C5134/35/36 signals are detailed by functionality on Table 4-1 through Table 4-12.
Table 4-1.
Keypad Interface Signal Description
Signal
Name
Type
KIN[7:0)
I
Table 4-2.
Description
Keypad Input Lines
Holding one of these pins high or low for 24 oscillator periods triggers a keypad
interrupt if enabled. Held line is reported in the KBCON register.
P1[7:0]
Programmable Counter Array Signal Description
Signal
Name
Type
ECI
I
Description
External Clock Input
Capture External Input
CEX[4:0]
Alternate
Function
I/O
Compare External Output
Alternate
Function
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
6
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
Table 4-3.
Serial I/O Signal Description
Signal
Name
Type
RxD
I
TxD
O
Table 4-4.
Signal
Name
Description
Serial Input
The serial input for Extended UART. This I/O is 5 Volt Tolerant.
Serial Output
The serial output for Extended UART. This I/O is 5 Volt Tolerant.
Alternate
Function
P3.0
P3.1
Timer 0, Timer 1 and Timer 2 Signal Description
Type
Description
Alternate
Function
Timer 0 Gate Input
INT0 serves as external run control for timer 0, when selected by GATE0 bit in
TCON register.
INT0
I
External Interrupt 0
INT0 input set IE0 in the TCON register. If bit IT0 in this register is set, bits IE0 are
set by a falling edge on INT0. If bit IT0 is cleared, bits IE0 is set by a low level on
INT0.
P3.2
Timer 1 Gate Input
INT1 serves as external run control for Timer 1, when selected by GATE1 bit in
TCON register.
INT1
I
T0
I
Timer Counter 0 External Clock Input
When Timer 0 operates as a counter, a falling edge on the T0 pin increments the
count.
P3.4
T1
I
Timer/Counter 1 External Clock Input
When Timer 1 operates as a counter, a falling edge on the T1 pin increments the
count.
P3.5
T2
T2EX
Table 4-5.
Signal
Name
LED[3:0]
External Interrupt 1
INT1 input set IE1 in the TCON register. If bit IT1 in this register is set, bits IE1 are
set by a falling edge on INT1. If bit IT1 is cleared, bits IE1 is set by a low level on
INT1.
I
Timer/Counter 2 External Clock Input
O
Timer/Counter 2 Clock Output
I
Timer/Counter 2 Reload/Capture/Direction Control Input
P3.3
P1.0
P1.1
LED Signal Description
Type
O
Description
Direct Drive LED Output
These pins can be directly connected to the Cathode of standard LEDs without
external current limiting resistors. The typical current of each output can be
programmed by software to 2, 6 or 10 mA. Several outputs can be connected
together to get higher drive capabilities.
Alternate
Function
P3.3
P3.5
P3.6
P3.7
7
7683C–USB–11/07
Table 4-6.
TWI Signal Description
Signal
Name
Type
SCL
I/O
SCL: TWI Serial Clock
SCL output the serial clock to slave peripherals.
SCL input the serial clock from master.
P4.0
SDA
I/O
SDA: TWI Serial Data
SCL is the bidirectional TWI data line.
P4.1
Table 4-7.
Alternate
Function
Description
SPI Signal Description
Signal
Name
Type
SS
I/O
Alternate
Function
Description
SS: SPI Slave Select . This I/O is 5 Volt tolerant
P1.1
MISO: SPI Master Input Slave Output line
MISO
I/O
SCK
I/O
When SPI is in master mode, MISO receives data from the slave peripheral. When
SPI is in slave mode, MISO outputs data to the master controller. This I/O is 5 Volt
tolerant
P1.5
SCK: SPI Serial Clock
SCK outputs clock to the slave peripheral or receive clock from the master.
P1.6
This I/O is 5 Volt tolerant.
MOSI: SPI Master Output Slave Input line
MOSI
I/O
When SPI is in master mode, MOSI outputs data to the slave peripheral. When
SPI is in slave mode, MOSI receives data from the master controller.
P1.7
This I/O is 5 Volt tolerant.
Table 4-8.
Signal
Name
P0[7:0]
P1[7:0]
Ports Signal Description
Type
I/O
I/O
Description
Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that
have 1s written to them float and can be used as high
impedance inputs. To avoid any parasitic current consumption,
Floating P0 inputs must be pulled to VDD or VSS.
Port 1
P1 is an 8-bit bidirectional I/O port with internal pull-ups.
Alternate Function
AD[7:0]
KIN[7:0]
T2
T2EX
ECI
CEX[4:0]
P2[7:0]
8
I/O
Port 2
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
A[15:8]
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
Signal
Name
Type
Description
Alternate Function
LED[3:0]
RxD
TxD
P3[7:0]
I/O
Port 3
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
P4[1:0]
I/O
Port 4
P4 is an 2-bit open port.
Table 4-9.
INT0
INT1
T0
T1
WR
RD
SCL
SDA
Clock Signal Description
Signal
Name
Type
XTAL1
I
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If
an external oscillator is used, its output is connected to this pin.
-
XTAL2
O
Output of the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If
an external oscillator is used, leave XTAL2 unconnected.
-
PLLF
I
PLL Low Pass Filter input
Receives the RC network of the PLL low pass filter (See Figure 5-1 on page 11 ).
-
Table 4-10.
Alternate
Function
USB Signal Description
Signal
Name
Type
D+
I/O
D-
I/O
VREF
O
Table 4-11.
Description
Description
USB Data + signal
Set to high level under reset.
USB Data - signal
Set to low level under reset.
USB Reference Voltage
Connect this pin to D+ using a 1.5 kΩ resistor to use the Detach function.
Alternate
Function
-
-
-
System Signal Description
Signal
Name
Type
AD[7:0]
I/O
A[15:8]
I/O
Description
Multiplexed Address/Data LSB for external access
Data LSB for Slave port access (used for 8-bit and 16-bit modes)
Address Bus MSB for external access
Data MSB for Slave port access (used for 16-bit mode only)
Alternate
Function
P0[7:0]
P2[7:0]
9
7683C–USB–11/07
Signal
Name
Type
RD
I/O
Alternate
Function
Description
Read Signal
Read signal asserted during external data memory read operation.
P3.7
Control input for slave port read access cycles.
WR
I/O
Write Signal
Write signal asserted during external data memory write operation.
P3.6
Control input for slave write access cycles.
RST
I/O
Reset
Holding this pin low for 64 oscillator periods while the oscillator is running resets
the device. The Port pins are driven to their reset conditions when a voltage lower
than VIL is applied, whether or not the oscillator is running.
This pin has an internal pull-up resistor which allows the device to be reset by
connecting a capacitor between this pin and VSS.
Asserting RST when the chip is in Idle mode or Power-down mode returns the chip
to normal operation.
This pin is set to 0 for at least 12 oscillator periods when an internal reset occurs
(hardware watchdog or Power monitor).
ALE
O
Address Latch Enable Output
The falling edge of ALE strobes the address into external latch. This signal is
active only when reading or writing external memory using MOVX instructions.
PSEN
O
Program Strobe Enable / Hardware conditions Input for ISP
-
-
-
Used as input under reset to detect external hardware conditions of ISP mode
External Access Enable
EA
This pin must be held low to force the device to fetch code from external program
memory starting at address 0000h. It is latched during reset and cannot be
dynamically changed during operation.
I
Table 4-12.
-
Power Signal Description
Signal
Name
Type
Description
AVSS
GND
Alternate Ground
AVSS is used to supply the on-chip PLL and the USB PAD.
-
AVDD
PWR
Alternate Supply Voltage
AVDD is used to supply the on-chip PLL and the USB PAD.
-
VSS
GND
Digital Ground
VSS is used to supply the buffer ring and the digital core.
-
VDD
PWR
Alternate
Function
Digital Supply Voltage
VDD is used to supply the buffer ring on all versions of the device.
It is also used to power the on-chip voltage regulator of the Standard versions or
the digital core of the Low Power versions.
-
USB pull-up Controlled Output
VREF
10
O
VREF is used to control the USB D+ 1.5 kΩ pull up.
The Vref output is in high impedance when the bit DETACH is set in the USBCON
register.
-
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
5. Typical Application
5.1
Recommended External components
All the external components described in the figure below must be implemented as close as possible from the microcontroller package.
The following figure represents the typical wiring schematic.
Figure 5-1.
Typical Application
VDD
100nF
VSS
VSS
VSS
AVDD
VDD
1.5K
USB
100nF
4.7µF
VRef
AT83C5134/35/3
VBUS
27R
D+
D+
XTAL1
27R
D-
22pF
DQ
22pF
GND
XTAL2
VSS
VSS
AVSS
560
150pF
VSS
PLLF
820pF
VSS
VSS
VSS
11
7683C–USB–11/07
5.2
PCB Recommandations
Figure 5-2.
USB Pads
Components must be
close to the
microcontroller
Wires must be routed in Parallel and
must be as short as possible
VRef
D+
D-
USB Connector
If possible, isolate D+ and D- signals from other signals
with ground wires
Note:
No sharp angle in above drawing.
Figure 5-3.
USB PLL
AVss PLLF
C2
R
microcontroller
C1
Components must be
close to the
Isolate filter components
with a ground wire
12
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
6. Clock Controller
6.1
Introduction
The AT83C5134/35/36 clock controller is based on an on-chip oscillator feeding an on-chip
Phase Lock Loop (PLL). All the internal clocks to the peripherals and CPU core are generated
by this controller.
The AT83C5134/35/36 X1 and X2 pins are the input and the output of a single-stage on-chip
inverter (see Figure 6-1) that can be configured with off-chip components as a Pierce oscillator
(see Figure 6-2). Value of capacitors and crystal characteristics are detailed in the section “DC
Characteristics”.
The X1 pin can also be used as input for an external 48 MHz clock.
The clock controller outputs three different clocks as shown in Figure 6-1:
• a clock for the CPU core
• a clock for the peripherals which is used to generate the Timers, PCA, WD, and Port
sampling clocks
• a clock for the USB controller
These clocks are enabled or disabled depending on the power reduction mode as detailed in
Section “Power Management”, page 135.
Figure 6-1.
Oscillator Block Diagram
÷2
0
Peripheral
Clock
1
CPU Core
Clock
PLL
X1
X2
IDL
CKCON.0
PCON.0
0
1
USB
Clock
X2
6.2
EXT48
PD
PLLCON.2
PCON.1
Oscillator
Two clock sources are available for CPU:
• Crystal oscillator on X1 and X2 pins: Up to 32 MHz
• External 48 MHz clock on X1 pin
13
7683C–USB–11/07
In order to optimize the power consumption, the oscillator inverter is inactive when the PLL output is not selected for the USB device.
Figure 6-2.
Crystal Connection
X1
C1
Q
C2
VSS
6.3
6.3.1
X2
PLL
PLL Description
The AT83C5134/35/36 PLL is used to generate internal high frequency clock (the USB Clock)
synchronized with an external low-frequency (the Peripheral Clock). The PLL clock is used to
generate the USB interface clock. Figure 6-3 shows the internal structure of the PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. This block makes the
comparison between the reference clock coming from the N divider and the reverse clock coming from the R divider and generates some pulses on the Up or Down signal depending on the
edge position of the reverse clock. The PLLEN bit in PLLCON register is used to enable the
clock generation. When the PLL is locked, the bit PLOCK in PLLCON register (see Figure 6-3) is
set.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by injecting or extracting charges from the external filter connected on PLLF pin (see Figure 6-4). Value
of the filter components are detailed in the Section “DC Characteristics”.
The VCO block is the Voltage Controlled Oscillator controlled by the voltage VREF produced by
the charge pump. It generates a square wave signal: the PLL clock.
Figure 6-3.
PLL Block Diagram and Symbol
PLLF
PLLCON.1
PLLEN
N divider
OSC
CLOCK
N3:0
Up
PFLD
CHP
Vref
VCO
USB Clock
Down
PLOCK
PLLCON.0
R divider
R3:0
OSCclk × ( R + 1 )
USBclk = ----------------------------------------------N+1
14
USB
CLOCK
USB Clock Symbol
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
Figure 6-4.
PLL Filter Connection
PLLF
R
C2
C1
VSS
VSS
The typical values are: R = 560 Ω, C1 = 820 pf, C2 = 150 pF.
6.3.2
PLL Programming
The PLL is programmed using the flow shown in Figure 6-5. As soon as clock generation is
enabled user must wait until the lock indicator is set to ensure the clock output is stable.
Figure 6-5.
PLL Programming Flow
PLL
Programming
Configure Dividers
N3:0 = xxxxb
R3:0 = xxxxb
Enable PLL
PLLEN = 1
PLL Locked?
LOCK = 1?
6.3.3
Divider Values
To generate a 48 MHz clock using the PLL, the divider values have to be configured following
the oscillator frequency. The typical divider values are shown in Table 6-1.
Table 6-1.
Typical Divider Values
Oscillator Frequency
R+1
N+1
PLLDIV
3 MHz
16
1
F0h
6 MHz
8
1
70h
8 MHz
6
1
50h
12 MHz
4
1
30h
16 MHz
3
1
20h
18 MHz
8
3
72h
20 MHz
12
5
B4h
24 MHz
2
1
10h
15
7683C–USB–11/07
6.4
Oscillator Frequency
R+1
N+1
PLLDIV
32 MHz
3
2
21h
40 MHz
12
10
B9h
Registers
Table 6-2.
CKCON0 (S:8Fh)
Clock Control Register 0
7
6
5
4
3
2
1
0
TWIX2
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
Bit Number
Bit
Mnemonic
Description
TWIX2
TWI Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit
has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
WDX2
Watchdog Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit
has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
PCAX2
Programmable Counter Array Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit
has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
SIX2
Enhanced UART Clock (Mode 0 and 2)
This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit
has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
T2X2
Timer2 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit
has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
T1X2
Timer1 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit
has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
1
T0X2
Timer0 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit
has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
0
X2
7
6
5
4
3
2
System Clock Control bit
Clear to select 12 clock periods per machine cycle (STD mode, FCPU = FPER = FOSC/2).
Set to select 6 clock periods per machine cycle (X2 mode, FCPU = FPER = FOSC).
Reset Value = 0000 0000b
16
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
Table 6-3.
CKCON1 (S:AFh)
Clock Control Register 1
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
SPIX2
Bit Number
Bit
Mnemonic
Description
7-1
-
0
SPIX2
Reserved
The value read from this bit is always 0. Do not set this bit.
SPI Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit
has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Reset Value = 0000 0000b
Table 6-4.
PLLCON (S:A3h)
PLL Control Register
7
6
5
4
3
2
1
0
-
-
-
-
-
EXT48
PLLEN
PLOCK
Bit Number
Bit
Mnemonic
Description
7-3
-
2
EXT48
External 48 MHz Enable Bit
Set this bit to bypass the PLL and disable the crystal oscillator.
Clear this bit to select the PLL output as USB clock and to enable the crystal oscillator.
1
PLLEN
PLL Enable Bit
Set to enable the PLL.
Clear to disable the PLL.
0
PLOCK
PLL Lock Indicator
Set by hardware when PLL is locked.
Clear by hardware when PLL is unlocked.
Reserved
The value read from this bit is always 0. Do not set this bit.
Reset Value = 0000 0000b
Table 6-5.
PLLDIV (S:A4h)
PLL Divider Register
7
6
5
4
3
2
1
0
R3
R2
R1
R0
N3
N2
N1
N0
Bit Number
Bit
Mnemonic
Description
7-4
R3:0
PLL R Divider Bits
3-0
N3:0
PLL N Divider Bits
Reset Value = 0000 0000
17
7683C–USB–11/07
7. SFR Mapping
The Special Function Registers (SFRs) of the AT83C5134/35/36 fall into the following
categories:
• C51 core registers: ACC, B, DPH, DPL, PSW, SP
• I/O port registers: P0, P1, P2, P3, P4
• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L,
RCAP2H
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON
• PCA (Programmable Counter Array) registers: CCON, CMOD, CCAPMx, CL, CH, CCAPxH,
CCAPxL (x: 0 to 4)
• Power and clock control registers: PCON
• Hardware Watchdog Timer registers: WDTRST, WDTPRG
• Interrupt system registers: IEN0, IPL0, IPH0, IEN1, IPL1, IPH1
• Keyboard Interface registers: KBE, KBF, KBLS
• LED register: LEDCON
• Two Wire Interface (TWI) registers: SSCON, SSCS, SSDAT, SSADR
• Serial Port Interface (SPI) registers: SPCON, SPSTA, SPDAT
• USB registers: Uxxx (17 registers)
• PLL registers: PLLCON, PLLDIV
• BRG (Baud Rate Generator) registers: BRL, BDRCON
• Others: AUXR, AUXR1, CKCON0, CKCON1
18
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
The table below shows all SFRs with their address and their reset value.
Table 7-1.
SFR Descriptions
Bit
Addressable
Non-Bit Addressable
0/8
1/9
F8h
UEPINT
0000 0000
CH
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
0000 0000
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
F0h
B
0000 0000
0000 0000
E8h
E0h
D8h
A0h
98h
90h
88h
80h
Note:
6/E
7/F
FFh
F7h
CL
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
0000 0000
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
UBYCTLX
0000 0000
UBYCTHX
0000 0000
EFh
E7h
CMOD
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
00XX X000
X000 0000
X000 0000
X000 0000
X000 0000
X000 0000
UEPCONX
1000 0000
UEPRST
0000 0000
TL2
0000 0000
TH2
0000 0000
UEPSTAX
0000 0000
UEPDATX
0000 0000
CFh
UEPNUM
0000 0000
C7h
T2CON
0000 0000
A8h
5/D
CCON
C8h
B0h
4/C
00X0 0000
PSW
0000 0000
B8h
3/B
LEDCON
ACC
0000 0000
D0h
C0h
2/A
T2MOD
XXXX XX00
P4
XXXX 1111
DFh
D7h
RCAP2L
0000 0000
RCAP2H
0000 0000
UEPIEN
0000 0000
SPCON
SPSTA
SPDAT
0001 0100
0000 0000
XXXX XXXX
USBADDR
1000 0000
UFNUMH
0000 0000
USBCON
0000 0000
USBINT
0000 0000
USBIEN
0000 0000
IPL0
SADEN
X000 000
0000 0000
UFNUML
0000 0000
P3
IEN1
X0XX X000
IPL1
IPH1
IPH0
X0XX X000
X0XX X000
X000 0000
1111 1111
BFh
IEN0
SADDR
CKCON1
0000 0000
0000 0000
0000 0000
P2
AUXR1
1111 1111
XXXX X0X0
PLLCON
XXXX XX00
PLLDIV
0000 0000
WDTRST
WDTPRG
XXXX XXXX
XXXX X000
SCON
SBUF
BRL
BDRCON
KBLS
KBE
KBF
0000 0000
XXXX XXXX
0000 0000
XXX0 0000
0000 0000
0000 0000
0000 0000
P1
SSCON
SSCS
SSDAT
SSADR
1111 1111
0000 0000
1111 1000
1111 1111
1111 1110
AUXR
XX0X 0000
TCON
TMOD
TL0
TL1
TH0
TH1
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
P0
1111 1111
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
0/8
1/9
2/A
3/B
6/E
A7h
97h
CKCON0
0000 0000
PCON
5/D
AFh
9Fh
00X1 0000
4/C
B7h
8Fh
87h
7/F
1. FCON access is reserved for the Flash API and ISP software.
Reserved
The Special Function Registers (SFRs) of the AT89C5131 fall into the following categories:
19
7683C–USB–11/07
Table 7-2.
C51 Core SFRs
Mnemonic
Add
Name
ACC
E0h
Accumulator
B
F0h
B Register
PSW
D0h
Program Status
Word
SP
81h
DPL
82h
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Stack Pointer
LSB of SPX
Data Pointer Low
byte
LSB of DPTR
DPH
83h
Data Pointer High
byte
MSB of DPTR
Table 7-3.
Table 7-4.
I/O Port SFRs
Mnemonic
Add
Name
P0
80h
Port 0
P1
90h
Port 1
P2
A0h
Port 2
P3
B0h
Port 3
P4
C0h
Port 4 (2bits)
Timer SFR’s
Mnemonic
Add
Name
TH0
8Ch
Timer/Counter 0 High byte
TL0
8Ah
Timer/Counter 0 Low byte
TH1
8Dh
Timer/Counter 1 High byte
TL1
8Bh
Timer/Counter 1 Low byte
TH2
CDh
Timer/Counter 2 High byte
TL2
CCh
Timer/Counter 2 Low byte
TCON
88h
TMOD
20
7
6
5
4
3
2
1
0
Timer/Counter 0 and 1
control
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
89h
Timer/Counter 0 and 1
Modes
GATE1
C/T1#
M11
M01
GATE0
C/T0#
M10
M00
T2CON
C8h
Timer/Counter 2 control
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
T2MOD
C9h
Timer/Counter 2 Mode
T2OE
DCEN
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
Table 7-4.
Timer SFR’s (Continued)
Mnemonic
Add
Name
RCAP2H
CBh
Timer/Counter 2
Reload/Capture High byte
RCAP2L
CAh
Timer/Counter 2
Reload/Capture Low byte
WDTRST
A6h
WatchDog Timer Reset
WDTPRG
A7h
WatchDog Timer Program
Table 7-5.
Add
Name
SCON
98h
Serial Control
SBUF
99h
Serial Data Buffer
SADEN
B9h
Slave Address Mask
SADDR
A9h
Slave Address
5
4
3
2
1
0
S2
S1
S0
7
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
7
6
5
4
3
2
1
0
BRR
TBCK
RBCK
SPD
SRC
Baud Rate Generator SFR’s
Mnemonic
Add
Name
BRL
9Ah
Baud Rate Reload
BDRCON
9Bh
Baud Rate Control
Table 7-7.
6
Serial I/O Port SFR’s
Mnemonic
Table 7-6.
7
PCA SFR’s
Mnemonic
Add
Name
CCON
D8h
PCA Timer/Counter Control
CMOD
D9h
PCA Timer/Counter Mode
CL
E9h
PCA Timer/Counter Low byte
CH
F9h
PCA Timer/Counter High byte
CCAPM
1
DAh
PCA Timer/Counter Mode 0
ECOM0
CAPP0
CAPN0
CCAPM
2
DBh
PCA Timer/Counter Mode 1
ECOM1
CAPP1
CAPN1
DCh
PCA Timer/Counter Mode 2
ECOM2
CAPP2
DDh
PCA Timer/Counter Mode 3
ECOM3
DEh
PCA Timer/Counter Mode 4
ECOM4
7
6
CF
CR
CIDL
WDTE
5
4
3
2
1
0
CCF4
CCF3
CCF2
CCF1
CCF0
CPS1
CPS0
ECF
MAT0
TOG0
PWM0
ECCF0
MAT1
TOG1
PWM1
ECCF1
CAPN2
MAT2
TOG2
PWM2
ECCF2
CAPP3
CAPN3
MAT3
TOG3
PWM3
ECCF3
CAPP4
CAPN4
MAT4
TOG4
PWM4
ECCF4
CCAPM
0
CCAPM
3
CCAPM
4
21
7683C–USB–11/07
Table 7-7.
PCA SFR’s
Mnemonic
Add
Name
CCAP0
H
PCA Compare Capture Module 0
H
CCAP1
H
FAh
CCAP2
H
FCh
CCAP3
H
FBh
FDh
FEh
CCAP4
H
7
6
5
4
3
2
1
0
PCA Compare Capture Module 1
H
CCAP0H7 CCAP0H6 CCAP0H5 CCAP0H4 CCAP0H3 CCAP0H2 CCAP0H1 CCAP0H0
PCA Compare Capture Module 2
H
CCAP2H7 CCAP2H6 CCAP2H5 CCAP2H4 CCAP2H3 CCAP2H2 CCAP2H1 CCAP2H0
PCA Compare Capture Module 3
H
CCAP1H7 CCAP1H6 CCAP1H5 CCAP1H4 CCAP1H3 CCAP1H2 CCAP1H1 CCAP1H0
CCAP3H7 CCAP3H6 CCAP3H5 CCAP3H4 CCAP3H3 CCAP3H2 CCAP3H1 CCAP3H0
CCAP4H7 CCAP4H6 CCAP4H5 CCAP4H4 CCAP4H3 CCAP4H2 CCAP4H1 CCAP4H0
PCA Compare Capture Module 4
H
PCA Compare Capture Module 0
L
CCAP0L EAh
CCAP1L EBh
CCAP2L ECh
CCAP3L EDh
CCAP4L EEh
PCA Compare Capture Module 1
L
CCAP0L7
CCAP0L6 CCAP0L5
CCAP0L4
CCAP0L3
CCAP0L2
CCAP0L1
CCAP0L0
PCA Compare Capture Module 2
L
CCAP1L7
CCAP1L6 CCAP1L5
CCAP1L4
CCAP1L3
CCAP1L2
CCAP1L1
CCAP1L0
CCAP2L7
CCAP2L6 CCAP2L5
CCAP2L4
CCAP2L3
CCAP2L2
CCAP2L1
CCAP2L0
CCAP3L7
CCAP3L6 CCAP3L5
CCAP3L4
CCAP3L3
CCAP3L2
CCAP3L1
CCAP3L0
CCAP4L7
CCAP4L6 CCAP4L5
CCAP4L4
CCAP4L3
CCAP4L2
CCAP4L1
CCAP4L0
PCA Compare Capture Module 3
L
PCA Compare Capture Module 4
L
Table 7-8.
Interrupt SFR’s
Mnemonic
Add
Name
IEN0
A8h
Interrupt Enable Control 0
IEN1
B1h
Interrupt Enable Control 1
EUSB
IPL0
B8h
Interrupt Priority Control Low 0
PPCL
PT2L
PSL
IPH0
B7h
Interrupt Priority Control High 0
PPCH
PT2H
PSH
IPL1
B2h
Interrupt Priority Control Low 1
IPH1
B3h
Interrupt Priority Control High 1
Table 7-9.
22
6
5
4
3
2
1
0
EA
EC
ET2
ES
ET1
EX1
ET0
EX0
ESPI
ETWI
EKB
PT1L
PX1L
PT0L
PX0L
PT1H
PX1H
PT0H
PX0H
PUSBL
PSPIL
PTWIL
PKBL
PUSBH
PSPIH
PTWIH
PKBH
PLL SFRs
Mnemonic
Add
Name
PLLCON
A3h
PLL Control
PLLDIV
A4h
PLL Divider
Table 7-10.
7
7
6
R3
5
R2
4
R1
3
R0
N3
2
1
0
EXT48
PLLEN
PLOCK
N2
N1
N0
Keyboard SFRs
Mnemonic
Add
Name
7
6
5
4
3
2
1
0
KBF
9Eh
Keyboard Flag
Register
KBF7
KBF6
KBF5
KBF4
KBF3
KBF2
KBF1
KBF0
KBE
9Dh
Keyboard Input Enable
Register
KBE7
KBE6
KBE5
KBE4
KBE3
KBE2
KBE1
KBE0
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
Table 7-10.
Keyboard SFRs
Mnemonic
Add
Name
KBLS
9Ch
Keyboard Level
Selector Register
Table 7-11.
7
6
5
4
3
2
1
0
KBLS7
KBLS6
KBLS5
KBLS4
KBLS3
KBLS2
KBLS1
KBLS0
7
6
5
4
3
2
1
0
TWI SFRs
Mnemonic
Add
Name
SSCON
93h
Synchronous Serial
Control
CR2
SSIE
STA
STO
SI
AA
CR1
CR0
SSCS
94h
Synchronous Serial
Control-Status
SC4
SC3
SC2
SC1
SC0
-
-
-
SSDAT
95h
Synchronous Serial
Data
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
SSADR
96h
Synchronous Serial
Address
A7
A6
A5
A4
A3
A2
A1
A0
7
6
5
4
3
2
1
0
Table 7-12.
SPI SFRs
Mnemonic
Add
Name
SPCON
C3h
Serial Peripheral
Control
SPR2
SPEN
SSDIS
MSTR
CPOL
CPHA
SPR1
SPR0
SPSTA
C4h
Serial Peripheral
Status-Control
SPIF
WCOL
SSERR
MODF
-
-
-
-
SPDAT
C5h
Serial Peripheral Data
R7
R6
R5
R4
R3
R2
R1
R0
Table 7-13.
USB SFR’s
Mnemonic
Add
Name
7
6
5
4
3
2
1
0
USBCON
BCh
USB Global Control
USBE
SUSPCLK
SDRMWU
P
DETACH
UPRSM
RMWUPE
CONFG
FADDEN
USBADDR
C6h
USB Address
FEN
UADD6
UADD5
UADD4
UADD3
UADD2
UADD1
UADD0
USBINT
BDh
USB Global Interrupt
-
-
WUPCPU
EORINT
SOFINT
-
-
SPINT
USBIEN
BEh
USB Global Interrupt
Enable
-
-
EWUPCP
U
EEORINT
ESOFINT
-
-
ESPINT
UEPNUM
C7h
USB Endpoint Number
-
-
-
-
EPNUM3
EPNUM2
EPNUM1
EPNUM0
UEPCONX
D4h
USB Endpoint X Control
EPEN
-
-
-
DTGL
EPDIR
EPTYPE1
EPTYPE0
UEPSTAX
CEh
USB Endpoint X Status
DIR
RXOUTB1
STALLRQ
TXRDY
STLCRC
RXSETUP
RXOUTB0
TXCMP
UEPRST
D5h
USB Endpoint Reset
-
-
EP5RST
EP4RST
EP3RST
EP2RST
EP1RST
EP0RST
UEPINT
F8h
USB Endpoint Interrupt
-
-
EP5INT
EP4INT
EP3INT
EP2INT
EP1INT
EP0INT
UEPIEN
C2h
USB Endpoint Interrupt
Enable
-
-
EP5INTE
EP4INTE
EP3INTE
EP2INTE
EP1INTE
EP0INTE
UEPDATX
CFh
USB Endpoint X FIFO
Data
FDAT7
FDAT6
FDAT5
FDAT4
FDAT3
FDAT2
FDAT1
FDAT0
23
7683C–USB–11/07
Table 7-13.
USB SFR’s
Mnemonic
Add
Name
7
6
5
4
3
2
1
0
UBYCTLX
E2h
USB Byte Counter Low
(EP X)
BYCT7
BYCT6
BYCT5
BYCT4
BYCT3
BYCT2
BYCT1
BYCT0
UBYCTHX
E3h
USB Byte Counter High
(EP X)
-
-
-
-
-
BYCT10
BYCT9
BYCT8
UFNUML
BAh
USB Frame Number
Low
FNUM7
FNUM6
FNUM5
FNUM4
FNUM3
FNUM2
FNUM1
FNUM0
UFNUMH
BBh
USB Frame Number
High
-
-
CRCOK
CRCERR
-
FNUM10
FNUM9
FNUM8
Table 7-14.
24
Other SFR’s
Mnemonic
Add
Name
7
6
5
4
3
2
1
0
PCON
87h
Power Control
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
AUXR
8Eh
Auxiliary Register 0
DPU
-
M0
-
XRS1
XRS2
EXTRAM
A0
AUXR1
A2h
Auxiliary Register 1
-
-
ENBOOT
-
GF3
-
-
DPS
CKCON0
8Fh
Clock Control 0
TWIX2
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
CKCON1
AFh
Clock Control 1
-
-
-
-
-
-
-
SPIX2
LEDCON
F1h
LED Control
LED3
LED2
LED1
LED0
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
8. Program/Code Memory
The AT83C5134/35/36 implement 16 or 32 Kbytes of on-chip program/code memory. Figure 8-1
shows the split of internal and external program/code memory spaces depending on the
product.
Figure 8-1.
Program/Code Memory Organization
FFFFh
FFFFh
32 Kbytes
External Code
48 Kbytes
External Code
8000h
7FFFh
4000h
3FFFh
32 Kbytes
ROM
16 Kbytes
ROM
0000h
0000h
AT83C5135
Note:
8.1
8.1.1
AT83C5136
If the program executes exclusively from on-chip code memory (not from external memory),
beware of executing code from the upper byte of on-chip memory and thereby disrupting I/O Ports
0 and 2 due to external prefetch. Fetching code constant from this location does not affect Ports 0
and 2.
External Code Memory Access
Memory Interface
The external memory interface comprises the external bus (Port 0 and Port 2) as well as the bus
control signals (PSEN, and ALE).
Figure 8-2 shows the structure of the external address bus. P0 carries address A7:0 while P2
carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 8-1 describes the external memory interface signals.
Figure 8-2.
External Code Memory Interface Structure
Flash
EPROM
AT89C5131
A15:8
P2
A15:8
ALE
P0
AD7:0
Latch
A7:0
A7:0
D7:0
PSEN
OE
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7683C–USB–11/07
Table 8-1.
8.1.2
External Data Memory Interface Signals
Signal
Name
Type
Alternate
Function
A15:8
O
Address Lines
Upper address lines for the external bus.
P2.7:0
AD7:0
I/O
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
P0.7:0
ALE
O
Address Latch Enable
ALE signals indicates that valid address information are available on lines AD7:0.
-
PSEN
O
Program Store Enable Output
This signal is active low during external code fetch or external code read (MOVC
instruction).
-
Description
External Bus Cycles
This section describes the bus cycles the AT83C5134/35/36 executes to fetch code (see
Figure 8-3) in the external program/code memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock periods in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2
mode (see the clock Section).
For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized form and
do not provide precise timing information.
Figure 8-3.
External Code Fetch Waveforms
CPU Clock
ALE
PSEN
P0 D7:0
P2 PCH
26
PCL
D7:0
PCH
PCL
D7:0
PCH
AT83C5134/35/36
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AT83C5134/35/36
9. AT89C5131 ROM
9.1
ROM Structure
The AT89C5131 ROM memory is divided in two different arrays:
• the code array: 16-32 Kbytes.
• the configuration byte:1 byte.
9.1.1
Hardware Configuration Byte
The configuration byte sets the starting microcontroller options and the security levels.
The starting default options are X1 mode, Oscillator A.
Table 9-1.
Hardware Security Byte (HSB)
HSB (S:EFh)
Power configuration Register
7
6
5
4
3
2
1
0
-
-
OSCON1
OSCON0
-
-
LB1
LB0
Bit
Bit
Number
Mnemonic
7
-
Reserved
6
-
Reserved
Description
Oscillator Control Bits
These two bits are used to control the oscillator in order to reduce consumption.
OSCON1 OSCON0 Description
1 1 The oscillator is configured to run from 0 to 32 MHz
1 0 The oscillator is configured to run from 0 to 16 MHz
0 1 The oscillator is configured to run from 0 to 8 MHz
0 0 This configuration shouldn’t be set
5-4
OSCON1-0
3
-
Reserved
2
-
Reserved
1-0
LB1-0
User Program Lock Bits
See Table 9-2 on page 28
HSB = xxxx xx11b
9.2
ROM Lock System
The program Lock system, when programmed, protects the on-chip program against software
piracy.
27
7683C–USB–11/07
9.2.1
Program ROM lock Bits
The lock bits when programmed according to Table 9-2 will provide different level of protection
for the on-chip code and data.
Table 9-2.
Program Lock bits
Program Lock Bits
Protection Description
Security
level
LB1
LB0
1
U
U
No program lock feature enabled.
3
P
U
Reading ROM data from programmer is disabled.
U: unprogrammed
P: programmed
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10. Stacked EEPROM
10.1
Overview
The AT83C5134/35/36 features a stacked 2-wire serial data EEPROM. The data EEPROM
allows to save from 512 Byte for AT24C04 version up to 32 Kbytes for AT24C256 version. The
EEPROM is internally connected to the microcontroller on SDA and SCL pins.
10.2
Protocol
In order to access this memory, it is necessary to use software subroutines according to the
AT 24Cx x da tashee t. Never thele ss , beca use the in te rnal pul l-u p re sis tors of the
AT83C5134/35/36 is quite high (around 100KΩ), the protocol should be slowed in order to be
sure that the SDA pin can rise to the high level before reading it.
Another solution to keep the access to the EEPROM in specification is to work with a software
pull-up.
Using a software pull-up, consists of forcing a low level at the output pin of the microcontroller
before configuring it as an input (high level).
The C51 the ports are “quasi-bidirectional” ports. It means that the ports can be configured as
output low or as input high. In case a port is configured as an output low, it can sink a current
and all internal pull-ups are disconnected. In case a port is configured as an input high, it is
pulled up with a strong pull-up (a few hundreds Ohms resistor) for 2 clock periods. Then, if the
port is externally connected to a low level, it is only kept high with a weak pull up (around
100KΩ), and if not, the high level is latched high thanks to a medium pull (around 10kΩ).
Thus, when the port is configured as an input, and when this input has been read at a low level,
there is a pull-up of around 100KΩ, which is quite high, to quickly load the SDA capacitance. So
in order to help the reading of a high level just after the reading of a low level, it is possible to
force a transition of the SDA port from an input state (1), to an output low state (0), followed by a
new transition from this output low state to input state; In this case, the high pull-up has been
replaced with a low pull-up which warranties a good reading of the data.
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11. On-chip Expanded RAM (ERAM)
The AT83C5134/35/36 provides additional Bytes of random access memory (RAM) space for
increased data parameters handling and high level language usage.
AT83C5134/35/36 devices have an expanded RAM in the external data space; maximum size
and location are described in Table 11-1.
Table 11-1.
Description of Expanded RAM
Address
Part Number
ERAM Size
Start
End
AT83C5134/35/36
1024
00h
3FFh
The AT83C5134/35/36 has on-chip data memory which is mapped into the following four separate segments.
1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly
addressable.
2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only.
3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly addressable only.
4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the
EXTRAM bit cleared in the AUXR register (see Table 11-1)
The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128
bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same
address space as the SFR. That means they have the same address, but are physically separate from SFR space.
Figure 11-1. Internal and External Data Memory Address
0FFh or 3FFh(*)
0FFh
0FFh
Upper
128 bytes
Internal
RAM
indirect accesses
ERAM
80h
0FFFFh
Special
Function
Register
direct accesses
External
Data
Memory
80h
7Fh
Lower
128 bytes
Internal
RAM
direct or indirect
accesses
00
00
00FFh up to 03FFh (*)
0000
(*) Depends on XRS1..0
When an instruction accesses an internal location above address 7Fh, the CPU knows whether
the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used
in the instruction.
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AT83C5134/35/36
• Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data,
accesses the SFR at location 0A0h (which is P2).
• Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For
example: MOV atR0, # data where R0 contains 0A0h, accesses the data byte at address
0A0h, rather than P2 (whose address is 0A0h).
• The ERAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and
MOVX instructions. This part of memory which is physically located on-chip, logically
occupies the first bytes of external data memory. The bits XRS0 and XRS1 are used to hide a
part of the available ERAM as explained in Table 11-1. This can be useful if external
peripherals are mapped at addresses already used by the internal ERAM.
• With EXTRAM = 0, the ERAM is indirectly addressed, using the MOVX instruction in
combination with any of the registers R0, R1 of the selected bank or DPTR. An access to
ERAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM =
0, MOVX atR0, # data where R0 contains 0A0H, accesses the ERAM at address 0A0H rather
than external memory. An access to external data memory locations higher than the
accessible size of the ERAM will be performed with the MOVX DPTR instructions in the same
way as in the standard 80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7
as write and read timing signals. Accesses to ERAM above 0FFH can only be done by the
use of DPTR.
• With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51.
MOVX at Ri will provide an eight-bit address multiplexed with data on Port0 and any output
port pins can be used to output higher order address bits. This is to provide the external
paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the highorder eight address bits (the contents of DPH) while Port0 multiplexes the low-order eight
address bits (DPL) with data. MOVX at Ri and MOVX @DPTR will generate either read or
write signals on P3.6 (WR) and P3.7 (RD).
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM)
internal data memory. The stack may not be located in the ERAM.
The M0 bit allows to stretch the ERAM timings; if M0 is set, the read and write pulses are
extended from 6 to 30 clock periods. This is useful to access external slow peripherals.
Table 11-2.
AUXR Register
AUXR - Auxiliary Register (8Eh)
7
6
5
4
3
2
1
0
DPU
-
M0
-
XRS1
XRS0
EXTRAM
AO
Bit
Bit
Number
Mnemonic
7
DPU
6
-
Description
Disable Weak Pull Up
Cleared to enabled weak pull up on standard Ports.
Set to disable weak pull up on standard Ports.
Reserved
The value read from this bit is indeterminate. Do not set this bit
Pulse length
5
M0
Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock periods
(default).
Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods.
31
7683C–USB–11/07
Bit
Bit
Number
Mnemonic
4
-
3
XRS1
2
1
XRS0
EXTRAM
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit
ERAM Size
XRS1XRS0
0
0
ERAM size
256 bytes
0
1
512 bytes
1
0
768 bytes
1
1
1024 bytes (default)
EXTRAM bit
Cleared to access internal ERAM using MOVX at Ri at DPTR.
Set to access external memory.
0
AO
ALE Output bit
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2
mode is used) (default).
Set, ALE is active only when a MOVX or MOVC instruction is used.
Reset Value = 0X0X 1100b
Not bit addressable
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12. Timer 2
The Timer 2 in the AT83C5134/35/36 is the standard C52 Timer 2. It is a 16-bit timer/counter:
the count is maintained by two cascaded eight-bit timer registers, TH2 and TL2. It is controlled
by T2CON (Table 12-1) and T2MOD (Table 12-2) registers. Timer 2 operation is similar to Timer
0 and Timer 1. C/T2 selects FOSC/12 (timer operation) or external pin T2 (counter operation) as
the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input.
Timer 2 has 3 operating modes: capture, auto reload and Baud Rate Generator. These modes
are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON).
Refer to the Atmel 8-bit microcontroller hardware documentation for the description of Capture
and Baud Rate Generator Modes.
Timer 2 includes the following enhancements:
• Auto-reload mode with up or down counter
• Programmable Clock-output
12.1
Auto-reload Mode
The Auto-reload mode configures Timer 2 as a 16-bit timer or event counter with automatic
reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (refer to the Atmel 8-bit
microcontroller hardware description). If DCEN bit is set, Timer 2 acts as an Up/down
timer/counter as shown in Figure 12-1. In this mode the T2EX pin controls the direction of count.
When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag
and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and
RCAP2L registers to be loaded into the timer registers TH2 and TL2.
When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the timer
registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers.
The EXF2 bit toggles when Timer 2 overflows or underflows according to the direction of the
count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution.
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Figure 12-1. Auto-reload Mode Up/Down Counter (DCEN = 1)
FCLK PERIPH
:6
0
1
T2
C/T2
TR2
T2CON
T2CON
(DOWN COUNTING RELOAD VALUE) T2EX:
FFh
(8-bit)
FFh
(8-bit)
if DCEN = 1, 1 = UP
if DCEN = 1, 0 = DOWN
if DCEN = 0, up counting
TOGGLE T2CON
EXF2
TL2
(8-bit)
TH2
(8-bit)
TF2
T2CON
RCAP2L
(8-bit)
Timer 2
INTERRUPT
RCAP2H
(8-bit)
(UP COUNTING RELOAD VALUE)
12.2
Programmable Clock Output
In the Clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock generator
(See Figure 12-2). The input clock increments TL2 at frequency FCLK PERIPH/2. The timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L
registers are loaded into TH2 and TL2. In this mode, Timer 2 overflows do not generate interrupts. The following formula gives the Clock-out frequency as a function of the system oscillator
frequency and the value in the RCAP2H and RCAP2L registers
F CLKPERIPH
Clock – OutFrequency = ---------------------------------------------------------------------------------------4 × ( 65536 – RCAP2H ⁄ RCAP2L )
For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz
(FCLK PERIPH/216) to 4 MHz (FCLK PERIPH/4). The generated clock signal is brought out to T2 pin
(P1.0).
Timer 2 is programmed for the Clock-out mode as follows:
• Set T2OE bit in T2MOD register.
• Clear C/T2 bit in T2CON register.
• Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L
registers.
• Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value
or a different one depending on the application.
• To start the timer, set TR2 run control bit in T2CON register.
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AT83C5134/35/36
It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. For
this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers.
Figure 12-2. Clock-out Mode C/T2 = 0
FCLK PERIPH
:6
TR2
T2CON
TL2
(8-bit)
TH2
(8-bit)
OVERFLOW
RCAP2L
(8-bit)
RCAP2H
(8-bit)
Toggle
T2
Q
D
T2OE
T2MOD
T2EX
EXF2
EXEN2
T2CON
Timer 2
INTERRUPT
T2CON
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7683C–USB–11/07
Table 12-1.
T2CON Register
T2CON - Timer 2 Control Register (C8h)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Bit
Number
Mnemonic
7
TF2
Description
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.
6
EXF2
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2 = 1.
When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt
is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter
mode (DCEN = 1).
5
RCLK
Receive Clock bit
Cleared to use Timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.
4
TCLK
Transmit Clock bit
Cleared to use Timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3
EXEN2
2
TR2
1
0
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for Timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is detected, if
Timer 2 is not used to clock the serial port.
Timer 2 Run control bit
Cleared to turn off Timer 2.
Set to turn on Timer 2.
C/T2#
Timer/Counter 2 select bit
Cleared for timer operation (input from internal clock system: FCLK PERIPH).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for
clock out mode.
CP/RL2#
Timer 2 Capture/Reload bit
If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to Auto-reload on
Timer 2 overflow.
Cleared to Auto-reload on Timer 2 overflows or negative transitions on T2EX pin if
EXEN2 = 1.
Set to capture on negative transitions on T2EX pin if EXEN2 = 1.
Reset Value = 0000 0000b
Bit addressable
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AT83C5134/35/36
Table 12-2.
T2MOD Register
T2MOD - Timer 2 Mode Control Register (C9h)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
T2OE
DCEN
Bit
Bit
Number
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
T2OE
Timer 2 Output Enable bit
Cleared to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.
0
DCEN
Down Counter Enable bit
Cleared to disable Timer 2 as up/down counter.
Set to enable Timer 2 as up/down counter.
Description
Reset Value = xxxx xx00b
Not bit addressable
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13. Programmable Counter Array (PCA)
The PCA provides more timing capabilities with less CPU intervention than the standard
timer/counters. Its advantages include reduced software overhead and improved accuracy. The
PCA consists of a dedicated timer/counter which serves as the time base for an array of five
compare/capture modules. Its clock input can be programmed to count any one of the following
signals:
÷6
• Peripheral clock frequency (FCLK PERIPH) ÷ 2
• Peripheral clock frequency (FCLK PERIPH)
• Timer 0 overflow
• External input on ECI (P1.2)
Each compare/capture modules can be programmed in any one of the following modes:
• rising and/or falling edge capture,
• software timer
• high-speed output, or
• pulse width modulator
Module 4 can also be programmed as a watchdog timer (see Section "PCA Watchdog Timer",
page 48).
When the compare/capture modules are programmed in the capture mode, software timer, or
high speed output mode, an interrupt can be generated when the module executes its function.
All five modules plus the PCA timer overflow share one interrupt vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins
are listed below. If the port pin is not used for the PCA, it can still be used for standard I/O.
PCA Component
External I/O Pin
16-bit Counter
P1.2/ECI
16-bit Module 0
P1.3/CEX0
16-bit Module 1
P1.4/CEX1
16-bit Module 2
P1.5/CEX2
16-bit Module 3
P1.6/CEX3
16-bit Module 4
P1.7/CEX4
The PCA timer is a common time base for all five modules (see Figure 13-1). The timer count
source is determined from the CPS1 and CPS0 bits in the CMOD register (Table 13-1) and can
be programmed to run at:
• 1/6 the peripheral clock frequency (FCLK PERIPH).
• 1/2 the peripheral clock frequency (FCLK PERIPH).
• The Timer 0 overflow
• The input on the ECI pin (P1.2)
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AT83C5134/35/36
Figure 13-1. PCA Timer/Counter
To PCA
modules
FCLK PERIPH/6
overflow
FCLK PERIPH/2
CH
T0 OVF
It
CL
16 Bit Up Counter
P1.2
CIDL
WDTE
CF
CR
CPS1
CPS0
ECF
CMOD
0xD9
CCF2
CCF1
CCF0
CCON
0xD8
Idle
Table 13-1.
CCF4 CCF3
CMOD Register
CMOD - PCA Counter Mode Register (D9h)
7
6
5
4
3
2
1
0
CIDL
WDTE
-
-
-
CPS1
CPS0
ECF
Bit
Bit
Number
Mnemonic
7
CIDL
Description
Counter Idle Control
Cleared to program the PCA Counter to continue functioning during idle Mode.
Set to program PCA to be gated off during idle.
Watchdog Timer Enable
6
WDTE
Cleared to disable Watchdog Timer function on PCA Module 4.
Set to enable Watchdog Timer function on PCA Module 4.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
CPS1
1
CPS0
0
ECF
PCA Count Pulse Select
CPS1CPS0
0
0
Selected PCA input
Internal clock fCLK PERIPH/6
0
1
1
Internal clock fCLK PERIPH/2
Timer 0 Overflow
External clock at ECI/P1.2 pin (max rate = fCLK PERIPH/ 4)
1
0
1
PCA Enable Counter Overflow Interrupt
Cleared to disable CF bit in CCON to inhibit an interrupt.
Set to enable CF bit in CCON to generate an interrupt.
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Reset Value = 00XX X000b
Not bit addressable
The CMOD register includes three additional bits associated with the PCA (See Figure 13-1 and
Table 13-1).
• The CIDL bit allows the PCA to stop during idle mode.
• The WDTE bit enables or disables the watchdog function on module 4.
• The ECF bit when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR)
to be set when the PCA timer overflows.
The CCON register contains the run control bit for the PCA and the flags for the PCA timer (CF)
and each module (see Table 13-2).
• Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this
bit.
• Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be
generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by
software.
• Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and
are set by hardware when either a match or a capture occurs. These flags can only be
cleared by software.
Table 13-2.
CCON Register
CCON - PCA Counter Control Register (D8h)
7
6
5
4
3
2
1
0
CF
CR
–
CCF4
CCF3
CCF2
CCF1
CCF0
Bit
Bit
Number
Mnemonic
7
CF
6
CR
5
–
4
CCF4
3
CCF3
2
CCF2
Description
PCA Counter Overflow flag
Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set.
CF may be set by either hardware or software but can only be cleared by software.
PCA Counter Run control bit
Must be cleared by software to turn the PCA counter off.
Set by software to turn the PCA counter on.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PCA Module 4 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 3 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 2 interrupt flag
40
Must be cleared by software.
Set by hardware when a match or capture occurs.
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
Bit
Bit
Number
Mnemonic
1
CCF1
0
CCF0
Description
PCA Module 1 Interrupt Flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 0 Interrupt Flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
Reset Value = 000X 0000b
Not bit addressable
The watchdog timer function is implemented in module 4 (See Figure 13-4).
The PCA interrupt system is shown in Figure 13-2.
Figure 13-2. PCA Interrupt System
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0
CCON
0xD8
PCA Timer/Counter
Module 0
Module 1
To Interrupt
priority decoder
Module 2
Module 3
Module 4
CMOD.0
ECF
ECCFn CCAPMn.0
IE.6
EC
IE.7
EA
PCA Modules: each one of the five compare/capture modules has six possible functions. It can
perform:
• 16-bit capture, positive-edge triggered
• 16-bit capture, negative-edge triggered
• 16-bit capture, both positive and negative-edge triggered
• 16-bit Software Timer
• 16-bit High-speed Output
• 8-bit Pulse Width Modulator
In addition, module 4 can be used as a Watchdog Timer.
Each module in the PCA has a special function register associated with it. These registers are:
CCAPM0 for module 0, CCAPM1 for module 1, etc. (see Table 13-3). The registers contain the
bits that control the mode that each module will operate in.
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• The ECCF bit (CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module) enables the
CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the
associated module.
• PWM (CCAPMn.1) enables the pulse width modulation mode.
• The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to
toggle when there is a match between the PCA counter and the module's capture/compare
register.
• The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be
set when there is a match between the PCA counter and the module's capture/compare
register.
• The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a
capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit
enables the positive edge. If both bits are set both edges will be enabled and a capture will
occur for either transition.
• The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.
Table 13-4 shows the CCAPMn settings for the various PCA functions.
Table 13-3. CCAPMn Registers (n = 0-4)
CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh)
CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh)
CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh)
CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh)
CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh)
7
6
5
4
3
2
1
0
-
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
Bit
Bit
Number
Mnemonic
7
-
6
ECOMn
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enable Comparator
Cleared to disable the comparator function.
Set to enable the comparator function.
Capture Positive
5
CAPPn
4
CAPNn
Cleared to disable positive edge capture.
Set to enable positive edge capture.
Capture Negative
Cleared to disable negative edge capture.
Set to enable negative edge capture.
Match
3
MATn
When MATn = 1, a match of the PCA counter with this module's compare/capture
register causes the
CCFn bit in CCON to be set, flagging an interrupt.
Toggle
2
42
TOGn
When TOGn = 1, a match of the PCA counter with this module's compare/capture
register causes the CEXn pin to toggle.
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Bit
Bit
Number
Mnemonic
1
PWMn
Description
Pulse Width Modulation Mode
Cleared to disable the CEXn pin to be used as a pulse width modulated output.
Set to enable the CEXn pin to be used as a pulse width modulated output.
Enable CCF Interrupt
0
ECCFn
Cleared to disable compare/capture flag CCFn in the CCON register to generate an
interrupt.
Set to enable compare/capture flag CCFn in the CCON register to generate an
interrupt.
Reset Value = X000 0000b
Not bit addressable
Table 13-4.
PCA Module Modes (CCAPMn Registers)
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMm ECCFn Module Function
0
0
0
0
0
0
0
No Operation
X
1
0
0
0
0
X
16-bit capture by a positive-edge
trigger on CEXn
X
0
1
0
0
0
X
16-bit capture by a negative trigger
on CEXn
X
1
1
0
0
0
X
16-bit capture by a transition on
CEXn
1
0
0
1
0
0
X
16-bit Software Timer/Compare
mode.
1
0
0
1
1
0
X
16-bit High Speed Output
1
0
0
0
0
1
0
8-bit PWM
1
0
0
1
X
0
X
Watchdog Timer (module 4 only)
There are two additional registers associated with each of the PCA modules. They are CCAPnH
and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a
compare should occur. When a module is used in the PWM mode these registers are used to
control the duty cycle of the output (see Table 13-5 and Table 13-6)
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Table 13-5. CCAPnH Registers (n = 0-4)
CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh)
CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh)
CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh)
CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh)
CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit
Bit
Number
Mnemonic
7-0
-
Description
PCA Module n Compare/Capture Control
CCAPnH Value
Reset Value = XXXX XXXXb
Not bit addressable
Table 13-6. CCAPnL Registers (n = 0-4)
CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh)
CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh)
CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh)
CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh)
CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit
Bit
Number
Mnemonic
7-0
-
Description
PCA Module n Compare/Capture Control
CCAPnL Value
Reset Value = XXXX XXXXb
Not bit addressable
Table 13-7. CH Register
CH - PCA Counter Register High (0F9h)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit
Bit
Number
Mnemonic
Description
7-0
-
PCA counter
CH Value
Reset Value = 0000 0000b
Not bit addressable
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Table 13-8. CL Register
CL - PCA Counter Register Low (0E9h)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit
Bit
Number
Mnemonic
7-0
-
Description
PCA Counter
CL Value
Reset Value = 0000 0000b
Not bit addressable
13.1
PCA Capture Mode
To use one of the PCA modules in the capture mode either one or both of the CCAPM bits
CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1)
is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of
the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and
CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn
SFR are set then an interrupt will be generated (see Figure 13-3).
Figure 13-3. PCA Capture Mode
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0 CCON
0xD8
PCA IT
PCA Counter/Timer
Cex.n
CH
CL
CCAPnH
CCAPnL
Capture
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4
0xDA to 0xDE
13.2
16-bit Software Timer/Compare Mode
The PCA modules can be used as software timers by setting both the ECOM and MAT bits in
the modules CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn
(CCAPMn SFR) bits for the module are both set (see Figure 13-4).
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7683C–USB–11/07
Figure 13-4. PCA Compare Mode and PCA Watchdog Timer
CCON
CF
Write to
CCAPnL
CR
CCF4 CCF3 CCF2 CCF1 CCF0
0xD8
Reset
PCA IT
Write to
CCAPnH
1
CCAPnH
0
CCAPnL
Enable
Match
16-bit Comparator
CH
RESET(1)
CL
PCA Counter/Timer
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CIDL
Note:
WDTE
CPS1 CPS0
ECF
CCAPMn, n = 0 to 4
0xDA to 0xDE
CMOD
0xD9
1. Only for Module 4
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.
Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur
while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user
software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be
controlled by accessing to CCAPMn register.
13.3
High Speed Output Mode
In this mode, the CEX output (on port 1) associated with the PCA module will toggle each time a
match occurs between the PCA counter and the module's capture registers. To activate this
mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (see
Figure 13-5).
A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.
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Figure 13-5. PCA High-speed Output Mode
CCON
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0
0xD8
Write to
CCAPnL Reset
PCA IT
Write to
CCAPnH
1
CCAPnH
0
CCAPnL
Enable
16-bit Comparator
CH
Match
CL
CEXn
PCA counter/timer
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CCAPMn, n = 0 to 4
0xDA to 0xDE
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen.
Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur
while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user
software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be
controlled by accessing to CCAPMn register.
13.4
Pulse Width Modulator Mode
All of the PCA modules can be used as PWM outputs. Figure 13-6 shows the PWM function.
The frequency of the output depends on the source for the PCA timer. All of the modules will
have the same frequency of output because they all share the PCA timer. The duty cycle of each
module is independently variable using the module's capture register CCAPLn. When the value
of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low,
when it is equal to or greater than the output will be high. When CL overflows from FF to 00,
CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches.
The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM
mode.
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7683C–USB–11/07
Figure 13-6. PCA PWM Mode
CCAPnH
Overflow
CCAPnL
“0”
Enable
8-bit Comparator
CEXn
<
≥
“1”
CL
PCA Counter/Timer
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CCAPMn, n = 0 to 4
0xDA to 0xDE
13.5
PCA Watchdog Timer
An on-board watchdog timer is available with the PCA to improve the reliability of the system
without increasing chip count. Watchdog timers are useful for systems that are susceptible to
noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be
programmed as a watchdog. However, this module can still be used for other modes if the
watchdog is not needed. Figure 13-4 shows a diagram of how the watchdog works. The user
pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit
value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be
generated. This will not cause the RST pin to be driven low.
In order to hold off the reset, the user has three options:
1. Periodically change the compare value so it will never match the PCA timer
2. Periodically change the PCA timer value so it will never match the compare values, or
3. Disable the watchdog by clearing the WDTE bit before a match occurs and then reenable it
The first two options are more reliable because the watchdog timer is never disabled as in option
#3. If the program counter ever goes astray, a match will eventually occur and cause an internal
reset. The second option is also not recommended if other PCA modules are being used.
Remember, the PCA timer is the time base for all modules; changing the time base for other
modules would not be a good idea. Thus, in most applications the first solution is the best option.
This watchdog timer won’t generate a reset out on the reset pin.
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14. Serial I/O Port
The serial I/O port in the AT83C5134/35/36 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (modes 1, 2
and 3). Asynchronous transmission and reception can occur simultaneously and at different
baud rates.
Serial I/O port includes the following enhancements:
• Framing error detection
• Automatic address recognition
14.1
Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To
enable the framing bit error detection feature, set SMOD0 bit in PCON register (see Figure 141).
Figure 14-1. Framing Error Block Diagram
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
SCON (98h)
Set FE Bit if Stop Bit is 0 (framing error) (SMOD0 = 1)
SM0 to UART Mode Control (SMOD0 = 0)
SMOD1 SMOD0
-
POF
GF1
GF0
PD
PCON (87h)
IDL
To UART Framing Error Control
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by
two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table
14-1) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear
FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure
14-2 and Figure 14-3).
Figure 14-2. UART Timings in Mode 1
RXD
D0
Start
Bit
D1
D2
D3
D4
Data Byte
D5
D6
D7
Stop
Bit
RI
SMOD0 = X
FE
SMOD0 = 1
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Figure 14-3. UART Timings in Modes 2 and 3
RXD
D0
Start
Bit
D1
D2
D3
D4
Data Byte
D5
D6
D7
D8
Ninth Stop
Bit
Bit
RI
SMOD0 = 0
RI
SMOD0 = 1
FE
SMOD0 = 1
14.2
Automatic Address Recognition
The automatic address recognition feature is enabled when the multiprocessor communication
feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command
frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON
register to generate an interrupt. This ensures that the CPU is not interrupted by command
frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received
command frame address matches the device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broadcast address.
Note:
14.2.1
The multiprocessor communication and automatic address recognition features cannot be
enabled in mode 0 (i.e., setting SM2 bit in SCON register in mode 0 has no effect).
Given Address
Each device has an individual address that is specified in SADDR register; the SADEN register
is a mask byte that contains don’t care bits (defined by zeros) to form the device’s given
address. The don’t care bits provide the flexibility to address one or more slaves at a time. The
following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
SADEN1111 1001b
Given1111 0XX1b
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Slave C:SADDR1111 0011b
SADEN1111 1101b
Given1111 00X1b
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t care bit; for slaves B and C, bit 0 is a 1. To communicate
with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves
B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111
0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1
clear, and bit 2 clear (e.g. 1111 0001b).
14.2.2
Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with
zeros defined as don’t care bits, e.g.:
SADDR0101 0110b
SADEN1111 1100b
Broadcast = SADDR OR SADEN1111 111Xb
The use of don’t care bits provides flexibility in defining the broadcast address, in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Broadcast1111 1X11b,
Slave B:SADDR1111 0011b
SADEN1111 1001b
Broadcast1111 1X11B,
Slave C:SADDR = 1111 0011b
SADEN1111 1101b
Broadcast1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of
the slaves, the master must send an address FFh. To communicate with slaves A and B, but not
slave C, the master can send and address FBh.
14.2.3
Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast
addresses are XXXX XXXXb (all don’t care bits). This ensures that the serial port will reply to any
address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not
support automatic address recognition.
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7683C–USB–11/07
SADEN - Slave Address Mask Register (B9h)
7
6
5
4
3
2
1
0
4
3
2
1
0
Reset Value = 0000 0000b
Not bit addressable
SADDR - Slave Address Register (A9h)
7
6
5
Reset Value = 0000 0000b
Not bit addressable
14.3
Baud Rate Selection for UART for Mode 1 and 3
The Baud Rate Generator for transmit and receive clocks can be selected separately via the
T2CON and BDRCON registers.
Figure 14-4. Baud Rate Selection
TIMER1
TIMER2
0
TIMER_BRG_RX
0
1
/ 16
Rx Clock
1
RCLK
RBCK
INT_BRG
TIMER1
TIMER2
0
1
TIMER_BRG_TX
0
1
/ 16
Tx Clock
TCLK
INT_BRG
52
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14.3.1
14.3.2
Baud Rate Selection Table for UART
TCLK
RCLK
TBCK
RBCK
Clock Source
Clock Source
(T2CON)
(T2CON)
(BDRCON)
(BDRCON)
UART Tx
UART Rx
0
0
0
0
Timer 1
Timer 1
1
0
0
0
Timer 2
Timer 1
0
1
0
0
Timer 1
Timer 2
1
1
0
0
Timer 2
Timer 2
X
0
1
0
INT_BRG
Timer 1
X
1
1
0
INT_BRG
Timer 2
0
X
0
1
Timer 1
INT_BRG
1
X
0
1
Timer 2
INT_BRG
X
X
1
1
INT_BRG
INT_BRG
Internal Baud Rate Generator (BRG)
When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG
overflow depending on the BRL reload value, the value of SPD bit (Speed Mode) in BDRCON
register and the value of the SMOD1 bit in PCON register.
Figure 14-5. Internal Baud Rate
Peripheral Clock
auto reload counter
overflow
BRG
0
/6
/2
0
1
INT_BRG
1
BRL
SPD
SMOD1
BRR
• The baud rate for UART is token by formula:
2SMOD1 x FCLK PERIPH
Baud_Rate =
2x6
(1-SPD)
2SMOD1 x FCLK PERIPH
(BRL) = 256 2x6
Table 14-1.
x 16 x [256 - (BRL)]
(1-SPD)
x 16 x Baud_Rate
SCON Register – SCON Serial Control Register (98h)
7
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
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7683C–USB–11/07
Bit
Bit
Number
Mnemonic
FE
Description
Framing Error bit (SMOD0 = 1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
7
SM0
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
6
SM1
Serial port Mode bit 1
SM0 SM1
Mode
0
0
0
0
1
1
1
0
2
Description
Shift Register
8-bit UART
9-bit UART
Baud Rate
FCPU PERIPH/6
Variable
FCPU PERIPH/32 or/16
1
9-bit UART
Variable
1
3
5
SM2
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually
mode 1. This bit should be cleared in mode 0.
4
REN
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
3
TB8
Transmitter Bit 8/Ninth bit to Transmit in Modes 2 and 3
2
RB8
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8/Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1
0
TI
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit
in the other modes.
RI
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 14-2. and Figure 143. in the other modes.
Reset Value = 0000 0000b
Bit addressable
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Example of computed value when X2 = 1, SMOD1 = 1, SPD = 1
FOSC = 16.384 MHz
Baud Rates
FOSC = 24 MHz
BRL
Error (%)
BRL
Error (%)
115200
247
1.23
243
0.16
57600
238
1.23
230
0.16
38400
229
1.23
217
0.16
28800
220
1.23
204
0.16
19200
203
0.63
178
0.16
9600
149
0.31
100
0.16
4800
43
1.23
-
-
Example of computed value when X2 = 0, SMOD1 = 0, SPD = 0
FOSC = 16.384 MHz
FOSC = 24 MHz
Baud Rates
BRL
Error (%)
BRL
Error (%)
4800
247
1.23
243
0.16
2400
238
1.23
230
0.16
1200
220
1.23
202
3.55
600
185
0.16
152
0.16
The baud rate generator can be used for mode 1 or 3 (refer to Figure 14-4.), but also for mode 0
for UART, thanks to the bit SRC located in BDRCON register (Table 14-4.)
14.4
UART Registers
SADEN - Slave Address Mask Register for UART (B9h)
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
Reset Value = 0000 0000b
SADDR - Slave Address Register for UART (A9h)
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
Reset Value = 0000 0000b
SBUF - Serial Buffer Register for UART (99h)
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
Reset Value = XXXX XXXXb
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BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah)
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
Reset Value = 0000 0000b
Table 14-2. T2CON Register
T2CON - Timer 2 Control Register (C8h)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Bit
Number
Mnemonic
7
TF2
Description
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.
6
EXF2
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2
= 1.
When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt is
enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode
(DCEN = 1)
5
RCLK
Receive Clock bit for UART
Cleared to use Timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.
4
TCLK
Transmit Clock bit for UART
Cleared to use Timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for Timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is detected, if
Timer 2 is not used to clock the serial port.
3
EXEN2
2
TR2
1
C/T2#
Timer/Counter 2 select bit
Cleared for timer operation (input from internal clock system: FCLK PERIPH).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock
out mode.
CP/RL2#
Timer 2 Capture/Reload bit
If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to Auto-reload on Timer
2 overflow.
Cleared to Auto-reload on Timer 2 overflows or negative transitions on T2EX pin if
EXEN2 = 1.
Set to capture on negative transitions on T2EX pin if EXEN2 = 1.
0
Timer 2 Run control bit
Cleared to turn off Timer 2.
Set to turn on Timer 2.
Reset Value = 0000 0000b
Bit addressable
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Table 14-3. PCON Register
PCON - Power Control Register (87h)
7
6
5
4
3
2
1
0
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
Bit
Bit
Number
Mnemonic
7
SMOD1
6
SMOD0
5
-
Description
Serial port Mode bit 1 for UART
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0 for UART
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
POF
Power-Off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by
software.
3
GF1
General-purpose Flag
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
2
GF0
General-purpose Flag
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
1
PD
Power-down Mode Bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0
IDL
Idle Mode Bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
Reset Value = 00x1 0000b
Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect
the value of this bit.
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Table 14-4. BDRCON Register
BDRCON - Baud Rate Control Register (9Bh)
7
6
5
4
3
2
1
0
-
-
-
BRR
TBCK
RBCK
SPD
SRC
Bit
Number
Bit
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
BRR
Baud Rate Run Control bit
Cleared to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
3
TBCK
Transmission Baud rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
2
RBCK
Reception Baud Rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
1
SPD
0
SRC
Description
Baud Rate Speed Control bit for UART
Cleared to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
Baud Rate Source select bit in Mode 0 for UART
Cleared to select FOSC/12 as the Baud Rate Generator (FCLK PERIPH/6 in X2 mode).
Set to select the internal Baud Rate Generator for UARTs in mode 0.
Reset Value = xxx0 0000b
Not bit addressable
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15. Dual Data Pointer Register
The additional data pointer can be used to speed up code execution and reduce code size.
The dual DPTR structure is a way by which the chip will specify the address of an external data
memory location. There are two 16-bit DPTR registers that address the external memory, and a
single bit called DPS = AUXR1.0 (see Table 15-1) that allows the program code to switch
between them (see Figure 15-1).
Figure 15-1. Use of Dual Pointer
External Data Memory
7
0
DPS
DPTR1
DPTR0
AUXR1(A2H)
DPH(83H) DPL(82H)
Table 15-1.
AUXR1 Register
AUXR1- Auxiliary Register 1(0A2h)
7
6
5
4
3
2
1
0
-
-
-
-
GF3
0
-
DPS
Bit
Bit
Number
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
GF3
2
0
Always cleared.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
DPS
Description
This bit is a general-purpose user flag.
Data Pointer Selection
Cleared to select DPTR0.
Set to select DPTR1.
Reset Value = xxxx x0x0b
Not bit addressable
a. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
ASSEMBLY LANGUAGE
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; Block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR.
However, note that the INC instruction does not directly force the DPS bit to a particular state,
but simply toggles it. In simple routines, such as the block move example, only the fact that DPS
is toggled in the proper sequence matters, not its actual value. In other words, the block move
routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.
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16. Interrupt System
16.1
Overview
The AT83C5134/35/36 has a total of 11 interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard
interrupt, USB interrupt and the PCA global interrupt. These interrupts are shown in Figure 16-1.
Figure 16-1. Interrupt Control System
IT0
High priority
interrupt
IPH, IPL
TCON.0
0
3
INT0
IE0
0
1
3
TF0
TCON.2
IT1
0
0
3
INT1
IE1
0
1
3
Interrupt
Polling
Sequence, Decreasing From
High-to-Low Priority
TF1
0
3
PCA IT
0
RI
TI
3
TF2
EXF2
3
0
0
3
KBD IT
0
3
TWI IT
0
3
SPI IT
0
3
USBINT
UEPINT
0
Individual Enable
Global Disable
Low Priority
Interrupt
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit
in the Interrupt Enable register (Table 16-2). This register also contains a global disable bit,
which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by
setting or clearing a bit in the Interrupt Priority register (Table 16-3.) and in the Interrupt Priority
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High register (Table 16-4). Table 16-1. shows the bit values and priority levels associated with
each combination.
16.2
Registers
The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located at
address 004BH and Keyboard interrupt vector is located at address 003BH. All other vectors
addresses are the same as standard C52 devices.
Table 16-1.
Priority Level Bit Values
IPH.x
IPL.x
Interrupt Level Priority
0
0
0 (Lowest)
0
1
1
1
0
2
1
1
3 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of
higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each
priority level there is a second priority structure determined by the polling sequence.
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Table 16-2. IEN0 Register
IEN0 - Interrupt Enable Register (A8h)
7
6
5
4
3
2
1
0
EA
EC
ET2
ES
ET1
EX1
ET0
EX0
Bit
Bit
Number
Mnemonic
7
EA
6
EC
Description
Enable All interrupt bit
Cleared to disable all interrupts.
Set to enable all interrupts.
PCA interrupt enable bit
Cleared to disable.
Set to enable.
5
ET2
Timer 2 overflow interrupt Enable bit
Cleared to disable Timer 2 overflow interrupt.
Set to enable Timer 2 overflow interrupt.
4
ES
Serial port Enable bit
Cleared to disable serial port interrupt.
Set to enable serial port interrupt.
3
ET1
Timer 1 overflow interrupt Enable bit
Cleared to disable Timer 1 overflow interrupt.
Set to enable Timer 1 overflow interrupt.
2
EX1
External interrupt 1 Enable bit
Cleared to disable external interrupt 1.
Set to enable external interrupt 1.
1
ET0
Timer 0 overflow interrupt Enable bit
Cleared to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0
EX0
External interrupt 0 Enable bit
Cleared to disable external interrupt 0.
Set to enable external interrupt 0.
Reset Value = 0000 0000b
Bit addressable
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Table 16-3. IPL0 Register
IPL0 - Interrupt Priority Register (B8h)
7
6
5
4
3
2
1
0
-
PPCL
PT2L
PSL
PT1L
PX1L
PT0L
PX0L
Bit
Bit
Number
Mnemonic
7
-
6
PPCL
PCA interrupt Priority bit
Refer to PPCH for priority level.
5
PT2L
Timer 2 overflow interrupt Priority bit
Refer to PT2H for priority level.
4
PSL
Serial port Priority bit
Refer to PSH for priority level.
3
PT1L
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
2
PX1L
External interrupt 1 Priority bit
Refer to PX1H for priority level.
1
PT0L
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
0
PX0L
External interrupt 0 Priority bit
Refer to PX0H for priority level.
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = x000 0000b
Bit addressable
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Table 16-4. IPH0 Register
IPH0 - Interrupt Priority High Register (B7h)
7
6
5
4
3
2
1
0
-
PPCH
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Bit
Bit
Number
Mnemonic
7
-
6
5
4
3
2
1
0
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PPCH
PCA interrupt Priority high bit.
PPCH PPCL Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PT2H
Timer 2 overflow interrupt Priority High bit
PT2H PT2L Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PSH
Serial port Priority High bit
Priority Level
PSH PSL
0
0
Lowest
0
1
1
0
1
1
Highest
PT1H
Timer 1 overflow interrupt Priority High bit
PT1H PT1L Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PX1H
External interrupt 1 Priority High bit
PX1H PX1L Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PT0H
Timer 0 overflow interrupt Priority High bit
PT0H PT0L Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PX0H
External interrupt 0 Priority High bit
PX0H PX0L Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
Reset Value = x000 0000b
Not bit addressable
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Table 16-5. IEN1 Register
IEN1 - Interrupt Enable Register (B1h)
7
6
5
4
3
2
1
0
-
EUSB
-
-
-
ESPI
ETWI
EKB
Bit
Bit
Number
Mnemonic
7
-
6
EUSB
5
-
Reserved
4
-
Reserved
3
-
Reserved
2
ESPI
SPI interrupt Enable bit
Cleared to disable SPI interrupt.
Set to enable SPI interrupt.
1
ETWI
TWI interrupt Enable bit
Cleared to disable TWI interrupt.
Set to enable TWI interrupt.
0
EKB
Keyboard interrupt Enable bit
Cleared to disable keyboard interrupt.
Set to enable keyboard interrupt.
Description
Reserved
USB Interrupt Enable bit
Cleared to disable USB interrupt.
Set to enable USB interrupt.
Reset Value = x0xx x000b
Not bit addressable
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Table 16-6. IPL1 Register
IPL1 - Interrupt Priority Register (B2h)
7
6
5
4
3
2
1
0
-
PUSBL
-
-
-
PSPIL
PTWIL
PKBDL
Bit
Bit
Number
Mnemonic
7
-
6
PUSBL
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
PSPIL
SPI Interrupt Priority bit
Refer to PSPIH for priority level.
1
PTWIL
TWI Interrupt Priority bit
Refer to PTWIH for priority level.
0
PKBL
Keyboard Interrupt Priority bit
Refer to PKBH for priority level.
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
USB Interrupt Priority bit
Refer to PUSBH for priority level.
Reset Value = X0XX X000b
Not bit addressable
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Table 16-7. IPH1 Register
IPH1 - Interrupt Priority High Register (B3h)
7
6
5
4
3
2
1
0
-
PUSBH
-
-
-
PSPIH
PTWIH
PKBH
Bit
Bit
Number
Mnemonic
7
-
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
USB Interrupt Priority High bit
PUSBHPUSBLPriority Level
0
0
Lowest
0
1
1
0
1
1
Highest
6
PUSBH
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
1
0
PSPIH
SPI Interrupt Priority High bit
PSPIHPSPIL Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PTWIH
TWI Interrupt Priority High bit
PTWIHPTWIL Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PKBH
Keyboard Interrupt Priority High bit
PKBH PKBL Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
Reset Value = X0XX X000b
Not bit addressable
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16.3
Interrupt Sources and Vector Addresses
Table 16-8.
Vector Table
Polling
Priority
Interrupt
Source
0
0
Reset
1
1
INT0
IE0
0003h
2
2
Timer 0
TF0
000Bh
3
3
INT1
IE1
0013h
4
4
Timer 1
IF1
001Bh
5
6
UART
RI+TI
0023h
6
7
Timer 2
TF2+EXF2
002Bh
7
5
PCA
CF + CCFn (n = 0-4)
0033h
8
8
Keyboard
KBDIT
003Bh
9
9
TWI
TWIIT
0043h
10
10
SPI
SPIIT
004Bh
11
11
0053h
12
12
005Bh
13
13
0063h
14
14
15
15
USB
Interrupt
Request
Vector
Number
Address
0000h
UEPINT + USBINT
006Bh
0073h
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17. Keyboard Interface
17.1
Introduction
The AT83C5134/35/36 implements a keyboard interface allowing the connection of a 8 x n
matrix keyboard. It is based on 8 inputs with programmable interrupt capability on both high or
low level. These inputs are available as an alternate function of P1 and allow to exit from idle
and power down modes.
17.2
Description
The keyboard interface communicates with the C51 core through 3 special function registers:
KBLS, the Keyboard Level Selection register (Table 17-3), KBE, The Keyboard interrupt Enable
register (Table 17-2), and KBF, the Keyboard Flag register (Table 17-1).
17.2.1
Interrupt
The keyboard inputs are considered as 8 independent interrupt sources sharing the same interrupt vector. An interrupt enable bit (KBD in IE1) allows global enable or disable of the keyboard
interrupt (see Figure 17-1). As detailed in Figure 17-2 each keyboard input has the capability to
detect a programmable level according to KBLS.x bit value. Level detection is then reported in
interrupt flags KBF.x that can be masked by software using KBE.x bits.
This structure allow keyboard arrangement from 1 by n to 8 by n matrix and allow usage of P1
inputs for other purpose.
Figure 17-1. Keyboard Interface Block Diagram
P1.0
Input Circuitry
P1.1
Input Circuitry
P1.2
Input Circuitry
P1.3
Input Circuitry
P1.4
Input Circuitry
P1.5
Input Circuitry
P1.6
Input Circuitry
P1.7
Input Circuitry
KBDIT
Keyboard Interface
Interrupt Request
KBD
IE1.0
Figure 17-2. Keyboard Input Circuitry
Vcc
0
P1:x
KBF.x
1
Internal Pull-up
70
KBE.x
KBLS.x
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17.2.2
17.3
Power Reduction Mode
P1 inputs allow exit from idle and power down modes as detailed in section “Power-down Mode”.
Registers
Table 17-1. KBF Register
KBF - Keyboard Flag Register (9Eh)
7
6
5
4
3
2
1
0
KBF7
KBF6
KBF5
KBF4
KBF3
KBF2
KBF1
KBF0
Bit Number
Bit
Mnemonic
Description
7
6
5
4
3
2
1
0
KBF7
Keyboard line 7 flag
Set by hardware when the Port line 7 detects a programmed level. It generates a
Keyboard interrupt request if the KBKBIE.7 bit in KBIE register is set.
Cleared by hardware when reading KBF SFR by software.
KBF6
Keyboard line 6 flag
Set by hardware when the Port line 6 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.6 bit in KBIE register is set.
Cleared by hardware when reading KBF SFR by software.
KBF5
Keyboard line 5 flag
Set by hardware when the Port line 5 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.5 bit in KBIE register is set.
Cleared by hardware when reading KBF SFR by software.
KBF4
Keyboard line 4 flag
Set by hardware when the Port line 4 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.4 bit in KBIE register is set.
Cleared by hardware when reading KBF SFR by software.
KBF3
Keyboard line 3 flag
Set by hardware when the Port line 3 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.3 bit in KBIE register is set.
Cleared by hardware when reading KBF SFR by software.
KBF2
Keyboard line 2 flag
Set by hardware when the Port line 2 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.2 bit in KBIE register is set.
Must be cleared by software.
KBF1
Keyboard line 1 flag
Set by hardware when the Port line 1 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.1 bit in KBIE register is set.
Cleared by hardware when reading KBF SFR by software.
KBF0
Keyboard line 0 flag
Set by hardware when the Port line 0 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.0 bit in KBIE register is set.
Cleared by hardware when reading KBF SFR by software.
Reset Value = 0000 0000b
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Table 17-2. KBE Register
KBE - Keyboard Input Enable Register (9Dh)
7
6
5
4
3
2
1
0
KBE7
KBE6
KBE5
KBE4
KBE3
KBE2
KBE1
KBE0
Bit
Number
Bit
Mnemonic
Description
7
KBE7
Keyboard line 7 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.7 bit in KBF register to generate an interrupt request.
6
KBE6
Keyboard line 6 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.6 bit in KBF register to generate an interrupt request.
5
KBE5
Keyboard line 5 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.5 bit in KBF register to generate an interrupt request.
4
KBE4
Keyboard line 4 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.4 bit in KBF register to generate an interrupt request.
3
KBE3
Keyboard line 3 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.3 bit in KBF register to generate an interrupt request.
2
KBE2
Keyboard line 2 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.2 bit in KBF register to generate an interrupt request.
1
KBE1
Keyboard line 1 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.1 bit in KBF register to generate an interrupt request.
0
KBE0
Keyboard line 0 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.0 bit in KBF register to generate an interrupt request.
Reset Value = 0000 0000b
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Table 17-3. KBLS Register
KBLS-Keyboard Level Selector Register (9Ch)
7
6
5
4
3
2
1
0
KBLS7
KBLS6
KBLS5
KBLS4
KBLS3
KBLS2
KBLS1
KBLS0
Bit Number
Bit
Mnemonic
Description
7
KBLS7
Keyboard line 7 Level Selection bit
Cleared to enable a low level detection on Port line 7.
Set to enable a high level detection on Port line 7.
6
KBLS6
Keyboard line 6 Level Selection bit
Cleared to enable a low level detection on Port line 6.
Set to enable a high level detection on Port line 6.
5
KBLS5
Keyboard line 5 Level Selection bit
Cleared to enable a low level detection on Port line 5.
Set to enable a high level detection on Port line 5.
4
KBLS4
Keyboard line 4 Level Selection bit
Cleared to enable a low level detection on Port line 4.
Set to enable a high level detection on Port line 4.
3
KBLS3
Keyboard line 3 Level Selection bit
Cleared to enable a low level detection on Port line 3.
Set to enable a high level detection on Port line 3.
2
KBLS2
Keyboard line 2 Level Selection bit
Cleared to enable a low level detection on Port line 2.
Set to enable a high level detection on Port line 2.
1
KBLS1
Keyboard line 1 Level Selection bit
Cleared to enable a low level detection on Port line 1.
Set to enable a high level detection on Port line 1.
0
KBLS0
Keyboard line 0 Level Selection bit
Cleared to enable a low level detection on Port line 0.
Set to enable a high level detection on Port line 0.
Reset Value = 0000 0000b
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18. Programmable LED
AT83C5134/35/36 have up to 4 programmable LED current sources, configured by the register
LEDCON.
Table 18-1. LEDCON Register
LEDCON (S:F1h) LED Control Register
7
6
5
LED3
Bit Number
7:6
5:4
3:2
1:0
4
LED2
Bit
Mnemonic
3
2
LED1
1
0
LED0
Description
LED3
Port
0
0
1
1
LED3
0
1
0
1
Configuration
Standard C51 Port
2 mA current source when P3.7 is low
4 mA current source when P3.7 is low
10 mA current source when P3.7 is low
LED2
Port
0
0
1
1
/LED2
0
1
0
1
Configuration
Standard C51 Port
2 mA current source when P3.6 is low
4 mA current source when P3.6 is low
10 mA current source when P3.6 is low
LED1
Port/ LED1
0
0
0
1
1
0
1
1
Configuration
Standard C51 Port
2 mA current source when P3.5 is low
4 mA current source when P3.5 is low
10 mA current source when P3.5 is low
LED0
Port/ LED0
0
0
0
1
1
0
1
1
Configuration
Standard C51 Port
2 mA current source when P3.3 is low
4 mA current source when P3.3 is low
10 mA current source when P3.3 is low
Reset Value = 00h
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19. Serial Peripheral Interface (SPI)
The Serial Peripheral Interface module (SPI) allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs.
19.1
Features
Features of the SPI module include the following:
• Full-duplex, three-wire synchronous transfers
• Master or Slave operation
• Eight programmable Master clock rates
• Serial clock with programmable polarity and phase
• Master mode fault error flag with MCU interrupt capability
• Write collision flag protection
19.2
Signal Description
Figure 19-1 shows a typical SPI bus configuration using one Master controller and many Slave
peripherals. The bus is made of three wires connecting all the devices:
Figure 19-1. SPI Master/Slaves Interconnection
Slave 1
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
VDD
Slave 4
Slave 3
MISO
MOSI
SCK
SS
0
1
2
3
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
PORT
Master
Slave 2
The Master device selects the individual Slave devices by using four pins of a parallel port to
control the four SS pins of the Slave devices.
19.2.1
Master Output Slave Input (MOSI)
This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI
line is used to transfer data in series from the Master to the Slave. Therefore, it is an output signal from the Master, and an input signal to a Slave. A byte (8-bit word) is transmitted most
significant bit (MSB) first, least significant bit (LSB) last.
19.2.2
Master Input Slave Output (MISO)
This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO
line is used to transfer data in series from the Slave to the Master. Therefore, it is an output signal from the Slave, and an input signal to the Master. A byte (8-bit word) is transmitted most
significant bit (MSB) first, least significant bit (LSB) last.
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19.2.3
SPI Serial Clock (SCK)
This signal is used to synchronize the data movement both in and out the devices through their
MOSI and MISO lines. It is driven by the Master for eight clock cycles which allows to exchange
one byte on the serial lines.
19.2.4
Slave Select (SS)
Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any
message for a Slave. It is obvious that only one Master (SS high level) can drive the network.
The Master may select each Slave device by software through port pins (Figure 19-1). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master
for a transmission.
In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI
Status register (SPSTA) to prevent multiple masters from driving MOSI and SCK (see
Section “Error Conditions”, page 79).
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS pin could be used as a general-purpose if the following conditions are met:
• The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind of
configuration can be found when only one Master is driving the network and there is no way
that the SS pin could be pulled low. Therefore, the MODF flag in the SPSTA will never be
set(1).
• The Device is configured as a Slave with CPHA and SSDIS control bits set(2) This kind of
configuration can happen when the system comprises one Master and one Slave only.
Therefore, the device should always be selected and there is no reason that the Master uses
the SS pin to select the communicating Slave device.
Notes:
1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA =’0’ because in this
mode, the SS is used to start the transmission.
19.2.5
Baud Rate
In Master mode, the baud rate can be selected from a baud rate generator which is controlled by
three bits in the SPCON register: SPR2, SPR1 and SPR0. The Master clock is chosen from one
of seven clock rates resulting from the division of the internal clock by 2, 4, 8, 16, 32, 64 or 128.
Table 19-1 gives the different clock rates selected by SPR2:SPR1:SPR0:
Table 19-1.
76
SPI Master Baud Rate Selection
SPR2
SPR1
SPR0
Clock Rate
Baud Rate Divisor (BD)
0
0
0
Don’t Use
No BRG
0
0
1
FCLK PERIPH/4
4
0
1
0
FCLK PERIPH/8
8
0
1
1
FCLK PERIPH/16
16
1
0
0
FCLK PERIPH/32
32
1
0
1
FCLK PERIPH/64
64
1
1
0
FCLK PERIPH/128
128
1
1
1
Don’t Use
No BRG
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19.3
Functional Description
Figure 19-2 shows a detailed structure of the SPI module.
Figure 19-2. SPI Module Block Diagram
Internal Bus
SPDAT
Shift Register
FCLK PERIPH
Clock
Divider
/4
/8
/16
/32
/64
/128
7
6
5
4
3
2
1
0
Receive Data Register
Pin
Control
Logic
Clock
Logic
MOSI
MISO
M
S
Clock
Select
SCK
SS
SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPCON
SPI
Control
SPI Interrupt Request
8-bit bus
1-bit signal
SPSTA
SPIF
19.3.1
WCOL SSERR MODF
-
-
-
-
Operating Modes
The Serial Peripheral Interface can be configured as one of the two modes: Master mode or
Slave mode. The configuration and initialization of the SPI module is made through one register:
• The Serial Peripheral CONtrol register (SPCON)
Once the SPI is configured, the data exchange is made using:
• SPCON
• The Serial Peripheral STAtus register (SPSTA)
• The Serial Peripheral DATa register (SPDAT)
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the
two serial data lines (MOSI and MISO). A Slave Select line (SS) allows individual selection of a
Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities.
When the Master device transmits data to the Slave device via the MOSI line, the Slave device
responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 19-3).
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Figure 19-3. Full-duplex Master/Slave Interconnection
8-bit Shift Register
SPI
Clock Generator
MISO
MISO
MOSI
MOSI
SCK
SS
Master MCU
8-bit Shift Register
SCK
VDD
SS
VSS
Slave MCU
19.3.1.1
Master Mode
The SPI operates in Master mode when the Master bit, MSTR (1), in the SPCON register is set.
Only one Master SPI device can initiate transmissions. Software begins the transmission from a
Master SPI module by writing to the Serial Peripheral Data Register (SPDAT). If the shift register
is empty, the byte is immediately transferred to the shift register. The byte begins shifting out on
MOSI pin under the control of the serial clock, SCK. Simultaneously, another byte shifts in from
the Slave on the Master’s MISO pin. The transmission ends when the Serial Peripheral transfer
data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes set, the received
byte from the Slave is transferred to the receive data register in SPDAT. Software clears SPIF
by reading the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading
the SPDAT.
19.3.1.2
Slave Mode
The SPI operates in Slave mode when the Master bit, MSTR (2) , in the SPCON register is
cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave device must
be set to’0’. SS must remain low until the transmission is complete.
In a Slave SPI module, data enters the shift register under the control of the SCK from the Master SPI module. After a byte enters the shift register, it is immediately transferred to the receive
data register in SPDAT, and the SPIF bit is set. To prevent an overflow condition, Slave software
must then read the SPDAT before another byte enters the shift register (3). A Slave SPI must
complete the write to the SPDAT (shift register) at least one bus cycle before the Master SPI
starts a transmission. If the write to the data register is late, the SPI transmits the data already in
the shift register from the previous transmission.
19.3.2
78
Transmission Formats
Software can select any of four combinations of serial clock (SCK) phase and polarity using two
bits in the SPCON: the Clock POLarity (CPOL (4)) and the Clock PHAse (CPHA4). CPOL defines
the default SCK line level in idle state. It has no significant effect on the transmission format.
CPHA defines the edges on which the input data are sampled and the edges on which the output data are shifted (Figure 19-4 and Figure 19-5). The clock phase and polarity should be
identical for the Master SPI device and the communicating Slave device.
1.
The SPI module should be configured as a Master before it is enabled (SPEN set). Also the Master SPI should be configured before the Slave SPI.
2.
The SPI module should be configured as a Slave before it is enabled (SPEN set).
3.
The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed.
4.
Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN =’0’).
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Figure 19-4. Data Transmission Format (CPHA = 0)
SCK cycle number
1
2
3
4
5
6
7
8
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
SPEN (internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI (from Master)
MISO (from Slave)
MSB
SS (to Slave)
Capture point
Figure 19-5. Data Transmission Format (CPHA = 1)
1
2
3
4
5
6
7
8
MOSI (from Master)
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
MISO (from Slave)
MSB
bit6
bit5
bit4
bit3
bit2
bit1
SCK cycle number
SPEN (internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
LSB
SS (to Slave)
Capture point
Figure 19-6. CPHA/SS Timing
MISO/MOSI
Byte 1
Byte 2
Byte 3
Master SS
Slave SS
(CPHA = 0)
Slave SS
(CPHA = 1)
As shown in Figure 19-5, the first SCK edge is the MSB capture strobe. Therefore the Slave
must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to
start the transmission. The SS pin must be toggled high and then low between each byte transmitted (Figure 19-2).
Figure 19-6 shows an SPI transmission in which CPHA is’1’. In this case, the Master begins driving its MOSI pin on the first SCK edge. Therefore the Slave uses the first SCK edge as a start
transmission signal. The SS pin can remain low between transmissions (Figure 19-1). This format may be preferable in systems having only one Master and only one Slave driving the MISO
data line.
19.3.3
Error Conditions
The following flags in the SPSTA signal SPI error conditions:
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19.3.3.1
Mode Fault (MODF)
Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is
inconsistent with the actual mode of the device. MODF is set to warn that there may have a
multi-master conflict for system control. In this case, the SPI system is affected in the following
ways:
• An SPI receiver/error CPU interrupt request is generated,
• The SPEN bit in SPCON is cleared. This disable the SPI,
• The MSTR bit in SPCON is cleared
When SS DISable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set when the
SS signal becomes “0”.
However, as stated before, for a system with one Master, if the SS pin of the Master device is
pulled low, there is no way that another Master attempt to drive the network. In this case, to prevent the MODF flag from being set, software can set the SSDIS bit in the SPCON register and
therefore making the SS pin as a general-purpose I/O pin.
Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed
by a write to the SPCON register. SPEN Control bit may be restored to its original set state after
the MODF bit has been cleared.
19.3.3.2
Write Collision (WCOL)
A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done
during a transmit sequence.
WCOL does not cause an interruption, and the transfer continues uninterrupted.
Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an
access to SPDAT.
19.3.3.3
Overrun Condition
An overrun condition occurs when the Master device tries to send several data bytes and the
Slave devise has not cleared the SPIF bit issuing from the previous data byte transmitted. In this
case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read of the
SPDAT returns this byte. All others bytes are lost.
This condition is not detected by the SPI peripheral.
19.3.4
Interrupts
Two SPI status flags can generate a CPU interrupt requests:
Table 19-2.
SPI Interrupts
Flag
Request
SPIF (SP Data Transfer)
SPI Transmitter Interrupt request
MODF (Mode Fault)
SPI Receiver/Error Interrupt Request (if SSDIS = “0”)
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been
completed. SPIF bit generates transmitter CPU interrupt requests.
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Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent
with the mode of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt
requests.
Figure 19-7 gives a logical view of the above statements.
Figure 19-7. SPI Interrupt Requests Generation
SPIF
SPI Transmitter
CPU Interrupt Request
SPI
CPU Interrupt Request
MODF
SPI Receiver/Error
CPU Interrupt Request
SSDIS
19.3.5
Registers
There are three registers in the module that provide control, status and data storage functions. These registers are
describes in the following paragraphs.
19.3.5.1
Serial Peripheral Control Register (SPCON)
• The Serial Peripheral Control Register does the following:
– Selects one of the Master clock rates
– Configure the SPI module as Master or Slave
– Selects serial clock polarity and phase
– Enables the SPI module
– Frees the SS pin for a general-purpose
Table 19-3 describes this register and explains the use of each bit.
Table 19-3.
SPCON Register
7
6
5
4
3
2
1
0
SPR2
SPEN
SSDIS
MSTR
CPOL
CPHA
SPR1
SPR0
Bit
Number
Bit Mnemonic
7
SPR2
6
SPEN
Description
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate.
Serial Peripheral Enable
Cleared to disable the SPI interface.
Set to enable the SPI interface.
SS Disable
5
SSDIS
5
MSTR
Cleared to enable SS in both Master and Slave modes.
Set to disable SS in both Master and Slave modes. In Slave mode, this bit has no
effect if CPHA = “0”.
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
Clock Polarity
4
CPOL
Cleared to have the SCK set to “0” in idle state.
Set to have the SCK set to “1” in idle state.
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Bit
Number
Bit Mnemonic
3
CPHA
Description
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle state (see CPOL).
Set to have the data sampled when the SCK returns to idle state (see CPOL).
2
1
SPR1
SPR0
SPR2
SPR1
SPR0
0
0
0
Serial Peripheral Rate
Reserved
0
0
1
FCLK PERIPH/4
0
1
0
FCLK PERIPH/8
0
1
1
FCLK PERIPH/16
1
0
0
FCLK PERIPH/32
1
0
1
FCLK PERIPH/64
1
1
0
FCLK PERIPH/128
1
1
1
Reserved
Reset Value = 0001 0100b
Not bit addressable
19.3.5.2
Serial Peripheral Status Register (SPSTA)
The Serial Peripheral Status Register contains flags to signal the following conditions:
• Data transfer complete
• Write collision
• Inconsistent logic level on SS pin (mode fault error)
Table 19-4 describes the SPSTA register and explains the use of every bit in the register.
Table 19-4. SPSTA Register
SPSTA - Serial Peripheral Status and Control register (0C4H)
Table 3.
7
6
5
4
3
2
1
0
SPIF
WCOL
SSERR
MODF
-
-
-
-
Bit Number
Bit
Mnemonic
Description
Serial Peripheral data transfer flag
7
SPIF
Cleared by hardware to indicate data transfer is in progress or has been approved by a
clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
Write Collision flag
6
WCOL
Cleared by hardware to indicate that no collision has occurred or has been approved by a
clearing sequence.
Set by hardware to indicate that a collision has been detected.
Synchronous Serial Slave Error flag
5
SSERR
Set by hardware when SS is deasserted before the end of a received data.
Cleared by disabling the SPI (clearing SPEN bit in SPCON).
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Bit Number
Bit
Mnemonic
Description
Mode Fault
4
MODF
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been
approved by a clearing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level.
3
-
2
-
1
-
0
-
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = 00X0 XXXXb
Not Bit addressable
19.3.5.3
Serial Peripheral Data Register (SPDAT)
The Serial Peripheral Data Register (Table 19-5) is a read/write buffer for the receive data register. A write to SPDAT places data directly into the shift register. No transmit buffer is available in
this model.
A Read of the SPDAT returns the value located in the receive buffer and not the content of the
shift register.
Table 19-5. SPDAT Register
SPDAT - Serial Peripheral Data Register (0C5H)
7
6
5
4
3
2
1
0
R7
R6
R5
R4
R3
R2
R1
R0
Reset Value = Indeterminate
R7:R0: Receive data bits
SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no ongoing exchange. However, special care should be taken when writing to them while a transmission is on-going:
• Do not change SPR2, SPR1 and SPR0
• Do not change CPHA and CPOL
• Do not change MSTR
• Clearing SPEN would immediately disable the peripheral
• Writing to the SPDAT will cause an overflow
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20. Two Wire Interface (TWI)
This section describes the 2-wire interface. The 2-wire bus is a bi-directional 2-wire serial communication standard. It is designed primarily for simple but efficient integrated circuit (IC) control.
The system is comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs connected to them. The serial data transfer is limited to 100 Kbit/s in
standard mode. Various communication configuration can be designed using this bus. Figure
20-1 shows a typical 2-wire bus configuration. All the devices connected to the bus can be master and slave.
Figure 20-1. 2-wire Bus Configuration
device1
device2
device3
...
deviceN
SCL
SDA
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Figure 20-2. Block Diagram
8
Address Register
SSADR
Comparator
Input
Filter
SDA
Output
Stage
SSDAT
ACK
Shift Register
Arbitration &
Sink Logic
Input
Filter
SCL
Output
Stage
Timing &
Control
logic
FCLK PERIPH/4
Internal Bus
8
Interrupt
Serial clock
generator
Timer 1
overflow
SSCON
Control Register
7
Status
Bits
SSCS
Status
Decoder
Status Register
8
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20.1
Description
The CPU interfaces to the 2-wire logic via the following four 8-bit special function registers: the
Synchronous Serial Control register (SSCON; Table 20-10), the Synchronous Serial Data register (SSDAT; Table 20-11), the Synchronous Serial Control and Status register (SSCS; Table 2012) and the Synchronous Serial Address register (SSADR Table 20-13).
SSCON is used to enable the TWI interface, to program the bit rate (see Table 20-3), to enable
slave modes, to acknowledge or not a received data, to send a START or a STOP condition on
the 2-wire bus, and to acknowledge a serial interrupt. A hardware reset disables the TWI
module.
SSCS contains a status code which reflects the status of the 2-wire logic and the 2-wire bus.
The three least significant bits are always zero. The five most significant bits contains the status
code. There are 26 possible status codes. When SSCS contains F8h, no relevant state information is available and no serial interrupt is requested. A valid status code is available in SSCS one
machine cycle after SI is set by hardware and is still present one machine cycle after SI has
been reset by software. to Table 20-9. give the status for the master modes and miscellaneous
states.
SSDAT contains a byte of serial data to be transmitted or a byte which has just been received. It
is addressable while it is not in process of shifting a byte. This occurs when 2-wire logic is in a
defined state and the serial interrupt flag is set. Data in SSDAT remains stable as long as SI is
set. While data is being shifted out, data on the bus is simultaneously shifted in; SSDAT always
contains the last byte present on the bus.
SSADR may be loaded with the 7-bit slave address (7 most significant bits) to which the TWI
module will respond when programmed as a slave transmitter or receiver. The LSB is used to
enable general call address (00h) recognition.
Figure 20-3 shows how a data transfer is accomplished on the 2-wire bus.
Figure 20-3. Complete Data Transfer on 2-wire Bus
MSB
SDA
acknowledgement
signal from receiver
acknowledgement
signal from receiver
SCL
1
2
S
start
condition
7
8
9
ACK
1
2
3-8
9
ACK
clock line held low
while interrupts are serviced
P
stop
condition
The four operating modes are:
• Master Transmitter
• Master Receiver
• Slave transmitter
• Slave receiver
Data transfer in each mode of operation is shown in Table to Table 20-9 and Figure 20-4. to
Figure 20-7.. These figures contain the following abbreviations:
S
86
: START condition
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R
: Read bit (high level at SDA)
W
: Write bit (low level at SDA)
A:
Acknowledge bit (low level at SDA)
A: Not acknowledge bit (high level at SDA)
Data: 8-bit data byte
P
: STOP condition
In Figure 20-4 to Figure 20-7, circles are used to indicate when the serial interrupt flag is set.
The numbers in the circles show the status code held in SSCS. At these points, a service routine
must be executed to continue or complete the serial transfer. These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software.
When the serial interrupt routine is entered, the status code in SSCS is used to branch to the
appropriate service routine. For each status code, the required software action and details of the
following serial transfer are given in Table to Table 20-9.
20.1.1
Master Transmitter Mode
In the master transmitter mode, a number of data bytes are transmitted to a slave receiver
(Figure 20-4). Before the master transmitter mode can be entered, SSCON must be initialised as
follows:
Table 20-1.
SSCON Initialization
CR2
SSIE
STA
STO
SI
AA
CR1
CR0
bit rate
1
0
0
0
X
bit rate
bit rate
CR0, CR1 and CR2 define the internal serial bit rate if external bit rate generator is not used.
SSIE must be set to enable TWI. STA, STO and SI must be cleared.
The master transmitter mode may now be entered by setting the STA bit. The 2-wire logic will
now test the 2-wire bus and generate a START condition as soon as the bus becomes free.
When a START condition is transmitted, the serial interrupt flag (SI bit in SSCON) is set, and the
status code in SSCS will be 08h. This status must be used to vector to an interrupt routine that
loads SSDAT with the slave address and the data direction bit (SLA+W).
When the slave address and the direction bit have been transmitted and an acknowledgement
bit has been received, SI is set again and a number of status code in SSCS are possible. There
are 18h, 20h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was
enabled (AA=logic 1). The appropriate action to be taken for each of these status code is
detailed in Table . This scheme is repeated until a STOP condition is transmitted.
SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to Table 7 to
Table 11. After a repeated START condition (state 10h) the TWI module may switch to the master receiver mode by loading SSDAT with SLA+R.
20.1.2
Master Receiver Mode
In the master receiver mode, a number of data bytes are received from a slave transmitter
(Figure 20-5). The transfer is initialized as in the master transmitter mode. When the START
condition has been transmitted, the interrupt routine must load SSDAT with the 7-bit slave
87
7683C–USB–11/07
address and the data direction bit (SLA+R). The serial interrupt flag SI must then be cleared
before the serial transfer can continue.
When the slave address and the direction bit have been transmitted and an acknowledgement
bit has been received, the serial interrupt flag is set again and a number of status code in SSCS
are possible. There are 40h, 48h or 38h for the master mode and also 68h, 78h or B0h if the
slave mode was enabled (AA=logic 1). The appropriate action to be taken for each of these status code is detailed in Table . This scheme is repeated until a STOP condition is transmitted.
SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to Table 7 to
Table 11. After a repeated START condition (state 10h) the TWI module may switch to the master transmitter mode by loading SSDAT with SLA+W.
20.1.3
Slave Receiver Mode
In the slave receiver mode, a number of data bytes are received from a master transmitter
(Figure 20-6). To initiate the slave receiver mode, SSADR and SSCON must be loaded as
follows:
Table 20-2.
SSADR: Slave Receiver Mode Initialization
A6
A5
A4
A3
A2
A1
A0
GC
own slave address
The upper 7 bits are the address to which the TWI module will respond when addressed by a
master. If the LSB (GC) is set the TWI module will respond to the general call address (00h);
otherwise it ignores the general call address.
Table 20-3.
SSCON: Slave Receiver Mode Initialization
CR2
SSIE
STA
STO
SI
AA
CR1
CR0
bit rate
1
0
0
0
1
bit rate
bit rate
CR0, CR1 and CR2 have no effect in the slave mode. SSIE must be set to enable the TWI. The
AA bit must be set to enable the own slave address or the general call address acknowledgement. STA, STO and SI must be cleared.
When SSADR and SSCON have been initialised, the TWI module waits until it is addressed by
its own slave address followed by the data direction bit which must be at logic 0 (W) for the TWI
to operate in the slave receiver mode. After its own slave address and the W bit have been
received, the serial interrupt flag is set and a valid status code can be read from SSCS. This status code is used to vector to an interrupt service routine.The appropriate action to be taken for
each of these status code is detailed in Table . The slave receiver mode may also be entered if
arbitration is lost while TWI is in the master mode (states 68h and 78h).
If the AA bit is reset during a transfer, TWI module will return a not acknowledge (logic 1) to SDA
after the next received data byte. While AA is reset, the TWI module does not respond to its own
slave address. However, the 2-wire bus is still monitored and address recognition may be
resume at any time by setting AA. This means that the AA bit may be used to temporarily isolate
the module from the 2-wire bus.
88
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AT83C5134/35/36
20.1.4
Slave Transmitter Mode
In the slave transmitter mode, a number of data bytes are transmitted to a master receiver
(Figure 20-7). Data transfer is initialized as in the slave receiver mode. When SSADR and
SSCON have been initialized, the TWI module waits until it is addressed by its own slave
address followed by the data direction bit which must be at logic 1 (R) for TWI to operate in the
slave transmitter mode. After its own slave address and the R bit have been received, the serial
interrupt flag is set and a valid status code can be read from SSCS. This status code is used to
vector to an interrupt service routine. The appropriate action to be taken for each of these status
code is detailed in Table . The slave transmitter mode may also be entered if arbitration is lost
while the TWI module is in the master mode.
If the AA bit is reset during a transfer, the TWI module will transmit the last byte of the transfer
and enter state C0h or C8h. the TWI module is switched to the not addressed slave mode and
will ignore the master receiver if it continues the transfer. Thus the master receiver receives all
1’s as serial data. While AA is reset, the TWI module does not respond to its own slave address.
However, the 2-wire bus is still monitored and address recognition may be resume at any time
by setting AA. This means that the AA bit may be used to temporarily isolate the TWI module
from the 2-wire bus.
20.1.5
Miscellaneous States
There are two SSCS codes that do not correspond to a define TWI hardware state (Table 20-9 ).
These codes are discuss hereafter.
Status F8h indicates that no relevant information is available because the serial interrupt flag is
not set yet. This occurs between other states and when the TWI module is not involved in a
serial transfer.
Status 00h indicates that a bus error has occurred during a TWI serial transfer. A bus error is
caused when a START or a STOP condition occurs at an illegal position in the format frame.
Examples of such illegal positions happen during the serial transfer of an address byte, a data
byte, or an acknowledge bit. When a bus error occurs, SI is set. To recover from a bus error, the
STO flag must be set and SI must be cleared. This causes the TWI module to enter the not
addressed slave mode and to clear the STO flag (no other bits in SSCON are affected). The
SDA and SCL lines are released and no STOP condition is transmitted.
20.2
Notes
the TWI module interfaces to the external 2-wire bus via two port pins: SCL (serial clock line)
and SDA (serial data line). To avoid low level asserting on these lines when the TWI module is
enabled, the output latches of SDA and SLC must be set to logic 1.
Table 20-4.
Bit Frequency Configuration
Bit Frequency ( kHz)
CR2
CR1
CR0
FOSCA= 12 MHz
FOSCA = 16 MHz
FOSCA divided by
0
0
0
47
62.5
256
0
0
1
53.5
71.5
224
0
1
0
62.5
83
192
0
1
1
75
100
160
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Bit Frequency ( kHz)
CR2
CR1
CR0
FOSCA= 12 MHz
FOSCA = 16 MHz
FOSCA divided by
1
0
0
-
-
Unused
1
0
1
100
133.3
120
1
1
0
200
266.6
60
1
1
1
0.5 <. < 62.5
0.67 <. < 83
Timer 1 in mode 2 can be used as TWI baudrate
generator with the following formula:
96.(256-”Timer1 reload value”)
Figure 20-4. Format and State in the Master Transmitter Mode
MT
Successfull
transmission
to a slave
receiver
S
SLA
08h
W
A
Data
A
P
28h
18h
Next transfer
started with a
repeated start
condition
S
SLA
W
10h
Not acknowledge
received after the
slave address
A
R
P
20h
MR
Not acknowledge
received after a data
byte
A
P
30h
Arbitration lost in slave
address or data byte
A or A
Other master
continues
38h
Arbitration lost and
addressed as slave
From master to slave
AT83C5134/35/36
From slave to master
Other master
continues
38h
Other master
continues
A
68h
90
A or A
Data
78h
A
B0h
To corresponding
states in slave mode
Any number of data bytes and their associated
acknowledge bits
7683C–USB–11/07
n
This number (contained in SSCS) corresponds
to a defined state of the 2-wire bus
AT83C5134/35/36
Table 20-5.
Status in Master Transmitter Mode
Application software response
Status
Code
SSSTA
Status of the Twowire Bus and Twowire Hardware
To SSCON
To/From SSDAT
SSSTA
SSSTO
SSI
SSAA
Next Action Taken by Two-wire Hardware
08h
A START condition has
Write SLA+W
been transmitted
X
0
0
X
Write SLA+W
X
0
0
X
10h
A repeated START
condition has been
transmitted
Write SLA+R
X
0
0
X
Write data byte
0
0
0
X
No SSDAT action
1
0
0
X
No SSDAT action
0
1
0
X
STOP condition will be transmitted and SSSTO flag
will be reset.
No SSDAT action
1
1
0
X
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Write data byte
0
0
0
X
No SSDAT action
1
0
0
X
No SSDAT action
0
1
0
X
STOP condition will be transmitted and SSSTO flag
will be reset.
No SSDAT action
1
1
0
X
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Write data byte
0
0
0
X
No SSDAT action
1
0
0
X
No SSDAT action
0
1
0
X
STOP condition will be transmitted and SSSTO flag
will be reset.
No SSDAT action
1
1
0
X
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Write data byte
0
0
0
X
No SSDAT action
1
0
0
X
No SSDAT action
0
1
0
X
STOP condition will be transmitted and SSSTO flag
will be reset.
No SSDAT action
1
1
0
X
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
No SSDAT action
0
0
0
X
Two-wire bus will be released and not addressed
slave mode will be entered.
No SSDAT action
1
0
0
X
A START condition will be transmitted when the bus
becomes free.
18h
20h
28h
30h
38h
SLA+W has been
transmitted; ACK has
been received
SLA+W has been
transmitted; NOT ACK
has been received
Data byte has been
transmitted; ACK has
been received
Data byte has been
transmitted; NOT ACK
has been received
Arbitration lost in
SLA+W or data bytes
SLA+W will be transmitted.
SLA+W will be transmitted.
SLA+R will be transmitted.
Logic will switch to master receiver mode
Data byte will be transmitted.
Repeated START will be transmitted.
Data byte will be transmitted.
Repeated START will be transmitted.
Data byte will be transmitted.
Repeated START will be transmitted.
Data byte will be transmitted.
Repeated START will be transmitted.
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Figure 20-5. Format and State in the Master Receiver Mode
MR
Successfull
transmission
to a slave
receiver
S
SLA
08h
R
Data
A
A
50h
40h
Data
A
P
58h
Next transfer
started with a
repeated start
condition
S
SLA
R
10h
Not acknowledge
received after the
slave address
A
W
P
MT
48h
Arbitration lost in slave
address or acknowledge bit
A or A
Other master
continues
38h
Arbitration lost and
addressed as slave
From slave to master
92
Other master
continues
38h
Other master
continues
A
68h
From master to slave
A
Data
n
78h
A
B0h
To corresponding
states in slave mode
Any number of data bytes and their associated
acknowledge bits
This number (contained in SSCS) corresponds
to a defined state of the 2-wire bus
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
Table 20-6.
Status in Master Receiver Mode
Application software response
Status
Code
SSSTA
Status of the Twowire Bus and Twowire Hardware
To SSCON
To/From SSDAT
SSSTA
SSSTO
SSI
SSAA
Next Action Taken by Two-wire Hardware
08h
A START condition has
Write SLA+R
been transmitted
X
0
0
X
Write SLA+R
X
0
0
X
10h
A repeated START
condition has been
transmitted
Write SLA+W
X
0
0
X
SLA+W will be transmitted.
Logic will switch to master transmitter mode.
Arbitration lost in
SLA+R or NOT ACK
bit
No SSDAT action
0
0
0
X
Two-wire bus will be released and not addressed
slave mode will be entered.
No SSDAT action
1
0
0
X
A START condition will be transmitted when the bus
becomes free.
SLA+R has been
transmitted; ACK has
been received
No SSDAT action
0
0
0
0
Data byte will be received and NOT ACK will be
returned.
No SSDAT action
0
0
0
1
Data byte will be received and ACK will be returned.
No SSDAT action
1
0
0
X
No SSDAT action
0
1
0
X
STOP condition will be transmitted and SSSTO flag
will be reset.
No SSDAT action
1
1
0
X
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Read data byte
0
0
0
0
Data byte will be received and NOT ACK will be
returned.
Read data byte
0
0
0
1
Data byte will be received and ACK will be returned.
Read data byte
1
0
0
X
Read data byte
0
1
0
X
STOP condition will be transmitted and SSSTO flag
will be reset.
Read data byte
1
1
0
X
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
38h
40h
48h
50h
58h
SLA+R has been
transmitted; NOT ACK
has been received
Data byte has been
received; ACK has
been returned
Data byte has been
received; NOT ACK
has been returned
SLA+R will be transmitted.
SLA+R will be transmitted.
Repeated START will be transmitted.
Repeated START will be transmitted.
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Figure 20-6. Format and State in the Slave Receiver Mode
Reception of the own
slave address and one or
more data bytes. All are
acknowledged.
S
SLA
W
Data
A
60h
A
Data
80h
Last data byte received
is not acknowledged.
A
P or S
80h
A0h
A
P or S
88h
Arbitration lost as master
and addressed as slave
A
68h
Reception of the general call
address and one or more data
bytes.
General Call
Data
A
70h
Last data byte received is
not acknowledged.
A
90h
Data
A
P or S
90h
A0h
A
P or S
98h
A
Arbitration lost as master and
addressed as slave by general call
78h
From master to slave
From slave to master
94
Data
n
A
Any number of data bytes and their associated
acknowledge bits
This number (contained in SSCS) corresponds
to a defined state of the 2-wire bus
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
Table 20-7.
Status in Slave Receiver Mode
Application Software Response
Status
Code
(SSCS)
To/from SSDAT
Status of the 2-wire bus and
2-wire hardware
Own SLA+W has been
received; ACK has been
returned
60h
68h
70h
78h
80h
88h
Arbitration lost in SLA+R/W as
master; own SLA+W has been
received; ACK has been
returned
General call address has been
received; ACK has been
returned
Arbitration lost in SLA+R/W as
master; general call address
has been received; ACK has
been returned
Previously addressed with own
SLA+W; data has been
received; ACK has been
returned
Previously addressed with own
SLA+W; data has been
received; NOT ACK has been
returned
90h
Previously addressed with
general call; data has been
received; ACK has been
returned
To SSCON
STA
STO
SI
AA
Next Action Taken By 2-wire Software
No SSDAT action or
X
0
0
0
Data byte will be received and NOT ACK will be
returned
No SSDAT action
X
0
0
1
Data byte will be received and ACK will be
returned
No SSDAT action or
X
0
0
0
Data byte will be received and NOT ACK will be
returned
No SSDAT action
X
0
0
1
Data byte will be received and ACK will be
returned
No SSDAT action or
X
0
0
0
Data byte will be received and NOT ACK will be
returned
No SSDAT action
X
0
0
1
Data byte will be received and ACK will be
returned
No SSDAT action or
X
0
0
0
Data byte will be received and NOT ACK will be
returned
No SSDAT action
X
0
0
1
Data byte will be received and ACK will be
returned
No SSDAT action or
X
0
0
0
Data byte will be received and NOT ACK will be
returned
No SSDAT action
X
0
0
1
Data byte will be received and ACK will be
returned
Read data byte or
0
0
0
0
Read data byte or
0
0
0
1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1
Read data byte or
1
0
0
0
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START
condition will be transmitted when the bus
becomes free
Read data byte
1
0
0
1
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1. A START condition will be
transmitted when the bus becomes free
Read data byte or
X
0
0
0
Data byte will be received and NOT ACK will be
returned
Read data byte
X
0
0
1
Data byte will be received and ACK will be
returned
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Table 20-7.
Status in Slave Receiver Mode (Continued)
Application Software Response
Status
Code
(SSCS)
98h
To/from SSDAT
Status of the 2-wire bus and
2-wire hardware
Previously addressed with
general call; data has been
received; NOT ACK has been
returned
STA
A0h
SI
AA
0
0
0
0
Read data byte or
0
0
0
1
Read data byte or
1
1
0
0
0
0
1
0
0
No SSDAT action or
0
0
0
1
1
0
0
0
0
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1. A START condition will be
transmitted when the bus becomes free
0
1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA
0
0
No SSDAT action or
Next Action Taken By 2-wire Software
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START
condition will be transmitted when the bus
becomes free
No SSDAT action or
No SSDAT action
96
STO
Read data byte or
Read data byte
A STOP condition or repeated
START condition has been
received while still addressed
as slave
To SSCON
Switched to the not addressed slave mode; no
recognition of own SLA or GCA
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1
0
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START
condition will be transmitted when the bus
becomes free
1
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1. A START condition will be
transmitted when the bus becomes free
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
Figure 20-7. Format and State in the Slave Transmitter Mode
Reception of the
S
own slave address
and one or more
data bytes
SLA
A
R
Data
A
A8h
Arbitration lost as master
and addressed as slave
B8h
Data
A
P or S
C0h
A
B0h
Last data byte transmitted.
Switched to not addressed
slave (AA=0)
A
All 1’s P or S
C8h
From master to slave
Data
From slave to master
Table 20-8.
A
Any number of data bytes and their associated
acknowledge bits
This number (contained in SSCS) corresponds
to a defined state of the 2-wire bus
n
Status in Slave Transmitter Mode
Application Software Response
Status
Code
(SSCS)
To/from SSDAT
Status of the 2-wire bus and
2-wire hardware
Own SLA+R has been
received; ACK has been
returned
A8h
B0h
B8h
Arbitration lost in SLA+R/W as
master; own SLA+R has been
received; ACK has been
returned
Data byte in SSDAT has been
transmitted; NOT ACK has
been received
To SSCON
STA
STO
SI
AA
Next Action Taken By 2-wire Software
Load data byte or
X
0
0
0
Last data byte will be transmitted and NOT ACK
will be received
Load data byte
X
0
0
1
Data byte will be transmitted and ACK will be
received
Load data byte or
X
0
0
0
Last data byte will be transmitted and NOT ACK
will be received
Load data byte
X
0
0
1
Data byte will be transmitted and ACK will be
received
Load data byte or
X
0
0
0
Last data byte will be transmitted and NOT ACK
will be received
Load data byte
X
0
0
1
Data byte will be transmitted and ACK will be
received
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7683C–USB–11/07
Table 20-8.
Status in Slave Transmitter Mode (Continued)
Application Software Response
Status
Code
(SSCS)
C0h
To/from SSDAT
Status of the 2-wire bus and
2-wire hardware
Data byte in SSDAT has been
transmitted; NOT ACK has
been received
STA
Last data byte in SSDAT has
been transmitted (AA=0); ACK
has been received
SI
AA
0
0
0
0
No SSDAT action or
0
0
0
1
No SSDAT action or
1
0
1
0
0
0
1
0
0
No SSDAT action or
0
0
0
1
0
1
0
0
0
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1. A START condition will be transmitted
when the bus becomes free
0
1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA
0
0
No SSDAT action or
Next Action Taken By 2-wire Software
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START
condition will be transmitted when the bus
becomes free
No SSDAT action or
No SSDAT action
Table 20-9.
STO
No SSDAT action or
No SSDAT action
C8h
To SSCON
Switched to the not addressed slave mode; no
recognition of own SLA or GCA
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1
0
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START
condition will be transmitted when the bus
becomes free
1
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1. A START condition will be transmitted
when the bus becomes free
Miscellaneous Status
Application Software Response
Status
Code
(SSCS)
98
To/from SSDAT
Status of the 2-wire bus and
2-wire hardware
To SSCON
STA
F8h
No relevant state information
available; SI= 0
No SSDAT action
00h
Bus error due to an illegal
START or STOP condition
No SSDAT action
STO
SI
AA
No SSCON action
0
1
0
Next Action Taken By 2-wire Software
Wait or proceed current transfer
X
Only the internal hardware is affected, no
STOP condition is sent on the bus. In all
cases, the bus is released and STO is reset.
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
20.3
Registers
Table 20-10. SSCON Register
SSCON - Synchronous Serial Control Register (93h)
7
6
5
4
3
2
1
0
CR2
SSIE
STA
STO
SI
AA
CR1
CR0
Bit Number
Bit
Mnemonic
Description
7
CR2
Control Rate bit 2
See .
6
SSIE
Synchronous Serial Interface Enable bit
Clear to disable SSLC.
Set to enable SSLC.
5
STA
Start flag
Set to send a START condition on the bus.
4
ST0
Stop flag
Set to send a STOP condition on the bus.
3
SI
Synchronous Serial Interrupt flag
Set by hardware when a serial interrupt is requested.
Must be cleared by software to acknowledge interrupt.
2
AA
Assert Acknowledge flag
Clear in master and slave receiver modes, to force a not acknowledge (high level on
SDA).
Clear to disable SLA or GCA recognition.
Set to recognise SLA or GCA (if GC set) for entering slave receiver or transmitter
modes.
Set in master and slave receiver modes, to force an acknowledge (low level on SDA).
This bit has no effect when in master transmitter mode.
1
CR1
Control Rate bit 1
See Table 20-4
0
CR0
Control Rate bit 0
See Table 20-4
Table 20-11. SSDAT (095h) - Synchronous Serial Data Register (read/write)
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
7
6
5
4
3
2
1
0
Bit Number
Bit
Mnemonic
Description
7
SD7
Address bit 7 or Data bit 7.
6
SD6
Address bit 6 or Data bit 6.
5
SD5
Address bit 5 or Data bit 5.
4
SD4
Address bit 4 or Data bit 4.
3
SD3
Address bit 3 or Data bit 3.
2
SD2
Address bit 2 or Data bit 2.
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Bit Number
Bit
Mnemonic
1
SD1
Address bit 1 or Data bit 1.
0
SD0
Address bit 0 (R/W) or Data bit 0.
Description
Table 20-12. SSCS (094h) Read - Synchronous Serial Control and Status Register
7
6
5
4
3
2
1
0
SC4
SC3
SC2
SC1
SC0
0
0
0
Bit Number
Bit
Mnemonic
Description
0
0
Always zero
1
0
Always zero
2
0
Always zero
3
SC0
4
SC1
5
SC2
Status Code bit 2
See Table 20-5 to Table 20-9
6
SC3
Status Code bit 3
See Table 20-5 to Table 20-9
7
SC4
Status Code bit 4
See Table 20-5 to Table 20-9
Status Code bit 0
See Table 20-5 to Table 20-9
Status Code bit 1
See Table 20-5 to Table 20-9
Table 20-13. SSADR (096h) - Synchronous Serial Address Register (read/write)
100
7
6
5
4
3
2
1
0
A7
A6
A5
A4
A3
A2
A1
A0
Bit Number
Bit
Mnemonic
Description
7
A7
Slave address bit 7.
6
A6
Slave address bit 6.
5
A5
Slave address bit 5.
4
A4
Slave address bit 4.
3
A3
Slave address bit 3.
2
A2
Slave address bit 2.
1
A1
Slave address bit 1.
0
GC
General call bit
Clear to disable the general call address recognition.
Set to enable the general call address recognition.
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21. USB Controller
.
21.1
Description
The USB device controller provides the hardware that the AT89C5131 needs to interface a USB
link to a data flow stored in a double port memory (DPRAM).
The USB controller requires a 48 MHz ±0.25% reference clock, which is the output of the
AT89C5131 PLL (see Section “PLL”, page 14) divided by a clock prescaler. This clock is used to
generate a 12 MHz Full-speed bit clock from the received USB differential data and to transmit
data according to full speed USB device tolerance. Clock recovery is done by a Digital Phase
Locked Loop (DPLL) block, which is compliant with the jitter specification of the USB bus.
The Serial Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuffing, CRC
generation and checking, and the serial-parallel data conversion.
The Universal Function Interface (UFI) realizes the interface between the data flow and the Dual
Port RAM.
Figure 21-1. USB Device Controller Block Diagram
48 MHz +/- 0.25%
DPLL 12 MHz
D+
D-
C51
Microcontroller
Interface
USB
D+/DBuffer
UFI
Up to 48 MHz
UC_sysclk
SIE
21.1.1
Serial Interface Engine (SIE)
The SIE performs the following functions:
• NRZI data encoding and decoding.
• Bit stuffing and un-stuffing.
• CRC generation and checking.
• Handshakes.
• TOKEN type identifying.
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• Address checking.
• Clock generation (via DPLL).
Figure 21-2. SIE Block Diagram
End of Packet
Detection
SYNC Detection
Start of Packet
Detection
NRZI ‘NRZ
Bit Un-stuffing
Packet Bit Counter
D+
D-
Clock
Recovery
Clk48
(48 MHz)
SysClk
(12 MHz)
PID Decoder
Address Decoder DataOut
8
Serial to
Parallel
CRC5 and CRC16
Generation/Check
USB Pattern Generator
Parallel to Serial Converter
Bit Stuffing
NRZI Converter
8
DataIn [7:0]
CRC16 Generator
21.1.2
102
Function Interface Unit (FIU)
The Function Interface Unit provides the interface between the AT89C5131 and the SIE. It manages transactions at the packet level with minimal intervention from the device firmware, which
reads and writes the endpoint FIFOs.
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Figure 21-3. UFI Block Diagram
FIU
DPLL
Asynchronous Information
CSREG 0 to 7
Transfer
Transfer
Control
Registers
FSM
Endpoint 5
Bank
Endpoint 4
Endpoint 3
Endpoint 2
Endpoint 1
Endpoint 0
DPR Control
USB Side
SIE
DPR Control
mP side
C51
Microcontroller
Interface
Up to 48 MHz
UC_sysclk
User DPRAM
Figure 21-4. Minimum Intervention from the USB Device Firmware
OUT Transactions:
HOST
UFI
C51
OUT DATA0 (n bytes)
OUT
ACK
DATA1
OUT
interrupt C51
NACK
DATA1
ACK
Endpoint FIFO read (n bytes)
IN Transactions:
HOST
UFI
C51
21.2
21.2.1
IN
IN
NACK
Endpoint FIFO write
IN
DATA1
ACK
DATA1
interrupt C51
Endpoint FIFO write
Configuration
General Configuration
• USB controller enable
Before any USB transaction, the 48 MHz required by the USB controller must be correctly
generated (See “Clock Controller” on page 13.).
The USB controller will be then enabled by setting the EUSB bit in the USBCON register.
• Set address
After a Reset or a USB reset, the software has to set the FEN (Function Enable) bit in the
USBADDR register. This action will allow the USB controller to answer to the requests sent
at the address 0.
When a SET_ADDRESS request has been received, the USB controller must only answer
to the address defined by the request. The new address will be stored in the USBADDR register. The FEN bit and the FADDEN bit in the USBCON register will be set to allow the USB
controller to answer only to requests sent at the new address.
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• Set configuration
The CONFG bit in the USBCON register has to be set after a SET_CONFIGURATION
request with a non-zero value. Otherwise, this bit has to be cleared.
21.2.2
Endpoint Configuration
• Selection of an Endpoint
The endpoint register access is performed using the UEPNUM register. The registers
– UEPSTAX
– UEPCONX
– UEPDATX
– UBYCTLX
– UBYCTHX
These registers correspond to the endpoint whose number is stored in the UEPNUM register. To select an Endpoint, the firmware has to write the endpoint number in the UEPNUM
register.
Figure 21-5. Endpoint Selection
Endpoint 0
UEPSTA0
UEPCON0
UBYCTH0
UEPDAT0
0
SFR registers
UBYCTL0
1
2
3
4
Endpoint 5
UEPSTA5
UEPCON5
UBYCTH5
UEPDAT5
X
UEPSTAX
UEPCONX
UBYCTHX
UEPDATX
UBYCTLX
5
UBYCTL5
UEPNUM
• Endpoint enable
Before using an endpoint, this one will be enabled by setting the EPEN bit in the UEPCONX
register.
An endpoint which is not enabled won’t answer to any USB request. The Default Control
Endpoint (Endpoint 0) will always be enabled in order to answer to USB standard requests.
• Endpoint type configuration
All Standard Endpoints can be configured in Control, Bulk, Interrupt or Isochronous mode.
The Ping-pong Endpoints can be configured in Bulk, Interrupt or Isochronous mode. The
configuration of an endpoint is performed by setting the field EPTYPE with the following
values:
– Control:EPTYPE = 00b
– Isochronous:EPTYPE = 01b
– Bulk:EPTYPE = 10b
– Interrupt:EPTYPE = 11b
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The Endpoint 0 is the Default Control Endpoint and will always be configured in Control type.
• Endpoint direction configuration
For Bulk, Interrupt and Isochronous endpoints, the direction is defined with the EPDIR bit of
the UEPCONX register with the following values:
– IN:EPDIR = 1b
– OUT:EPDIR = 0b
For Control endpoints, the EPDIR bit has no effect.
• Summary of Endpoint Configuration:
Do not forget to select the correct endpoint number in the UEPNUM register before accessing to endpoint specific registers.
Table 21-1.
Summary of Endpoint Configuration
Endpoint Configuration
EPEN
EPDIR
EPTYPE
UEPCONX
Disabled
0b
Xb
XXb
0XXX XXXb
Control
1b
Xb
00b
80h
Bulk-in
1b
1b
10b
86h
Bulk-out
1b
0b
10b
82h
Interrupt-In
1b
1b
11b
87h
Interrupt-Out
1b
0b
11b
83h
Isochronous-In
1b
1b
01b
85h
Isochronous-Out
1b
0b
01b
81h
• Endpoint FIFO reset
Before using an endpoint, its FIFO will be reset. This action resets the FIFO pointer to its
original value, resets the byte counter of the endpoint (UBYCTLX and UBYCTHX registers),
and resets the data toggle bit (DTGL bit in UEPCONX).
The reset of an endpoint FIFO is performed by setting to 1 and resetting to 0 the corresponding bit in the UEPRST register.
For example, in order to reset the Endpoint number 2 FIFO, write 0000 0100b then 0000
0000b in the UEPRST register.
Note that the endpoint reset doesn’t reset the bank number for ping-pong endpoints.
21.3
21.3.1
Read/Write Data FIFO
FIFO Mapping
Depending on the selected endpoint through the UEPNUM register, the UEPDATX register
allows to access the corresponding endpoint data fifo.
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Figure 21-6. Endpoint FIFO Configuration
Endpoint 0
UEPSTA0
UEPCON0
UBYCTH0
UEPDAT0
0
SFR registers
UBYCTL0
1
2
3
4
Endpoint 5
UEPSTA5
UEPCON5
UBYCTH5
UEPDAT5
X
UEPSTAX
UEPCONX
UBYCTHX
UEPDATX
UBYCTLX
5
UBYCTL5
UEPNUM
21.3.2
Read Data FIFO
The read access for each OUT endpoint is performed using the UEPDATX register.
After a new valid packet has been received on an Endpoint, the data are stored into the FIFO
and the byte counter of the endpoint is updated (UBYCTLX and UBYCTHX registers). The firmware has to store the endpoint byte counter before any access to the endpoint FIFO. The byte
counter is not updated when reading the FIFO.
To read data from an endpoint, select the correct endpoint number in UEPNUM and read the
UEPDATX register. This action automatically decreases the corresponding address vector, and
the next data is then available in the UEPDATX register.
21.3.3
Write Data FIFO
The write access for each IN endpoint is performed using the UEPDATX register.
To write a byte into an IN endpoint FIFO, select the correct endpoint number in UEPNUM and
write into the UEPDATX register. The corresponding address vector is automatically increased,
and another write can be carried out.
Warning 1: The byte counter is not updated.
Warning 2: Do not write more bytes than supported by the corresponding endpoint.
21.4
Bulk/Interrupt Transactions
Bulk and Interrupt transactions are managed in the same way.
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21.4.1
Bulk/Interrupt OUT Transactions in Standard Mode
Figure 21-7. Bulk/Interrupt OUT transactions in Standard Mode
HOST
OUT
C51
UFI
DATA0 (n bytes)
ACK
RXOUTB0
Endpoint FIFO read byte 1
OUT
DATA1
Endpoint FIFO read byte 2
NAK
OUT
Endpoint FIFO read byte n
DATA1
Clear RXOUTB0
NAK
OUT
DATA1
ACK
RXOUTB0
Endpoint FIFO read byte 1
An endpoint will be first enabled and configured before being able to receive Bulk or Interrupt
packets.
When a valid OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the corresponding
endpoint, store the number of data bytes by reading the UBYCTLX and UBYCTHX registers. If
the received packet is a ZLP (Zero Length Packet), the UBYCTLX and UBYCTHX register values are equal to 0 and no data has to be read.
When all the endpoint FIFO bytes have been read, the firmware will clear the RXOUTB0 bit to
allow the USB controller to accept the next OUT packet on this endpoint. Until the RXOUTB0 bit
has been cleared by the firmware, the USB controller will answer a NAK handshake for each
OUT requests.
If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be
stored, but the USB controller will consider that the packet is valid if the CRC is correct and the
endpoint byte counter contains the number of bytes sent by the Host.
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21.4.2
Bulk/Interrupt OUT Transactions in Ping-pong Mode
Figure 21-8. Bulk/Interrupt OUT Transactions in Ping-pong Mode
HOST
OUT
C51
UFI
DATA0 (n Bytes)
ACK
RXOUTB0
Endpoint FIFO Bank 0 - Read Byte 1
OUT
Endpoint FIFO Bank 0 - Read Byte 2
DATA1 (m Bytes)
ACK
Endpoint FIFO Bank 0 - Read Byte n
Clear RXOUTB0
OUT
RXOUTB1
DATA0 (p Bytes)
Endpoint FIFO Bank 1 - Read Byte 1
ACK
Endpoint FIFO Bank 1 - Read Byte 2
Endpoint FIFO Bank 1 - Read Byte m
Clear RXOUTB1
RXOUTB0
Endpoint FIFO Bank 0 - Read Byte 1
Endpoint FIFO Bank 0 - Read Byte 2
Endpoint FIFO Bank 0 - Read Byte p
Clear RXOUTB0
An endpoint will be first enabled and configured before being able to receive Bulk or Interrupt
packets.
When a valid OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the
USB controller. This triggers an interrupt if enabled. The firmware has to select the corresponding endpoint, store the number of data bytes by reading the UBYCTLX and UBYCTHX registers.
If the received packet is a ZLP (Zero Length Packet), the UBYCTLX and UBYCTHX register values are equal to 0 and no data has to be read.
When all the endpoint FIFO bytes have been read, the firmware will clear the RXOUB0 bit to
allow the USB controller to accept the next OUT packet on the endpoint bank 0. This action
switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has been cleared by the firmware,
the USB controller will answer a NAK handshake for each OUT requests on the bank 0 endpoint
FIFO.
When a new valid OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by
the USB controller. This triggers an interrupt if enabled. The firmware empties the bank 1 endpoint FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been cleared by the
firmware, the USB controller will answer a NAK handshake for each OUT requests on the bank 1
endpoint FIFO.
The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each new valid
packet receipt.
The firmware has to clear one of these two bits after having read all the data FIFO to allow a new
valid packet to be stored in the corresponding bank.
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A NAK handshake is sent by the USB controller only if the banks 0 and 1 has not been released
by the firmware.
If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be
stored, but the USB controller will consider that the packet is valid if the CRC is correct.
21.4.3
Bulk/Interrupt IN Transactions in Standard Mode
Figure 21-9. Bulk/Interrupt IN Transactions in Standard Mode
UFI
HOST
C51
Endpoint FIFO Write Byte 1
IN
Endpoint FIFO Write Byte 2
NAK
Endpoint FIFO Write Byte n
Set TXRDY
IN
DATA0 (n Bytes)
ACK
TXCMPL
Clear TXCMPL
Endpoint FIFO Write Byte 1
An endpoint will be first enabled and configured before being able to send Bulk or Interrupt
packets.
The firmware will fill the FIFO with the data to be sent and set the TXRDY bit in the UEPSTAX
register to allow the USB controller to send the data stored in FIFO at the next IN request concerning this endpoint. To send a Zero Length Packet, the firmware will set the TXRDY bit without
writing any data into the endpoint FIFO.
Until the TXRDY bit has been set by the firmware, the USB controller will answer a NAK handshake for each IN requests.
To cancel the sending of this packet, the firmware has to reset the TXRDY bit. The packet stored
in the endpoint FIFO is then cleared and a new packet can be written and sent.
When the IN packet has been sent and acknowledged by the Host, the TXCMPL bit in the UEPSTAX register is set by the USB controller. This triggers a USB interrupt if enabled. The firmware
will clear the TXCMPL bit before filling the endpoint FIFO with new data.
The firmware will never write more bytes than supported by the endpoint FIFO.
All USB retry mechanisms are automatically managed by the USB controller.
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21.4.4
Bulk/Interrupt IN Transactions in Ping-pong Mode
Figure 21-10. Bulk/Interrupt IN Transactions in Ping-pong Mode
HOST
C51
UFI
Endpoint FIFO Bank 0 - Write Byte 1
IN
Endpoint FIFO Bank 0 - Write Byte 2
NACK
Endpoint FIFO Bank 0 - Write Byte n
Set TXRDY
IN
Endpoint FIFO Bank 1 - Write Byte 1
DATA0 (n Bytes)
Endpoint FIFO Bank 1 - Write Byte 2
ACK
Endpoint FIFO Bank 1 - Write Byte m
TXCMPL
Clear TXCMPL
Set TXRDY
IN
DATA1 (m Bytes)
Endpoint FIFO Bank 0 - Write Byte 1
Endpoint FIFO Bank 0 - Write Byte 2
ACK
Endpoint FIFO Bank 0 - Write Byte p
TXCMPL
Clear TXCMPL
Set TXRDY
IN
DATA0 (p Bytes)
Endpoint FIFO Bank 1 - Write Byte 1
ACK
An endpoint will be first enabled and configured before being able to send Bulk or Interrupt
packets.
The firmware will fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request
concerning the endpoint. The FIFO banks are automatically switched, and the firmware can
immediately write into the endpoint FIFO bank 1.
When the IN packet concerning the bank 0 has been sent and acknowledged by the Host, the
TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware
will clear the TXCMPL bit before filling the endpoint FIFO bank 0 with new data. The FIFO banks
are then automatically switched.
When the IN packet concerning the bank 1 has been sent and acknowledged by the Host, the
TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware
will clear the TXCMPL bit before filling the endpoint FIFO bank 1 with new data.
The bank switch is performed by the USB controller each time the TXRDY bit is set by the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller
will answer a NAK handshake for each IN requests concerning this bank.
Note that in the example above, the firmware clears the Transmit Complete bit (TXCMPL) before
setting the Transmit Ready bit (TXRDY). This is done in order to avoid the firmware to clear at
the same time the TXCMPL bit for bank 0 and the bank 1.
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The firmware will never write more bytes than supported by the endpoint FIFO.
21.5
21.5.1
Control Transactions
Setup Stage
The DIR bit in the UEPSTAX register will be at 0.
Receiving Setup packets is the same as receiving Bulk Out packets, except that the RXSETUP
bit in the UEPSTAX register is set by the USB controller instead of the RXOUTB0 bit to indicate
that an Out packet with a Setup PID has been received on the Control endpoint. When the
RXSETUP bit has been set, all the other bits of the UEPSTAX register are cleared and an interrupt is triggered if enabled.
The firmware has to read the Setup request stored in the Control endpoint FIFO before clearing
the RXSETUP bit to free the endpoint FIFO for the next transaction.
21.5.2
Data Stage: Control Endpoint Direction
The data stage management is similar to Bulk management.
A Control endpoint is managed by the USB controller as a full-duplex endpoint: IN and OUT. All
other endpoint types are managed as half-duplex endpoint: IN or OUT. The firmware has to
specify the control endpoint direction for the data stage using the DIR bit in the UEPSTAX register.
The firmware has to use the DIR bit before data IN in order to meet the data-toggle
requirements:
• If the data stage consists of INs,
the firmware has to set the DIR bit in the UEPSTAX register before writing into the FIFO and
sending the data by setting to 1 the TXRDY bit in the UEPSTAX register. The IN transaction
is complete when the TXCMPL has been set by the hardware. The firmware will clear the
TXCMPL bit before any other transaction.
• If the data stage consists of OUTs,
the firmware has to leave the DIR bit at 0. The RXOUTB0 bit is set by hardware when a new
valid packet has been received on the endpoint. The firmware must read the data stored into
the FIFO and then clear the RXOUTB0 bit to reset the FIFO and to allow the next transaction.
To send a STALL handshake, see “STALL Handshake” on page 114.
21.5.3
Status Stage
The DIR bit in the UEPSTAX register will be reset at 0 for IN and OUT status stage.
The status stage management is similar to Bulk management.
• For a Control Write transaction or a No-Data Control transaction, the status stage consists of
a IN Zero Length Packet (see “Bulk/Interrupt IN Transactions in Standard Mode” on page
109). To send a STALL handshake, see “STALL Handshake” on page 114.
• For a Control Read transaction, the status stage consists of a OUT Zero Length Packet (see
“Bulk/Interrupt OUT Transactions in Standard Mode” on page 107).
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21.6
21.6.1
Isochronous Transactions
Isochronous OUT Transactions in Standard Mode
An endpoint will be first enabled and configured before being able to receive Isochronous
packets.
When a OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB controller.
This triggers an interrupt if enabled. The firmware has to select the corresponding endpoint,
store the number of data bytes by reading the UBYCTLX and UBYCTHX registers. If the
received packet is a ZLP (Zero Length Packet), the UBYCTLX and UBYCTHX register values
are equal to 0 and no data has to be read.
The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in
FIFO has a corrupted CRC. This bit is updated after each new packet receipt.
When all the endpoint FIFO bytes have been read, the firmware will clear the RXOUTB0 bit to
allow the USB controller to store the next OUT packet data into the endpoint FIFO. Until the
RXOUTB0 bit has been cleared by the firmware, the data sent by the Host at each OUT transaction will be lost.
If the RXOUTB0 bit is cleared while the Host is sending data, the USB controller will store only
the remaining bytes into the FIFO.
If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be
stored, but the USB controller will consider that the packet is valid if the CRC is correct.
21.6.2
Isochronous OUT Transactions in Ping-pong Mode
An endpoint will be first enabled and configured before being able to receive Isochronous
packets.
When a OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the USB
controller. This triggers an interrupt if enabled. The firmware has to select the corresponding
endpoint, store the number of data bytes by reading the UBYCTLX and UBYCTHX registers. If
the received packet is a ZLP (Zero Length Packet), the UBYCTLX and UBYCTHX register values are equal to 0 and no data has to be read.
The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in
FIFO has a corrupted CRC. This bit is updated after each new packet receipt.
When all the endpoint FIFO bytes have been read, the firmware will clear the RXOUB0 bit to
allow the USB controller to store the next OUT packet data into the endpoint FIFO bank 0. This
action switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has been cleared by the firmware, the data sent by the Host on the bank 0 endpoint FIFO will be lost.
If the RXOUTB0 bit is cleared while the Host is sending data on the endpoint bank 0, the USB
controller will store only the remaining bytes into the FIFO.
When a new OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by the
USB controller. This triggers an interrupt if enabled. The firmware empties the bank 1 endpoint
FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been cleared by the firmware, the data sent by the Host on the bank 1 endpoint FIFO will be lost.
The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each new
packet receipt.
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The firmware has to clear one of these two bits after having read all the data FIFO to allow a new
packet to be stored in the corresponding bank.
If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be
stored, but the USB controller will consider that the packet is valid if the CRC is correct.
21.6.3
Isochronous IN Transactions in Standard Mode
An endpoint will be first enabled and configured before being able to send Isochronous packets.
The firmware will fill the FIFO with the data to be sent and set the TXRDY bit in the UEPSTAX
register to allow the USB controller to send the data stored in FIFO at the next IN request concerning this endpoint.
If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB
controller.
When the IN packet has been sent, the TXCMPL bit in the UEPSTAX register is set by the USB
controller. This triggers a USB interrupt if enabled. The firmware will clear the TXCMPL bit
before filling the endpoint FIFO with new data.
The firmware will never write more bytes than supported by the endpoint FIFO
21.6.4
Isochronous IN Transactions in Ping-pong Mode
An endpoint will be first enabled and configured before being able to send Isochronous packets.
The firmware will fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request
concerning the endpoint. The FIFO banks are automatically switched, and the firmware can
immediately write into the endpoint FIFO bank 1.
If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB
controller.
When the IN packet concerning the bank 0 has been sent, the TXCMPL bit is set by the USB
controller. This triggers a USB interrupt if enabled. The firmware will clear the TXCMPL bit
before filling the endpoint FIFO bank 0 with new data. The FIFO banks are then automatically
switched.
When the IN packet concerning the bank 1 has been sent, the TXCMPL bit is set by the USB
controller. This triggers a USB interrupt if enabled. The firmware will clear the TXCMPL bit
before filling the endpoint FIFO bank 1 with new data.
The bank switch is performed by the USB controller each time the TXRDY bit is set by the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller
won’t send anything at each IN requests concerning this bank.
The firmware will never write more bytes than supported by the endpoint FIFO.
21.7
21.7.1
Miscellaneous
USB Reset
The EORINT bit in the USBINT register is set by hardware when a End Of Reset has been
detected on the USB bus. This triggers a USB interrupt if enabled. The USB controller is still
enabled, but all the USB registers are reset by hardware. The firmware will clear the EORINT bit
to allow the next USB reset detection.
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21.7.2
STALL Handshake
This function is only available for Control, Bulk, and Interrupt endpoints.
The firmware has to set the STALLRQ bit in the UEPSTAX register to send a STALL handshake
at the next request of the Host on the endpoint selected with the UEPNUM register. The
RXSETUP, TXRDY, TXCMPL, RXOUTB0 and RXOUTB1 bits must be first reset to 0. The bit
STLCRC is set at 1 by the USB controller when a STALL has been sent. This triggers an interrupt if enabled.
The firmware will clear the STALLRQ and STLCRC bits after each STALL sent.
The STALLRQ bit is cleared automatically by hardware when a valid SETUP PID is received on
a CONTROL type endpoint.
Important note: when a Clear Halt Feature occurs for an endpoint, the firmware will reset this
endpoint using the UEPRST register in order to reset the data toggle management.
21.7.3
Start of Frame Detection
The SOFINT bit in the USBINT register is set when the USB controller detects a Start of Frame
PID. This triggers an interrupt if enabled. The firmware will clear the SOFINT bit to allow the next
Start of Frame detection.
21.7.4
Frame Number
When receiving a Start of Frame, the frame number is automatically stored in the UFNUML and
UFNUMH registers. The CRCOK and CRCERR bits indicate if the CRC of the last Start of
Frame is valid (CRCOK set at 1) or corrupted (CRCERR set at 1). The UFNUML and UFNUMH
registers are automatically updated when receiving a new Start of Frame.
21.7.5
Data Toggle Bit
The Data Toggle bit is set by hardware when a DATA0 packet is received and accepted by the
USB controller and cleared by hardware when a DATA1 packet is received and accepted by the
USB controller. This bit is reset when the firmware resets the endpoint FIFO using the UEPRST
register.
For Control endpoints, each SETUP transaction starts with a DATA0 and data toggling is then
used as for Bulk endpoints until the end of the Data stage (for a control write transfer). The Status stage completes the data transfer with a DATA1 (for a control read transfer).
For Isochronous endpoints, the device firmware will ignore the data-toggle.
21.8
21.8.1
Suspend/Resume Management
Suspend
The Suspend state can be detected by the USB controller if all the clocks are enabled and if the
USB controller is enabled. The bit SPINT is set by hardware when an idle state is detected for
more than 3 ms. This triggers a USB interrupt if enabled.
In order to reduce current consumption, the firmware can put the USB PAD in idle mode, stop
the clocks and put the C51 in Idle or Power-down mode. The Resume detection is still active.
The USB PAD is put in idle mode when the firmware clear the SPINT bit. In order to avoid a new
suspend detection 3ms later, the firmware has to disable the USB clock input using the SUSPCLK bit in the USBCON Register. The USB PAD automatically exits of idle mode when a wakeup event is detected.
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The stop of the 48 MHz clock from the PLL should be done in the following order:
1. Clear suspend interrupt bit in USBINT (required to allow the USB pads to enter power
down mode).
2. Enable USB resume interrupt.
3. Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUSPCLK bit
in the USBCON register.
4. Disable the PLL by clearing the PLLEN bit in the PLLCON register.
5. Make the CPU core enter power down mode by setting PDOWN bit in PCON.
21.8.2
Resume
When the USB controller is in Suspend state, the Resume detection is active even if all the
clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit is set by
hardware when a non-idle state occurs on the USB bus. This triggers an interrupt if enabled.
This interrupt wakes up the CPU from its Idle or Power-down state and the interrupt function is
then executed. The firmware will first enable the 48 MHz generation and then reset to 0 the
SUSPCLK bit in the USBCON register if needed.
The firmware has to clear the SPINT bit in the USBINT register before any other USB operation
in order to wake up the USB controller from its Suspend mode.
The USB controller is then re-activated.
Figure 21-11. Example of a Suspend/Resume Management
USB Controller Init
SPINT
Detection of a SUSPEND State
Clear SPINT
Set SUSPCLK
Disable PLL
microcontroller in Power-down
WUPCPU
Detection of a RESUME State
Enable PLL
Clear SUSPCLK
Clear WUPCPU Bit
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21.8.3
Upstream Resume
A USB device can be allowed by the Host to send an upstream resume for Remote Wake Up
purpose.
When the USB controller receives the SET_FEATURE request: DEVICE_REMOTE_WAKEUP,
the firmware will set to 1 the RMWUPE bit in the USBCON register to enable this functionality.
RMWUPE value will be 0 in the other cases.
If the device is in SUSPEND mode, the USB controller can send an upstream resume by clearing first the SPINT bit in the USBINT register and by setting then to 1 the SDRMWUP bit in the
USBCON register. The USB controller sets to 1 the UPRSM bit in the USBCON register. All
clocks must be enabled first. The Remote Wake is sent only if the USB bus was in Suspend
state for at least 5 ms. When the upstream resume is completed, the UPRSM bit is reset to 0 by
hardware. The firmware will then clear the SDRMWUP bit.
Figure 21-12. Example of REMOTE WAKEUP Management
USB Controller Init
SET_FEATURE: DEVICE_REMOTE_WAKEUP
Set RMWUPE
SPINT
Detection of a SUSPEND State
Suspend Management
Need USB Resume
Enable Clocks
Clear SPINT
UPRSM = 1
Set SDMWUP
UPRSM
Upstream RESUME Sent
Clear SDRMWUP
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21.9
Detach Simulation
In order to be re-enumerated by the Host, the AT83C5134/35/36 has the possibility to simulate a
DETACH - ATTACH of the USB bus.
The VREF output voltage is between 3.0V and 3.6V. This output can be connected to the D+ pullup as shown in Figure 21-13. This output can be put in high-impedance when the DETACH bit is
set to 1 in the USBCON register. Maintaining this output in high impedance for more than 3 µs
will simulate the disconnection of the device. When resetting the DETACH bit, an attach is then
simulated.
Figure 21-13. Example of VREF Connection
VREF
1.5 kW
1
2
DD+
3
4
AT89C5131
VCC
DD+
GND
USB-B Connector
Figure 21-14. Disconnect Timing
D+
VIHZ(min)
VIL
VSS
D> = 2,5 ms
Disconnect
Detected
Device
Disconnected
21.10 USB Interrupt System
21.10.1
Interrupt System Priorities
Figure 21-15. USB Interrupt Control System
D+
D-
00
01
10
11
USB
Controller
EUSB
EA
IE1.6
IE0.7
Interrupt Enable
IPH/L
Priority Enable
Lowest Priority Interrupts
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Table 21-2.
21.10.2
Priority Levels
IPHUSB
IPLUSB
USB Priority Level
0
0
0
0
1
1
1
0
2
1
1
3
Lowest
Highest
USB Interrupt Control System
As shown in Figure 21-16, many events can produce a USB interrupt:
• TXCMPL: Transmitted In Data (see Table 21-9 on page 125). This bit is set by hardware
when the Host accept a In packet.
• RXOUTB0: Received Out Data Bank 0 (see Table 21-9 on page 125). This bit is set by
hardware when an Out packet is accepted by the endpoint and stored in bank 0.
• RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints) (see Table 21-9 on
page 125). This bit is set by hardware when an Out packet is accepted by the endpoint and
stored in bank 1.
• RXSETUP: Received Setup (see Table 21-9 on page 125). This bit is set by hardware when
an SETUP packet is accepted by the endpoint.
• STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (see Table 21-9 on page
125). This bit is set by hardware when a STALL handshake has been sent as requested by
STALLRQ, and is reset by hardware when a SETUP packet is received.
• SOFINT: Start of Frame Interrupt (See “USBIEN Register USBIEN (S:BEh) USB Global
Interrupt Enable Register” on page 122.). This bit is set by hardware when a USB Start of
Frame packet has been received.
• WUPCPU: Wake-Up CPU Interrupt (See “USBIEN Register USBIEN (S:BEh) USB Global
Interrupt Enable Register” on page 122.). This bit is set by hardware when a USB resume is
detected on the USB bus, after a SUSPEND state.
• SPINT: Suspend Interrupt (See “USBIEN Register USBIEN (S:BEh) USB Global Interrupt
Enable Register” on page 122.). This bit is set by hardware when a USB suspend is detected
on the USB bus.
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Figure 21-16. USB Interrupt Control Block Diagram
Endpoint X (X = 0..5)
TXCMP
UEPSTAX.0
RXOUTB0
UEPSTAX.1
EPXINT
UEPINT.X
RXOUTB1
UEPSTAX.6
EPXIE
UEPIEN.X
RXSETUP
UEPSTAX.2
STLCRC
UEPSTAX.3
WUPCPU
USBINT.5
EWUPCPU
USBIEN.5
EUSB
IE1.6
EORINT
USBINT.4
EEORINT
USBIEN.4
SOFINT
USBINT.3
ESOFINT
USBIEN.3
SPINT
USBINT.0
ESPINT
USBIEN.0
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21.11 USB Registers
Table 21-3.
USBCON Register
USBCON (S:BCh)
USB Global Control Register
7
6
5
4
3
2
1
0
USBE
SUSPCLK
SDRMWUP
DETACH
UPRSM
RMWUPE
CONFG
FADDEN
Bit Number
Bit Mnemonic
7
USBE
6
SUSPCLK
5
USB Enable
Set this bit to enable the USB controller.
Clear this bit to disable and reset the USB controller, to disable the USB
transceiver an to disable the USB controller clock inputs.
Suspend USB Clock
Set this bit to disable the 48 MHz clock input (Resume Detection is still active).
Clear this bit to enable the 48 MHz clock input.
SDRMWUP
Send Remote Wake Up
Set this bit to force an external interrupt on the USB controller for Remote Wake
UP purpose.
An upstream resume is send only if the bit RMWUPE is set, all USB clocks are
enabled AND the USB bus was in SUSPEND state for at least 5 ms. See UPRSM
below.
This bit is cleared by software.
DETACH
Detach Command
Set this bit to simulate a Detach on the USB line. The VREF pin is then in a floating
state.
Clear this bit to maintain VREF at high level.
UPRSM
Upstream Resume (read only)
This bit is set by hardware when SDRMWUP has been set and if RMWUPE is
enabled.
This bit is cleared by hardware after the upstream resume has been sent.
4
3
2
Description
RMWUPE
Remote Wake-Up Enable
Set this bit to enabled request an upstream resume signaling to the host.
Clear this bit otherwise.
Note: Do not set this bit if the host has not set the DEVICE_REMOTE_WAKEUP
feature for the device.
1
0
CONFG
Configured
This bit will be set by the device firmware after a SET_CONFIGURATION request
with a non-zero value has been correctly processed.
It will be cleared by the device firmware when a SET_CONFIGURATION request
with a zero value is received. It is cleared by hardware on hardware reset or when
an USB reset is detected on the bus (SE0 state for at least 32 Full Speed bit times:
typically 2.7 µs).
FADDEN
Function Address Enable
This bit will be set by the device firmware after a successful status phase of a
SET_ADDRESS transaction.
It will not be cleared afterwards by the device firmware. It is cleared by hardware
on hardware reset or when an USB reset is received (see above). When this bit is
cleared, the default function address is used (0).
Reset Value = 00h
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Table 21-4.
USBINT Register
USBINT (S:BDh)
USB Global Interrupt Register
7
6
5
4
3
2
1
0
-
-
WUPCPU
EORINT
SOFINT
-
-
SPINT
Bit Number
Bit
Mnemonic
Description
7-6
-
5
WUPCPU
Reserved
The value read from these bits is always 0. Do not set these bits.
Wake Up CPU Interrupt
This bit is set by hardware when the USB controller is in SUSPEND state and is reactivated by a non-idle signal FROM USB line (not by an upstream resume). This
triggers a USB interrupt when EWUPCPU is set in Table 21-5 on page 122.
When receiving this interrupt, user has to enable all USB clock inputs.
This bit will be cleared by software (USB clocks must be enabled before).
EORINT
End Of Reset Interrupt
This bit is set by hardware when a End Of Reset has been detected by the USB
controller. This triggers a USB interrupt when EEORINT is set (see Figure 21-5 on page
122).
This bit will be cleared by software.
3
SOFINT
Start of Frame Interrupt
This bit is set by hardware when an USB Start of Frame PID (SOF) has been detected.
This triggers a USB interrupt when ESOFINT is set (see Table 21-5 on page 122).
This bit will be cleared by software.
2
-
Reserved
The value read from this bit is always 0. Do not set this bit.
1
-
Reserved
The value read from this bit is always 0. Do not set this bit.
4
0
SPINT
Suspend Interrupt
This bit is set by hardware when a USB Suspend (Idle bus for three frame periods: a J
state for 3 ms) is detected. This triggers a USB interrupt when ESPINT is set in see
Table 21-5 on page 122.
This bit will be cleared by software BEFORE any other USB operation to re-activate the
macro.
Reset Value = 00h
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Table 21-5.
USBIEN Register
USBIEN (S:BEh)
USB Global Interrupt Enable Register
7
6
5
4
3
2
1
0
-
-
EWUPCPU
EEORINT
ESOFINT
-
-
ESPINT
Bit Number
Bit Mnemonic
7-6
-
5
EWUPCPU
Description
Reserved
The value read from these bits is always 0. Do not set these bits.
Enable Wake Up CPU Interrupt
Set this bit to enable Wake Up CPU Interrupt. (See “USBIEN Register USBIEN
(S:BEh) USB Global Interrupt Enable Register” on page 122.)
Clear this bit to disable Wake Up CPU Interrupt.
EEOFINT
Enable End Of Reset Interrupt
Set this bit to enable End Of Reset Interrupt. (See “USBIEN Register USBIEN
(S:BEh) USB Global Interrupt Enable Register” on page 122.). This bit is set after
reset.
Clear this bit to disable End Of Reset Interrupt.
3
ESOFINT
Enable SOF Interrupt
Set this bit to enable SOF Interrupt. (See “USBIEN Register USBIEN (S:BEh) USB
Global Interrupt Enable Register” on page 122.).
Clear this bit to disable SOF Interrupt.
2
-
1
-
4
0
ESPINT
Reserved
The value read from these bits is always 0. Do not set these bits.
Enable Suspend Interrupt
Set this bit to enable Suspend Interrupts (see the “USBIEN Register USBIEN
(S:BEh) USB Global Interrupt Enable Register” on page 122).
Clear this bit to disable Suspend Interrupts.
Reset Value = 10h
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Table 21-6.
USBADDR Register
USBADDR (S:C6h)
USB Address Register
7
6
5
4
3
2
1
0
FEN
UADD6
UADD5
UADD4
UADD3
UADD2
UADD1
UADD0
Bit Number
Bit
Mnemonic
Description
7
FEN
6-0
UADD[6:0]
Function Enable
Set this bit to enable the address filtering function.
Cleared this bit to disable the function.
USB Address
This field contains the default address (0) after power-up or USB bus reset.
It will be written with the value set by a SET_ADDRESS request received by the device
firmware.
Reset Value = 80h
Table 21-7.
UEPNUM Register
UEPNUM (S:C7h)
USB Endpoint Number
7
6
5
4
3
2
1
0
-
-
-
-
EPNUM3
EPNUM2
EPNUM1
EPNUM0
Bit Number
Bit Mnemonic
7-4
-
3-0
EPNUM[3:0]
Description
Reserved
The value read from these bits is always 0. Do not set these bits.
Endpoint Number
Set this field with the number of the endpoint which will be accessed when reading
or writing to, UEPDATX Register UEPDATX (S:CFh) USB FIFO Data Endpoint X (X
= EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number),
UBYCTLX Register UBYCTLX (S:E2h) USB Byte Count Low Register X (X =
EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number),
UBYCTHX Register UBYCTHX (S:E3h) USB Byte Count High Register X (X =
EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number) or
UEPCONX Register UEPCONX (S:D4h) USB Endpoint X Control Register. This
value can be 0, 1, 2, 3, 4, or 5.
Reset Value = 00h
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Table 21-8.
UEPCONX Register
UEPCONX (S:D4h)
USB Endpoint X Control Register
7
6
5
4
3
2
1
0
EPEN
-
-
-
DTGL
EPDIR
EPTYPE1
EPTYPE0
Bit Number
Endpoint Enable
Set this bit to enable the endpoint according to the device configuration. Endpoint 0 will
always be enabled after a hardware or USB bus reset and participate in the device
configuration.
Clear this bit to disable the endpoint according to the device configuration.
7
EPEN
6
-
Reserved
The value read from this bit is always 0. Do not set this bit.
5
-
Reserved
The value read from this bit is always 0. Do not set this bit.
4
-
Reserved
The value read from this bit is always 0. Do not set this bit.
3
DTGL
Data Toggle (Read-only)
This bit is set by hardware when a valid DATA0 packet is received and accepted.
This bit is cleared by hardware when a valid DATA1 packet is received and accepted.
EPDIR
Endpoint Direction
Set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints.
Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.
This bit has no effect for Control endpoints.
2
1-0
Note:
Bit Mnemonic Description
EPTYPE[1:0]
Endpoint Type
Set this field according to the endpoint configuration (Endpoint 0 will always be
configured as control):
00Control endpoint
01Isochronous endpoint
10Bulk endpoint
11Interrupt endpoint
1. (X = EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number)
Reset Value = 80h when UEPNUM = 0 (default Control Endpoint)
Reset Value = 00h otherwise for all other endpoints
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Table 21-9.
UEPSTAX (S:CEh) USB Endpoint X Status Register
7
6
5
4
3
2
1
0
DIR
RXOUTB1
STALLRQ
TXRDY
STL/CRC
RXSETUP
RXOUTB0
TXCMP
Bit Number
Bit
Mnemonic
Description
DIR
Control Endpoint Direction
This bit is used only if the endpoint is configured in the control type (seeSection “UEPCONX Register UEPCONX (S:D4h)
USB Endpoint X Control Register”).
This bit determines the Control data and status direction.
The device firmware will set this bit ONLY for the IN data stage, before any other USB operation. Otherwise, the device
firmware will clear this bit.
6
RXOUTB1
Received OUT Data Bank 1 for Endpoints 4, 5 and 6 (Ping-pong mode)
This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 1 (only in Ping-pong
mode). Then, the endpoint interrupt is triggered if enabled (see“UEPINT Register UEPINT (S:F8h read-only) USB
Endpoint Interrupt Register” on page 128) and all the following OUT packets to the endpoint bank 1 are rejected (NAK’ed)
until this bit has been cleared, excepted for Isochronous Endpoints.
This bit will be cleared by the device firmware after reading the OUT data from the endpoint FIFO.
5
STALLRQ
Stall Handshake Request
Set this bit to request a STALL answer to the host for the next handshake.Clear this bit otherwise.
For CONTROL endpoints: cleared by hardware when a valid SETUP PID is received.
7
4
3
2
1
0
TXRDY
TX Packet Ready
Set this bit after a packet has been written into the endpoint FIFO for IN data transfers. Data will be written into the
endpoint FIFO only after this bit has been cleared. Set this bit without writing data to the endpoint FIFO to send a Zero
Length Packet.
This bit is cleared by hardware, as soon as the packet has been sent for Isochronous endpoints, or after the host has
acknowledged the packet for Control, Bulk and Interrupt endpoints. When this bit is cleared, the endpoint interrupt is
triggered if enabled (see“UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register” on page 128).
STLCRC
Stall Sent/CRC error flag
- For Control, Bulk and Interrupt Endpoints:
This bit is set by hardware after a STALL handshake has been sent as requested by STALLRQ. Then, the endpoint
interrupt is triggered if enabled (see“UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register” on
page 128)
It will be cleared by the device firmware.
- For Isochronous Endpoints (Read-Only):
This bit is set by hardware if the last received data is corrupted (CRC error on data).
This bit is updated by hardware when a new data is received.
RXSETUP
Received SETUP
This bit is set by hardware when a valid SETUP packet has been received from the host. Then, all the other bits of the
register are cleared by hardware and the endpoint interrupt is triggered if enabled (see“UEPINT Register UEPINT (S:F8h
read-only) USB Endpoint Interrupt Register” on page 128).
It will be cleared by the device firmware after reading the SETUP data from the endpoint FIFO.
RXOUTB0
Received OUT Data Bank 0 (see also RXOUTB1 bit for Ping-pong Endpoints)
This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 0. Then, the endpoint
interrupt is triggered if enabled (see“UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register” on
page 128) and all the following OUT packets to the endpoint bank 0 are rejected (NAK’ed) until this bit has been cleared,
excepted for Isochronous Endpoints. However, for control endpoints, an early SETUP transaction may overwrite the
content of the endpoint FIFO, even if its Data packet is received while this bit is set.
This bit will be cleared by the device firmware after reading the OUT data from the endpoint FIFO.
TXCMPL
Transmitted IN Data Complete
This bit is set by hardware after an IN packet has been transmitted for Isochronous endpoints and after it has been
accepted (ACK’ed) by the host for Control, Bulk and Interrupt endpoints. Then, the endpoint interrupt is triggered if
enabled (see“UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register” on page 128).
This bit will be cleared by the device firmware before setting TXRDY.
Reset Value = 00h
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Table 21-10. UEPDATX Register
UEPDATX (S:CFh)
USB FIFO Data Endpoint X (X = EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number)
7
6
5
4
3
2
1
0
FDAT7
FDAT6
FDAT5
FDAT4
FDAT3
FDAT2
FDAT1
FDAT0
Bit Number
Bit Mnemonic
7-0
FDAT[7:0]
Description
Endpoint X FIFO data
Data byte to be written to FIFO or data byte to be read from the FIFO, for the Endpoint X (see EPNUM).
Reset Value = XXh
Table 21-11. UBYCTLX Register
UBYCTLX (S:E2h)
USB Byte Count Low Register X (X = EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number)
7
6
5
4
3
2
1
0
BYCT7
BYCT6
BYCT5
BYCT4
BYCT3
BYCT2
BYCT1
BYCT0
Bit Number
Bit Mnemonic
7-0
BYCT[7:0]
Description
Byte Count LSB
Least Significant Byte of the byte count of a received data packet. The most significant part is provided by the
UBYCTHX Register UBYCTHX (S:E3h) USB Byte Count High Register X (X = EPNUM set in UEPNUM Register
UEPNUM (S:C7h) USB Endpoint Number) (see Figure 21-11 on page 126). This byte count is equal to the
number of data bytes received after the Data PID.
Reset Value = 00h
Table 21-12. UBYCTHX Register
UBYCTHX (S:E3h)
USB Byte Count High Register X (X = EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
BYCT9
BYCT8
Bit Number
Bit Mnemonic
7-2
-
2-0
Description
Reserved
The value read from these bits is always 0. Do not set these bits.
BYCT[10:8]
Byte Count MSB
Most Significant Byte of the byte count of a received data packet. The Least significant part is provided by
UBYCTLX Register UBYCTLX (S:E2h) USB Byte Count Low Register X (X = EPNUM set in UEPNUM
Register UEPNUM (S:C7h) USB Endpoint Number) (see Figure 21-11 on page 126).
Reset Value = 00h
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Table 21-13. UEPRST Register
UEPRST (S:D5h)
USB Endpoint FIFO Reset Register
7
6
5
4
3
2
1
0
-
-
EP5RST
EP4RST
EP3RST
EP2RST
EP1RST
EP0RST
Bit Number
Bit
Mnemonic
Description
7
-
Reserved
The value read from this bit is always 0. Do not set this bit.
6
-
Reserved
The value read from this bit is always 0. Do not set this bit.
5
4
3
2
1
0
EP5RST
Endpoint 5 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset
or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
EP4RST
Endpoint 4 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset
or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
EP3RST
Endpoint 3 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset
or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
EP2RST
Endpoint 2 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset
or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
EP1RST
Endpoint 1 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset
or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
EP0RST
Endpoint 0 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset
or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Reset Value = 00h
127
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Table 21-14. UEPINT Register
UEPINT (S:F8h read-only)
USB Endpoint Interrupt Register
7
6
5
4
3
2
1
0
-
-
EP5INT
EP4INT
EP3INT
EP2INT
EP1INT
EP0INT
Bit Number
Bit
Mnemonic
Description
7
-
Reserved
The value read from this bit is always 0. Do not set this bit.
6
-
Reserved
The value read from this bit is always 0. Do not set this bit.
Endpoint 5 Interrupt
5
EP5INT
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 5. The endpoint interrupt sources are in the UEPSTAX register and can be:
TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP5IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
Endpoint 4 Interrupt
4
EP4INT
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 4. The endpoint interrupt sources are in the UEPSTAX register and can be:
TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP4IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
Endpoint 3 Interrupt
3
EP3INT
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 3. The endpoint interrupt sources are in the UEPSTAX register and can be:
TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP3IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
Endpoint 2 Interrupt
2
EP2INT
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 2. The endpoint interrupt sources are in the UEPSTAX register and can be:
TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP2IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
Endpoint 1 Interrupt
1
EP1INT
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 1. The endpoint interrupt sources are in the UEPSTAX register and can be:
TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP1IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
Endpoint 0 Interrupt
0
EP0INT
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 0. The endpoint interrupt sources are in the UEPSTAX register and can be:
TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP0IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
Reset Value = 00h
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Table 21-15. UEPIEN Register
UEPIEN (S:C2h)
USB Endpoint Interrupt Enable Register
7
6
5
4
3
2
1
0
-
-
EP5INTE
EP4INTE
EP3INTE
EP2INTE
EP1INTE
EP0INTE
Bit Number
Bit
Mnemonic
Description
7
-
Reserved
The value read from this bit is always 0. Do not set this bit.
6
-
Reserved
The value read from this bit is always 0. Do not set this bit.
5
EP5INTE
Endpoint 5 Interrupt Enable
Set this bit to enable the interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
4
EP4INTE
Endpoint 4 Interrupt Enable
Set this bit to enable the interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
3
EP3INTE
Endpoint 3 Interrupt Enable
Set this bit to enable the interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
2
EP2INTE
Endpoint 2 Interrupt Enable
Set this bit to enable the interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
1
EP1INTE
Endpoint 1 Interrupt Enable
Set this bit to enable the interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
0
EP0INTE
Endpoint 0 Interrupt Enable
Set this bit to enable the interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
Reset Value = 00h
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Table 21-16. UFNUMH Register
UFNUMH (S:BBh, read-only)
USB Frame Number High Register
7
6
5
4
3
2
1
0
-
-
CRCOK
CRCERR
-
FNUM10
FNUM9
FNUM8
Bit
Number
5
Bit Mnemonic Description
CRCOK
4
CRCERR
3
-
2-0
Frame Number CRC OK
This bit is set by hardware when a new Frame Number in Start of Frame Packet is
received without CRC error.
This bit is updated after every Start of Frame packet receipt.
Important note: the Start of Frame interrupt is generated just after the PID receipt.
Frame Number CRC Error
This bit is set by hardware when a corrupted Frame Number in Start of Frame packet is
received.
This bit is updated after every Start of Frame packet receipt.
Important note: the Start of Frame interrupt is generated just after the PID receipt.
Reserved
The value read from this bit is always 0. Do not set this bit.
FNUM[10:8]
Frame Number
FNUM[10:8] are the upper 3 bits of the 11-bit Frame Number (see the “UFNUML Register
UFNUML (S:BAh, read-only) USB Frame Number Low Register” on page 130). It is
provided in the last received SOF packet (see SOFINT in the “USBIEN Register USBIEN
(S:BEh) USB Global Interrupt Enable Register” on page 122). FNUM is updated if a
corrupted SOF is received.
Reset Value = 00h
Table 21-17. UFNUML Register
UFNUML (S:BAh, read-only)
USB Frame Number Low Register
7
6
5
4
3
2
1
0
FNUM7
FNUM6
FNUM5
FNUM4
FNUM3
FNUM2
FNUM1
FNUM0
Bit Number
Bit
Mnemonic
Description
7-0
FNUM[7:0]
Frame Number
FNUM[7:0] are the lower 8 bits of the 11-bit Frame Number (See “UFNUMH Register
UFNUMH (S:BBh, read-only) USB Frame Number High Register” on page 130.).
Reset Value = 00h
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22. Reset
22.1
Introduction
The reset sources are: Power Management, Hardware Watchdog, PCA Watchdog and Reset
input.
Figure 22-1. Reset schematic
Power
Monitor
Hardware
Watchdog
Internal Reset
PCA
Watchdog
RST
22.2
Reset Input
The Reset input can be used to force a reset pulse longer than the internal reset controlled by
the Power Monitor. RST input has a pull-up resistor allowing power-on reset by simply connecting an external capacitor to V S S as shown in Figure 22-2. Resistor value and input
characteristics are discussed in the Section “DC Characteristics” of the AT83C5134/35/36
datasheet.
Figure 22-2. Reset Circuitry and Power-On Reset
VCC
RST
RRST
+
RST
To internal reset
a. RST input circuitry
22.3
VSS
b. Power-on Reset
Reset Output
As detailed in Section “Hardware Watchdog Timer”, page 138, the WDT generates a 96-clock
period pulse on the RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit, a 1 kΩ resistor must be
added as shown Figure 22-3.
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Figure 22-3. Recommended Reset Output Schematic
VDD
RST
RST
1K
AT89C5131A-M
VSS
+
VSS
132
To other
on-board
circuitry
AT83C5134/35/36
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AT83C5134/35/36
23. Power Monitor
The POR/PFD function monitors the internal power-supply of the CPU core memories and the
peripherals, and if needed, suspends their activity when the internal power supply falls below a
safety threshold. This is achieved by applying an internal reset to them.
By generating the Reset the Power Monitor insures a correct start up when AT89C5131 is powered up.
23.1
Description
In order to startup and maintain the microcontroller in correct operating mode, VCC has to be stabilized in the VCC operating range and the oscillator has to be stabilized with a nominal amplitude
compatible with logic level VIH/VIL.
These parameters are controlled during the three phases: power-up, normal operation and
power going down. See Figure 23-1.
Figure 23-1. Power Monitor Block Diagram
VCC
CPU core
Power On Reset
Power Fail Detect
Voltage Regulator
Regulated
Supply
Memories
Peripherals
(1)
XTAL1
Internal Reset
RST pin
PCA
Watchdog
Note:
Hardware
Watchdog
1. Once XTAL1 High and low levels reach above and below VIH/VIL. a 1024 clock period delay
will extend the reset coming from the Power Fail Detect. If the power falls below the Power Fail
Detect threshold level, the Reset will be applied immediately.
The Voltage regulator generates a regulated internal supply for the CPU core the memories and
the peripherals. Spikes on the external Vcc are smoothed by the voltage regulator.
The Power fail detect monitor the supply generated by the voltage regulator and generate a
reset if this supply falls below a safety threshold as illustrated in the Figure 23-2 below.
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Figure 23-2. Power Fail Detect
Vcc
t
Reset
Vcc
When the power is applied, the Power Monitor immediately asserts a reset. Once the internal
supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL
clock input. The internal reset will remain asserted until the Xtal1 levels are above and below
VIH and VIL. Further more. An internal counter will count 1024 clock periods before the reset is
de-asserted.
If the internal power supply falls below a safety level, a reset is immediately asserted.
.
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24. Power Management
24.1
Idle Mode
An instruction that sets PCON.0 indicates that it is the last instruction to be executed before
going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but
not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety:
the Stack Pointer, Program Counter, Program Status Word, Accumulator and all other registers
maintain their data during Idle. The port pins hold the logical states they had at the time Idle was
activated. ALE and PSEN hold at logic high level.
There are two ways to terminate the Idle mode. Activation of any enabled interrupt will cause
PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced,
and following RETI the next instruction to be executed will be the one following the instruction
that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during normal operation or during an Idle. For example, an instruction that activates Idle can also set one
or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is
still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset.
24.2
Power-down Mode
To save maximum power, a power-down mode can be invoked by software (refer to Table 13,
PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked power-down
mode is the last instruction executed. The internal RAM and SFRs retain their value until the
power-down mode is terminated. VCC can be lowered to save further power. Either a hardware
reset or an external interrupt can cause an exit from power-down. To properly terminate powerdown, the reset or external interrupt should not be executed before VCC is restored to its normal
operating level and must be held active long enough for the oscillator to restart and stabilize.
Only:
• external interrupt INT0,
• external interrupt INT1,
• Keyboard interrupt and
• USB Interrupt
are useful to exit from power-down. For that, interrupt must be enabled and configured as level
or edge sensitive interrupt input. When Keyboard Interrupt occurs after a power down mode,
1024 clocks are necessary to exit to power-down mode and enter in operating mode.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed
in Figure 24-1. When both interrupts are enabled, the oscillator restarts as soon as one of the
two inputs is held low and power-down exit will be completed when the first input is released. In
this case, the higher priority interrupt service routine is executed. Once the interrupt is serviced,
the next instruction to be executed after RETI will be the one following the instruction that put
AT83C5134/35/36 into power-down mode.
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Figure 24-1. Power-down Exit Waveform
INT0
INT1
XTAL
Active Phase
Power-down Phase
Oscillator restart Phase
Active Phase
Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect the SFRs.
Exit from power-down by either reset or external interrupt does not affect the internal RAM
content.
Note:
If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is
unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is
not entered.
This table shows the state of ports during idle and power-down modes.
Table 24-1.
Mode
Program
Memory
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
PORTI2
Idle
Internal
1
1
Port
Data(1)
Port Data
Port Data
Port Data
Port Data
Idle
External
1
1
Floating
Port Data
Address
Port Data
Port Data
Power-down
Internal
0
0
Port
Data(1)
Port Data
Port Data
Port Data
Port Data
Power-down
External
0
0
Floating
Port Data
Port Data
Port Data
Port Data
Note:
136
State of Ports
1. Port 0 can force a 0 level. A “one” will leave port floating.
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24.3
Registers
Table 24-2. PCON Register
PCON (S:87h)
Power Control Register
7
6
5
4
3
2
1
0
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
Bit Number
Bit
Mnemonic
Description
7
SMOD1
Serial Port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6
SMOD0
Serial Port Mode bit 0
Set to select FE bit in SCON register.
Clear to select SM0 bit in SCON register
5
-
Reserved
The value read from this bit is always 0. Do not set this bit.
4
POF
Power-Off Flag
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by
software.
Clear to recognize next reset type.
3
GF1
General-purpose Flag 1
Set by software for general-purpose usage.
Cleared by software for general-purpose usage.
2
GF0
General-purpose Flag 0
Set by software for general-purpose usage.
Cleared by software for general-purpose usage.
1
PD
Power-down mode bit
Set this bit to enter in power-down mode.
Cleared by hardware when reset occurs.
0
IDL
Idle mode bit
Set this bit to enter in Idle mode.
Cleared by hardware when interrupt or reset occurs.
Reset Value = 10h
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25. Hardware Watchdog Timer
The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT
(WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user
must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is
enabled, it will increment every machine cycle while the oscillator is running and there is no way
to disable the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET LOW pulse at the RST-pin.
25.1
Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to
WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH)
and this will reset the device. When WDT is enabled, it will increment every machine cycle while
the oscillator is running. This means the user must reset the WDT at least every 16383 machine
cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write
only register. The WDT counter cannot be read or written. When WDT overflows, it will generate
an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x TCLK PERIPH, where
TCLK PERIPH = 1/FCLK PERIPH. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.
To have a more powerful WDT, a 27 counter has been added to extend the Time-out capability,
ranking from 16 ms to 2s at FOSCA = 12 MHz. To manage this feature, refer to WDTPRG register
description, Table 25-2.
Table 25-1.
WDTRST Register
WDTRST - Watchdog Reset Register (0A6h)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Reset Value = XXXX XXXXb
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.
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Table 25-2.
WDTPRG Register
WDTPRG - Watchdog Timer Out Register (0A7h)
7
6
5
4
3
2
1
0
-
-
-
-
-
S2
S1
S0
Bit
Bit
Number
Mnemonic
7
-
6
-
5
-
4
-
3
-
2
S2
WDT Time-out select bit 2
1
S1
WDT Time-out select bit 1
0
S0
WDT Time-out select bit 0
Description
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
S2 S1 S0 Selected Time-out
0 0 0 16384x2^(214 - 1) machine cycles, 16.3 ms at FOSC = 12 MHz
0 0 1 16384x2^(215 - 1) machine cycles, 32.7 ms at FOSC = 12 MHz
0 1 0 16384x2^(216 - 1) machine cycles, 65.5 ms at FOSC = 12 MHz
0 1 1 16384x2^(217 - 1) machine cycles, 131 ms at FOSC = 12 MHz
1 0 0 16384x2^(218 - 1) machine cycles, 262 ms at FOSC = 12 MHz
1 0 1 16384x2^(219 - 1) machine cycles, 542 ms at FOSC = 12 MHz
1 1 0 16384x2^(220 - 1) machine cycles, 1.05 s at FOSC = 12 MHz
1 1 1 16384x2^(221 - 1) machine cycles, 2.09 s at FOSC = 12 MHz
16384x2^S machine cycles
Reset value = XXXX X000
25.2
WDT During Power-down and Idle
In Power-down mode the oscillator stops, which means the WDT also stops. While in Powerdown mode the user does not need to service the WDT. There are 2 methods of exiting Powerdown mode: by a hardware reset or via a level activated external interrupt which is enabled prior
to entering Power-down mode. When Power-down is exited with hardware reset, servicing the
WDT should occur as it normally should whenever the AT83C5134/35/36 is reset. Exiting
Power-down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent
the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until
the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service
routine.
To ensure that the WDT does not overflow within a few states of exiting of power-down, it is better to reset the WDT just before entering power-down.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
AT83C5134/35/36 while in Idle mode, the user should always set up a timer that will periodically
exit Idle, service the WDT, and re-enter Idle mode.
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26. Reduced EMI Mode
The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still
generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit.
The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer
output but remains active during MOVX and MOVC instructions and external fetches. During
ALE disabling, ALE pin is weakly pulled high.
Table 26-1. AUXR Register
AUXR - Auxiliary Register (8Eh)
7
6
5
4
3
2
1
0
DPU
-
M0
-
XRS1
XRS0
EXTRAM
AO
Bit
Bit
Number
Mnemonic
7
DPU
6
-
Description
Disable Weak Pull Up
Cleared to enabled weak pull up on standard Ports
Set to disable weak pull up on standard Ports
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Pulse length
5
M0
Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock periods
(default).
Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods.
Reserved
4
-
3
XRS1
ERAM Size
2
XRS0
XRS1
0
0
1
1
1
EXTRAM
The value read from this bit is indeterminate. Do not set this bit.
XRS0
0
1
0
1
ERAM size
256 bytes
512 bytes
768 bytes
1024 bytes (default)
EXTRAM bit
Cleared to access internal ERAM using MOVX at Ri at DPTR.
Set to access external memory.
0
AO
ALE Output bit
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2
mode is used) (default).
Set, ALE is active only during a MOVX or MOVC instruction is used.
Reset Value = 0X0X 1100b
Not bit addressable
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27. Electrical Characteristics
27.1
Absolute Maximum Ratings
Note:
Ambient Temperature Under Bias:
I = industrial ........................................................-40°C to 85°C
Storage Temperature .................................... -65°C to + 150°C
Voltage on VCC from VSS ......................................-0.5V to + 6V
Voltage on Any Pin from VSS .....................-0.5V to VCC + 0.2V
27.2
Stresses at or above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions may affect
device reliability.
DC Parameters
TA = -40°C to +85°C; VSS = 0V; VCC = 2.7 - 3.6V; F = 0 to 40 MHz
Symbol
Parameter
Min
VIL
Input Low Voltage
VIH
Input High Voltage except XTAL1, RST
VIH1
Input High Voltage, XTAL1, RST
VOL
Output Low Voltage, ports 1, 2, 3 and 4(6)
VOL1
VOH
VOH1
RRST
Output Low Voltage, port 0, ALE, PSEN
Typ(5)
Max
Unit
-0.5
0.2Vcc - 0.1
V
0.2 VCC + 0.9
VCC + 0.5
V
0.7 VCC
VCC + 0.5
V
(6)
Output High Voltage, ports 1, 2, 3, 4 and 5
Output High Voltage, port 0, ALE, PSEN
RST Pullup Resistor
0.3
V
IOL = 100 µA(4)
0.45
V
IOL = 0.8 mA(4)
1.0
V
IOL = 1.6mA(4)
0.3
V
IOL = 200 µA(4)
0.45
V
IOL = 1.6 mA(4)
1.0
V
IOL = 3.5 mA(4)
VCC - 0.3
V
VCC - 0.7
V
VCC - 1.5
V
VCC - 0.3
V
VCC - 0.7
V
VCC - 1.5
V
50
100
Test Conditions
200
kΩ
IOH = -10 µA
IOH = -30 µA
IOH = -60 µA
VCC = 2.7 - 3.6V
IOH = -200 µA
IOH = -1.6 mA
IOH = -3.5 mA
VCC = 2.7 - 3.6V
IIL
Logical 0 Input Current ports 1, 2, 3 and 4
-50
µA
Vin = 0.45V
ILI
Input Leakage Current
±10
µA
0.45V < Vin < VCC
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3
and 4
-650
µA
Vin = 2.0V
CIO
Capacitance of I/O Buffer
10
pF
Fc = 1 MHz
TA = 25°C
IPD
Power-down Current
100
µA
2.7V < VCC < 3.6V(3)
ICC
Power Supply Current
ICCOP = 0.33xF(MHz)+1.46
VCC = 3.3V (1)(2)
ICCIDLE = 0.3xF(MHz)+1.46
ICCwrite = 0.8xF(MHz)+15
VPFDP
142
Power Fail High Level Threshold
2.7
V
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AT83C5134/35/36
Symbol
VPFDM
Notes:
Typ(5)
Parameter
Min
Max
Unit
Power Fail Low Level Threshold
2.2
V
Power fail hysteresis VPFDP - VPFDM
0.15
V
Test Conditions
1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 27-4.), VIL =
VSS + 0.5V,
VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure
27-1.).
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC 0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 27-2).
3. Power-down ICC is measured with all output pins disconnected; EA = VCC, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 27-3.). In addition, the WDT must be inactive and the POF flag must be set.
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
Figure 27-1. ICC Test Condition, Active Mode
VCC
ICC
VCC
VCC
P0
RST
(NC)
CLOCK
SIGNAL
EA
XTAL2
XTAL1
VSS
All other pins are disconnected.
143
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Figure 27-2. ICC Test Condition, Idle Mode
VCC
ICC
VCC
P0
VCC
RST
(NC)
CLOCK
SIGNAL
VCC
EA
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 27-3. ICC Test Condition, Power-down Mode
VCC
ICC
VCC
VCC
P0
VCC
RST
(NC)
EA
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 27-4. Clock Signal Waveform for ICC Tests in Active and Idle Modes
VCC-0.5V
0.45V
TCLCH
TCHCL
TCLCH = TCHCL = 5ns.
27.2.1
LED’s
Table 27-1.
Symbol
IOL
Note:
144
0.7VCC
0.2VCC-0.1
LED Outputs DC Parameters
Parameter
Output Low Current, P3.6 and P3.7 LED modes
Min
Typ
Max
Unit
Test Conditions
1
2
4
mA
2 mA configuration
2
4
8
mA
4 mA configuration
5
10
20
mA
10 mA configuration
1. (TA = -20°C to +50°C, VCC - VOL = 2 V ± 20%)
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
27.3
USB DC Parameters
1 - VBUS
2-D3-D+
4 - GND
R
3
2
USB “B”
Receptacle
VREF
Rpad
Rpad
4
D+
D-
1
R = 1.5 kΩ
Rpad = 27Ω
Symbol
Parameter
Min
USB Reference Voltage
3.0
VIH
Input High Voltage for D+ and D- (Driven)
2.0
VIHZ
Input High Voltage for D+ and D- (Floating)
2.7
VIL
Input Low Voltage for D+ and D-
VOH
Output High Voltage for D+ and D-
VOL
Output Low Voltage for D+ and D-
VREF
27.4
27.4.1
Typ
Max
Unit
3.6
V
V
3.6
V
0.8
V
2.8
3.6
V
0.0
0.3
V
AC Parameters
Explanation of the AC Symbols
Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The
other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for.
Example:TAVLL = Time for Address Valid to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.
TA = -40°C to +85°C; VSS = 0V; VCC = 2.7 - 3.6V; F = 0 to 40 MHz.
TA = -40°C to +85°C; VSS = 0V; VCC = 2.7 - 3.6V.
(Load Capacitance for port 0, ALE and PSEN = 60 pF; Load Capacitance for all other outputs =
60 pF.)
Table 27-3, Table 27-6 and Table 27-9 give the description of each AC symbols.
Table 27-4, Table 27-8 and Table 27-10 give for each range the AC parameter.
Table 27-5, Table 27-8 and Table 27-11 give the frequency derating formula of the AC parameter for each speed range description. To calculate each AC symbols. take the x value and use
this value in the formula.
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Example: TLLIV and 20 MHz, Standard clock.
x = 30 ns
T = 50 ns
TCCIV = 4T - x = 170 ns
27.4.2
External Program Memory Characteristics
Table 27-2. Symbol Description
Symbol
T
Table 27-3.
Parameter
Oscillator Clock Period
TLHLL
ALE Pulse Width
TAVLL
Address Valid to ALE
TLLAX
Address Hold after ALE
TLLIV
ALE to Valid Instruction In
TLLPL
ALE to PSEN
TPLPH
PSEN Pulse Width
TPLIV
PSEN to Valid Instruction In
TPXIX
Input Instruction Hold after PSEN
TPXIZ
Input Instruction Float after PSEN
TAVIV
Address to Valid Instruction In
TPLAZ
PSEN Low to Address Float
AC Parameters for a Fix Clock (F = 40 MHz)
Symbol
Min
T
25
ns
TLHLL
40
ns
TAVLL
10
ns
TLLAX
10
ns
TLLIV
70
Units
ns
TLLPL
15
ns
TPLPH
55
ns
TPLIV
TPXIX
146
Max
35
0
ns
ns
TPXIZ
18
ns
TAVIV
85
ns
TPLAZ
10
ns
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
Table 27-4.
27.4.3
AC Parameters for a Variable Clock
Symbol
Type
Standard
Clock
X2 Clock
X Parameter
Units
TLHLL
Min
2T-x
T-x
10
ns
TAVLL
Min
T-x
0.5 T - x
15
ns
TLLAX
Min
T-x
0.5 T - x
15
ns
TLLIV
Max
4T-x
2T-x
30
ns
TLLPL
Min
T-x
0.5 T - x
10
ns
TPLPH
Min
3T-x
1.5 T - x
20
ns
TPLIV
Max
3T-x
1.5 T - x
40
ns
TPXIX
Min
x
x
0
ns
TPXIZ
Max
T-x
0.5 T - x
7
ns
TAVIV
Max
5T-x
2.5 T - x
40
ns
TPLAZ
Max
x
x
10
ns
External Program Memory Read Cycle
12 TCLCL
TLHLL
TLLIV
ALE
TLLPL
TPLPH
PSEN
PORT 0
TLLAX
TAVLL
INSTR IN
TPLIV
TPLAZ
A0-A7
TPXIX
INSTR IN
TPXAV
TPXIZ
A0-A7
INSTR IN
TAVIV
PORT 2
ADDRESS
OR SFR-P2
ADDRESS A8-A15
ADDRESS A8-A15
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7683C–USB–11/07
27.4.4
External Data Memory Characteristics
Table 27-5. Symbol Description
Symbol
Table 27-6.
Parameter
TRLRH
RD Pulse Width
TWLWH
WR Pulse Width
TRLDV
RD to Valid Data In
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
TLLDV
ALE to Valid Data In
TAVDV
Address to Valid Data In
TLLWL
ALE to WR or RD
TAVWL
Address to WR or RD
TQVWX
Data Valid to WR Transition
TQVWH
Data set-up to WR High
TWHQX
Data Hold After WR
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE high
AC Parameters for a Variable Clock (F = 40 MHz)
Symbol
Min
TRLRH
130
ns
TWLWH
130
ns
TRLDV
TRHDX
100
0
Units
ns
ns
TRHDZ
30
ns
TLLDV
160
ns
TAVDV
165
ns
100
ns
TLLWL
50
TAVWL
75
ns
TQVWX
10
ns
TQVWH
160
ns
TWHQX
15
ns
TRLAZ
TWHLH
148
Max
10
0
ns
40
ns
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
Table 27-7.
27.4.5
AC Parameters for a Variable Clock
Symbol
Type
Standard
Clock
X2 Clock
X Parameter
Units
TRLRH
Min
6T-x
3T-x
20
ns
TWLWH
Min
6T-x
3T-x
20
ns
TRLDV
Max
5T-x
2.5 T - x
25
ns
TRHDX
Min
x
x
0
ns
TRHDZ
Max
2T-x
T-x
20
ns
TLLDV
Max
8T-x
4T -x
40
ns
TAVDV
Max
9T-x
4.5 T - x
60
ns
TLLWL
Min
3T-x
1.5 T - x
25
ns
TLLWL
Max
3T+x
1.5 T + x
25
ns
TAVWL
Min
4T-x
2T-x
25
ns
TQVWX
Min
T-x
0.5 T - x
15
ns
TQVWH
Min
7T-x
3.5 T - x
25
ns
TWHQX
Min
T-x
0.5 T - x
10
ns
TRLAZ
Max
x
x
0
ns
TWHLH
Min
T-x
0.5 T - x
15
ns
TWHLH
Max
T+x
0.5 T + x
15
ns
External Data Memory Write Cycle
TWHLH
ALE
PSEN
TLLWL
TWLWH
WR
TLLAX
PORT 0
A0-A7
TQVWX
TQVWH
TWHQX
DATA OUT
TAVWL
PORT 2
ADDRESS
OR SFR-P2
ADDRESS A8-A15 OR SFR P2
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7683C–USB–11/07
27.4.6
External Data Memory Read Cycle
TWHLH
TLLDV
ALE
PSEN
TLLWL
TRLRH
RD
TRHDZ
TAVDV
TLLAX
PORT 0
TRHDX
A0-A7
DATA IN
TRLAZ
TAVWL
PORT 2
27.4.7
ADDRESS
OR SFR-P2
ADDRESS A8-A15 OR SFR P2
Serial Port Timing - Shift Register Mode
Table 27-8. Symbol Description (F = 40 MHz)
Symbol
Table 27-9.
Parameter
TXLXL
Serial port clock cycle time
TQVHX
Output data set-up to clock rising edge
TXHQX
Output data hold after clock rising edge
TXHDX
Input data hold after clock rising edge
TXHDV
Clock rising edge to input data valid
AC Parameters for a Fix Clock (F = 40 MHz)
Symbol
Min
Max
Units
TXLXL
300
ns
TQVHX
200
ns
TXHQX
30
ns
TXHDX
0
ns
117
TXHDV
ns
Table 27-10. AC Parameters for a Variable Clock
150
Symbol
Type
Standard
Clock
X2 Clock
X Parameter
for -M Range
TXLXL
Min
12 T
6T
TQVHX
Min
10 T - x
5T-x
50
ns
TXHQX
Min
2T-x
T-x
20
ns
TXHDX
Min
x
x
0
ns
TXHDV
Max
10 T - x
5 T- x
133
ns
Units
ns
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
27.4.8
Shift Register Timing Waveform
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
TXLXL
CLOCK
TXHQX
TQVXH
OUTPUT DATA
WRITE to SBUF
INPUT DATA
0
1
2
3
4
5
6
TXHDX
TXHDV
VALID
VALID
SET TI
VALID
VALID
VALID
VALID
VALID
External Clock Drive Characteristics (XTAL1)
Table 27-11. AC Parameters
Symbol
Parameter
Min
Max
Units
TCLCL
Oscillator Period
21
ns
TCHCX
High Time
5
ns
TCLCX
Low Time
5
ns
TCLCH
Rise Time
5
ns
TCHCL
Fall Time
5
ns
60
%
TCHCX/TCLCX
27.4.10
VALID
SET RI
CLEAR RI
27.4.9
7
Cyclic ratio in X2 mode
40
External Clock Drive Waveforms
VCC-0.5V
0.45V
0.7VCC
0.2VCC-0.1
TCHCX
TCLCX
TCHCL
TCLCH
TCLCL
27.4.11
AC Testing Input/Output Waveforms
VCC -0.5V
0.2 VCC + 0.9
INPUT/OUTPUT
0.2 VCC - 0.1
0.45V
AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing
measurement are made at VIH min for a logic “1” and VIL max for a logic “0”.
27.4.12
Float Waveforms
FLOAT
VOH - 0.1 V
VOL + 0.1 V
VLOAD
VLOAD + 0.1 V
VLOAD - 0.1 V
For timing purposes as port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH
≥ ±20 mA.
151
7683C–USB–11/07
27.4.13
Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
INTERNAL
CLOCK
STATE4
STATE5
STATE6
STATE1
STATE2
STATE3
STATE4
STATE5
P1
P1
P1
P1
P1
P1
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
XTAL2
ALE
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
EXTERNAL PROGRAM MEMORY FETCH
PSEN
P0
DATA
SAMPLED
FLOAT
P2 (EXT)
PCL OUT
DATA
SAMPLED
FLOAT
PCL OUT
DATA
SAMPLED
FLOAT
PCL OUT
INDICATES ADDRESS TRANSITIONS
READ CYCLE
RD
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
P0
DPL OR Rt OUT
P2
DATA
SAMPLED
FLOAT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
WRITE CYCLE
WR
P0
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
DPL OR Rt OUT
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
DATA OUT
P2
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PORT OPERATION
MOV PORT SRC
OLD DATA NEW DATA
P0 PINS SAMPLED
P0 PINS SAMPLED
MOV DEST P0
MOV DEST PORT (P1. P2. P3)
(INCLUDES INTO. INT1. TO T1)
SERIAL PORT SHIFT CLOCK
P1, P2, P3 PINS SAMPLED
RXD SAMPLED
P1, P2, P3 PINS SAMPLED
RXD SAMPLED
TXD (MODE 0)
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however,
ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA = 25°C fully loaded) RD and WR propagation
delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC
specifications.
152
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AT83C5134/35/36
Table 27-12. Memory AC Timing
VDD = 3.3V ± 10%, TA = -40 to +85°C
Symbol
27.5
Parameter
Min
Typ
Max
Unit
TSVRL
Input PSEN Valid to RST Edge
50
ns
TRLSX
Input PSEN Hold after RST Edge
50
ns
USB AC Parameters
Rise Time
Fall Time
90%
VHmin
90%
VCRS
10%
10%
Differential
Data Lines
VLmax
tF
tR
Table 27-13. USB AC Parameters
Symbol
Parameter
Min
tR
Rise Time
tF
Fall Time
Max
Unit
4
20
ns
4
20
ns
11.9700
12.0300
Mb/s
Crossover Voltage
1.3
2.0
V
tDJ1
Source Jitter Total to Next
Transaction
-3.5
3.5
ns
tDJ2
Source Jitter Total for Paired
Transactions
-4
4
ns
tJR1
Receiver Jitter to Next
Transaction
-18.5
18.5
ns
tJR2
Receiver Jitter for Paired
Transactions
-9
9
ns
tFDRATE
VCRS
27.6
Full-speed Data Rate
Typ
Test Conditions
SPI Interface AC Parameters
27.6.0.1
Definition of Symbols
Table 27-14. SPI Interface Timing Symbol Definitions
Signals
Conditions
C
Clock
H
High
I
Data In
L
Low
O
Data Out
V
Valid
X
No Longer Valid
Z
Floating
153
7683C–USB–11/07
27.6.0.2
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 27-15. SPI Interface Master AC Timing
VDD = 2.7 to 5.5 V, TA = -40 to +85°C
Symbol
Parameter
Min
Max
Unit
Slave Mode
TCHCH
Clock Period
2
TPER
TCHCX
Clock High Time
0.8
TPER
TCLCX
Clock Low Time
0.8
TPER
TSLCH, TSLCL
SS Low to Clock edge
100
ns
TIVCL, TIVCH
Input Data Valid to Clock Edge
50
ns
TCLIX, TCHIX
Input Data Hold after Clock Edge
50
ns
TCLOV, TCHOV
Output Data Valid after Clock Edge
TCLOX, TCHOX
Output Data Hold Time after Clock Edge
0
ns
TCLSH, TCHSH
SS High after Clock Edge
0
ns
TSLOV
SS Low to Output Data Valid
4TPER+20
ns
TSHOX
Output Data Hold after SS High
2TPER+100
ns
TSHSL
SS High to SS Low
TILIH
Input Rise Time
2
µs
TIHIL
Input Fall Time
2
µs
TOLOH
Output Rise time
100
ns
TOHOL
Output Fall Time
100
ns
50
ns
2TPER+120
Master Mode
Note:
154
TCHCH
Clock Period
4
TPER
TCHCX
Clock High Time
2TPER-20
ns
TCLCX
Clock Low Time
2TPER-20
ns
TIVCL, TIVCH
Input Data Valid to Clock Edge
50
ns
TCLIX, TCHIX
Input Data Hold after Clock Edge
50
ns
TCLOV, TCHOV
Output Data Valid after Clock Edge
TCLOX, TCHOX
Output Data Hold Time after Clock Edge
20
0
ns
ns
TPER is XTAL period when SPI interface operates in X2 mode or twice XTAL period when SPI
interface operates in X1 mode.
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
27.6.0.3
Waveforms
Figure 27-5. SPI Slave Waveforms (CPHA= 0)
SS
(input)
TSLCH
TSLCL
TCHCH
SCK
(CPOL= 0)
(input)
TCHCX
TSHSL
TCLCX
TCHCL
SCK
(CPOL= 1)
(input)
TCLOX
TCHOX
TCLOV
TCHOV
TSLOV
MISO
(output)
TCLCH
TCLSH
TCHSH
SLAVE MSB OUT
BIT 6
TSHOX
SLAVE LSB OUT
(1)
TIVCH TCHIX
TIVCL TCLIX
MOSI
(input)
Note:
MSB IN
BIT 6
LSB IN
1. Not Defined but generally the MSB of the character which has just been received.
Figure 27-6. SPI Slave Waveforms (CPHA= 1)
SS
(input)
TSLCH
TSLCL
SCK
(CPOL= 0)
(input)
TCHCH
TCHCX
TSHSL
TCLCX
TCHCL
SCK
(CPOL= 1)
(input)
TCHOV
TCLOV
TSLOV
MISO
(output)
TCLCH
TCLSH
TCHSH
(1)
SLAVE MSB OUT
BIT 6
TCHOX
TCLOX
TSHOX
SLAVE LSB OUT
TIVCH TCHIX
TIVCL TCLIX
MOSI
(input)
Note:
MSB IN
BIT 6
LSB IN
1. Not Defined but generally the LSB of the character which has just been received.
155
7683C–USB–11/07
Figure 27-7. SPI Master Waveforms (SSCPHA= 0)
SS
(output)
TCHCH
SCK
(CPOL= 0)
(output)
TCHCX
TCLCH
TCLCX
TCHCL
SCK
(CPOL= 1)
(output)
TIVCH TCHIX
TIVCL TCLIX
MOSI
(input)
MSB IN
BIT 6
LSB IN
TCLOX
TCLOV
TCHOV
MISO
(output)
Note:
Port Data
MSB OUT
TCHOX
BIT 6
LSB OUT
Port Data
1. SS handled by software using general purpose port pin.
Figure 27-8. SPI Master Waveforms (SSCPHA= 1)
SS(1)
(output)
TCHCH
SCK
(CPOL= 0)
(output)
TCHCX
TCLCH
TCLCX
TCHCL
SCK
(CPOL= 1)
(output)
TIVCH TCHIX
TIVCL TCLIX
MOSI
(input)
MISO
(output)
MSB IN
BIT 6
TCLOV
TCLOX
TCHOX
TCHOV
Port Data
MSB OUT
BIT 6
LSB IN
LSB OUT
Port Data
SS handled by software using general purpose port pin.
156
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28. Ordering Information
Table Possible Order Entries
Part Number
Memory Size
Supply Voltage
Temperature Range
Package
Packing
AT83C5134xxx-PNTUL
8KB
2.7 to 3.6V
Industrial & Green
QFN32
Tray
AT83C5135xxx-PNTUL
16KB
2.7 to 3.6V
Industrial & Green
QFN32
Tray
AT83C5136xxx-PNTUL
32KB
2.7 to 3.6V
Industrial & Green
QFN32
Tray
AT83C5136xxx-PLTUL
32KB
2.7 to 3.6V
Industrial & Green
QFN/MLF48
Tray
AT83C5136xxx-TISUL
32KB
2.7 to 3.6V
Industrial & Green
SO28
Stick
AT83C5136-RDTUL
32
2.7 to 3.6V
Industrial & Green
VQFP64
Tray
AT83C5136xxx-DDW
32KB
2.7 to 3.6V
Industrial & Green
Die
Inked Wafer
AT83EC5136xxx-PNTUL
32KB with 512-byte of
EEPROM
2.7 to 3.6V
Industrial & Green
QFN/MLF48
Tray
AT83EI5136xxx-PNTUL
32KB with 32-kbyte of
EEPROM
2.7 to 3.6V
Industrial & Green
QFN/MLF48
Tray
157
7683C–USB–11/07
29. Packaging Information
29.1
158
64-lead VQFP
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
29.2
48-lead MLF
159
7683C–USB–11/07
160
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
29.3
28-lead SO
161
7683C–USB–11/07
29.4
162
QFN32
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
30. Document Revision History
30.1
Changes from Rev A. to Rev. B
1. Added QFN32 package.
30.2
Changes from Rev B. to Rev. C
1. Updated package drawings.
163
7683C–USB–11/07
1
Features .................................................................................................... 1
2
Description ............................................................................................... 1
3
Block Diagram .......................................................................................... 3
4
Pinout Description ................................................................................... 4
5
6
4.1
Pinout ................................................................................................................ 4
4.2
Signals............................................................................................................... 6
Typical Application ................................................................................ 11
5.1
Recommended External components ............................................................. 11
5.2
PCB Recommandations .................................................................................. 12
Clock Controller ..................................................................................... 13
6.1
Introduction...................................................................................................... 13
6.2
Oscillator.......................................................................................................... 13
6.3
PLL .................................................................................................................. 14
6.4
Registers ......................................................................................................... 16
7
SFR Mapping .......................................................................................... 18
8
Program/Code Memory ......................................................................... 25
8.1
9
External Code Memory Access ....................................................................... 25
AT89C5131 ROM .................................................................................... 27
9.1
ROM Structure................................................................................................. 27
9.2
ROM Lock System........................................................................................... 27
10 Stacked EEPROM................................................................................... 29
10.1
Overview.......................................................................................................... 29
10.2
Protocol ........................................................................................................... 29
11 On-chip Expanded RAM (ERAM) .......................................................... 30
12 Timer 2 .................................................................................................... 33
12.1
Auto-reload Mode ............................................................................................ 33
12.2
Programmable Clock Output ........................................................................... 34
13 Programmable Counter Array (PCA).................................................... 38
164
13.1
PCA Capture Mode ......................................................................................... 45
13.2
16-bit Software Timer/Compare Mode ............................................................ 45
13.3
High Speed Output Mode ................................................................................ 46
13.4
Pulse Width Modulator Mode .......................................................................... 47
AT83C5134/35/36
7683C–USB–11/07
AT83C5134/35/36
13.5
PCA Watchdog Timer...................................................................................... 48
14 Serial I/O Port ......................................................................................... 49
14.1
Framing Error Detection .................................................................................. 49
14.2
Automatic Address Recognition ...................................................................... 50
14.3
Baud Rate Selection for UART for Mode 1 and 3............................................ 52
14.4
UART Registers............................................................................................... 55
15 Dual Data Pointer Register.................................................................... 59
16 Interrupt System .................................................................................... 61
16.1
Overview.......................................................................................................... 61
16.2
Registers ......................................................................................................... 62
16.3
Interrupt Sources and Vector Addresses......................................................... 69
17 Keyboard Interface ................................................................................ 70
17.1
Introduction...................................................................................................... 70
17.2
Description....................................................................................................... 70
17.3
Registers ......................................................................................................... 71
18 Programmable LED................................................................................ 74
19 Serial Peripheral Interface (SPI) ........................................................... 75
19.1
Features .......................................................................................................... 75
19.2
Signal Description............................................................................................ 75
19.3
Functional Description ..................................................................................... 77
20 Two Wire Interface (TWI) ....................................................................... 84
20.1
Description....................................................................................................... 86
20.2
Notes ............................................................................................................... 89
20.3
Registers ......................................................................................................... 99
21 USB Controller ..................................................................................... 101
21.1
Description..................................................................................................... 101
21.2
Configuration ................................................................................................. 103
21.3
Read/Write Data FIFO................................................................................... 105
21.4
Bulk/Interrupt Transactions............................................................................ 106
21.5
Control Transactions ..................................................................................... 111
21.6
Isochronous Transactions ............................................................................. 112
21.7
Miscellaneous................................................................................................ 113
21.8
Suspend/Resume Management .................................................................... 114
165
7683C–USB–11/07
21.9
Detach Simulation ......................................................................................... 117
21.10
USB Interrupt System.................................................................................... 117
21.11
USB Registers ............................................................................................... 120
22 Reset ..................................................................................................... 131
22.1
Introduction.................................................................................................... 131
22.2
Reset Input .................................................................................................... 131
22.3
Reset Output ................................................................................................. 131
23 Power Monitor ...................................................................................... 133
23.1
Description..................................................................................................... 133
24 Power Management ............................................................................. 135
24.1
Idle Mode....................................................................................................... 135
24.2
Power-down Mode......................................................................................... 135
24.3
Registers ....................................................................................................... 137
25 Hardware Watchdog Timer ................................................................. 138
25.1
Using the WDT .............................................................................................. 138
25.2
WDT During Power-down and Idle ................................................................ 139
26 Reduced EMI Mode .............................................................................. 141
27 Electrical Characteristics .................................................................... 142
27.1
Absolute Maximum Ratings .......................................................................... 142
27.2
DC Parameters.............................................................................................. 142
27.3
USB DC Parameters ..................................................................................... 145
27.4
AC Parameters .............................................................................................. 145
27.5
USB AC Parameters...................................................................................... 153
27.6
SPI Interface AC Parameters ........................................................................ 153
28 Ordering Information ........................................................................... 157
29 Packaging Information ........................................................................ 158
29.1
64-lead VQFP................................................................................................ 158
29.2
48-lead MLF .................................................................................................. 159
29.3
28-lead SO .................................................................................................... 161
29.4
QFN32 ........................................................................................................... 162
30 Document Revision History ................................................................ 163
166
30.1
Changes from Rev A. to Rev. B .................................................................... 163
30.2
Changes from Rev B. to Rev. C .................................................................... 163
AT83C5134/35/36
7683C–USB–11/07
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7683C–USB–11/07
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