ATA663331/ATA663354 - Complete

ATA663331/ATA663354
LIN SBC(1) including LIN Transceiver, Voltage Regulator,
Dual Low-side Driver and a High-side Switch
DATASHEET
Features
● Supply voltage up to 40V
● Operating voltage VVS = 5V to 28V
● Supply current
● Sleep mode: typically 10µA
● Silent mode: typically 47µA
● Very low current consumption at low supply voltages (2V < VVS < 5.5V):
typically 130µA
● Linear low-drop voltage regulator, 85mA current capability:
● MLC (multi-layer ceramic) capacitor with 0 ESR
● Normal, fail-safe, and silent mode
● Atmel ATA663354: VVCC = 5.0V ±2%
● Atmel ATA663331: VVCC = 3.3V ±2%
● Sleep mode: VCC is switched off
● VCC undervoltage detection with open drain reset output (NRES, 4ms reset time)
● Voltage regulator is short-circuit and over-temperature protected
● LIN physical layer according to LIN 2.0, 2.1, 2.2, 2.2A and SAEJ2602-2
● Bus pin is over-temperature and short-circuit protected versus GND and battery
● Two low-side protected switches and one high-side protected switch
● Wake-up capability via LIN bus (100µs dominant) and WKin pin
● Wake-up source recognition
● TXD time-out timer
● Advanced EMC and ESD performance
● Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications
Rev.1.3”
● Interference and damage protection according to ISO7637
● Qualified according to AEC-Q100
● Package: DFN16 with wettable flanks (Moisture Sensitivity Level 1)
Note:
1. LIN SBC: LIN system basis chip
9231A-AUTO-08/15
1.
Description
Designed in compliance with LIN specifications 2.0, 2.1, 2.2, 2.2A and SAEJ2602-2, the Atmel® ATA6633xx is a new
generation of system basis chips with a fully integrated LIN transceiver, a low-drop voltage regulator (3.3V/5V/85mA), two
low-side drivers, and one high-side driver. This combination makes it possible to develop simple, but powerful, slave nodes
in LIN bus systems. Atmel ATA6633xx is designed to handle low-speed data communication in vehicles (such as in
convenience electronics). Improved slope control at the LIN driver ensures secure data communication up to 20kBaud. The
bus output is designed to withstand high voltage. Sleep mode and silent mode guarantee minimized current consumption
even in the case of a floating or short-circuited LIN bus.
Figure 1-1. Block Diagram
Atmel ATA663331/ATA663354
15
VS
14
LIN
12
WKin
16
VCC
VCC
Normal and
Fail-safe
Mode
Receiver
RXD
-
1
+
RF-filter
WKout
LIN
5
WKin
Wake-up module
VCC
Short-circuit and
overtemperature
protection
TXD
EN
GND
4
TXD
Time-out
timer
2
13
Slew rate control
Voltage regulator
Sleep
mode
Control
Normal/Silent/
VCC
unit
switched Fail-safe Mode
5V
off
VCC
3
NRES
9
HSout
11
LS1out
10
LS2out
Undervoltage reset
HSin
8
LS1in
6
LS2in
2
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ATA663331/ATA663354 [DATASHEET]
9231A–AUTO–08/15
HS transistor driver
with short-circuit and
overtemperature
protection
Dual transistor driver
with short-circuit and
overtemperature
protection
2.
Pin Configuration
Figure 2-1. Pinning DFN16
RXD
VCC
EN
NRES
TXD
WKout
Table 2-1.
VS
Atmel
ATA663331
ATA663354
LIN
GND
DFN16
3 x 5.5
WKin
LS1in
LS1out
LS2in
LS2out
HSin
HSout
Pin Description
Pin
Symbol
1
RXD
2
EN
3
NRES
Function
Receive data output
Enables normal mode if the input is high
VCC undervoltage output, open drain, low at reset
4
TXD
5
WKout
Low-voltage output to indicate local wake-up request
6
LS1in
Low-side 1 control input
7
LS2in
Low-side 2 control input
8
HSin
High-side control input
9
HSout
High-side output
10
LS2out
Low-side 2 output
11
LS1out
Low-side 1 output
12
WKin
High-voltage input for local wake-up request
13
GND
Ground
14
LIN
LIN bus line input/output
15
VS
Supply voltage
16
VCC
Backside
Transmit data input
Output voltage regulator 3.3V/5V/85mA
Heat slug, power-ground connection
ATA663331/ATA663354 [DATASHEET]
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3.
Pin Description
3.1
Supply Pin (VS)
LIN operating voltage is VVS = 5V to 28V. In order to avoid false bus messages, undervoltage detection is implemented to
disable transmission if VVS falls below typ. 4.5V. After switching on VVS, the IC starts in fail-safe mode and the voltage
regulator is switched on.
The supply current in sleep mode is typically 10µA and 47µA in silent mode.
3.2
Ground Pin (GND)
The IC does not affect the LIN bus in the event of GND disconnection. It can handle ground shifts of up to 11.5% with respect
to VVS.
3.3
Voltage Regulator Output Pin (VCC)
The internal 3.3V/5V voltage regulator is capable of driving loads up to 85mA, supplying the microcontroller and other ICs on
the PCB, and is protected against overload by means of current limitation and overtemperature shutdown. Furthermore, the
output voltage is monitored and causes a reset signal at the NRES output pin if it drops below a defined threshold
VVCC_th_uv_down.
3.4
Undervoltage Reset Output Pin (NRES)
If the VVCC voltage falls below the undervoltage detection threshold VVCC_th_uv_down, NRES switches to low after tres_f. Even if
VVCC = 0V the NRES stays low because it is internally driven from the VS voltage. If VS voltage ramps down, NRES stays
low until VVS < 1.5V and then becomes high-impedant.
The undervoltage delay implemented keeps NRES low for tReset = 4ms after VVCC reaches its nominal value.
3.5
Bus Pin (LIN)
A low-side driver is implemented with internal current limitation and thermal shutdown as well as an internal pull-up resistor
in compliance with LIN specification 2.x. The voltage range is from –27V to +40V. This pin exhibits no reverse current from
the LIN bus to VS, even in the event of a GND shift or supply disconnection. The LIN receiver thresholds are compatible with
the LIN protocol specification.
The fall time (transition from recessive to dominant state) and the rise time (transition from dominant to recessive state) are
slope-controlled.
During a short-circuit at the LIN pin to VBAT, the output limits the output current to IBUS_LIM. Due to the power dissipation, the
chip temperature exceeds TLINoff and the LIN output is switched off. The chip cools down and after a hysteresis of Thys,
switches the output on again. RXD stays on high because LIN is high. The VCC regulator works independently during LIN
overtemperature switch-off.
During a short circuit from LIN to GND the IC can be switched into sleep or silent mode and even in this case the current
consumption is lower than 100µA in sleep mode and lower than 120µA in silent mode. If the short circuit disappears, the IC
starts with a remote wake-up.
The reverse current is < 2µA at pin LIN during loss of VVS. This is optimal behavior for bus systems where some slave nodes
are supplied from battery or ignition.
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3.6
Bus Data Input/Output (TXD)
In normal mode the TXD pin is the microcontroller interface for controlling the state of the LIN output. TXD must be pulled to
ground in order to drive the LIN bus low. If TXD is high or unconnected (internal pull-up resistor), the LIN output transistor is
turned off and the bus is in the recessive state. If the TXD pin stays at GND level while switching into normal mode, it must
be pulled to high level longer than 10µs before the LIN driver can be activated. This feature prevents the bus line from being
unintentionally driven to dominant state after normal mode has been activated (also if a short circuit occurs at TXD to GND).
If TXD is short-circuited to GND, it is possible to switch to sleep mode via the EN- pin after t > tdom.
In fail-safe mode this pin is used as an output and signals the fail-safe source.
An internal timer prevents the bus line from being driven permanently in the dominant state. If TXD is forced to low longer
than tdom > 20ms, the LIN bus driver is switched to the recessive state. Nevertheless, when switching to sleep mode, the
actual level at the TXD pin is relevant.
To reactivate the LIN bus driver, switch TXD to high (> 10µs).
3.7
Bus Data Output Pin (RXD)
In normal mode this pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is reported by a high
level at RXD; LIN low (dominant state) is reported by a low level at RXD. The output is a push-pull stage switching between
VCC and GND. The AC characteristics are measured with an external load capacitor of 20pF.
In silent mode the RXD output switches to high.
3.8
Enable Input Pin (EN)
The enable input pin controls the operation mode of the device. If EN is high, the circuit is in normal mode, with transmission
paths from TXD to LIN and from LIN to RXD both active. The VCC voltage regulator operates with 3.3V/5V/85mA output
capability.
If EN is switched to low while TXD is still high, the device is forced into silent mode. No data transmission is then possible
and the current consumption is reduced to IVSsilent typ. 47µA. The VCC regulator maintains full functionality.
If EN is switched to low while TXD is low, the device is forced into sleep mode. No data transmission is possible and the
voltage regulator is switched off.
Pin EN provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected.
3.9
Wake Input Pin (WKin)
The WKin pin is a high-voltage input used to wake up the device from sleep mode or silent mode. It is usually connected to
an external switch in the application to generate a local wake-up. A pull-up current source with typically 10µA is
implemented. The voltage threshold for a wake-up signal is typically 2V below the VS voltage. If a local wake up is not
needed in the application, the WKin pin can be connected directly to the VS pin.
3.10
Wake Output Pin (WKout)
The WKout pin is a low-voltage output used for waking up a microcontroller or other device. It is a push-pull output stage
switching between VCC and GND. It is directly controlled by the WKin pin. If VWKin ≥ VWKinH, WKout is low and no wake-up is
detected. If VWKin < VWKinL, WKout is high and the device is switched into fail-safe mode if it was previously in a low-power
mode such as sleep or silent mode. Please note that during silent, fail-safe and normal mode, the output pin WKout is
always showing the state of pin WKin.
If a local wake up is not needed in the application, the WKout pin can be left open.
3.11
Low-side Driver Pins (LS1out, LS2out, LS1in, LS2in)
LS1out and LS2out are the low-side driver outputs. They are only functional in normal mode (see also the “Operating
Modes” section). These outputs are both short-circuit protected by means of output voltage monitoring and protected against
overheating. They additionally include an active clamping circuitry to provide a freewheeling path needed for inductive loads.
The clamping voltage VLSclamp is typically > 44V. Please note that an upper energy limit is defined both for single and for
repetitive clamping events. This must be considered when choosing the load, because overheating caused by excessive
clamping energy is not covered by the output protection and may therefore cause damage to the device.
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If the LS1in pin or the LS2in pin stay at GND level while switching into normal mode, it must be pulled to high level longer
than 10µs before the low-side driver can be activated. This feature prevents the low-side drivers (LS1out pin or LS2out pin
respectively) from being unintentionally switched ON after normal mode has been activated. To reactivate the low-side
drivers, switch LS1in or LS2in to high (> 10µs).
A disconnection of VS where the low sides are still supplied by VBAT through a load does not have any impact on the
clamping feature. That is, voltages above the minimum clamping voltage level VLSclamp activate the energy freewheeling path
within the low-side transistor.
The low-side switches are controlled via the low voltage input pins LS1in and LS2in. If the inputs are at high and the IC is in
normal mode (i. e., EN is high and there is no undervoltage supply condition), the outputs are switched ON. For fail-safe
reasons, both inputs are equipped with a pull-down resistor to GND. This will keep the low-side switches off in case of a
missing connection from the controller.
If an overload condition is detected, the appropriate driver stage is shut down. The protective shutdown of the low-side
outputs is latched. That is, the corresponding control line LSxin has to go to low first before the output can be restarted
again. Because the short-circuit detection is done by means of drain-to-source voltage monitoring, the switch-on event of the
transistor is blanked out from the monitoring, so that a capacitor connected to the low-side output does not trigger the
protection circuit upon activation of the transistor. Please see also following diagram for illustration:
Figure 3-1. Short-Circuit Detection Timing
LSxin
SC detection threshold
VLSxout
Switch on with shorted load
SC Monitor
LS State
OFF
ON
Short is removed again
OFF
OFF
ON
tLSdeb
As can be seen in Figure 3-1, the output transistor is not switched on again until the control pin “LSxin” is switched off and on
again by the microcontroller. As explained above, the short-circuit monitor is only enabled after the transistor reaches full
conductivity. That is why the SC monitor line does not show any signal on the first and the last switching-on event in the
figure above. Without a short present at the output, the transistor takes much more time to establish its operation point than
if there is a short present.
3.12
High-side Driver Pins (HSout, HSin)
This high-side switch is designed for low-power loads such as LEDs, sensors or a voltage divider for measuring the supply
voltage. It is functional in all operation modes of the chip but sleep mode. Its structure is connected to the VS supply pin. This
pin is protected against short-circuits and also overheating.
The high-side switch is controlled via the low-voltage input pin HSin. If the input is at high, the output is switched on. For failsafe reasons, the HSin input is equipped with a pull-down resistor to GND. This keeps the high-side switch off in case of a
missing connection from the controller.
Please note that in case of a disconnected system ground, the module can be supplied via the connected load on the highside output and an internal ESD structure. This is the case if the load has a different ground connection than the PCB. See
also the “Absolute Maximum Ratings” section for current limits in such cases.
As is the case with low-side switches, the protective shutdown of the high-side output is debounced and latched. In other
words, after a protective shutdown of the driver stage, the control line HSin has to go to low first before the output can be
restarted.
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4.
Functional Description
4.1
Physical Layer Compatibility
Because the LIN physical layer is independent of higher LIN layers (such as the LIN protocol layer), all nodes with a LIN
physical layer according to revision 2.x can be mixed with LIN physical layer nodes found in older versions (i.e., LIN 1.0, LIN
1.1, LIN 1.2, LIN 1.3) without any restrictions.
4.2
Operating Modes
Figure 4-1. Operating Modes
a: VS > VVS_th_U_F_up (2.4V)
b: VS < VVS_th_U_down (1.9V)
c: Bus wake-up event (LIN)
d: VCC < VCC_th_uv_down (4.2V)
e: VS < VVS_th_N_F_down (3.9V)
f: VS > VVS_th_F_N_up (4.9V)
g: Local wake up (WKin)
Unpowered Mode
All circuitry OFF
a
b
c & f,
g&f
c & f,
g & f,
d
Fail-safe Mode
VCC: ON
VCC monitor active
Communication: OFF
Wake-up Signaling
Undervoltage Signaling
EN = 0
TXD = 0
&f
(1)
EN = 0
TXD = 1
(1)
&d&f
EN = 1
&f
d,
e
b
Sleep Mode
VCC: OFF
Communication: OFF
EN = 1
1.
Table 4-1.
EN = 1
Normal Mode
&f
“Go to sleep”
command EN = 0
TXD = 0
Note:
b
Silent Mode
&f
VCC: ON
VCC monitor active
Communication: ON
EN = 0
“Go to silent”
command
TXD = 1
VCC: ON
VCC monitor active
Communication: OFF
Condition f is valid for VS ramp up; at VS ramp down condition e is valid instead of f.
Operating Modes
Voltage
Operating Modes Transceiver Regulator
Low-side
Outputs
High-side Output
LIN
TXD
RXD
Fail-safe
OFF
ON
OFF
HSin-dependent
Recessive
Signaling fail-safe
sources (see Table 4-2)
Normal
ON
ON
LSindependent
HSin-dependent
TXDdependent
Follows data
transmission
Silent
OFF
ON
OFF
HSin-dependent
Recessive
High
High
Sleep/Unpowered
OFF
OFF
OFF
OFF
Recessive
Low
Low
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4.2.1
Normal Mode
This is the normal transmitting and receiving mode of the LIN interface. Furthermore, the low-side drivers can only be
operated in this mode. The VCC voltage regulator works with 3.3V/5V output voltage.
If an undervoltage condition occurs, NRES is switched to low and the IC changes its state to fail-safe mode.
4.2.2
Silent Mode
A falling edge at EN while TXD is high switches the IC into silent mode. The TXD signal has to be logic high during the mode
select window. The transmission path is disabled in silent mode. The voltage regulator is active. The overall supply current
from VBAT is a combination of the IVSsilent of typ. 47µA plus the VCC regulator output current IVCC.
Figure 4-2. Switching to Silent Mode
Normal Mode
Silent Mode
EN
TXD
Mode select window
td = 3.2µs
NRES
VCC
Delay time silent mode
td_silent = maximum 20µs
LIN
LIN switches directly to recessive mode
In silent mode the internal slave termination between the LIN pin and VS pin is disabled to minimize the current consumption
in case the LIN pin is short-circuited to GND. Only a weak pull-up current (typically 10µA) is present between the LIN pin and
the VS pin. The silent mode can be activated regardless of the current level on the LIN pin or WKin pin.
If an undervoltage condition occurs, NRES is switched to low and the Atmel® ATA6633xx changes its state to fail-safe mode.
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4.2.3
Sleep Mode
A falling edge at EN while TXD is low switches the IC into sleep mode. The TXD signal has to be logic low during the mode
select window.
Figure 4-3. Switching to Sleep Mode
Sleep Mode
Normal Mode
EN
Mode select window
TXD
td = 3.2µs
NRES
VCC
Delay time sleep mode
td_sleep = maximum 20µs
LIN
LIN switches directly to recessive mode
In order to avoid any influence on the LIN pin while switching to sleep mode, it is possible to switch the EN to low up to 3.2µs
earlier than the TXD. The best and easiest way is to generate two simultaneous falling edges at TXD and EN.
In sleep mode the transmission path is disabled. Supply current from VBat is typically IVSsleep = 10µA. The VCC regulator is
switched off; NRES and RXD are low. The internal slave termination between pin LIN and pin VS is disabled to minimize the
current consumption in case pin LIN is short-circuited to GND. Only a weak pull-up current (typically 10µA) between pin LIN
and pin VS is present. The sleep mode can be activated independently from the current level on pin LIN. A voltage less than
the LIN pre-wake detection VLINL at pin LIN activates the internal LIN receiver and starts the wake-up detection timer.
If TXD is short-circuited to GND, it is possible to switch to sleep mode via EN after t > tdom.
4.2.4
Fail-safe Mode
The device automatically switches to fail-safe mode at system power-up. The voltage regulator is switched on. The NRES
output remains low for tres = 4ms and resets the microcontroller. LIN communication is switched off. The IC stays in this
mode until EN is switched to high. The IC then changes to normal mode. A low at NRES switches the IC directly into fail-safe
mode. During fail-safe mode the TXD pin is an output and signals together with the RXD output pin the fail-safe source.
If the device enters fail-safe mode coming from the normal mode (EN=1) due to a VVS undervoltage condition
(VVS < VVS_th_N_F_down), it is possible to switch into sleep mode or silent mode through a falling edge at the EN input. The
current consumption can be reduced further with this feature.
A wake-up event from either silent mode or sleep mode is signaled to the microcontroller using the two pins RXD and TXD.
A VVS undervoltage condition is also signaled at these two pins. The coding is shown in Table 4-2.
A wake-up event switches the IC to fail-safe mode.
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Table 4-2.
Signaling in Fail-safe Mode
Fail-safe Sources
TXD
RXD
LIN wake-up (LIN pin)
Low
Low
Local wake-up (WKin pin)
Low
High
VVS_th_N_F_down (battery) undervoltage detection (VVS < 3.9V)
High
Low
4.3
Wake-up Scenarios from Silent Mode or Sleep Mode
4.3.1
Remote Wake-up via LIN Bus
4.3.1.1 Remote Wake-up from Silent Mode
A remote wake-up from silent mode is only possible if TXD is high. A voltage less than the LIN pre-wake detection VLINL at
pin LIN activates the internal LIN receiver and starts the wake-up detection timer. A falling edge at the LIN pin followed by a
dominant bus level maintained for a certain time period (> tbus) and the following rising edge at pin LIN (see Figure 4-4)
results in a remote wake-up request. The device switches from silent mode to fail-safe mode, the VCC voltage regulator
remains activated and the internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by
a low level at pin RXD and TXD (strong pull-down at TXD). EN high can be used to switch directly to normal mode.
Figure 4-4. LIN Wake-up from Silent Mode
Bus wake-up filtering time
tbus
Fail-safe Mode
Normal Mode
LIN bus
RXD
High
Low
TXD
High
Low (strong pull-down)
High
VCC
EN High
EN
NRES
10
Undervoltage detection active
ATA663331/ATA663354 [DATASHEET]
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4.3.1.2 Remote Wake-up from Sleep Mode
A voltage less than the LIN pre-wake detection VLINL at the LIN pin activates the internal LIN receiver and starts the wake-up
detection timer.
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (> tbus) together with a
subsequent rising edge at the LIN pin results in a remote wake-up request. The device switches from sleep mode to fail-safe
mode.
The VCC regulator is activated, and the internal LIN slave termination resistor is switched ON. The remote wake-up request
is indicated by a low level at RXD and TXD (strong pull-down at TXD) (see Figure 4-5).
EN high can be used to switch directly from sleep/silent to fail-safe mode. If EN is still high after VVCC ramp-up and the
undervoltage reset time, the IC switches to normal mode.
Figure 4-5. LIN Wake-up from Sleep Mode
Bus wake-up filtering time
tbus
Fail-safe Mode
Normal Mode
High
LIN bus
Low
RXD
Low (strong pull-down)
TXD
High
High
On state
VCC
Off state
tVCC
EN High
EN
Reset
time
NRES
Low
Microcontroller
start-up time delay
4.3.2
Local Wake-up via WKin Pin
A falling edge at the WKin pin followed by a low level maintained for a certain time period (> tWKin) results in a local wake-up
request. The device switches to fail-safe mode. The internal slave termination resistor is switched on. The local wake-up
request is indicated by a low level at the TXD pin to generate an interrupt for the microcontroller. When the WKin pin is low,
it is possible to switch to silent mode or sleep mode via the EN pin. In this case, the wake-up signal has to be switched to
high > 10µs before the negative edge at WKin starts a new local wake-up request.
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Figure 4-6. Local Wake-up from Sleep Mode
Fail-safe Mode
Normal Mode
State change
WKin
RXD
High
TXD
Low (strong pull-down)
Wake filtering time
tWKin
On state
VCC
Off state
tVCC
EN High
EN
Reset
time
NRES
Low
Microcontroller
start-up time delay
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Figure 4-7. Local Wake-up from Silent Mode
Fail-safe Mode
Normal Mode
State change
WKin
High
RXD
TXD
Low (strong pull-down)
Wake filtering time
tWKin
VCC
EN High
EN
NRES
4.3.3
Wake-up Source Recognition
The device can distinguish between different wake-up sources (see Table 4-3). The wake-up source can be read on the TXD
and RXD pin in fail-safe mode. These flags are immediately reset if the microcontroller sets the EN pin to high and the IC is
in normal mode.
Table 4-3.
Signaling in Fail-safe Mode
Fail-safe Sources
TXD
RXD
LIN wake-up (LIN pin)
Low
Low
Local wake-up (WKin pin)
Low
High
VVS_th_N_F_down (battery) undervoltage detection (VVS < 3.9V)
High
Low
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4.4
Behavior under Low Supply Voltage Conditions
After the battery voltage has been connected to the application circuit, the voltage at the VS pin increases according to the
block capacitor. If VVS is higher than the minimum VS operation threshold VVS_th_U_F_up (typ. 2.25V), the IC mode changes
from unpowered mode to fail-safe mode. As soon as VVS exceeds the undervoltage threshold VVS_th_F_N_up (typ. 4.6V), the
LIN transceiver and the dual low-side switches can be activated. The VCC output voltage reaches its nominal value after
tVCC. This parameter depends on the externally applied VCC capacitor and the load. The NRES output is low for the reset
time delay treset. During this time treset, no mode change is possible.
The behaviour of VCC, NRES and VS is shown in following diagrams (ramp-up and ramp-down):
V (V)
Figure 4-8. VCC and NRES versus VS (Ramp-up) for Atmel ATA663331
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VS
NRES
VCC
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
1.0
0.5
0.0
VS (V)
V (V)
Figure 4-9. VCC and NRES versus VS (Ramp-down) for Atmel ATA663331
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VS
NRES
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
VS (V)
14
ATA663331/ATA663354 [DATASHEET]
9231A–AUTO–08/15
3.0
VCC
2.5
2.0
1.5
V (V)
Figure 4-10. VCC and NRES versus VS (Ramp-up) for ATA663354
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VS
NRES
VCC
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
2.0
1.5
1.0
0.5
0.0
VS (V)
V (V)
Figure 4-11. VCC and NRES versus VS (Ramp-down) for ATA663354
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VS
NRES
VCC
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
VS (V)
Please note that the upper graphs are only valid if the VS ramp-up and ramp-down time is much slower than the VCC rampup time tVcc and the NRES delay time treset.
If during sleep mode the voltage level of VVS drops below the undervoltage detection threshold VVS_th_N_F_down (typ. 4.3V),
the operation mode is not changed and no wake-up is possible. Only if the supply voltage on pin VS drops below the VS
operation threshold VVS_th_U_down (typ. 2.05V), does the IC switch to unpowered mode.
If during silent mode the VCC voltage drops below the VCC undervoltage threshold VVCC_th_uv_down the IC switches into failsafe mode. If the supply voltage on pin VS drops below the VS operation threshold VVS_th_U_down (typ. 2.05V), does the IC
switch to unpowered mode.
If during normal mode the voltage level on pin VS drops below the VS undervoltage detection threshold VVS_th_N_F_down
(typ. 4.3V), the IC switches to fail-safe mode. This means the LIN transceiver and the dual low-side drivers are disabled in
order to avoid malfunctions or false bus messages. The voltage regulator remains active.
For ATA663331: In this undervoltage situation it is possible to switch the device into sleep mode or silent mode by a
falling edge at the EN input. This feature ensures that switching into these two current saving modes is always possible, allowing current consumption to be even further reduced.
When the VCC voltage drops below the VCC undervoltage threshold VVCC_th_uv_down (typ. 2.6V) the IC switches into
fail-safe mode.
For ATA663354: Because of the VCC undervoltage condition in this situation, the IC is in fail-safe mode and can be
switched into sleep mode only.
Only when the supply voltage VVS drops below the operation threshold VVS_th_U_down (typ. 2.05V) does the IC switch to
unpowered mode.
The current consumption of the ATA6633xx in silent mode or in fail-safe mode is always below 170µA, even when the supply
voltage VVS is lower than the regulator’s nominal output voltage VCC.
ATA663331/ATA663354 [DATASHEET]
9231A–AUTO–08/15
15
4.5
Voltage Regulator
Figure 4-12. VCC Voltage Regulator: Supply Voltage Ramp-up and Ramp-down
V
VS
12V
VCC
3.3V/5.0V
VVCC_th_uv_up
VVCC_th_uv_down
2.4V
t
tVCC
tReset
tres_f
NRES
3.3V/5.0V
t
The voltage regulator needs an external capacitor for compensation and to smooth the disturbances from the
microcontroller. It is recommended to use a MLC capacitor with a minimum capacitance of 3.5µF together with a 100nF
ceramic capacitor. Depending on the application, the values of these capacitors can be modified by the customer.
When the Atmel® ATA6633xx is being soldered onto the PCB, it is mandatory to connect the heat slug with a wide GND plate
on the printed board to achieve a good heat sink.
The main power dissipation of the IC is created from the VCC output current IVCC, which is needed for the application. Figure
4-13 shows the safe operating area of the Atmel ATA6633xx without considering any output current of the drivers (LS1out,
LS2out, HSout).
Figure 4-13. Power Dissipation: Safe Operating Area: Regulator’s Output Current IVCC versus Supply Voltage VVS at
Different Ambient Temperatures (Rthja = 45K/W assumed)
90
Tamb = 85°C
80
Tamb = 95°C
I_Vcc [mA]
70
Tamb = 105°C
60
50
Tamb = 115°C
40
Tamb = 125°C
30
20
10
0
5
6
7
8
9
10
11
12
VVS [V]
16
ATA663331/ATA663354 [DATASHEET]
9231A–AUTO–08/15
13
14
15
16
17
18
5.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Supply voltage VVS
- DC voltage
- Ta = 25°C, tPulse ≤ 500ms, IVCC ≤ 85mA
- Ta = 25°C, tPulse ≤ 2min, IVCC ≤ 85mA
VVS
Logic pin voltage levels (TXD, EN, HSin,
LS1in, LS2in, NRES)
LIN bus levels VLIN
- DC voltage
- Pulse time ≤ 500ms
VVCC
- DC voltage
- DC input current
Min.
Typ.
Max.
Unit
–0.3
+40
+43.5
+28
VLOGIC
–0.3
+5.5
V
VLIN
–27
+40
+43.5
V
V
VVCC
IVCC
–0.3
+5.5
+200
V
mA
V
Logic level pins injection currents
- tPulse ≤ 2min
ILOGIC
–5
+5
HSout
- DC voltage
- DC output current
- DC current injection levels
VHSout < 0V and VHSout > VVS
VHSout
IHSout
IHSout
–0.3
–50
–20
VVS + 0.3
+10
V
mA
mA
VLSout
ILSout
–0.3
+42.5
+250
V
mA
EAS
EAR
10
2
LS1out and LS2out
- DC voltage
- DC output current
LS1out and LS2out clamping energies
- Single event
- Repetitive (f ≤ 5Hz)
WKin voltage levels
- DC voltage
-Transient voltage according to ISO7637
(coupling 1nF), (with 2.7k serial resistor)
VWKin
mA
mJ
–0.3
+40
–150
+100
V
ESD according to IBEE LIN EMC
Test spec. 1.0 following IEC 61000-4-2
- Pin VS, WKin and LIN to GND
(WKin with ext. circuitry acc. applications
diagram)
±6
kV
ESD according to ISO10605,
with 330pF/330
- Pin HSout (100 series resistor, 22nF to
GND) to GND
±6
kV
±6
±5
kV
kV
±3
kV
±750
V
ESD (HBM following STM5.1 with
1.5k / 100pF)
- Pin VS, LIN, HSout to GND
- Pin WKin to GND
Component Level ESD (HBM acc. ANSI/ESD
STM5.1)
JESD22-A114
AEC-Q100 (002)
CDM ESD STM 5.3.1
ATA663331/ATA663354 [DATASHEET]
9231A–AUTO–08/15
17
5.
Absolute Maximum Ratings (Continued)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
ESD machine model
AEC-Q100-RevF(003)
Min.
Typ.
Max.
Unit
±200
V
Junction temperature
Tj
–40
+150
°C
Storage temperature
Ts
–55
+150
°C
6.
Thermal Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Thermal resistance junction to heat slug
RthjC
8
K/W
Thermal resistance junction to ambient,
where heat slug is soldered to PCB
according to JEDEC
Rthja
45
K/W
Thermal shutdown of VCC regulator
TVCCoff
150
165
180
°C
Thermal shutdown of LIN output
TLINoff
150
165
180
°C
Thermal shutdown of driver stages
TDSoff
150
165
180
°C
Thermal shutdown hysteresis
7.
Thys
10
°C
Electrical Characteristics
5V < VVS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
1
Test Conditions
1.1 Nominal DC voltage range
1.2
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
VS pin
Supply current in sleep
mode
VS
VVS
5
13.5
28
V
A
Sleep mode
VLIN > VVS – 0.5V
VVS < 14V, T = 27°C
VS
IVSsleep
5
10
15
µA
B
Sleep mode
VLIN > VVS – 0.5V
VVS < 14V
VS
IVSsleep
3
11
18
µA
A
Sleep mode, VLIN = 0V
Bus shorted to GND
VVS < 14V
VS
IVSsleep_short
20
50
100
µA
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
18
ATA663331/ATA663354 [DATASHEET]
9231A–AUTO–08/15
7.
Electrical Characteristics (Continued)
5V < VVS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Bus recessive
5.5V < VVS < 14V, all drivers off
without load at VCC
T = 27°C
VS
IVSsilent
30
47
58
µA
B
Bus recessive
5.5V < VVS < 14V, all drivers off
without load at VCC
VS
IVSsilent
30
50
64
µA
A
Bus recessive
2V < VVS < 5.5V, all drivers off
without load at VCC
VS
IVSsilent
50
130
170
µA
A
Silent mode
5.5V < VVS < 14V, all drivers off
Bus shorted to GND
without load at VCC
VS
IVSsilent_short
50
80
120
µA
A
Bus recessive
VVS < 14V, all drivers off
without load at VCC
VS
IVSrec
150
230
300
µA
A
Bus dominant (internal LIN
pull-up resistor active)
VVS < 14V, all drivers off
without load at VCC
VS
IVSdom
200
700
950
µA
A
Bus recessive
5.5V < VVS < 14V, all drivers off
without load at VCC
VS
IVSfail
40
55
80
µA
A
Bus recessive
2V < VVS < 5.5V, all drivers off
without load at VCC
VS
IVSsilent
50
130
170
µA
A
VS undervoltage threshold Decreasing supply voltage
1.7 (switching from normal
mode to fail-safe mode)
Increasing supply voltage
VS
VVS_th_N_F_
3.9
4.3
4.7
V
A
VVS_th_F_N_up
4.1
4.6
4.9
V
A
1.8 VS undervoltage hysteresis
Supply current in silent
1.3
mode
1.4
Supply current in normal
mode
Supply current in normal
1.5
mode
Supply current in fail-safe
1.6
mode
VS operation threshold
1.9 (switching to unpowered
mode)
VS
VS
VVS_hys_F_N
0.1
0.25
0.4
V
A
Switch to unpowered mode
VS
VVS_th_U_down
1.9
2.05
2.3
V
A
Switch from unpowered mode
to fail-safe mode
VS
VVS_th_U_F_up
2.0
2.25
2.4
V
A
VS
VVS_hys_U
0.1
0.2
0.3
V
A
0.2
0.4
V
A
V
A
1.10 VS undervoltage hysteresis
2
down
RXD output pin
2.1
Low level output sink
capability
Normal mode,
VLIN = 0V, IRXD = 2mA
RXD
VRXDL
2.2
High level output source
capability
Normal mode
VLIN = VVS, IRXD = –2mA
RXD
VRXDH
VVCC –
0.4V
TXD
VTXDL
–0.3
+0.8
V
A
VVCC +
0.3V
V
A
100
k
A
+3
µA
A
3
VVCC –
0.2V
TXD input/output pin
3.1 Low-level voltage input
3.2 High-level voltage input
3.3 Pull-up resistor
VTXD = 0V
3.4 High-level leakage current VTXD = VVCC
TXD
VTXDH
2
TXD
RTXD
40
TXD
ITXD
–3
70
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA663331/ATA663354 [DATASHEET]
9231A–AUTO–08/15
19
7.
Electrical Characteristics (Continued)
5V < VVS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
Test Conditions
Fail-safe Mode
Low-level output sink
VLIN = VVS
3.5
current at wake-up request VWAKE = 0V
VTXD = 0.4V
4
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
TXD
ITXD
2
2.5
8
mA
A
EN
VENL
–0.3
+0.8
V
A
VVCC +
0.3V
V
A
200
k
A
+3
µA
A
0.2
0.4
V
A
4
6
ms
A
EN input pin
4.1 Low-level voltage input
4.2 High-level voltage input
EN
VENH
2
4.3 Pull-down resistor
VEN = VVCC
EN
REN
50
4.4 Low-level input current
VEN = 0V
EN
IEN
–3
5
125
NRES open drain output pin
5.1 Low-level output voltage
VVS ≥ 5.5V
INRES = 2mA
NRES
VNRESL
5.2 Undervoltage reset time
VVS ≥ 5.5V
CNRES = 20pF
NRES
tReset
2
Reset debounce time for
falling edge
VVS ≥ 5.5V
CNRES = 20pF
NRES
tres_f
0.5
10
µs
A
5.4 Switch-off leakage current VNRES = 5.5V
NRES
INRES_L
–3
+3
µA
A
4V < VVS < 18V
(0mA to 50mA)
VCC
VVCCnor
3.234
3.366
V
A
4.5V < VVS < 18V
(0mA to 85mA)
VCC
VVCCnor
3.234
3.366
V
C
VCC
VVCClow
VVS – VD
3.366
V
A
5.3
6
VCC voltage regulator Atmel ATA663331
6.1 Output voltage VCC
6.2
Output voltage VVCC at low
3V < VVS < 4V
VVS
6.3 Regulator drop voltage
VVS > 3V, IVCC = –15mA
VCC
VD1
100
150
mV
A
6.4 Regulator drop voltage
VVS > 3V, IVCC = –50mA
VCC
VD2
300
500
mV
A
6.5 Line regulation maximum
4V < VVS < 18V
VCC
VCCline
0.1
0.2
%
A
6.6 Load regulation maximum 5mA < IVCC < 50mA
VCC
VCCload
0.1
0.5
%
A
6.7 Output current limitation
VVS > 4V
VCC
IVCClim
–180
–120
mA
A
6.8 Load capacity
MLC capacitor
VCC
Cload
3.5
4.7
µF
D
VCC undervoltage
threshold (NRES ON)
Referred to VCC
VVS > 4V
VCC
VVCC_th_uv_
2.3
2.6
2.8
V
A
VCC undervoltage
threshold (NRES OFF)
Referred to VCC
VVS > 4V
VCC
VVCC_th_uv_up
2.4
2.7
2.9
V
A
6.10
Hysteresis of VCC
undervoltage threshold
Referred to VCC
VVS > 4V
VCC
VVCC_hys_uv
100
200
300
mV
A
6.11
Ramp-up time VVS > 4V to CVCC = 4.7µF
VCC = 3.3V
Iload = –5mA at VCC
VCC
tVCC
1
1.5
ms
A
5.5V < VVS < 18V
(0mA to 50mA)
VCC
VVCCnor
4.9
5.1
V
A
6V < VVS < 18V
(0mA to 85mA)
VCC
VVCCnor
4.9
5.1
V
C
Output voltage VVCC at low
4V < VVS < 5.5V
VVS
VCC
VVCClow
VVS – VD
5.1
V
A
6.9
7
VCC voltage regulator Atmel ATA663354
7.1 Output voltage VCC
7.2
down
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
20
ATA663331/ATA663354 [DATASHEET]
9231A–AUTO–08/15
7.
Electrical Characteristics (Continued)
5V < VVS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
7.3 Regulator drop voltage
VVS > 4V, IVCC = –20mA
VCC
7.4 Regulator drop voltage
VVS > 4V, IVCC = –50mA
VCC
VD1
100
200
mV
A
VD2
300
500
mV
A
7.5 Regulator drop voltage
VVS > 3.3V, IVCC = –15mA
VCC
VD3
7.6 Line regulation maximum
5.5V < VVS < 18V
VCC
VCCline
150
mV
A
0.2
%
A
7.7 Load regulation maximum 5mA < IVCC < 50mA
VCC
VCCload
0.1
7.8 Output current limitation
VVS > 5.5V
VCC
IVCClim
–180
0.5
%
A
–120
mA
A
7.9 Load capacity
MLC capacitor
µF
D
0.1
VCC
Cload
3.5
4.7
VCC undervoltage
threshold (NRES ON)
Referred to VCC
VVS > 4V
VCC
VVCC_th_uv_
4.2
4.4
4.6
V
A
VCC undervoltage
threshold (NRES OFF)
Referred to VCC
VVS > 4V
VCC
VVCC_th_uv_up
4.3
4.6
4.8
V
A
7.11
Hysteresis of undervoltage Referred to VCC
threshold
VVS > 5.5V
VCC
VVCC_hys_uv
100
200
300
mV
A
7.12
Ramp-up time VVS > 5.5V
to VVCC = 5V
VCC
tVCC
1
1.5
ms
A
7.10
8
8.1
CVCC = 4.7µF
Iload = –5mA at VCC
down
LIN bus driver: bus load conditions:
Load 1 (Small): 1nF, 1k; Load 2 (Large): 10nF, 500; CRXD = 20pF, Load 3 (Medium): 6.8nF, 660 characterized on samples
10.7 and 10.8 specifies the timing parameters for proper operation at 20kBit/s and 10.9kBit/s and 10.10kBit/s at 10.4kBit/s
Driver recessive output
voltage
Load1/Load2
LIN
VBUSrec
8.2 Driver-dominant voltage
VVS = 7V
Rload = 500
LIN
8.3 Driver-dominant voltage
VVS = 18V
Rload = 500
8.4 Driver-dominant voltage
0.9 
VVS
VVS
V
A
V_LoSUP
1.2
V
A
LIN
V_HiSUP
2
V
A
VVS = 7V
Rload = 1000
LIN
V_LoSUP_1k
0.6
V
A
8.5 Driver-dominant voltage
VVS = 18V
Rload = 1000
LIN
V_HiSUP_1k
0.8
V
A
8.6 Pull-up resistor to VVS
The serial diode is mandatory
LIN
RLIN
20
47
k
A
In pull-up path with Rslave
ISerDiode = 10mA
LIN
VSerDiode
0.4
1.0
V
D
LIN
IBUS_LIM
40
120
200
mA
A
LIN
IBUS_PAS_dom
–1
–0.35
mA
A
Driver off
8V < VVS < 18V
8V < VBUS < 18V
VBUS ≥ VVS
LIN
IBUS_PAS_rec
Leakage current when
control unit disconnected
GNDDevice = VVS
from ground.
8.11
VVS = 12V
Loss of local ground must
0V < VBUS < 18V
not affect communication in
the residual network
LIN
IBUS_NO_gnd
8.7
Voltage drop at the serial
diodes
8.8
LIN current limitation
VBUS = VBat_max
Input leakage current
Input leakage current at the
Driver off
8.9 receiver including pull-up
VBUS = 0V
resistor as specified
VVS = 12V
Leakage current LIN
8.10
recessive
–10
30
10
20
µA
A
+0.5
+10
µA
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA663331/ATA663354 [DATASHEET]
9231A–AUTO–08/15
21
7.
Electrical Characteristics (Continued)
5V < VVS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
LIN
IBUS_NO_bat
LIN
CLIN
VBUS_CNT = (Vth_dom + Vth_rec)/2
LIN
VBUS_CNT
0.475 
VVS
9.2 Receiver dominant state
VEN = 5V/3.3V
LIN
VBUSdom
–27
9.3 Receiver recessive state
VEN = 5V/3.3V
LIN
VBUSrec
0.6 VVS
LIN
VBUShys
0.028 
VVS
LIN
VLINH
LIN
Dominant time for wake-up
VLIN = 0V
via LIN bus
Leakage current at
disconnected battery. Node
has to sustain the current VVS disconnected
VSUP_Device = GND
8.12 that can flow under this
condition. Bus must remain 0V < VBUS < 18V
operational under this
condition.
8.13
9
9.1
Capacitance on the LIN pin
to GND
Min.
Typ.
Max.
Unit
Type*
0.1
2
µA
A
20
pF
D
0.525 
VVS
V
A
0.4 
VVS
V
A
LIN bus receiver
Center of receiver
threshold
0.5 
VVS
40
V
A
0.175 
VVS
V
A
VVS – 2V
VVS +
0.3V
V
A
VLINL
–27
VVS –
3.3V
V
A
LIN
tbus
50
100
150
µs
A
Time delay for mode
change from fail-safe mode
10.2
V = 5V/3.3V
to normal mode via the EN EN
pin
EN
tnorm
5
15
20
µs
A
Time delay for mode
change from normal mode
10.3
VEN = 0V
to sleep mode via the EN
pin
EN
tsleep
5
15
20
µs
A
TXD
tdom
20
40
60
ms
A
EN
ts_n
5
15
40
µs
A
10.7 Duty cycle 1
THRec(max) = 0.744  VVS
THDom(max) = 0.581  VVS
VVS= 7.0V to 18V
tBit = 50µs
D1 = tbus_rec(min)/(2  tBit)
LIN
D1
0.396
10.8 Duty cycle 2
THRec(min) = 0.422  VVS
THDom(min) = 0.284  VVS
VVS = 7.6V to 18V
tBit = 50µs
D2 = tbus_rec(max)/(2  tBit)
LIN
D2
9.4 Receiver input hysteresis
9.5
Pre-wake detection LIN
High-level input voltage
9.6
Pre-wake detection LIN
Low-level input voltage
10
Internal timers
10.1
10.4
TXD-dominant time-out
time
Vhys = Vth_rec – Vth_dom
Activates the LIN receiver
VTXD = 0V
Time delay for mode
10.6 change from silent mode to VEN = 5V/3.3V
normal mode via the EN pin
0.1 
VVS
A
0.581
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
22
ATA663331/ATA663354 [DATASHEET]
9231A–AUTO–08/15
A
7.
Electrical Characteristics (Continued)
5V < VVS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
10.9 Duty cycle 3
THRec(max) = 0.778  VVS
THDom(max) = 0.616  VVS
VVS = 7.0V to 18V
tBit = 96µs
D3 = tbus_rec(min)/(2  tBit)
LIN
D3
0.417
10.10 Duty cycle 4
THRec(min) = 0.389  VVS
THDom(min) = 0.251  VVS
VVS = 7.6V to 18V
tBit = 96µs
D4 = tbus_rec(max)/(2  tBit)
LIN
D4
LIN
tSLOPE_fall
tSLOPE_rise
3.5
22.5
µs
A
TXD
tDTOrel
10
20
µs
B
VVS = 7.0V to 18V
trx_pd = max(trx_pdr , trx_pdf)
RXD
trx_pd
6
µs
A
VVS = 7.0V to 18V
trx_sym = trx_pdr – trx_pdf
RXD
trx_sym
–2
+2
µs
A
WKin
VWKinH
VVS – 1V
VVS +
0.3V
V
A
VVS –
3.3V
V
A
–3
µA
A
+5
µA
A
100
150
µs
A
0.2
0.4
V
A
V
A
10.11
Slope time falling and rising
VVS = 7.0V to 18V
edge at LIN
TXD release time after
10.12 dominant time-out
detection
11
11.1
Propagation delay of
receiver
Unit
Type*
A
0.590
A
WKin pin
12.1 High-level input voltage
12.2 Low-level input voltage
Initializes a wake-up signal
WKin
VWKinL
–1
12.3 WKin pull-up current
VVS < 28V, VWKin = 0V
WKin
IWKin
–30
12.4 High-level leakage current VVS = 28V, VWKin = 28V
WKin
IWKinL
–5
Debounce time of low pulse
12.5
VWKin = 0V
for wake-up via WKin pin
WKin
tWKin
50
13
Max.
Receiver electrical AC parameters of the LIN physical layer
LIN receiver, RXD load conditions: CRXD = 20pF
Symmetry of receiver
11.2 propagation delay rising
edge minus falling edge
12
Typ.
–10
WKout pin
13.1
Low level output sink
capability
VWKin = VVS
IWKout = 2mA
WKout
VWKoutL
13.2
High level output source
capability
VWKin = 0V
IWKout = –2mA
WKout
VWKoutH
ILSout = 100mA
LSout
RDSon,LS
3

A
14.2 Leakage current
–0.2V < VLSout < 40V
LSout
ILSleak
10
µA
A
14.3 Active clamping voltage
ILSout = 20mA
LSout
VLSclamp
43
44
48
V
A
Short-circuit detection
14.4
threshold
5.5V < VVS < 28V
LSout
VSCth_LS
1.25
1.5
1.75
V
A
14.9 Switch-on slope (fall time)
VVS = 16V
Rload = 100
Cload = 1nF
transition from 80% down to
20% of VVS
LSout
tLSslope,fall
5
20
µs
A
14
14.1
VVCC –
0.4V
VVCC –
0.2V
LS1out, LS2out pins
Output drain-to-source on
resistance
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA663331/ATA663354 [DATASHEET]
9231A–AUTO–08/15
23
7.
Electrical Characteristics (Continued)
5V < VVS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
LSout
tLSslope,rise
14.11 Switch-on delay
VVS = 16V
Rload = 100
Cload = 1nF
time from LSin = high to
VLSout = 50% of VVS
LSout
14.12 Switch-off delay
VVS = 16V
Rload = 100
Cload = 1nF
time from LSin = low to
VLSout = 50% of VVS
VVS = 16V
Rload = 100
14.10 Switch-off slope (rise time) Cload = 1nF
transition from 20% to 80% of
VVS
14.13
15
Short circuit detection
debouncing time
Typ.
Max.
Unit
Type*
5
20
µs
A
tLSdel
5
30
µs
A
LSout
tLSdel
20
50
µs
A
LSout
tLsdeb
2
10
µs
B
LSin
VLSin_L
–0.3
0.3VVCC
V
A
VVCC +
0.3
V
A
150
k
A
+1
µA
A
kHz
D
3.75
LS1in, LS2in pins
15.1 Low-level voltage input
15.2 High-level voltage input
LSin
VLSin_H
0.7VVCC
15.3 Pull-down resistor
VLSin = VVCC
LSin
RLSin
50
15.4 Low-level input current
VLSin = 0V
LSin
ILSin
–1
RLoad,LSxout ≥ 100
LLoad,LSxout ≤ 1mH
LSin
fLSin,max
1
IHSout = –20mA
HSout
RDSon,HS
20

A
16.2 Leakage current
–0.2V < VHSout < VVS + 0.2V
HSout
Ileak,HS
2
µA
A
16.5 Switch-off slope (fall time)
VVS = 16V
Rload = 560
Cload = 1nF
transition from 80% down to
20% of VVS
HSout
tHSslope,fall
0.5
5
µs
A
HSout
tHSslope,rise
0.5
5
µs
A
16.7 Switch-on delay
VVS = 16V
Rload = 560
Cload = 1nF
time from HSin=HIGH to
VHSout = 50% of VVS
HSout
tHSdel
3
20
µs
A
16.8 Switch-off delay
VVS = 16V
Rload = 560
Cload = 1nF
time from HSin=LOW to
VHSout = 50% of VVS
HSout
tHSdel
3
20
µs
A
15.5
16
16.1
Maximum switching
frequency
100
HSout pin
Output drain-to-source on
resistance
VVS = 16V
Rload = 560
16.6 Switch-on slope (rise time) Cload = 1nF
transition from 20% to 80% of
VVS
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
24
ATA663331/ATA663354 [DATASHEET]
9231A–AUTO–08/15
7.
Electrical Characteristics (Continued)
5V < VVS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
Pin
Symbol
Min.
Short-circuit detection
threshold
HSout
VSCth_HS
16.10 Short-circuit deb. time
HSout
HSin
16.9
17
Test Conditions
Typ.
Max.
Unit
Type*
VVS – 6V
VVS – 2V
V
A
tHS_deb
2
10
µs
A
VHSin_L
–0.3
0.3VVCC
V
A
VVCC +
0.3
V
A
150
k
A
+1
µA
A
kHz
D
HSin pin
17.1 Low-level voltage input
17.2 High-level voltage input
HSin
VHSin_H
0.7VVCC
17.3 Pull-down resistor
VHSin = VVCC
HSin
RHSin
50
17.4 Low-level input current
VHSin = 0V
HSin
IHSin
–1
Rload = 560
LSin
fHSin,max
5
17.5
Maximum switching
frequency
100
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Figure 7-1. Definition of Bus Timing Characteristics
tBit
tBit
tBit
TXD
(Input to transmitting node)
tBus_dom(max)
tBus_rec(min)
Thresholds of
receiving node1
THRec(max)
VS
(Transceiver supply
of transmitting node)
THDom(max)
LIN Bus Signal
Thresholds of
receiving node2
THRec(min)
THDom(min)
tBus_dom(min)
tBus_rec(max)
RXD
(Output of receiving node1)
trx_pdf(1)
trx_pdr(1)
RXD
(Output of receiving node2)
trx_pdr(2)
trx_pdf(2)
ATA663331/ATA663354 [DATASHEET]
9231A–AUTO–08/15
25
8.
Application Circuits
Figure 8-1. Typical Application Circuit
VBAT
C4
C5
4.7µF
10µF/50V + C1
100nF
R1
10kΩ
D2
RXD
VCC
R2
1kΩ
VCC
EN
VS
C2
Microcontroller
NRES
TXD
WKout
Atmel
ATA663331
ATA663354
DFN16
3 x 5.5
100nF
Master node
pull-up
LIN
C3
220pF
GND
WKin
LS1in
LS1out
LS2in
LS2out
HSin
HSout
WKin (opt.)
S1
Rel1
µC
M
µC
LED1
Rel2
Heat Slug must be connected to ground.
ATA663331/ATA663354 [DATASHEET]
9231A–AUTO–08/15
GND
R3
2.7kΩ
R9
26
R4
10kΩ
LIN
GND
Note:
D1
9.
Ordering Information
Extended Type Number
Package
Remarks
ATA663331-GDQW
DFN16
3.3V LIN system basis chip, Pb-free, 6k, taped and reeled
ATA663354-GDQW
DFN16
5V LIN system basis chip, Pb-free, 6k, taped and reeled
Package Information
Top View
D
16
technical drawings
according to DIN
specifications
E
PIN 1 ID
1
A
Side View
A3
A1
Dimensions in mm
Two Step Singulation process
Partially Plated Surface
Bottom View
8
E2
1
Z
COMMON DIMENSIONS
(Unit of Measure = mm)
16
9
e
D2
Z 10:1
L
10.
b
Symbol
MIN
NOM
MAX
A
0.8
0.85
0.9
A1
0.0
0.035
0.05
A3
0.16
0.21
0.26
D
5.4
5.5
5.6
D2
4.6
4.7
4.8
E
2.9
3
3.1
E2
1.5
1.6
1.7
L
0.35
0.4
0.45
b
e
0.25
0.3
0.65
0.35
NOTE
10/11/13
TITLE
Package Drawing Contact:
[email protected]
Package: VDFN_5.5x3_16L
Exposed pad 4.7x1.6
GPC
DRAWING NO.
REV.
6.543-5168.01-4
1
ATA663331/ATA663354 [DATASHEET]
9231A–AUTO–08/15
27
11.
Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
28
Revision No.
History
9231A-AUTO-08/15
Initial revision.
ATA663331/ATA663354 [DATASHEET]
9231A–AUTO–08/15
XXXXXX
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© 2015 Atmel Corporation. / Rev.: 9231A–AUTO–08/15
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