ATA6843/ATA6844 BLDC Motor Driver and LIN System Basis Chip DATASHEET Features ● Broad operation voltage range from 5.25V to 32V ● Atmel® ATA6843 temperature range TJ = 150°C ● Atmel ATA6844 extended temperature range TJ = 200°C ● Direct driving of six external NMOS transistors with a maximum switching frequency of 50kHz ● Integrated charge pump to provide gate voltages for high-side drivers and to supply the gate of the external battery reverse protection NMOS ● Built-in 5V/3.3V voltage regulator with current limitation ● Reset signal for the microcontroller ● Sleep Mode with supply current of typically < 45µA ● Wake-up via LIN bus or high voltage input ● Programmable window watchdog ● Battery overvoltage protection and battery undervoltage management ● Overtemperature warning and protection (shutdown) ● Jump start compatible ● LIN transceiver conformal to LIN 2.1 and SAEJ2602-2 with outstanding EMC and ESD performance ● QFN48 package 7mm 7mm 9189K-AUTO-02/15 1. Description The Atmel® ATA6843 and Atmel ATA6844 are system basis chips for three-phase brushless DC motor controllers designed in Atmel’s state-of-the-art 0.8µm SOI technology SMART-I.S.™1. In combination with a microcontroller and six discrete power MOSFETs, the system basis chip forms a BLDC motor control unit for automotive applications. In addition, the circuits provide a 3.3V/5V linear regulator and a window watchdog. The circuit includes various control and protection functions like overvoltage and overtemperature protection, short circuit detection, and undervoltage management. Thanks to these function blocks, the driver fulfils a maximum of safety requirements and offers a high integration level to save cost and space in various applications. The target applications are most suitable for the automotive market due to the robust technology and the high qualification level. Atmel ATA6844, in particular, is designed for applications in a high-temperature environment. Figure 1-1. Block Diagram Charge Pump /RESET WD VINT Regulator /IH1-3 DG2 RX Hall B Hall A LIN 2 ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 WDEN GND EN SCREF Hall C WD Timer LIN LINGND TX Driver Control Atmel ATA6843/44 DG3 LIN Microcontroller DG1 High-side Driver 3 H3 High-side Driver 2 H2 High-side Driver 1 H1 S1 S2 Supervisor: Short Circuit Overtemperature Undervoltage COAST Oscillator CC Timer CC SLEEP Control Logic RWD IL1-3 VBG PBAT CPOUT CPHI2 CPLO2 CPHI1 CPLO1 VG VG Regulator VCC Regulator Hall C Hall B S3 Low-side Driver 1 L1 Low-side Driver 2 L2 Low-side Driver 3 L3 PGND VCC VINT VBAT VMODE VBAT Hall A 2. Pin Configuration /COAST EN VBAT NC VCC PGND L3 L2 L1 VG PBAT NC Figure 2-1. Pinning QFN48 CPLO1 CPHI1 CPLO2 CPHI2 CPOUT S1 H1 S2 H2 S3 H3 DG3 IL1 /IH1 RXD DG1 DG2 IL3 /IH3 IL2 /IH2 48 47 46 45 44 43 42 41 40 39 38 37 36 1 35 2 34 3 33 4 Atmel YWW 32 5 6 ATA6843/ATA6844 31 30 7 ZZZZZ-AL 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 LIN NC TXD VMODE VINT RWD CC /RESET WD WDEN SLEEP SCREF NC GND LINGND Note: YWW Date code (Y = Year - above 2000, WW = week number) ATA683x Product name ZZZZZ Wafer lot number AL Assembly sub-lot number Table 2-1. Pin Description Pin Symbol I/O Function 1 VMODE I 2 VINT I/O 3 RWD I 4 CC I/O RC combination to adjust cross conduction time 5 /RESET O Reset signal for microcontroller 6 WD I Watchdog trigger signal 7 WDEN I Enable and disable the watchdog 8 SLEEP I Microcontroller output to switch system in Sleep Mode 9 SCREF I Short circuit comparator Reference input 10 NC Selector for VCC and interface logic voltage level Blocking capacitor Resistor defining the watchdog interval Connect to GND 11 GND I Ground 12 LINGND I Ground for LIN, Connect to GND 13 LIN I/O 14 NC 15 TXD I Transmit signal to LIN bus from microcontroller 16 IL3 I Control Input for output L3 17 /IH3 I Control Input for output H3 18 IL2 I Control Input for output L2 19 /IH2 I Control Input for output H2 20 IL1 I Control Input for output L1 21 /IH1 I Control Input for output H1 LIN-bus terminal Connect to GND ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 3 Table 2-1. 4 Pin Description Pin Symbol I/O Function 22 RXD O Receive signal from LIN bus for microcontroller 23 DG1 O Diagnostic output 1 24 DG2 O Diagnostic output 2 25 DG3 O Diagnostic output 3 26 H3 O Gate voltage high-side 3 27 S3 I/O Voltage at half bridge 3 28 H2 O Gate voltage high-side 2 29 S2 I/O Voltage at half bridge 2 30 H1 O Gate voltage high-side 1 31 S1 I/O Voltage at half bridge 1 32 CPOUT I/O Charge pump output capacitor 33 CPHI2 I Charge pump capacitor 2 34 CPLO2 O Charge pump capacitor 2 35 CPHI1 I Charge pump capacitor 1 36 CPLO1 O Charge pump capacitor 1 37 NC 38 PBAT I 39 VG I/O Blocking capacitor 40 L1 O Gate voltage H-bridge, low-side 1 41 L2 O Gate voltage H-bridge, low-side 2 42 L3 O Gate voltage H-bridge, low-side 3 43 PGND I Power ground for H-bridge and charge pump 44 VCC O 5V/100mA supply for microcontroller Connect to GND Power supply (after reverse protection) for charge pump and gate drivers 45 NC 46 VBAT I Supply voltage for IC core (after reverse protection) 47 EN I High voltage enable input 48 /COAST I Control input for coast function of bridge ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 Connect to GND 3. Functional Description 3.1 Power Supply Unit with Supervisor Functions 3.1.1 Power Supply The IC has to be supplied by a reverse-protected battery voltage. To prevent damage to the IC, proper external protection circuitry has to be added. It is recommended to use at least one capacitor combination of storage and RF capacitors be-hind the reverse protection circuitry, which is connected close to the VBAT and GND pins of the IC. A fully integrated low-power and low-drop regulator (VINT regulator), stabilized by an external blocking capacitor, provides the necessary low-voltage supply needed for the wake-up process. A trimmed low-power band gap is used as reference for the VINT regulator as well as for the VCC regulator. All internal blocks are supplied by VINT regulator. VINT regulator must not be used for any external supply purposes. Nothing inside the IC except the logic interface to the external microcontroller is supplied by the 5V/3.3V VCC regulator. Both voltage regulators are checked by a “power-good comparator”, which keeps the whole chip in reset as long as the internal supply voltage (VINT regulator output) is too low and gnerates a reset for the external microcontroller if the out-put voltage of the VCC regulator is not sufficient. 3.1.2 Voltage Supervisor This function is implemented to protect the IC and the external power MOS transistors from damage due to overvoltage on PBAT input. In the event of overvoltage (VTHOV) or undervoltage (VTHUV), the external NMOS motor driver transistors will be switched off. The failure state will be flagged on DG2 pin. It is recommended to block PBAT with an external RF capacitor to suppress high frequency disturbances. 3.1.3 Temperature Supervisor An integrated temperature sensor prevents the IC from overheating. If the temperature is above the overtemperature prewarning threshold TJPW set, the diagnostic pin DG3 will be switched to HIGH to signal this event to the external microcontroller. The microcontroller should take actions to reduce the power dissipation in the IC. If the temperature rises above the overtemperature shutdown threshold TJ switch off, the VCC regulator and all output drivers together with the LIN transceiver will be switched OFF immediately and the /RESET signal will go LOW. Both thresholds have a built-in hysteresis to avoid oscillations. The IC will return to normal operation (Active Mode) when it has cooled down below the shutdown threshold. When the junction temperature drops below the pre-warning threshold, bit DG3 will be switched LOW. ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 5 3.2 Active Mode and Sleep Mode The IC has two modes: Active Mode and Sleep Mode. By default the IC starts in Active Mode (normal operation) after poweron. An Enter Sleep Mode procedure switches the IC from Active Mode to Sleep Mode (standby). Enter Active Mode procedures wake up the IC back from Sleep Mode. When in Sleep Mode the internal 5V supply (VINT regulator), the EN input pin, and a small part of the LIN receiver remain active to ensure a proper startup of the system. The VCC regulator is turned off. The Enter Sleep Mode and Enter Active Mode procedures are implemented as follows: Enter Sleep Mode: Pin SLEEP is a low-voltage input supplied by the VCC regulator. It is ESD protected by diodes against VCC and GND. Thus the input voltage at pin SLEEP must not go below GND or exceed the output voltage of the VCC regulator. A transition from HIGH to LOW followed by a permanent LOW signal for a minimum time period tgotosleep (typical 10µs) at pin SLEEP switches the IC to Sleep Mode as the SLEEP is edge triggered. VCC is switched off in Sleep Mode. It is recommended to keep SLEEP LOW during normal operation. Enter Active Mode Using Pin EN: Pin EN is a high-voltage input for external wake-up signals. Its input structure consists of a comparator with a built-in hysteresis. It is ESD-protected by diodes against GND and VBAT, and for this reason the applied input voltage must not go below GND or exceed VBAT. Pulling EN up to VBAT switches the IC to Active Mode. EN is debounced and edge triggered. Enter Active Mode Using the LIN Interface: Using the LIN interface provides a second possibility to wake-up the IC (see Figure 3-1). A voltage lower than the LIN prewake detection VLINL at pin LIN activates the internal LIN receiver and starts the wake-up detection timer. A falling edge at pin LIN followed by a dominant bus level VBUSdom maintained for a minimum time period (Tbus) and ending with a rising edge leads to a remote wake-up request. The device switches from Sleep Mode to Active Mode. The VCC regulator is activated and the internal LIN slave termination resistor is switched on. Figure 3-1. Wake-up Using the LIN Interface Active Mode Sleep Mode Active Mode SLEEP Tdebounce VCC LIN Tgotosleep = 10µs Tbus = 90µs Regulator Wake-up Time = 4 x TOSC In Sleep Mode the device has a very low current consumption even during short circuits or floating conditions on the bus. A floating bus can arise if the Master pull-up resistor is missing, e.g., it is switched off when the LIN-Master is in Sleep Mode or even if the power supply of the Master node is switched off. In order to minimize the current consumption IVBAT during voltage levels at the LIN-pin below the LIN pre-wake threshold, the receiver is activated only for a specific time tmon. If tmon elapses while the voltage at the bus is lower than Pre-wake detection low (VLINL) and higher than the LIN dominant level, the receiver is switched off again and the circuit changes back to sleep mode. The current consumption is then the result of IVBAT plus ILINwake. If a dominant state is reached on the bus no wake-up will occur. Even if the voltage rises above the Pre-wake detection high (VLINH), the IC will stay in sleep mode (see Figure 3-2). This means the LIN-bus must be above the Pre-wake detection threshold VLINH for a few microseconds before a new LIN wake-up is possible. 6 ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 Figure 3-2. Floating LIN-bus During Sleep Mode LIN Pre-wake VLINL LIN BUS LIN dominant state VBUSdom tmon IVSsleep + ILINwake IVSfail IVS IVSsleep Mode of operation Sleep Mode Int. Pull-up Resistor RLIN IVSsleep Wake-up Detection Phase Sleep Mode off (disabled) If the Atmel® ATA6843/ATA6844 is in Sleep Mode and the voltage level at the LIN is in dominant state (VLIN < VBUSdom) for a time period exceeding tmon (during a short circuit at LIN, for example), the IC switches back to Sleep mode. The VBAT current consumption then consists of IVBAT plus ILINWAKE. After a positive edge at pin LIN the IC switches directly to Active Mode (see Figure 3-3). Figure 3-3. Short Circuit to GND on the LIN-bus During Sleep Mode LIN Pre-wake LIN BUS VLINL LIN dominant state VBUSdom tmon tmon IVSfail IVS Mode of operation Int. Pull-up Resistor RLIN IVSsleep Sleep Mode Wake-up Detection Phase off (disabled) IVSsleep + ILINwake Sleep Mode Fail-Safe Mode on (enabled) ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 7 3.3 5V/3.3V VCC Regulator The 5V/3.3V regulator is fully integrated. It requires an external electrolytic capacitor in the range of 2.2µF up to 10µF and with an ESR in the range from 2 to 15 for stability (see Figure 3-4). The output voltage can be configured as either 5V or 3.3V by connecting pin VMODE to either pin VINT or GND. Since the regulator is not designed to be switched between both output voltages during operation, it is advisable to hard-wire VMODE pin. The logic levels of the microcontroller interface are adapted to the VCC regulator output voltage. The maximum output current (IOS1) of the regulator is 100mA. For TJ > 150°C the IOS1 of Atmel® ATA6844 is reduced to 80mA. The VCC regulator has a built-in short circuit protection. A comparator checks the output voltage of the VCC regulator and keeps the external microcontroller in reset as long as the voltage is below the lower operation minimum (shown in Figure 3-5). Figure 3-4. ESR versus Load Current for External Capacitors with Different Values ESR versus Load Current at Pin VCC ESR versus Load Current at Pin VCC 40 25 35 20 ESRmax (CVCC = 10µF) ESRmax (CVCC = 2.2µF) 25 ESR (Ω) ESR (Ω) 30 20 15 15 10 10 0 0 0 25 50 75 100 125 150 Load Current (mA) Figure 3-5. /RESET as Function of the VCC Output Voltage VCC 100% VCC 88% VCC 80% VCC 0V /RESET 8 ESRmin (CVCC = 10µF) 5 ESRmin (CVCC =2.2µF) 5 ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 0 25 50 75 100 Load Current (mA) 125 150 3.4 Reset and Watchdog Management The watchdog timing is based on the trimmed internal watchdog oscillator. Its period time TOSC is determined by the external resistor RWD. A HIGH signal on WDEN pin enables the watchdog function; a LOW signal disables it. Since the WDEN pin is equipped with an internal pull-up resistor the watchdog is enabled by default. In order to keep the current consumption as low as possible the watchdog is switched off during Sleep Mode. The timing diagram in Figure 3-6 shows the watchdog and external reset timing. Figure 3-6. Timing Diagram of the Watchdog in Conjunction with the /RESET Signal VCC 88% VCC Watchdog trigger edge /RESET Watchdog trigger in t2 window tresshort WD t1 tres td tres t2 t1 t2 td Reset and lead Reset and lead time, Watchdog cycle, time, no trigger trigger during lead time no trigger t1 Watchdog cycle, trigger during t2 window After power-up of the VCC regulator (VCC output exceeds 88% of its nominal value) /RESET output stays LOW for the timeout period tres (typical 10ms). Subsequently /RESET output switches to HIGH. During the following time td (typical 500ms) a rising edge at the input WD is expected otherwise another external reset will be triggered. When the watchdog has been correctly triggered for the first time, normal watchdog operation begins. A normal watchdog cycle consists of two time sections t1 and t2 followed by a short pulse for the time tresshort at /RESET if no valid trigger has been applied at pin WD during t2. Rising edges on WD pin during t1 also cause a short pulse on /RESET. Start for such a cycle is always the time of the last rising edge either on WD pin or on /RESET pin. If the watchdog is disabled (WDEN = LOW), only the initial reset for the time tres after power-up will be generated. Additional resets will be generated if the VCC output voltage drops below 80% of its nominal value. The following example demonstrates how to calculate the timing scheme for valid watchdog trigger pulses, which the external microcontroller has to provide in order to prevent undesired resets. Example: Using an external resistor RWD = 33k ±1% results in typical parameters as follows: TOSC = 12.4µs t1 = 980 TOSC = 12.1ms ±10% t2 = 780 TOSC = 9.6ms ±10% t1 + t2 = 21.7ms ±10% Hence, the minimum time the external microcontroller has to wait before pin WD can be triggered is in worst case tmin = 1.1 t1 = 13.3ms. The maximum time for the watchdog trigger on WD pin is tmax = 0.9 (t1 + t2) = 19.5ms. Thus watchdog trigger input must remain within tmax – tmin = 6.2ms. ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 9 Other values can be set up by picking a different resistor value for RWD. The dependency of TOSC on the value of RWD is shown in Figure 3-7. Figure 3-7. TOSC versus RWD 45 40 TOSC (µs) 35 TOSC (μs) 30 TOSCmax (µs) 25 20 TOSCmin (µs) 15 10 5 0 10 20 30 40 50 60 70 80 90 100 RWD (kΩ) The tolerance of TOSC is ±10% for resistors RWD with maximum ±1% in tolerance. 3.5 Charge Pump A charge pump has been implemented in order to provide sufficient voltage to operate the external high-side power-NMOS transistors and the VG regulator, which drives the low-side Power-NMOS transistors. The charge pump output voltage at CPOUT pin is controlled to settle typically about 15V above the voltage at pin PBAT. A built-in supervisor circuit checks if the output voltage is sufficient to operate the VG regulator and external Power-NMOS transistors. The output voltage is accepted as good when it rises above VCPCPGOOD. A charge pump failure is flagged at DG2 if this minimum can not be reached or if the output voltage drops below the lower threshold of VCPCPGOOD due to overloading. The two shuffle capacitors should have the same value. The value of the reservoir capacitor should be at least twice the value of one shuffle capacitor. Two external shuffle capacitors and an external reservoir capacitor have to be provided. The typical value for the two shuffle capacitors is 100nF, and for the reservoir capacitor is 1.5µF. All capacitors should be ceramic. The greater the capacitors are, the greater the output current capability. 3.6 VG Regulator The VG regulator provides a stable voltage to supply the low-side gate drivers and to deliver sufficient voltage for the external low-side Power-NMOS transistors. Typically the output voltage is 12V. In order to guarantee reliable operation even with a low battery voltage, the VG regulator is supplied by the charge pump output. For stability, an external ceramic capacitor of typically 470nF has to be provided. There is no internal supervision of the VG output voltage. 3.7 Output Drivers and Control Inputs IL1-IL3, /IH1-/IH3 and /COAST This IC offers six push-pull output drivers for the external low-side and high-side power-NMOS transistors. To guarantee reliable operation, the low-side drivers are supplied by the VG regulator while the high-side drivers are supplied directly by the charge pump. All drivers are designed to operate at switching frequencies in the range of DC up to 50kHz. The maximum gate charge that can be delivered to each external Power-NMOS transistor at 50kHz is 100nC. The output drivers L1 to L3 and H1 to H3 are directly controlled by the digital input pins IL1 to IL3 and /IH1 to /IH3 (see Table 3-1 on page 11). IL1 to IL3 are high active digital inputs equipped with an internal pull-down resistor, while /IH1 to /IH3 are low active digital inputs equipped with an internal pull-up resistor. The pin /COAST is a low active input with internal pull-up resistor, which forces low all output drivers L1-L3 and H1-H3, and turns off all external FETs. As a safety function, /COAST allows to emergency switch off all output drivers to coast a BLDC motor. 10 ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 To operate the output drivers properly the following requirements have to be fulfilled: 1. Device is in Active Mode. 2. In case of watchdog is enabled, at least one valid watchdog trigger has been accepted. 3. The voltage at pin PBAT lies within its operation range. Neither undervoltage nor overvoltage is present. 4. The charge pump output voltage has been accepted as good, thus it exceeded VCPCPGOOD. 5. No overtemperature shutdown has occurred. 6. /COAST is high If a short circuit is detected by one of the sense inputs S1 to S3, the output drivers will be switched off after a blanking time tSC of typically 6 µs and the output DG1 will be flagged (see also Section 3.8 “Short Circuit Detection and Short Circuit Comparator Reference Input” on page 11). The output drivers will be enabled again and DG1 will be cleared with a rising edge at one of the control inputs IL1 to IL3, or falling edge at one of the control inputs /IH1 to /IH3. Additional logic prevents short circuits due to switching on one power-NMOS transistor while the opposite one in the same branch is switched on already. Table 3-1. 3.8 Status of the Output Drivers Depending on the Control Inputs Mode Control Inputs IL(1..3) Control Inputs /IH(1..3) /COAST Driver Stage for External Power MOS L(1..3), H(1..3) Comments Sleep X X X OFF Sleep Mode Active X X 0 OFF Coast function active Active 0 1 1 OFF Active 1 1 1 L(1..3) ON, H(1..3) OFF Active 0 0 1 L(1..3) OFF, H(1..3) ON Active 1 0 1 OFF Shoot-through protection Short Circuit Detection and Short Circuit Comparator Reference Input Short circuits in the motor bridge circuitry are sensed by S1 to S3 inputs. Internal comparators monitor the voltage differences between the drain and the source terminals of the external power-NMOS transistors and compare it to voltage VSCREF applied at pin SCREF. If one transistor switches on and its drain-source voltage exceeds VSCREF threshold after a blanking time tSC (see Figure 3-8 on page 12), a short circuit in this branch will be detected. In this case, the short-circuit detected output will be switched off immediately and pin DG1 will be set to HIGH. With a rising edge at any of the pins IL1 to IL3 or a falling edge at any of the pins /IH1 to /IH3, the diagnostic output DG1will be reset and the drivers switched on again. Note, valid voltage range for short-circuit reference is 0.5V ≤ VSCREF ≤ 3.3V. Voltages outside this range will lead to incorrect short circuit thresholds. If pin SCREF is floating VSCREF will be set to approximately 2.5V by an integrated resistive voltage divider. 3.9 Cross Conduction Timer In order to prevent damage of the motor bridge due to peak currents a non-overlapping phase for switching the powerNMOS transistors is mandatory. Therefore, a cross conduction timer has been implemented to prevent switching on any output driver for a time tCC after any other driver has been switched off. This also accounts for toggling any other driver after a short circuit was detected. An external RC parallel combination defines the value for tCC and can be estimated as follows: tCC = KCC RCC (k) CCC (nF), KCC is specified in Section 8. “Electrical Characteristics” on page 16. The RC combination is connected between CC and GND pins. When one of the drivers has been switched off the RC combination is charged to 5V (VINT) and discharged with its time constant. Any low to high transition at IL1 to IL3 or any high to low transition at /IH1 to IH3 will be masked out at the driver outputs until the voltage at CC pin drops below 67% of its initial value (VINT). The timer will be re-triggered at any time by any falling edge at the control inputs. This is shown in the following figure. ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 11 Figure 3-8. Interaction of Short Circuit Detection and Cross Conduction Timer IL1 L1 Ignore VS1 Shut off for tSC = 6µs if VS1 > 4V /IH1 H1 Shut off IL3 Ignore VPBAT - VS1 if VPBAT - VS1 > 4V for tSC = 6µs L3 VCC = VVINT Ignore VS3 Shut off for tSC = 6µs if VS3 > 4V CC VCC = 67% VVINT tcc tcc tcc At least 5k minimum and 5nF at maximum should be used as values for the RC combination. 10k is recommended. If the non-overlapping phase is controlled by the external microcontroller, it is possible to do without the external capacitor. The minimum time tCC is defined by the parasitic capacitance at CC pin. 3.10 Diagnostic Outputs DG1 - DG3 As mentioned in the sections above, the diagnostic outputs DG1 to DG3 are used to signal failures. This is summarized in the following table. Note: This is only valid for VCC > VtHRESHLow. Otherwise all diagnostic outputs will be tristated. Table 3-2. Status of the Diagnostic Outputs (Normal Operation) Device Status Diagnostic Outputs CPOK OT1 OV UV SC DG1 DG2 DG3 Comments 0 X X X X – 1 – Charge pump failure X 1 X X X – – 1 Overtemperature prewarning X X 1 X X – 1 – Overvoltage X X X 1 X – 1 – Undervoltage X X X 1 X represents: no effect) OT1: overtemperature warning OV: overvoltage of PBAT UV: undervoltage of PBAT SC: short circuit CPOK: charge pump OK 1 – – Short circuit X Note: In order to differentiate between LIN and EN wake-up, DG1 output will be set to LOW or HIGH respectively. LOW indicates wake-up by LIN, HIGH indicates wake-up by EN. DG1 output will be cleared by the first valid watchdog trigger after wake-up or by the first rising edge at IL1 to IL3 if the watchdog is disabled or by the first falling edge at /IH1 to /IH3if the watchdog is disabled. 12 ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 Table 3-3. Indicating Wake-up Source Diagnostic Outputs 3.11 DG1 DG2 DG3 Wake-up Source 1 – – EN 0 – – LIN LIN Transceiver Atmel® ATA6843 and Atmel ATA6844 include a fully integrated LIN transceiver complying with LIN specification 2.1 and SAEJ2602 2. The transceiver consists of a low-side driver with slew rate control, wave shaping, current limiting, and a high voltage comparator followed by a debouncing unit in the receiver. During transmission, the data applied at pin TXD will be transferred to the bus driver to generate a bus signal on LIN pin. TXD input has an internal pull-up resistor. To minimize the electromagnetic emission of the bus line, the bus driver has a built-in slew rate control and wave-shaping unit. The transmission will be aborted by a thermal shutdown or by a transition to Sleep Mode. Figure 3-9. Definition of Bus Timing Parameters tBit tBit tBit TXD (Input to transmitting node) tBus_dom(max) tBus_rec(min) Thresholds of THRec(max) VS (Transceiver supply of transmitting node) receiving node1 THDom(max) LIN Bus Signal Thresholds of receiving node2 THRec(min) THDom(min) tBus_dom(min) tBus_rec(max) RXD (Output of receiving node1) trx_pdf(1) trx_pdr(1) RXD (Output of receiving node2) trx_pdr(2) trx_pdf(2) The recessive BUS level is generated from the integrated 30k pull-up resistor in series with an active diode. This diode protects against reverse currents on the bus line in case of a voltage difference between the bus line and VSUP (VBUS > VSUP). No additional termination resistor is necessary to use the IC as a LIN slave. If this IC is used as a LIN master, the LIN pin is terminated by an external 1 k resistor in series with a diode to VBAT. As PWM communication directly over the LIN transceiver in both directions is possible, there is no TXD timeout feature implemented in the LIN transceiver. ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 13 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are referenced to pin GND. (xxx) Values for the Atmel® ATA6844. Parameters Pin Symbol Min. Max. Input voltage Negative input current PGND VPGND –0.3 +0.3 VBAT IVBAT –15 mA Negative input current PBAT IPBAT –20 mA Supply voltage VBAT VVBAT +40 V +40 V Supply voltage Unit V PBAT VPBAT /RESET, DG1, DG2, DG3, RXD V/RESET, VDG1, VDG2, VDG3, VRXD –0.3 VVCC + 0.3 V IL1-3, /IH1-3, WD, WDD, SLEEP, TXD VIL1-3, V/IH1-3, VWD, VSLEEP, VTXD –0.3 VVCC + 0.3 V VINT, VCC VINT, VVVCC –0.3 +5.5 V Analog input voltage RWD, CC, SCREF VRWD , VCC, VSCREF –0.3 VVCC + 0.3 V Digital input voltage EN VEN –0.3 VVBAT + 0.3 V Digital input voltage –0.3 VVINT + 0.3 V +16 V Logic output voltage Logic input voltage Output voltage VMODE VVMODE Output voltage VG VVG Input voltage LIN VVLIN –27 VVBAT + 2 V S1, S2, S3 VS1, VS2, VS3 (–6) +40 V Output voltage Output voltage L1, L2, L3 VL1, VL2, VL3 VPGND – 0.3 VVG + 0.3 V Output voltage H1, H2, L3 VH1, VH2, VH3 VS1, 2, 3 – 1 VS1, 2, 3 + 16 V Charge pump CPLO1, 2 VCPLO1, VCPLO2 VPBAT + 0.3 V Charge pump CPHI1, 2 VCPHI1, VCPHI2 VCPOUT + 0.3 V Output voltage CPOUT VCPOUT Storage temperature Reverse current V °C –55 ICPLOx_R, ICPHIx_R, IVG_R, ICPOUT_R, ISx_R –2 mA –1 mA Lx, Hx Estimated values take TJ > 150°C into account. Note: 5. CPLOx, CPHIx, VG, CPOUT, Sx +52 +150 TStorage ILx_R, IHx_R Thermal Resistance Parameters Symbol Value Unit Thermal resistance junction to heat slug Rthjc <5 K/W Thermal resistance junction to ambient when heat slug is soldered to PCB Rthja 25 K/W 14 ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 6. Operating Range The operating conditions define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied unless otherwise stated explicitly. (xxx) Values for the Atmel® ATA6844 Parameters Symbol Min Max Unit (1) VVBAT 5.5 VTHOV V (2) VVBAT 4.3 5.5 V (3) Operating supply voltage Operating supply voltage Operating supply voltage VVBAT VTHOV 40 V Ambient temperature range TA –40 +150 °C Junction temperature range Notes: 1. Full functionality TJ –40 +150 (200) °C 7. 2. Output drivers are switched off, extended range for parameters for voltage regulators 3. Output drivers and charge pump are switched off Noise and Surge Immunity, ESD and Latch-up Parameters Standard and Test Conditions Value Conducted interferences ISO 7637-1 Conducted disturbances CISP25 ESD according to IBEE LIN EMC - Pins LIN, PBAT, VBAT - Pin EN (33k serial resistor) Test specification 1.0 following IEC 61000-4-2 Level 4(1) Level 5 ±6kV ±5kV ESD HBM with 1.5k/100pF ESD- STM5.1-2001 JESD22-A114E 2007 CEI/IEC 60749-26: 2006 AEC-Q100-002-Ref_D ±2kV ESD HBM with 1.5k/100pF Pins EN, LIN, PBAT, VBAT against GND ESD- STM5.1-2001 JESD22-A114E 2007 CEI/IEC 60749-26: 2006 AEC-Q100-002-Ref_D ±8kV ESD CDM (field induced method) Note: 1. Test pulse 5: Vbat max = 40V ESD STM5.3.1 - 1999 ±500V Static latch-up tested according to AEC-Q100-004 and JESD78. ● 3 to 6 samples, 0 failures ● Electrical post-stress testing at room temperature In test, the voltage at the pins VBAT, LIN, CP, VBATSW, Hx, and Sx must not exceed 45V when not able to drive the specified current. ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 15 8. Electrical Characteristics All parameters given are valid for 5.5V ≤ VVBAT ≤ VTHOVLO and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. (xxx) Values for the Atmel® ATA6844. No. Parameters 1 Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Power Supply and Supervisor Functions 1.1 Current consumption VVBAT VVBAT = 13.5V(1) 46 IVBAT 7 mA A 1.3 Current consumption VVBAT in Standby Mode VVBAT = 13.5V 46 IVBAT 65 µA A 1.4 Current consumption VPBAT in Standby Mode VPBAT = 13.5V 38 IVPBAT 9.0 20.0 µA A VVBAT > 7V 2 VVINT 4.7 5.3 V A 38 VTHOVLO 32.0 34.0 V A 1.7 Overvoltage hysteresis 38 VTOVhys 1.5 2.5 V A Undervoltage lock-out 1.8 threshold 38 VTHUVRC 4.75 5.25 V A 38 VTUVhys 0.2 0.4 V A TJPW set 120 (170) 145 (195) 170 (220) °C B 1.12 Thermal prewarning reset TJPW reset 105 (155) 130 (180) 155 (205) °C B Thermal prewarning hysteresis TJPW °C B 1.5 Internal power supply 1.6 1.9 Overvoltage lock-out threshold Undervoltage threshold hysteresis 1.11 Thermal prewarning set 1.13 5.0 15 1.14 Thermal shutdown off TJ switch off 150 (200) 175 (225) 200 (250) °C B 1.15 Thermal shutdown on TJ switch on 135 (185) 160 (210) 185 (235) °C B °C B 1.16 Thermal shutdown hysteresis TJ switch off 1.17 Ratio thermal shutdown off/thermal prewarning set TJ switch off/ TJPW set 1.05 1.15 B TJ switch on/ TJPW reset 1.05 1.15 B Ratio thermal shutdown 1.18 on/thermal prewarning reset 2 15 5V/3.3V Regulator 2.1 Regulated output voltage VMODE = VINT, 7V < VBAT < 40V VMODE = GND, 5.5V < VBAT < 40V ILoad = 0 to 100mA 2.2 Regulated output voltage VMODE = VINT, 7V < VBAT < 40V VMODE = GND, 5.5V < VBAT < 40V ILoad = 0 to 80mA 150°C < TJ < 200°C 44 VVCC 2.3 Regulated output voltage VMODE = VINT, 5.5V < VBAT < 7V VMODE = GND, 5V < VBAT < 5.5V ILoad = 0 to 60mA 44 VVCC 44 VVCC 4.85 3.20 5.15 3.40 4.85 3.20 5.15 3.40 4.50 2.97 5.15 3.40 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 16 ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 V A V A V A 8. Electrical Characteristics (Continued) All parameters given are valid for 5.5V ≤ VVBAT ≤ VTHOVLO and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. (xxx) Values for the Atmel® ATA6844. No. Parameters Test Conditions Pin 2.4 Regulated output voltage VMODE = VINT, 5.5V < VBAT < 7V VMODE = GND, 5V < VBAT < 5.5V ILoad = 0 to 50mA 150°C < TJ < 200°C 44 2.5 Line regulation VMODE = VINT, 7V < VBAT < 40V VMODE = GND, 5.5V < VBAT < 40V ILoad = 50mA, –40°C < TJ < 150°C 44 2.6 Load regulation VMODE = VINT, VBAT > 7V VMODE = GND, VBAT > 5.5V ILoad = 0 to 100mA ILoad = 0 to 80mA, 150°C < TJ < 200°C 44 2.7 Output current limit VMODE = VINT, VBAT > 7V VMODE = GND, VBAT > 5.5V ILoad at RESET 44 2.8 Output current limit VMODE = VINT, VBAT > 7V VMODE = GND, VBAT > 5.5V ILoad at RESET, 150°C < TJ < 200°C Symbol VVCC Min. Typ. 4.50 2.97 Max. 5.15 3.40 50 50 Unit Type* V A mV A mV A mA A mA C V A V A 50 50 IOS1 100 100 360 360 70 70 360 360 44 IOS1 2.12 HIGH threshold VMODE 1 VVMODE H 2.13 LOW threshold VMODE 1 VVMODE L 0.7 VCC threshold voltage level VMODE = VINT for /RESET (VMODE = GND) 5 VtHRESHLow 3.8 2.5 4.2 2.8 V A B VMODE = VINT (VMODE = GND) 5 HYSRESth 0.2 0.13 0.6 0.4 V A B 5 tres 8 12 ms A 5 tresshort 1.6 2.4 ms A 5 td 400 600 ms A 5 tdelayRESL 2 µs C (5) TOSC 13.55 µs A 3 3.1 Reset and Watchdog 3.2 Hysteresis 3.3 Length of pulse at /RESET 3.4 Length of short pulse at /RESET 3.5 Wait for the first WD trigger 3.6 4.0 Time for VCC < VtHRESL before activating /RESET 3.8 Watchdog oscillator period RRWD = 33k ±1% 11.09 3.12 Close window (5) t1 980 TOSC 3.13 Open window (5) t2 780 TOSC 5 VOLRES 5 RPURES 3.14 Output low-level at pin /RESET 3.15 Internal pull-up resistor at pin /RESET IOLRES = 1mA 5 10 A A 0.4 V A 15 k D *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 17 8. Electrical Characteristics (Continued) All parameters given are valid for 5.5V ≤ VVBAT ≤ VTHOVLO and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. (xxx) Values for the Atmel® ATA6844. No. Parameters Test Conditions Pin Symbol Min. 4.1 Low-level output current Normal mode; VLIN = 0V, VRXD = 0.4V 22 ILRXD 2 4.2 High-level output current Normal mode; VLIN = VBAT VRXD = VCC – 0.4V 22 IHRXD 4 Typ. Max. Unit Type* LIN Transceiver –2 0.9 VBAT mA D mA D V A 4.3 Driver recessive output voltage VTXD = VCC; ILIN = 0mA 13 VBUSrec 4.4 Driver dominant voltage VBUSdom_DRV_LoSUP VVBAT = 7.3V Rload = 500 13 V_LoSUP 1.2 V A 4.5 Driver dominant voltage VBUSdom_DRV_HiSUP VVBAT = 18V Rload = 500 13 V_HiSUP 2 V A 4.6 Driver dominant voltage VBUSdom_DRV_LoSUP VVBAT = 7.3V Rload = 1000 13 V_LoSUP_1k 0.6 V A 4.7 Driver dominant voltage VBUSdom_DRV_HiSUP VVBAT = 18V Rload = 1000 13 V_HiSUP_1k_ 0.8 V A 4.8 Pull up resistor to VS Serial diode required 13 RLIN 20 47 k A 4.9 Current limitation VBUS = VBAT_max 13 IBUS_LIM 50 200 mA A 13 IBUS_PAS_dom –1 mA A Driver off 8V < VBAT < 18V 8V < VBUS < 18V VBUS = VBAT 13 IBUS_PAS_rec 20 µA A Leakage current at ground loss Control unit disconnected GNDDevice = VS 4.12 from ground VBAT = 12V Loss of local ground must 0V < VBUS < 18V not affect communication in the residual network 13 IBUS_NO_gnd +1 mA A Node has to sustain the current that can flow under VBAT disconnected 4.13 this condition. Bus must VSUP_Device = GND remain operational under 0V < VBUS < 18V this condition 13 IBUS 100 µA A VBUS_CNT = (Vth_dom + Vth_rec)/2 13 VBUS_CNT 0.525 VVBAT V A 4.15 Receiver dominant state VEN = 5V 13 VBUSdom 0.4 VVBAT V A 4.16 Receiver recessive state VEN = 5V 13 VBUSrec V A 4.17 Receiver input hysteresis VHYS = Vth_rec – Vth_dom 13 VBUShys V A Input leakage current Input leakage current at driver off 4.10 the receiver including pullVBUS = 0V up resistor as specified VBAT = 12V Leakage current LIN 4.11 recessive 4.14 Center of receiver threshold –1 0.475 VVBAT 0.5 VVBAT 0.6 VVBAT 0.175 VVBAT *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 18 ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 8. Electrical Characteristics (Continued) All parameters given are valid for 5.5V ≤ VVBAT ≤ VTHOVLO and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. (xxx) Values for the Atmel® ATA6844. No. Parameters Test Conditions Pin Symbol Min. 4.18 Duty cycle 1 7V < VVBAT < 18V THrec(max) = 0.744 VVBAT THDom(max) = 0.581 VVBAT tBit = 50µs D1 = tBus_rec(min)/(2 tBit) Load1: 1nF + 1k Load2: 10nF + 500 13 D1 0.396 4.19 Duty cycle 2 7V < VVBAT < 18V THrec(min) = 0.422 VVBAT THDom(min) = 0.284 VVBAT tBit = 50µs D2 = tBus_rec(max)/(2×tBit) Load1: 1nF + 1k Load2: 10nF + 500 13 D2 4.20 Duty cycle 3 7V < VVBAT < 18V THrec(max) = 0.778 VVBAT THDom(max) = 0.616 VVBAT tBit = 96µs D3 = tBus_rec(min)/(2 tBit) Load1: 1nF + 1k Load2: 10nF + 500 13 D3 4.21 Duty cycle 4 7V < VVBAT < 18V THrec(max) = 0.389 VVBAT THDom(max) = 0.251 VVBAT tBit = 96µs D4 = tBus_rec(min)/(2 tBit) Load1: 1nF + 1k Load2: 10nF + 500 13 D4 0.590 7V < VVBAT < 18V trec_pd = max(trx_pdr, trx_pdf) 22 trx_pd 6 µs A 7V < VVBAT < 18V trx_sym = trx_pdr – trx_pdf 22 trx_sym –2 +2 µs A 4.22 Receiver propagation delay Symmetry of receiver 4.23 propagation delay rising edge minus falling edge Typ. Max. Unit Type* A 0.581 A 0.417 A A 4.24 Dominant time for wake-up VLIN = 0V via LIN Bus 13 TBUS 30 90 150 µs A 4.25 Monitoring time for wakeup over LIN Bus 13 Tmon 6 10 15 ms B 4.26 Pre-wake detection LIN Low-Level Input Voltage 13 VLINL –27 VVBAT – 3.3 V A 4.27 Pre-wake detection LIN High-Level Input Voltage 13 VLINH VVBAT – 2 VVBAT + 0.3 V A 4.28 LIN Pre-Wake pull-up current 13 ILINWake –30 µA A 4.29 Capacitance on LIN Pin to GND 13 CLIN pF D Switches the LIN receiver on VVBAT < 27V VLIN = 0V –10 10 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 19 8. Electrical Characteristics (Continued) All parameters given are valid for 5.5V ≤ VVBAT ≤ VTHOVLO and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. (xxx) Values for the Atmel® ATA6844. No. Parameters Pin Symbol 5.1 Input low-level threshold 6-8, 1521, 48 VIL 5.2 Input high-level threshold 6-8, 1521, 48 VIH 0.7 VVCC 5.3 Hysteresis 6-8, 1521, 48 HYS 0.3 5 Test Conditions Min. Typ. Max. Unit Type* Control Inputs WD, WDEN, SLEEP, TXD, IL1-3, /IH1-3, /COAST 0.3 VVCC V A V A C 5.4 Pull-down resistor WD, SLEEP, IL1-3 6, 8, 16, 18, 20 RPD 25 50 100 k A 5.5 Pull-up resistor WDEN, TXD, /IH1-3, /COAST 7, 15, 17, 19, 21, 48 RPU 25 50 100 k A 8 tgotosleep 9 10 11 µs A 6.1 Charge pump voltage VVBAT > 7V ILoadCPOUT = 0A ILoadVG = 0A CCP1,2 = 47nF CCPOUT = 220nF 32 VCPOUT VVBAT + 11V VVBAT + 18 V A 6.2 Charge pump voltage VVBAT > 7V ILoadCPOUT = 7.5mA, ILoadVG = 0A CCP1,2 = 47nF CCPOUT = 220nF 32 VCPOUT VVBAT +10V V A µs B 8.0 V A 14 V A 5.7 Debounce time SLEEP 6 Charge Pump 6.3 Period charge pump oscillator 6.4 Charge pump output voltage for active drivers 7 TCP 2.5 32 VCPCPGOOD 5.25 11 VG Regulator 7.1 VG Regulator Output Voltage VBAT = 13.5V VCPOUT = 20V ILoadVG = 7.5mA 39 VVG 7.2 VG Regulator Line Regulation VBAT = 13.5V VCPOUT1 = 20V, VCPOUT2 = 35V ILoadVG = 7.5mA 39 VVG_Line 100 mV A 7.3 VG Regulator Load Regulation VBAT = 13.5V VCPOUT = 25V ILoadVG1 = 1mA, ILoadVG2 = 60mA 39 VVG_Load 100 mV A 40-42 VLxH VVG V D 8 12.5 H-bridge Driver 8.1 Low-side driver HIGH output voltage 8.2 ON-resistance of sink stage of pins Lx ILX = 100mA 40-42 RDSON_LxL 20 A 8.3 ON-resistance of source stage of pins Lx ILX = 100mA 40-42 RDSON_LxH 20 A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 20 ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 8. Electrical Characteristics (Continued) All parameters given are valid for 5.5V ≤ VVBAT ≤ VTHOVLO and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. (xxx) Values for the Atmel® ATA6844. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 40-42 to 43 RLxsink 45 75 115 k A 8.6 Sink resistance between Lx and GND 8.7 ON-resistance of sink stage of pins Hx VSx = 0V 26, 28, 30 RDSON_HxL 20 A 8.8 ON-resistance of source stage of pins Hx VSx = VVBAT IHx = 100mA 26, 28, 30 RDSON_HxH 20 A 8.13 Output voltage low level pins Hx VSx = 0V IHx = 1mA 26, 28, 30 VHxL 0.3 V A 8.14 Output voltage high level pins Hx IHx = –100µA 26, 28, 30 VHxHstat VVCPOUT – 1V VVCPOUT V A 8.15 Sink resistance between Hx and Sx 26-31 RHxsink 45 115 k A 8.16 Sink resistance between Sx and GND 27, 29, 31, 38 RSxsink M D Propagation delay time, 8.17 low-side driver from high to low 40-42 tLxHL 0.9 µs A Propagation delay time, 8.18 low-side driver from low to high 40-42 tLxLH 0.9 µs A 75 1 Dynamic Parameters 8.19 Fall time low-side driver VVBAT = 13.5V CGx = 5nF 40-42 tLxf 0.3 µs A 8.20 Rise time low-side driver VVBAT = 13.5V CGx = 5nF 40-42 tLxr 0.3 µs A Propagation delay time, 8.21 high-side driver from high to low 26, 28, 30 tHxHL 0.9 µs A Propagation delay time, 8.22 high-side driver from low to high 26, 28, 30 tHxLH 0.9 µs A 8.23 Fall time high-side driver VVBAT = 13.5V, CGx = 5nF 26, 28, 30 tHxf 0.3 µs A 8.24 Rise time high-side driver VVBAT = 13.5V, CGx = 5nF 26, 28, 30 tHxr 0.3 µs A 9 VSCREF 0.5 3.3 V A 9, 27, 29, 31 VSCREF –10 +10 % A 9 VSCREF_DEF V C 8.28 Internal resistor to GND 9 RiGND 80 100 120 k A 8.29 Internal resistor to VBAT 9 RiVBAT 80 100 120 k A 8.25 Valid Short circuit detection voltage range 8.26 Accuracy Short circuit detection voltage 8.27 Default Short Circuit detection voltage 0.5V ≤≤ VSCREF ≤≤ 3.3V 2.5 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 21 8. Electrical Characteristics (Continued) All parameters given are valid for 5.5V ≤ VVBAT ≤ VTHOVLO and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. (xxx) Values for the Atmel® ATA6844. No. Parameters Test Conditions Pin 8.30 Short circuit blanking time Symbol Min. Typ. Max. tSC 5.4 6 6.6 KCC 0.345 0.405 0.465 Unit Type* µs A Cross Conduction Timer 8.31 9 Cross conduction time constant B Input EN 9.1 Input low level threshold 47 VIL 2.3 3.6 V A 9.2 Input high level threshold 47 VIH 2.8 4.0 V A 9.3 Hysteresis 47 HYS V C 9.4 Pull-down resistor 47 RPD 50 100 200 k A 9.5 Debounce time 47 tdb 10 20 25 µs A 2 mA A mA A 10 0.47 Diagnostic Outputs DG1, DG2, DG3 10.1 Low level output current VDG = 0.4V 23-25 IL 10.2 High level output current VDG = VCC – 0.4V 23-25 IH –2 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 22 ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 9. Application This section describes the principal application for which the Atmel® ATA6843/ATA6844 was designed. Figure 9-1. Typical Application Battery + CCPOUT CCP1 CPBAT PBAT CPOUT CPHI2 CPLO2 CCP2 CPHI1 CPLO1 CVG VG VMODE VBAT VINT CVINT CVBAT CVCC VCC VCC Regulator VG Regulator Charge Pump /RESET WD VINT Regulator /IH1-3 DG1 DG2 WDEN GND SCREF EN LINGND LIN DAC WD Timer LIN RWD ADC High-side Driver 2 H2 High-side Driver 1 H1 S1 S3 CC Timer RCC Low-side Driver 1 L1 Low-side Driver 2 L2 Low-side Driver 3 L3 PGND RX TX Driver Control Atmel ATA6843/44 DG3 H3 S2 Supervisor: Short Circuit Overtemperature Undervoltage COAST Oscillator CC SLEEP Control Logic RWD Microcontroller IL1-3 VBG High-side Driver 3 CCC VCC Hall C Hall B Hall A LIN KL 15 ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 23 Table 9-1. Typical External Components Component Min. Typical Max. 220nF/10V 470nF CVINT Blocking capacitor at VINT 100nF CVCC Blocking capacitor at VCC 1.5µF 10µF ESL (CVCC) Serial inductance to CVCC including PCB 1nH 20nH ESR (CVCC) Serial resistance to CVCC including PCB 2 15 CVG Blocking capacitor at VG 220nF 470nF, 25V 1µF CCP1 Charge pump shuffle capacitor 47nF 100nF/25V 220nF CCP2 Charge pump shuffle capacitor 47nF 100nF/25V 220nF Charge pump reservoir capacitor 470nF 15 CCPx/25V 3.3µF Resistor defining internal bias currents for watchdog oscillator 10k 33 k 91k RCC Cross conduction time definition resistor 5k CCC Cross conduction time definition capacitor 330pF CVBAT Blocking capacitor VBAT 100nF CPBAT Blocking capacitor PBAT 100nF CCPOUT RRWD 24 Function ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 10k 5nF 10. Ordering Information Extended Type Number Package Remarks ATA6843-PLQW-1 QFN48 Pb-free, 4k ATA6844-PLQW-1 QFN48 Pb-free, 4k Package Information Top View D 48 1 technical drawings according to DIN specifications E PIN 1 ID Dimensions in mm A Side View A3 A1 12 Bottom View D2 13 24 25 12 E2 COMMON DIMENSIONS 1 A 36 48 37 e A (10:1) L 11. (Unit of Measure = mm) Symbol MIN NOM MAX A 0.8 0.85 0.9 A1 A3 0 0.16 0.035 0.21 0.05 0.26 D 6.9 7 7.1 D2 5.5 5.6 5.7 E 6.9 7 7.1 E2 5.5 5.6 5.7 L 0.35 0.4 0.45 b e 0.2 0.25 0.5 0.3 NOTE b 05/20/14 TITLE Package Drawing Contact: packagedrawings[email protected] Package: QFN_7x7_48L Exposed pad 5.6x5.6 GPC DRAWING NO. REV. 6.543-5188.03-4 1 ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 25 12. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 9189K-AUTO-02/15 9189J-AUTO-05/14 9189I-AUTO-03/14 History Section 10 “Ordering Information” on page 25 updated Section 11 “Package Information” on page 25 updated Section 8 “Electrical Characteristics” numbers 8.4 and 8.5 on page 20 removed Section 3.8 “Short Circuit Detection and Short Comparator Reference Input” on page 11 updated Section 4 “Absolute Maximum Ratings” on page 14 updated Section 8 “Electrical Characteristics” numbers 8.9 to 8.12 on page 21 removed 9189H-AUTO-07/12 Figure 3-1 “Wake-up Using the LIN Interface” on page 6 updated Section 11 “Package Information” on page 25 updated 9189G-AUTO-03/12 Section 4 “Absolute Maximum Ratings” on page 14 changed 9189F-AUTO-10/11 Section 8 “Electrical Characteristics” numbers 8.1, 8.4, 8.7, 8.9, 8.10, 8.11, 812, 8.17, 8.19, 8.21 and 8.26 on pages 23 to 25 changed Example test changed and text under figure 3-5 on page 11 added Section 8 “Electrical Characteristics” number 3.8 on page 20 changed 9189E-AUTO-08/11 Section 8 “Electrical Characteristics” number 8.31 on page 25 changed Figure 9-1 “Typical Application” on page 26 changed Table 9-1 “Typical External Components” on page 27 changed Features on page 1 changed 9189D-AUTO-03/11 Section 8 “Electrical Characteristics” number 1.6 on page 19 changed Section 8 “Electrical Characteristics” numbers 8.10 and 8.12 on page 24 changed 9189C-AUTO-01/11 9189B-AUTO-10/10 26 Section 8 “Electrical Characteristics” numbers 8.28 and 8.29 on page 25 added Section 4 “Absolute Maximum Ratings” on page 17 changed Section 8 “Electrical Characteristics” numbers 8.23 and 8.24 on page 25 changed. ATA6843/ATA6844 [DATASHEET] 9189K–AUTO–02/15 XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2015 Atmel Corporation. / Rev.: 9189K–AUTO–02/15 Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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