Features • Operating Voltage: 5V • Access Time: 30, 45 ns • Very Low Power Consumption • • • • • • • • – Active: 600 mW (Max) – Standby: 1 µW (Typ) Wide Temperature Range: -55⋅C to +125⋅C 400 Mils Width Packages: FP32 and SB32 TTL Compatible Inputs and Outputs Asynchronous No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2@125°C Tested up to a Total Dose of 30 krads (Si) according to MIL STD 883 Method 1019 QML Q and V with SMD 5962-89598 ESCC with Specification 9301/047 Description The M65608E is a very low power CMOS static RAM organized as 131072 x 8 bits. Utilizing an array of six transistors (6T) memory cells, the M65608E combines an extremely low standby supply current (Typical value = 0.2 µA) with a fast access time at 30 ns over the full military temperature range. The high stability of the 6T cell provides excellent protection against soft errors due to noise. Rad. Tolerant 128Kx8, 5-Volt Very Low Power CMOS SRAM M65608E The M65608E is processed according to the methods of the latest revision of the MIL PRF 38535 or ESCC 9000. 4151P–AERO–11/12 Block Diagram Pin Configuration 32-lead DIL side-brazed 400 MILS 32-lead Flatpack 400 MILS NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CS2 WE A13 A8 A9 A11 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 M65608E 4151P–AERO–11/12 M65608E Pin Description Table 1. Pin Names Names Description A0 - A16 Address inputs I/O0 - I/O7 Data Input/Output CS1 Chip select 1 CS2 Chip select 2 WE Write Enable OE Output Enable VCC Power GND Ground Table 2. Truth Table CS1 CS2 WE OE Inputs/ Outputs H X X X Z Deselect/ Power-down X L X X Z Deselect/Power-down L H H L Data Out Read L H L X Data In Write L H H H Z Note: Mode Output Disable L = low, H = high, X = H or L, Z = high impedance. 3 4151P–AERO–11/12 Electrical Characteristics Absolute Maximum Ratings Supply voltage to GND potential: ........................ -0.5V + 7.0V Stresses beyond those listed under "Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure between recommended DC operating and absolute maximum rating conditions for extended periods may affect device reliability. *NOTE: Voltage range on any input: ............ GND - 0.5V to VCC + 0.5 Voltage range on any ouput: ........... GND - 0.5V to VCC + 0.5 Storage temperature: ..................................... -65⋅C to +150⋅C Output Current from Output Pins: ................................ 20 mA Electrostatic Discharge Voltage (MIL STD 883D method 3015): .................................. > 2000V Military Operating Range Operating Voltage Operating Temperature 5V + 10% -55⋅C to + 125⋅C Recommended DC Operating Conditions Parameter Description Minimum Typical Maximum Unit VCC Supply voltage 4.5 5.0 5.5 V GND Ground 0.0 0.0 0.0 V VIL Input low voltage GND - 0.5 0.0 0.8 V VIH Input high voltage 2.2 – VCC + 0.5 V Parameter Description Cin(Note:) Cout(Note:) Capacitance Note: 4 Minimum Typical Maximum Unit Input low voltage – – 8 pF Output high voltage – – 8 pF Guaranteed but not tested. M65608E 4151P–AERO–11/12 M65608E DC Parameters DC Test Conditions TA = -55°C to + 125°C; Vss = 0V; VCC = 4.5V to 5.5V Symbol Description Minimum Typical Maximum Unit IIX (1) Input leakage current -1 – 1 µA IOZ(1) Output leakage current -1 – 1 µA VOL (2) Output low voltage – – 0.4 V VOH (3) Output high voltage 2.4 – – V 1. GND < Vin < VCC, GND < Vout < VCC Output Disabled. 2. 3. VCC min. IOL = 8 mA VCC min. IOH = -4 mA. Consumption Symbol Description 65608E-30 65608E-45 Unit Value ICCSB (1) Standby supply current 2 2 mA max ICCSB1 (2) Standby supply current 300 300 µA max ICCOP (3) Dynamic operating current 110 100 mA max 1. 2. 3. CS1 > VIH or CS2 < VIL and CS1 < VIL. CS1 > VCC - 0.3V or, CS2 < GND + 0.3V and CS1 < 0.2V. F = 1/TAVAV, Iout = 0 mA, WE = OE = VIH, Vin = GND or VCC, VCC max. 5 4151P–AERO–11/12 AC Parameters AC Test Conditions Input Pulse Levels: ................................................................................................. GND to 3.0V Input Rise/Fall Times: .......................................................................................................... 5 ns Input Timing Reference Levels: .......................................................................................... 1.5V Output loading IOL/IOH (see Figure 1 and Figure 2) ...................................................... +30 pF AC Test Loads Waveforms Figure 1 6 Figure 2 Figure 3 M65608E 4151P–AERO–11/12 M65608E Data Retention Mode Atmel CMOS RAM’s are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. During data retention chip select CS1 must be held high within VCC to VCC -0.2V or, chip select CS2 must be held down within GND to GND +0.2V. 2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, minimizing power dissipation. 3. During power up and power-down transitions CS1 and OE must be kept between VCC + 0.3V and 70% of VCC, or with CS2 between GND and GND -0.3V. 4. The RAM can begin operation > TR ns after VCC reaches the minimum operation voltages (4.5V). Timing Data Retention Characteristics Minimum Typical TA = 25 ⋅C Maximum Unit VCC for data retention 2.0 – – V TCDR Chip deselect to data retention time 0.0 – – ns TR Operation recovery time TAVAV(1) – – ns ICCDR1 Data retention current at 2.0V – 0.1 150 µA ICCDR2(2) Data retention current at 3.0V – 0.2 200 µA Parameter Description VCCDR Notes: 1. TAVAV = Read Cycle Time 2. CS1 = VCC or CS2 = CS1 = GND, Vin = GND/VCC, this parameter is only tested at VCC = 2V. 3. Parameters guaranteed but not tested 7 4151P–AERO–11/12 Write Cycle Symbol Parameter 65608-30 65608-45 Unit Value TAVAW Write cycle time 30 45 ns min TAVWL Address set-up time 0 0 ns min TAVWH Address valid to end of write 22 35 ns min TDVWH Data set-up time 18 20 ns min TE1LWH CS1 low to write end 22 35 ns min TE2HWH CS2 high to write end 22 35 ns min TWLQZ Write low to high Z(1) 8 15 ns max TWLWH Write pulse width 22 35 ns min TWHAX Address hold from to end of write 0 0 ns min TWHDX Data hold time 0 0 ns min TWHQX Write high to low Z(1) 0 0 ns min Note: Write Cycle 1 8 1. Parameters guaranteed, not tested, with output loading 5 pF. WE Controlled, OE High During Write M65608E 4151P–AERO–11/12 M65608E Write Cycle 2 WE Controlled, OE Low Write Cycle 3 CS1 or CS2 Controlled Note: The internal write time of the memory is defined by the overlap of CS1 Low and CS2 High and WE Low. Both signals must be actived to initiate a write and either signal can terminate a write by going inactived. The data input setup and hold timing should be referenced to the active edge of the signal that terminates the write. Data out is high impedance if OE = VIH. 9 4151P–AERO–11/12 Read Cycle Symbol Parameter 65608-30 65608-45 Unit Value TAVAV Read cycle time 30 45 ns min TAVQV Address access time 30 45 ns max TAVQX Address valid to low Z(1) 5 5 ns min TE1LQV Chip-select1 access time 30 45 ns max TE1LQX CS1 low to low Z(1) 3 3 ns min TE1HQZ CS1 high to high Z(1) 15 20 ns max TE2HQV Chip-select2 access time 30 45 ns max TE2HQX CS2 high to low Z(1) 3 3 ns min TE2LQZ CS2 low to high Z(1) 15 20 ns max TGLQV Output Enable access time 12 15 ns max TGLQX OE low to low Z(1) 0 0 ns min TGHQZ OE high to high Z(1) 8 15 ns max Note: 10 1. Parameters Guaranteed, not tested, with output loading 5 pF. M65608E 4151P–AERO–11/12 M65608E Read Cycle 1 Address Controlled (CS1= OE Low, CS2=WE High) Read Cycle 2 CS1 Controlled (CS2=WE High) Read Cycle 3 CS2 Controlled (WE High, CS1 Low) 11 4151P–AERO–11/12 Ordering Information Part Number Temperature Range Speed Package Flow 25⋅°C 30 ns SB32.4 Engineering Samples 25⋅°C 30 ns FP32.4 Engineering Samples 5962-8959847QZC -55⋅ to +125⋅°C 30 ns SB32.4 QML Q 5962-8959847QTC -55⋅ to +125⋅°C 30 ns FP32.4 QML Q 5962-8959818MZC -55⋅ to +125⋅°C 45 ns SB32.4 QML Q 5962-8959818MTC -55⋅ to +125⋅°C 45 ns FP32.4 QML Q 5962-8959847VZC -55⋅ to +125⋅°C 30 ns SB32.4 QML V 5962-8959847VTC -55⋅ to +125⋅°C 30 ns FP32.4 QML V 5962-8959818VZC -55⋅ to +125⋅°C 45 ns SB32.4 QML V 5962-8959818VTC -55⋅ to +125⋅°C 45 ns FP32.4 QML V 930104703 -55⋅ to +125⋅°C 30 ns SB32.4 ESCC 930104704 -55⋅ to +125⋅°C 30 ns FP32.4 ESCC 930104701 -55⋅ to +125⋅°C 45 ns SB32.4 ESCC 930104702 -55⋅ to +125⋅°C 45 ns FP32.4 ESCC MM065608EV-30-E 25⋅°C 30 ns Die Engineering Samples 5962-8959847Q6A -55⋅ to +125⋅°C 30 ns Die QML Q 5962-8959847V6A -55⋅ to +125⋅°C 30 ns Die QML V MMC9-65608EV-30-E (1) MMDJ-65608EV-30-E Note: 12 1. Contact Atmel for availability. M65608E 4151P–AERO–11/12 M65608E Package Drawings 32-lead Flat Pack 400 Mils T H E E1 L T L e INDEX MARK D1 e1 D b1 A1 A2 BRAZE c Q A E2 E3 S2 S A A1 A2 b b1 c D D1 E E1 E2 E3 b S1 U MM Min 2.16 0.41 0.13 0.38 Max 2.66 0.47 0.48 0.70 0.08 20.63 20.11 10.26 9.70 6.96 8.26 0.18 21.03 20.27 10.56 9.86 7.26 9.02 INCH Min Max 0.085 0.105 0.016 .018 0.005 0.015 0.019 0.027 0.003 0.007 0.812 0.828 0.792 0.798 0.404 0.416 0.382 0.388 0.274 0.286 0.325 0.355 e e1 L H Q R S S1 S2 T U MM Min Max 1.19 1.35 18.92 19.18 =1.27x15 6.995 8.495 25.6 26.2 0.68 0.84 0.76 1.14 0.13 0.76 1.02 0.08 1.27 INCH Min Max 0.047 0.053 0.745 0.755 =0.05x15 0.275 0.334 1.007 1.031 0.027 0.033 0.030 0.045 0.005 0.030 0.040 0.003 0.05 13 4151P–AERO–11/12 Package Drawings 32-lead Side Braze 400 Mils 14 M65608E 4151P–AERO–11/12 M65608E Document Revision History Changes from Rev. L to Rev. M 1. Change in “Consumption” on page 5. ICCOP. Changes from Rev. M to Rev. N 1. Update of footnotes under “Data Retention Characteristics” table 2. Update of Absolute Maximum Ratings section Changes from Rev. N to Rev. O 1. Update of “Ordering Information” section 2. Correction of typo erros in the note of “Write Cycle 3” section 3. Addition of headlines in pictures of “Read Cycle” section 4. Update of features section 5. Correction of typo error in the write signal, in the pin configuration section : W replaced by WE Changes from Rev. O to Rev. P 1. 32-lead Flat Pack package drawing updated on page 13. An index mark is now printed on the top lid to identify the pin n° 1. 15 4151P–AERO–11/12 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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