ATA6823C - Complete

ATA6823C
H-bridge Motor Driver
DATASHEET
Features
● PWM and direction-controlled driving of four externally-powered NMOS transistors
● A programmable dead time is included to avoid peak currents within the H-bridge
● Integrated charge pump to provide gate voltages for high-side drivers and to supply
the gate of the external battery reverse protection NMOS
● 5V/3.3V regulator and current limitation function
● Reset derived from 5V/3.3V regulator output voltage
● Sleep mode with supply current of typically < 45µA, wake-up by signal on pins EN2
or on LIN interface
● A programmable window watchdog
● Battery overvoltage protection and battery undervoltage management
● Overtemperature warning and protection (shutdown)
● LIN 2.1 compliant
● 3.3V/5V regulator with trimmed band gap
● QFN32 package
9209G-AUTO-02/15
1.
Description
The Atmel® ATA6823C is designed for automotive body and powertrain applications. The IC is used to drive a continuous
current motor in a full H-bridge configuration. An external microcontroller controls the driving function of the IC by providing a
PWM signal and a direction signal and allows the use of the IC in a motor-control application. The PWM control is performed
by the low-side switch; the high-side switch is permanently on in the driving phase. The VMODE configuration pin can be set
to 5V or 3.3V mode (for regulator and interface high level). The window watchdog has a programmable time, programmable
by choosing a certain value of the external watchdog resistor RWD, internally trimmed to an accuracy of 10%. For
communication a LIN transceiver 2.1 is integrated.
Figure 1-1. Block Diagram
M
CP
VRES
RGATE
RGATE
H2
H1
S1
S2
RGATE
RGATE
L1
L2
PGND
CPLO
GND
Charge
Pump
HS Driver 2
HS Driver 1
LS Driver 1
LS Driver 2
VBAT
CPIH
DG3
OT
UV
12V
Regulator
VG
VBAT
PBAT
OTP
12 bit
CC
CC timer
Oscillator
CP
DG2
DG1
Logic Control
Vint 5V
Regulator
VINT
Supervisor
OV
WD timer
VBAT
EN2
VBG
VBATSW
VCC 5V
Regulator
VCC
WD EN1
Battery
VCC
2
ATA6823C [DATASHEET]
9209G–AUTO–02/15
LIN
LIN
Bandgap
VMODE
/RESET
DIR
PWM
Microcontroller
RX
TX
Pin Configuration
EN2
VBATSW
VBAT
VCC
PGND
L1
L2
PBAT
Figure 2-1. Pinning QFN32
VMODE
VINT
RWD
CC
/RESET
WD
GND
LIN
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
Atmel YWW
21
ATA6823C
20
ZZZZZ-AL
19
18
17
9 10 11 12 13 14 15 16
VG
CPLO
CPHI
VRES
H2
S2
H1
S1
TX
DIR
PWM
EN1
RX
DG3
DG2
DG1
2.
Note:
YWW
ATA6823
ZZZZZ
AL
Date code (Y = Year - above 2000, WW = week number)
Product name
Wafer lot number
Assembly sub-lot number
Table 2-1.
Pin Description
Pin
Symbol
I/O
Function
1
VMODE
I
2
VINT
I/O
3
RWD
I
4
CC
I/O
RC combination to adjust cross conduction time
5
/RESET
O
Reset signal for microcontroller
6
WD
I
Watchdog trigger signal
7
GND
I
Ground for chip core
8
LIN
I/O
9
TX
I
Transmit signal to LIN bus from microcontroller
10
DIR
I
Defines the rotation direction for the motor
Selector for VCC and interface logic voltage level
Blocking capacitor 220nF/10V/X7R
Resistor defining the watchdog interval
LIN-bus terminal
11
PWM
I
PWM input controls motor speed
12
EN1
I
Microcontroller output to keep the chip in active mode
13
RX
O
Receive signal from LIN bus for microcontroller
14
DG3
O
Diagnostic output 3
15
DG2
O
Diagnostic output 2
16
DG1
O
Diagnostic output 1
17
S1
I/O
Source voltage H-bridge, high-side 1
18
H1
O
Gate voltage H-bridge, high-side 1
19
S2
I/O
Source voltage H-bridge, high-side 2
20
H2
O
Gate voltage H-bridge, high-side 2
21
VRES
I/O
Gate voltage for reverse protection NMOS, blocking capacitor 470nF/25V/X7R
ATA6823C [DATASHEET]
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3
Table 2-1.
Pin Description (Continued)
Pin
4
Symbol
I/O
Function
22
CPHI
I
23
CPLO
O
24
VG
I/O
25
PBAT
I
Power supply (after reverse protection) for charge pump and H-bridge
26
L2
O
Gate voltage H-bridge, low-side 2
27
L1
O
Gate voltage H-bridge, low-side 1
28
PGND
I
Power ground for H-bridge and charge pump
29
VCC
O
5V/100 mA supply for microcontroller, blocking capacitor 2.2µF/10V/X7R
Charge pump capacitor 220nF/25V/X7R
Blocking capacitor 470nF/25V/X7R
30
VBAT
I
Supply voltage for IC core (after reverse protection)
31
VBATSW
O
100 PMOS switch from VVBAT
32
EN2
I
Enable input
ATA6823C [DATASHEET]
9209G–AUTO–02/15
3.
Functional Description
3.1
Power Supply Unit with Supervisor Functions
3.1.1
Power Supply
The IC is supplied by a reverse-protected battery voltage. To prevent it from destruction, proper external protection circuitry
has to be added. It is recommended to use at least a capacitor combination of storage and HF caps behind the reverse
protection circuitry and closed to the VBAT pin of the IC (see Figure 1-1 on page 2).
A fully-internal low-power and low-drop regulator, stabilized by an external blocking capacitor provides the necessary lowvoltage supply needed for the wake-up process. The low-power band gap reference is trimmed and is used for the bigger
VCC regulator, too. All internal blocks are supplied by the internal regulator.
Note:
The internal supply voltage VINT must not be used for any other supply purpose!
Nothing inside the IC except the logic interface to the microcontroller is supplied by the 5V/3.3V VCC regulator.
A power-good comparator checks the output voltage of the VINT regulator and keeps the whole chip in reset as long as the
voltage is too low.
There is a high-voltage switch which brings out the battery voltage to the pin VBATSW for measurement purposes. This
switch is switched ON for VCC = HIGH and stays ON in case of a watchdog reset going to sleep mode, VBATSW turns OFF.
The signal can be used to switch on external voltage regulators, etc.
3.1.2
Voltage Supervisor
This block is intended to protect the IC and the external power MOS transistors against overvoltage on battery level and to
manage undervoltage on it.
Function: in case of both overvoltage alarm (VTHOV) and of undervoltage alarm (VTHUV) the external NMOS motor bridge
transistors will be switched off. The failure state will be flagged via DG2. No other actions will be carried out. The voltage
supervision block is connected to VBAT and filtered by a first-order low pass with a corner frequency of typical 15kHz.
3.1.3
Temperature Supervisor
There is a temperature sensor integrated on-chip to prevent the IC from overheating due to a failure in the external circuitry
and to protect the external NMOSFET transistors.
In case of detected overtemperature (150°C), the diagnostic pin DG3 will be switched to “H” to signalize this event to the
microcontroller. It should undertake actions to reduce the power dissipation in the IC. In case of detected overtemperature
(165°C), the VCC regulator and all drivers including the LIN transceiver will be switched OFF immediately and /RESET will go
LOW.
Both temperature thresholds are correlated. The absolute tolerance is ±10°C and there is a built-in hysteresis of about 10°C
to avoid fast oscillations. After cooling down below the 155°C threshold; the IC will go into active mode.
The LIN interface has a separate thermal shutdown with disabled the low-side driver at typically 165°C.
3.2
Sleep Mode
To be able to guarantee the low quiescent current of the inactive IC, a sleep mode is established. In sleep mode it is possible
to wake-up the IC by using the pins EN2 or LIN. In sleep mode, the following blocks are active:
● Band gap
●
●
●
Internal 5V regulator (VINT) with external blocking capacitor of 220nF
Input structure for detecting the EN2 pins threshold
Wake-up block of the LIN receive part
ATA6823C [DATASHEET]
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3.3
Wake-up and Sleep Mode Strategy
The IC has two modes: Sleep and Active. The change between the modes is described below.
The default state after power-on is active mode.
The wake-up procedure brings the IC from a standby mode (sleep) to an active mode (active). The internal 5V supply VINT,
the EN2 pin input structure and a certain part of the LIN receiver are permanently active to ensure a proper startup of the
system.
The Go to Active and Go to Sleep procedures are implemented as follows:
● Go to Active by activating pin EN2
The input EN2 is intended as a switch-on pin from an external signal. Its input structure consists of a comparator with built-in
hysteresis. It is ESD-protected by diodes against GND and VVBAT; for this reason the input voltage level must be positive and
not higher than VVBAT.
Pulling the EN2 pin up to the VVBAT level will drive the IC into active mode. EN2 is debounced with a time constant of 20µs,
based on a 100 kHz clock.
● Go to Active using the LIN interface
The second possibility for wake-up can be performed using the LIN transceiver. In sleep mode, the LIN receiver is partially
active.
The wake-up by LIN requires 2 steps:
1. If the voltage on pin LIN is below a value of V/DATwake (about VVBAT – 2V) the receive part of the LIN interface is
active (not to be confused with active mode of the whole IC). The active receive part is able to detect a valid LOW
on the LIN pin.
2.
If LIN = LOW during a filter time twakeLIN (typically 70µs) the IC will change to active mode. A short change back to
HIGH during the filter time will reset the filter. This information is stored in a latch after entering active mode
If the change to active mode was caused by LIN, the EN1 or EN2 pins may remain LOW without disturbing the active mode.
● Stay in Active via EN1
The input EN1 is intended to keep the IC in active mode via a signal from the microcontroller. The input is ESD-protected by
diodes against GND and VCC. Therefore, the input voltage must be positive and not higher than VCC. EN1 cannot be used to
switch from Sleep to Active because the VCC regulator is off in the sleep mode and VCC will be zero.
● Go to Sleep
A HIGH to LOW transition at pin EN1 and a following permanent LOW for the time tgotosleep (typically 20µs) switches the IC to
sleep mode.
Figure 3-1 illustrates the wake-up by LIN. The status PREWAKE is characterized by the activated receive block of the LIN
interface. After going to active mode, the VCC regulator starts working.
Go to Sleep is possible with a valid HIGH to LOW transition at pin EN1 (permanent LOW for longer than tdb) if EN1 was in a
valid HIGH state (HIGH for longer than tdb) before.
Switching characteristic of the outputs:
When the IC is set to SLEEP MODE by a “high to low” transition at pin EN1, the low-side transistors of the external H-bridge
are switched on for a short time. This causes a shortcircuit current pulse in the bridge because one of the high-side
transistors is usually on. The pulse length is similar to the one of the implemented short circuit detection time tsc. For the
selection of the external FETs it needs to be considered that in the case of a short circuit condition the current in the
transistors will flow for a time tsc with a maximum of 15µs according to Section 8. “Electrical Characteristics” on page 15, item
7.29. For the selection of the external FETs this short circuit behavior has to be taken into consideration, so that they will not
be damaged in the event of a short circuit condition caused by a failure or caused by the described sleep mode switching.
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ATA6823C [DATASHEET]
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Figure 3-1. Wake-up by pin LIN
Active Mode
Sleep Mode
Active Mode
EN1
VCC
LIN
Tgotosleep = 20µs
3.4
Twakelin = 70µs
Regulator Wake-up Time
5V/3.3V VCC Regulator
The 5V/3.3V regulator is fully integrated on-chip. It requires only a 2.2µF ceramic capacitor for stability and has 100mA
current capability. Using the VMODE pin, the output voltage can be selected to either 5V or 3.3V. Switching of the output
voltage during operation is not intended to be supported. The VMODE pin must be hard-wired to either VINT for 5V or to
GND for 3.3V. The logic HIGH level of the microcontroller interface will be adapted to the VCC regulator voltage.
The output voltage accuracy is in general < ±3%; in the 5V mode with VVBAT < 9V it is limited to < 5%.
To prevent destruction of the IC, the current delivered by the regulator is limited to maximum 100mA to 350mA. The
delivered voltage will break down and a reset may occur.
Please note that this regulator is the main heat source on the chip. The maximum output current at maximum battery voltage
and high ambient temperature can only guaranteed if the IC is mounted on an efficient heat sink.
A power-good comparator checks the output voltage of the VCC regulator and keeps the external microcontroller in reset as
long as the voltage is too low.
Figure 3-2. Correlation between VCC Output Voltage and Reset Threshold
5.15V
4.9V
VCC1
4.85V
VtHRESH
4.1V
VCC1-VtHRESH = VCC1 - VtHRESH
The voltage difference between the regulated output voltage and the upper reset threshold voltage is higher than 75mV
(VMODE = HIGH) and higher than 50mV (VMODE = LOW).
ATA6823C [DATASHEET]
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3.5
Reset and Watchdog Management
The timing basis of the watchdog is provided by the trimmed internal oscillator. Its period TOSC is adjustable via the external
resistor RWD.
The watchdog expects a triggering signal (a rising edge) from the microcontroller at the WD input within a period time
window of TWD. In order to save current consumption, the watchdog is switched off during sleep mode.
Figure 3-3. Timing Diagram of the Watchdog Function
tresshort
tres
/RESET
td
td
t1
t2
t1
t2
WD
3.5.1
Timing Sequence
For example, with an external resistor RWD = 33k ±1% we get the following typical parameters of the watchdog.
TOSC = 12.32µs, t1 = 12.1ms, t2 = 9.61ms, TWD = 16.88ms ±10%
The times tres = 70ms and td = 70ms are fixed values with a tolerance of 10%.
After ramp-up of the battery voltage (power-on reset), the VCC regulator is switched on. The reset output, /RESET, stays low
for the time tres (typically 70ms), then switches to high. For an initial lead time td (typically 70ms for setups in the controller)
the watchdog waits for a rising edge on WD to start its normal window watchdog sequence. If no rising edge is detected, the
watchdog will reset the microcontroller for tres and wait td for the rising edge on WD.
Times t1 (close window) and t2 (open window) form the window watchdog sequence. To avoid receiving a reset from the
watchdog, the triggering signal from the microcontroller must hit the time frame of t2 = 9.61ms. The trigger event will restart
the watchdog sequence.
Figure 3-4. TWD versus RWD
60
50
typ
TWD (ms)
max
40
30
min
20
10
0
10
20
30
40
50
60
70
80
90
100
RWD (kΩ)
If triggering fails, /RESET will be pulled to ground for a shortened reset time of typically 2 ms. The watchdog start sequence
is similar to the power-on reset.
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ATA6823C [DATASHEET]
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The internal oscillator is trimmed to a tolerance of < ±10%. This means that t1 and t2 can also vary by ±10%. The following
calculation shows the worst case calculation of the watchdog period Twd which the microcontroller has to provide.
t1min = 0.90  t1 = 10.87ms, t1max = 1.10  t1 = 13.28ms
t2min = 0.90  t2 = 8.65ms, t2max = 1.10  t2 = 10.57ms
Twdmax = t1min + t2min = 10.87ms + 8.65ms = 19.52ms
Twdmin = t1max = 13.28ms
Twd = 16.42ms ±3.15ms (±19.1%)
Figure 3-4 above shows the typical watchdog period TWD depending on the value of the external resistor ROSC.
A reset will be active for VCC < VtHRESx; the level VtHRESx is realized with a hysteresis (HYSRESth).
3.6
LIN Transceiver
A bi-directional bus interface is implemented for data transfer between the LIN bus and the local LIN protocol controller.
The transceiver consists of a low side driver (1.2V at 40mA) with slew rate control, wave shaping, current limitation, and a
high-voltage comparator followed by a debouncing unit in the receiver.
3.6.1
Transmit Mode
During transmission, the data at the pin TX will be transferred to the bus driver to generate a bus signal on pin LIN.
To minimize the electromagnetic emission of the bus line, the bus driver has an integrated slew rate control and waveshaping unit. Transmission will be interrupted in the following cases:
● Thermal shutdown active or overtemperature LIN active
●
Sleep mode
Figure 3-5. Definition of Bus Timing Parameters
tBit
tBit
tBit
TX
(input to transmitting Node)
tBus_dom(max)
tBus_rec(min)
Thresholds of
receiving node 1
THRec(max)
VVBAT
(Transceiver
supply
of transmitting
node)
THDom(max)
LIN Bus Signal
Thresholds of
receiving node 2
THRec(min)
THDom(min)
tBus_dom(min)
tBus_rec(max)
RX
(output of receiving Node 1)
trx_pdf(1)
trx_pdr(1)
RX
(output of receiving Node 2)
trx_pdr(2)
trx_pdf(2)
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The recessive BUS level is generated from the integrated 30k pull-up resistor in series with an active diode. This diode prevents the reverse current of VBUS during differential voltage between VSUP and BUS (VBUS > VSUP).
No additional termination resistor is necessary to use the ATA6823C in LIN slave nodes. If this IC is used for LIN master
nodes, it is necessary that the BUS pin be terminated via an external 1 k resistor in series with a diode to VBAT.
3.6.2
TXD Dominant Time-out Function
The TXD input has an internal pull-down resistor. An internal timer prevents the bus line from being driven permanently in
dominant state. If TXD is forced low longer than tdom > 18.4ms, the pin LIN will be switched off to recessive mode. To reset
this mode switch TXD to high (> 10µs) before switching LIN to dominant again.
3.7
Control Inputs EN1, EN2, DIR, PWM
3.7.1
Pins EN1, EN2
Any of the enable pins may be used to activate the IC with a HIGH. EN1 is a low level input, EN2 can withstand a voltage up
to 40V. Internal pull-down resistors are included.
3.7.2
Pin DIR
Logical input to control the direction of the external motor to be controlled by the IC. An internal pull-down resistor is
included.
3.7.3
Pin PWM
Logical input for PWM information delivered by external microcontroller. Duty cycle and frequency at this pin are passed
through to the H-bridge. An internal pull-down resistor is included.
Table 3-1.
Status of the IC Depending on Control Inputs and Detected Failures
ON
DIR
PWM
H1
L1
H2
L2
0
X
X
OFF
OFF
OFF
OFF
Standby mode
1
0
PWM
ON
OFF
/PWM
PWM
Motor PWM forward
1
1
PWM
/PWM
PWM
ON
OFF
Motor PWM reverse
The internal signal ON is high when
● At least one valid trigger has been accepted (SYNC = 1)
●
●
●
VVBAT is inside the specified range (UV = 0 and nOV = 1)
The charge pump has reached its minimum voltage (CPOK = 1) and
The device is not overheated (OT2 = 0)
In case of a short circuit, the appropriate transistor is switched off after a debounce time of about 10µs. In order to avoid
cross current through the bridge, a cross conduction timer is implemented. Its time constant is programmable by means of
an RC combination.
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9209G–AUTO–02/15
Table 3-2.
Status of the Diagnostic Outputs
CPOK
OT1
OV
UV
SC
DG1
DG2
DG3
0
X
X
X
X
–
1
–
Charge pump failure
X
1
X
X
X
–
–
1
Overtemperature warning
X
X
1
X
X
–
1
–
Overvoltage
X
X
X
1
X
–
1
–
Undervoltage
1
–
–
Short circuit
X
Note:
X
X
X
1
X represents: don't care – no effect)
OT1: Overtemperature warning
OV: Overvoltage of VBAT
UV: Undervoltage of VBAT
SC: Short circuit
CPOK: Charge pump OK
In order to be able to distinguish between a wake-up from LIN or from EN2, the source of wake-up is flagged in DG1 until the
first valid trigger (LIN = 0, EN2 = 1).
3.8
VG Regulator
The VG regulator is used to generate the gate voltage for the low-side driver. Its output voltage will be used as one input for
the charge pump, which generates the gate voltage for the high-side driver. The purpose of the regulator is to limit the gate
voltage for the external power MOS transistors to 12V. It needs a ceramic capacitor of 470nF for stability. The output voltage
is reduced if the supply voltage at VBAT falls below 12V.
3.9
Charge Pump
The integrated charge pump is needed to supply the gates of the external power MOS transistors. It needs a shuffle
capacitor of 220nF and a reservoir capacitor of 470nF. Without load, the output voltage on the reservoir capacitor is VVBAT
plus VG. The charge pump is clocked with a dedicated internal oscillator of 100KHz. The charge pump is designed to reach
a good EMC level.
3.10
Thermal Shutdown
There is a thermal shutdown block implemented. With rising junction temperature, a first warning level will be reached at
150°C. At this point the IC stays fully functional and a warning will be sent to the microcontroller. At junction temperature
165°C the VCC regulator will be switched off and a reset occurs.
3.11
H-bridge Driver
The IC includes two push-pull drivers for control of two external power NMOS used as high-side drivers and two push-pull
drivers for control of two external power NMOS used as low-side drivers. The drivers are able to be used with standard and
logic-level power NMOS.
The drivers for the high-side control use the charge pump voltage to supply the gates with a voltage of VG above the battery
voltage level. The low-side drivers are supplied by VG directly. It is possible to control the external load (motor) in the
forward and reverse direction (see Table 3-1 on page 10). The duty cycle of the PMW controls the speed. A duty cycle of
100% is possible in both directions.
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3.11.1 Cross Conduction Time
To prevent high peak currents in the H-bridge, a non-overlapping phase for switching the external power NMOS is realized.
An external RC combination defines the cross conduction time in the following way:
tCC (µs) = 0.41  RCC (k)  CCC (nF) (tolerance: ±5% ±0.15µs)
The RC combination is charged to 5V and the switching level of the internal comparator is 67% of the start level.
The resistor RCC must be greater than 5k and should be as close as possible to 10k, the CCC value has to be ≤ 5nF. Use
of COG capacitor material is recommended. The time measurement is triggered by the PWM or DIR signal crossing the 50%
level.
Figure 3-6. Timing of the Drivers
PWM or
DIR
50%
t
tLxHL
tLxf
tLxLH
tLxr
80%
tCC
Lx
20%
t
tHxLH
tCC
tHxr
tHxHL
tHxf
80%
Hx
20%
t
The delays tHxLH and tLxLH include the cross conduction time tCC.
3.12
Short Circuit Detection
To detect a short in H-bridge circuitry, internal comparators detect the voltage difference between source and drain of the
external power NMOS. If the transistors are switched ON and the source-drain voltage difference is higher than the value
VSC (4V with tolerances) for a time > tSC (typically 10µs) the signal SC (short circuit) will be set and the drivers will be
switched off immediately. The diagnostic pin DG1 will be set to “H”. With the next transition on pin PWM, the bit will be
cleared and the corresponding drivers, depending on the DIR pin, will be switched on again.
There is a PBAT supervision block implemented to detect the possible voltage drop on PBAT during a short circuit. If the
voltage at PBAT falls under VSCPB (5.6V with tolerances) for a time > tSC the drivers will be switched off immediately and DG1
will be set to “H”. It will be cleared as above.
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4.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Pin Description
Pin Name
Min.
Max.
Unit
GND
0
0
V
Power ground
PGND
–0.3
+0.3
V
Reverse protected battery voltage
VBAT
+40
V
Reverse current out of pin
VBAT
Reverse protected battery voltage
PBAT
Ground
Reverse current out of pin
–1
mA
+40
V
PBAT
–20
Digital output
/RESET
–0.3
VVCC + 0.3
V
Digital output
DG1, DG2, DG3
–0.3
VVCC + 0.3
V
4.9V output, external blocking capacitor
VINT
–0.3
+5.5
V
Cross conduction time capacitor/resistor
combination
CC
–0.3
VVINT + 0.3
V
Digital input coming from microcontroller
WD
–0.3
VVINT + 0.3
V
RWD
–0.3
VVCC + 0.3
V
Watchdog timing resistor
Digital input direction control
mA
DIR
–0.3
VVCC + 0.3
V
Digital input PWM control + Test mode
PWM
–0.3
VVCC + 0.3
V
Digital input for enable control
EN1
–0.3
VVCC + 0.3
V
Digital input for enable control
EN2
–0.3
VVBAT + 0.3
V
VCC
–0.3
+5.5
V
VMODE
–0.3
VVINT + 0.3
V
+16
V
5V regulator output
Digital input
12V output, external blocking capacitor
VG
Digital output
RX
–0.3
VVCC + 0.3
V
Digital input
TX
–0.3
VVCC + 0.3
V
LIN data pin
LIN
–27
VVBAT + 2
V
(2)
Source external high-side NMOS
S1, S2
(–2)
Gates external low-side NMOS
L1, L2
VPGND – 0.3
(1)
V
VVG + 0.3
V
(1)
V
Gates of external high-side NMOS
H1, H2
Charge pump
CPLO
VPBAT + 0.3
V
Charge pump
CPHI
VVRES + 0.3
V
Charge pump output
Switched VBAT
Storage temperature
Reverse current
Notes:
1.
x = 1.2
2.
t < 0.5s
3.
Load dump of t < 0.5s tolerated
VSx – 1
+40
VSx + 16
(3)
VRES
+40
V
VBATSW
–0.3
VVBAT + 0.3
V
STORE
–40
+150
°C
CPLO, CPHI, VG,
VRES, Sx
–2
mA
Lx, Hx
–1
mA
ATA6823C [DATASHEET]
9209G–AUTO–02/15
13
5.
Thermal Resistance
Parameters
Thermal resistance junction to heat slug
Symbol
Value
Unit
Rthjc
<5
K/W
Thermal resistance junction to ambient when heat
Rthja
29
K/W
slug is soldered to PCB(1)
Note:
1. Thermal resistance junction ambient: 29K/W (at airflow of 0 LFPM), valid for JEDEC Standard 4-layer Thermal test
board with 5 x 5 thermal via matrix (100µm drill hole, filled vias).
6.
Operating Range
The operating conditions define the limits for functional operation and parametric characteristics of the device. Functionality outside
these limits is not implied unless otherwise stated explicitly.
Parameters
Symbol
Min.
Max.
Unit
(1)
VVBAT1
VTHUV
VTHOV
V
(2)
Operating supply voltage
VVBAT2
6
VTHUV
V
Operating supply voltage(3)
VVBAT3
3
<6
V
(4)
VVBAT4
0
<3
V
(5)
VVBAT5
> VTHOV
40
V
(6)
Operating supply voltage
Operating supply voltage
Operating supply voltage
Operating supply voltage
VVBAT6
7
18
V
Normal functionality
Tj
–40
+150
°C
Normal functionality, overtemperature warning
Tj
150
165
°C
Tj
165
180
°C
Drivers for H1, H2, L1, L2, and LIN are switched
OFF, VCC regulator is OFF
Note:
1. Full functionality
2. H-bridge drivers are switched off (undervoltage detection)
3. H-bridge drivers are switched off, 5V/3.3V regulator with reduced parameters, RESET works correctly
4. H-bridge drivers are switched off, 5V regulator not working, RESET not correct
5. H-bridge drivers are switched off
6. Full LIN functionality in conformance with LIN specification 2.1
7.
Noise and Surge Immunity, ESD and Latch-up
Parameters
Standard and Test Conditions
Conducted interferences
ISO 7637-1
Conducted disturbances
CISP25
ESD according to IBEE LIN EMC
- Pins LIN, PBAT, VBAT
- Pin EN2 (33 k serial resistor)
Test specification 1.0 following IEC 61000-4-2
Value
Level 4(1)
Level 5
±6kV
±5kV
ESD HBM with 1.5k/100pF
ESD- STM5.1-2001
JESD22-A114E 2007
CEI/IEC 60749-26: 2006
AEC-Q100-002-Ref_D
±3kV
ESD HBM with 1.5k/100pF
Pins EN2, LIN, PBAT, VBAT against GND
ESD- STM5.1-2001
JESD22-A114E 2007
CEI/IEC 60749-26: 2006
AEC-Q100-002-Ref_D
±8kV
ESD STM5.3.1 - 1999
±1kV
ESD CDM (field induced method)
Note:
1. Test pulse 5: Vbat max = 40V
14
ATA6823C [DATASHEET]
9209G–AUTO–02/15
Static latch-up tested according to AEC-Q100-004 and JESD78.
● 3 to 6 samples, 0 failures
●
Electrical post stress testing at room temperature
In test, the voltage at the pins VBAT, LIN, CP, VBATSW, Hx, and Sx must not exceed 45V when not able to drive the
specified current.
8.
Electrical Characteristics
All parameters given are valid for VTHUV ≤ VVBAT ≤ VTHOV and for –40°C ≤ ambient ≤ 125°C unless stated otherwise.
No. Parameters
1
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Power Supply and Supervisor Functions
1.1
Current consumption
VVBAT
VVBAT = 13.5V(1)
25, 30
IVBAT1
7
mA
A
1.2
Current consumption
VVBAT in Standby mode
VVBAT =13.5V
25, 30
IVBAT2
50
µA
A
1.3 Internal power supply
2
VINT
4.94
V
A
1.4 Band gap voltage
3
VBG
1.235
V
A
Overvoltage threshold Up
1.5
VVBAT
30
VTHOV_UP
21.2
22.7
V
A
1.5.1
Overvoltage threshold
Down VVBAT
30
VTHOV_DOWN
19.8
21.3
V
A
1.6
Overvoltage threshold
hysteresis VVBAT
30
VTOVhys
1
2.4
V
A
1.7
Undervoltage threshold
Up VVBAT
30
VTHUV_UP
6.8
7.4
V
A
1.7.1
Undervoltage threshold
Down VVBAT
30
VTHUV_DOWN
6.5
7.0
V
A
1.8
Undervoltage threshold
hysteresis VVBAT
Measured during
qualification only
30
VTUVhys
0.2
0.6
V
A
1.9
On resistance of VVBAT
switch
VVBAT = 13.5V
31
RON_VBATSW
100

A
2.1 Regulated output voltage
9V < VVBAT < 40V
Iload = 0mA to 100mA
29
VCC1
4.85
(3.2)
5.15
(3.4)
V
A
2.2 Regulated output voltage
6V < VVBAT ≤ 9V
Iload = 0mA to 100mA
29
VCC2
4.75
(3.2)
5.25
(3.4)
V
A
2.3 Line regulation
Iload = 0mA to 100mA
29
DC line
regulation
50
mV
A
2
5V/3.3V Regulator
<1
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1.
EN, DIR, PWM = high
2.
The use of X7R material is recommended
3.
For higher values, stability at zero load is not guaranteed
4.
Tested during qualification only
5.
Value depends on TOSC; function tested with digital test pattern
6.
Tested during characterization only
7.
Supplied by charge pump
8.
See Section 3.11.1 “Cross Conduction Time” on page 12
9.
Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
ATA6823C [DATASHEET]
9209G–AUTO–02/15
15
8.
Electrical Characteristics (Continued)
All parameters given are valid for VTHUV ≤ VVBAT ≤ VTHOV and for –40°C ≤ ambient ≤ 125°C unless stated otherwise.
No. Parameters
Test Conditions
Pin
Symbol
2.4 Load regulation
Iload = 0mA to 100mA
29
DC load
regulation
2.5 Output current limitation
VVBAT > 6V
29
IOS1
Min.
Typ.
Max.
Unit
Type*
<10
50
mV
A
100
350
mA
A
2.6
Serial inductance to CVCC
including PCB
29
ESL
1
20
nH
D
2.7
Serial resistance to CVCC
including PCB
29
ESR
0
0.5

D
29
CVCC
1.1
3.3
µF
D
2.9 HIGH threshold VMODE
1
VMODE H
4.0
V
A
2.10 LOW threshold VMODE
1
VMODE L
V
A
VCC threshold voltage level VMODE = “H”
for /RESET
(VMODE = “L”)
29
VtHRESH
V
A
Tracking of reset threshold
VMODE = “H”
3.1a with regulated output
(VMODE = “L”)
voltage
29
VVCC1-VtHRESH
75
(50)
mV
A
3.2
VCC threshold voltage level VMODE = “H”
for /RESET
(VMODE = “L”)
29
VtHRESL
4.0
(2.65)
V
A
3.3
Hysteresis of /RESET
level
29
HYSRESth
70
mV
A
3.4
Length of pulse at /RESET
(5)
pin
5
tres
7000
T100
A
3.5
Length of short pulse at
/RESET pin
(5)
5
tresshort
200
T100
A
3.6
Wait for the first WD
trigger
(5)
5
td
7000
T100
A
3.7
Time for VCC < VtHRESL
(4)
before activating /RESET
29
tdelayRESL
0.5
2
µs
C
Resistor defining internal
3.8 bias currents for watchdog
oscillator
3
RRWD
10
91
k
D
3.9 Watchdog oscillator period RRWD = 33k
3
TOSC
11.09
13.55
µs
A
6
VILWD
0.3 
VVCC
V
A
2.8 Blocking cap at VCC
3
3.1
3.11
(2), (3)
0.7
Reset and Watchdog
VMODE = “H”
(VMODE = “L”)(4)
Watchdog input
low-voltage threshold
4.9
(3.25)
200
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1.
EN, DIR, PWM = high
2.
The use of X7R material is recommended
3.
For higher values, stability at zero load is not guaranteed
4.
Tested during qualification only
5.
Value depends on TOSC; function tested with digital test pattern
6.
Tested during characterization only
7.
Supplied by charge pump
8.
See Section 3.11.1 “Cross Conduction Time” on page 12
9.
Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
16
ATA6823C [DATASHEET]
9209G–AUTO–02/15
600
(400)
8.
Electrical Characteristics (Continued)
All parameters given are valid for VTHUV ≤ VVBAT ≤ VTHOV and for –40°C ≤ ambient ≤ 125°C unless stated otherwise.
No. Parameters
Test Conditions
Pin
Symbol
Min.
3.12
Watchdog input
high-voltage threshold
6
VIHWD
0.7 
VVCC
3.13
Hysteresis of watchdog
input voltage threshold
6
VhysWD
0.3
Typ.
Max.
0.7
Unit
Type*
V
A
V
A
3.14 Close window
(5)
6
t1
980 
TOSC
A
3.15 Open window
(5)
6
t2
780 
TOSC
A
At IOLRES = 1mA
5
VOLRES
5
RPURES
5
3.16
Output low-voltage of
/RESET
3.17
Internal pull-up resistor at
pin /RESET
4
10
0.4
V
A
15
k
A
LIN Transceiver, 7V ≤ VVBAT ≤ 18V
4.1 Low-level output current
Normal mode;
VLIN = 0V, VRX = 0.4V
13
ILRXD
2
mA
A
4.2 High-level output current
Normal mode; VLIN = VVBAT
VRX = VCC – 0.4V
13
IHRXD
1
mA
A
0.9 
VVBAT
V
A
4.3
Driver recessive output
voltage
RLOAD = 1000 to VBAT
8
VBUSrecdrv
4.4
Driver dominant voltage
VBUSdom_DRV_LoSUP
VVBAT = 7.0V
Rload = 500
8
V_LoSUP
1.2
V
A
4.5
Driver dominant voltage
VBUSdom_DRV_HiSUP
VVBAT = 18V
Rload = 500
8
V_HiSUP
2
V
A
4.6
Driver dominant voltage
VBUSdom_DRV_LoSUP
VVBAT = 7.0V
Rload = 1000
8
V_LoSUP_1k
0.6
V
A
4.7
Driver dominant voltage
VBUSdom_DRV_HiSUP
VVBAT = 18V
Rload = 1000
8
V_HiSUP_1k_
0.8
V
A
Serial diode required
8
RLIN
20
47
k
A
8
CLIN
20
pF
D
8
IBUS_LIM
50
200
mA
A
8
IBUS_PAS_dom
–1
mA
A
4.8a Pull up resistor to VVBAT
4.8b
Capacitance on LIN pin to
GND
4.9 Current limitation
VBUS = VVBAT_max
Input leakage current
Input leakage current at
driver off
4.10 the receiver including pullVBUS = 0V
up resistor as specified
VVBAT = 12V
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1.
EN, DIR, PWM = high
2.
The use of X7R material is recommended
3.
For higher values, stability at zero load is not guaranteed
4.
Tested during qualification only
5.
Value depends on TOSC; function tested with digital test pattern
6.
Tested during characterization only
7.
Supplied by charge pump
8.
See Section 3.11.1 “Cross Conduction Time” on page 12
9.
Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
ATA6823C [DATASHEET]
9209G–AUTO–02/15
17
8.
Electrical Characteristics (Continued)
All parameters given are valid for VTHUV ≤ VVBAT ≤ VTHOV and for –40°C ≤ ambient ≤ 125°C unless stated otherwise.
No. Parameters
Test Conditions
Pin
Symbol
Leakage current LIN
4.11
recessive
Driver off
7V < VVBAT < 18V
7V < VBUS < 18V
VBUS = VVBAT
8
IBUS_PAS_rec
Leakage current at ground
loss
Control unit disconnected
4.12 from ground
Loss of local ground must
not affect communication
in the residual network
7V < VVBAT < 18V
GNDDevice = VVBAT
VVBAT = 12V
0V < VBUS < 18V
8
IBUS_NO_gnd
Node has to sustain the
current that can flow under
4.13 this condition. Bus must
remain operational under
this condition
7V < VVBAT < 18V
VVBAT disconnected
VSUP_Device = GND
0V < VBUS < 18V
8
IBUS
Center of receiver
threshold
7V < VVBAT < 18V
VBUS_CNT =
(Vth_dom + Vth_rec)/2
8
VBUS_CNT
4.15 Receiver dominant state
7V < VVBAT < 18V
VEN = 5V
8
VBUSdom
4.16 Receiver recessive state
7V < VVBAT < 18V
VEN = 5V
8
VBUSrec
4.17 Receiver input hysteresis
7V < VVBAT < 18V
VHYS = Vth_rec – Vth_dom
8
VBUShys
4.18 Duty cycle 1
7V < VVBAT < 18V
THrec(max) = 0.744  VVBAT
THDom(max) = 0.581  VVBAT
tBit = 50µs
D1 = tBus_rec(min)/(2  tBit)
Load1: 1nF + 1k
Load2: 10nF + 500
8
D1
4.14
Min.
Typ.
Max.
Unit
Type*
20
µA
A
+1
mA
A
100
µA
A
0.525 
VVBAT
V
A
0.4 
VVBAT
V
A
V
A
V
A
–1
0.475 
VVBAT
0.5 
VVBAT
0.6 
VVBAT
0.175 
VVBAT
0.396
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1.
EN, DIR, PWM = high
2.
The use of X7R material is recommended
3.
For higher values, stability at zero load is not guaranteed
4.
Tested during qualification only
5.
Value depends on TOSC; function tested with digital test pattern
6.
Tested during characterization only
7.
Supplied by charge pump
8.
See Section 3.11.1 “Cross Conduction Time” on page 12
9.
Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
18
ATA6823C [DATASHEET]
9209G–AUTO–02/15
A
8.
Electrical Characteristics (Continued)
All parameters given are valid for VTHUV ≤ VVBAT ≤ VTHOV and for –40°C ≤ ambient ≤ 125°C unless stated otherwise.
No. Parameters
Test Conditions
Pin
Symbol
4.19 Duty cycle 2
7V < VVBAT < 18V
THrec(min) = 0.422  VVBAT
THDom(min) = 0.284  VVBAT
tBit = 50µs
D2 = tBus_rec(max)/(2×tBit)
Load1: 1nF + 1k
Load2: 10nF + 500
8
D2
4.20 Duty cycle 3
7V < VVBAT < 18V
THrec(max) = 0.778  VVBAT
THDom(max) = 0.616  VVBAT
tBit = 96µs
D3 = tBus_rec(min)/(2  tBit)
Load1: 1nF + 1k
Load2: 10nF + 500
8
D3
4.21 Duty cycle 4
7V < VVBAT < 18V
THrec(min) = 0.389  VVBAT
THDom(min) = 0.251  VVBAT
tBit = 96µs
D4 = tBus_rec(max)/(2 × tBit)
Load1: 1nF + 1k
Load2: 10nF + 500
8
D4
0.590
7V < VVBAT < 18V
trec_pd = max (trx_pdr, trx_pdf)
13
trx_pd
6
µs
7V < VVBAT < 18V
trx_sym = trx_pdr – trx_pdf
13
trx_sym
–2
+2
µs
7V < VVBAT < 18V
VLIN = 0V
8
TBUS
30
150
µs
A
0.3 
VVCC
V
A
V
A
4.22
Receiver propagation
delay
Symmetry of receiver
4.23 propagation delay rising
edge minus falling edge
4.24
5
Dominant time for wakeup via LIN-bus
Min.
Typ.
Max.
Unit
0.581
Type*
A
0.417
A
90
A
A
Control Inputs EN1, DIR, PWM, WD, TX
5.1
Input low-voltage
threshold
12, 10,
11, 6, 9
VIL
5.2
Input high-voltage
threshold
12, 10,
11, 6, 9
VIH
0.7 
VVCC
12, 10,
11, 6, 9
HYS
0.3
0.5
0.7
V
A
12, 10,
11, 6,
RPD
25
50
100
k
A
5.3 Hysteresis
5.4 Pull-down resistor
EN1, DIR, PWM, WD
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1.
EN, DIR, PWM = high
2.
The use of X7R material is recommended
3.
For higher values, stability at zero load is not guaranteed
4.
Tested during qualification only
5.
Value depends on TOSC; function tested with digital test pattern
6.
Tested during characterization only
7.
Supplied by charge pump
8.
See Section 3.11.1 “Cross Conduction Time” on page 12
9.
Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
ATA6823C [DATASHEET]
9209G–AUTO–02/15
19
8.
Electrical Characteristics (Continued)
All parameters given are valid for VTHUV ≤ VVBAT ≤ VTHOV and for –40°C ≤ ambient ≤ 125°C unless stated otherwise.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
5.5 Pull-up resistor
TX
9
RPU
25
50
100
k
A
12, 10,
11, 6, 9
trf
100
ns
D
(6)
12
tdb
3  T100
µs
B
6.1 Charge pump voltage
Load = 0A
21
VCP
VVBAT
+ VVG
V
A
6.2 Charge pump voltage
Load = 3mA,
CCP = 100nF
21
VCP
VVBAT
+ VVG – 1
V
A
21
T100
9
11
µs
A
24
IVGCPz
0.6
mA
A
4
mA
A
5.6 Rise/fall time
5.7 Debounce time EN1
6
2  T100
Charge Pump
6.3
Period charge pump
oscillator
6.4
CP load current in VG
without CP load
6.5
CP load current in VG with Load = 3mA,
CP load
CCP = 100nF
24
IVGCP
6.6
Charge pump OK
threshold UP
21
VCPOK_UP
5.05
6.15
V
A
6.7
Charge pump OK
threshold DOWN
21
VCPOK_DOWN
4.25
5.35
V
A
VVG –
0.5V
VVG
V
A
7
Load = 0A
H-bridge Driver
7.1
Low-side driver HIGH
output voltage
26, 27
VLxH
7.2
ON-resistance of sink
stage of pins L1, L2
26, 27
RDSON_LxL,
x = 1, 2
20

A
7.3
ON-resistance of source
stage of pins L1, L2
26, 27
RDSON_LxH,
x = 1, 2
20

A
mA
A
–100
mA
A
140
k
A
Output peak current at
7.4 pins L1, L2, switched to
LOW
VLx = 3V
26, 27
ILxL,
x = 1, 2
Output peak current at
7.5 pins L1, L2, switched to
HIGH
VLx = 3V
26, 27
ILxH,
x = 1, 2
26, 27
RPDLx
x = 1, 2
7.6
Pull-down resistance at
pins L1, L2
100
30
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1.
EN, DIR, PWM = high
2.
The use of X7R material is recommended
3.
For higher values, stability at zero load is not guaranteed
4.
Tested during qualification only
5.
Value depends on TOSC; function tested with digital test pattern
6.
Tested during characterization only
7.
Supplied by charge pump
8.
See Section 3.11.1 “Cross Conduction Time” on page 12
9.
Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
20
ATA6823C [DATASHEET]
9209G–AUTO–02/15
8.
Electrical Characteristics (Continued)
All parameters given are valid for VTHUV ≤ VVBAT ≤ VTHOV and for –40°C ≤ ambient ≤ 125°C unless stated otherwise.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
7.7
ON-resistance of sink
stage of pins H1, H2
VSx = 0
18, 20
RDSON_HxL,
x = 1, 2
20

A
7.8
ON-resistance of source
stage of pins H1, H2
VSx = VVBAT
18, 20
RDSON_HxH,
x = 1, 2
20

A
7.9
VVBAT = 13.5V
Output peak current at
V = VVBAT
pins Hx, switched to LOW Sx
VHx = VVBAT + 3V
18, 20
IHxL,
x = 1, 2
mA
A
7.10
VVBAT = 13.5V
Output peak current at
V = VVBAT
pins Hx, switched to HIGH Sx
VHx = VVBAT + 3V
18, 20
IHxH,
x = 1, 2
–100
mA
A
7.11
VSx = 0V
Static switch output low
I = 1mA
voltage at pins Hx and Lx Hx
ILx = 1mA
18, 20,
26, 27
VHxL, VLxL
x = 1, 2
0.3
V
A
ILx = –10µA
(PWM = static)
18, 20
VHxHstat1(7)
VVBAT +
VVG – 1
VVBAT +
VVG
V
A
VVBAT = VPBAT = 9V,
I_VG = –20mA
17, 18,
19, 20
RPDHx
30
150
k
A
Figure 3-6 on page 12
VVBAT = 13.5V
26, 27
tLxHL
0.5
µs
A
Propagation delay time,
7.16 low-side driver from low to VVBAT = 13.5V
high
26, 27
tLxLH
0.5 + tCC
µs
A
7.17 Fall time low-side driver
VVBAT = 13.5V
CGx = 5nF
26, 27
tLxf
0.5
µs
A
7.18 Rise time low-side driver
VVBAT = 13.5V
26, 27
tLxr
0.5
µs
A
Propagation delay time,
Figure 3-6 on page 12
7.19 high-side driver from high
VVBAT = 13.5V
to low
18, 20
tHxHL
0.5
µs
A
Propagation delay time,
7.20 high-side driver from low
to high
VVBAT = 13.5V
18, 20
tHxLH
0.5 + tCC
µs
A
7.21 Fall time high-side driver
VVBAT = 13.5V,
CGx = 5nF
18, 20
tHxf
0.5
µs
A
Static high-side switch
7.12 output high-voltage pins
H1, H2
7.13
Sink resistance between
Hx and Sx
100
Dynamic Parameters
Propagation delay time,
7.15 low-side driver from high
to low
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1.
EN, DIR, PWM = high
2.
The use of X7R material is recommended
3.
For higher values, stability at zero load is not guaranteed
4.
Tested during qualification only
5.
Value depends on TOSC; function tested with digital test pattern
6.
Tested during characterization only
7.
Supplied by charge pump
8.
See Section 3.11.1 “Cross Conduction Time” on page 12
9.
Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
ATA6823C [DATASHEET]
9209G–AUTO–02/15
21
8.
Electrical Characteristics (Continued)
All parameters given are valid for VTHUV ≤ VVBAT ≤ VTHOV and for –40°C ≤ ambient ≤ 125°C unless stated otherwise.
No. Parameters
Test Conditions
7.22 Rise time high-side driver VVBAT = 13.5V
7.23 Cross conduction time
Symbol
18, 20
tHxr
Min.
4
tCC
3.75
7.24 External resistor
4
RCC
5
7.25 External capacitor
4
CCC
4
RONCC
17, 19
VSC
3.5
17, 19
tSC
5
7.26
RON of tCC switching
transistor
7.28
Short circuit detection
voltage
RCC = 10k, CCC = 1nF(8)
Pin
(9)
7.29 Short circuit detection time (10)
Typ.
Max.
Unit
Type*
0.5
µs
A
4.45
µs
A
k
D
5
nF
D
200

A
4
4.7
V
A
10
15
µs
A
7.30
VG regulator output
voltage
VVBAT = VPBAT = 18V,
I_VG = –20mA
24
VVG
11
14
V
A
7.31
VG regulator output
voltage switch mode
VVBAT = VPBAT = 9V,
I_VG = –20mA
24
VVGswitch
7
9
V
A
8
Input EN2
8.1
Input low-voltage
threshold
32
VIL
2.3
3.6
V
A
8.2
Input high-voltage
threshold
32
VIH
2.8
4.0
V
A
32
HYS
V
A
8.4 Pull-down resistor
32
RPD
200
k
A
8.5 Rise/fall time
32
trf
100
ns
D
32
tdb
2  T100
3  T100
µs
B
15, 16
IL
2
mA
A
15, 16
IH
1
mA
A
8.3 Hysteresis
8.6 Debounce time
9
(6)
(6)
0.47
50
100
Diagnostic Outputs DG1, DG2, DG3
9.1 Low level output current
9.2 High level output current
VDG = 0.4V(6)
(6)
VDG = VCC – 0.4V
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1.
EN, DIR, PWM = high
2.
The use of X7R material is recommended
3.
For higher values, stability at zero load is not guaranteed
4.
Tested during qualification only
5.
Value depends on TOSC; function tested with digital test pattern
6.
Tested during characterization only
7.
Supplied by charge pump
8.
See Section 3.11.1 “Cross Conduction Time” on page 12
9.
Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
22
ATA6823C [DATASHEET]
9209G–AUTO–02/15
9.
Application
9.1
General Remark
This section describes the principal application for which the ATA6823C was designed. Because Atmel® cannot be
considered to understand fully all aspects of the system, application, and environment, no warranties of fitness for a
particular purpose are given.
Table 9-1.
Typical External Components
Component
Function
Value
CVINT
Blocking capacitor at VINT
220nF, 10V, X7R
Tolerance
50%
CVCC
Blocking capacitor at VCC
2.2µF, 10V, X7R
50%
CCC
Cross conduction time definition capacitor
Typical 330pF, 100V, COG
RCC
Cross conduction time definition resistor
Typical 10k
CVG
Blocking capacitor at VG
Typical 470nF, 25V, X7R
CCP
Charge pump capacitor
Typical 220nF, 25V, X7R
CVRES
Reservoir capacitor
Typical 470nF, 25V, X7R
RRWD
Watchdog time definition resistor
Typical 51k
RLINex
Pull-up resistor for LIN bus (master only)
Typical 1k
CLINex
Filter capacitor for LIN bus
Typical 220pF, 100V
10.
Errata
10.1
Faulty Pulse at DG1
50%
A faulty pulse of approximately 100ns appears at pin 16 (DG1), signalizing short circuit condition, under following
circumstances:
General condition: PWM = HIGH
and
detected undervoltage of VBAT (signalized at pin 15 = DG2)
or
detected overvoltage of VBAT (signalized at pin 15 = DG2)
or
detected undervoltage of the charge pump (signalized at pin 15 = DG2)
or
overtemperature shutdown.
10.2
Problem Fix/Workaround
Set the software to ignore the faulty pulse.
ATA6823C [DATASHEET]
9209G–AUTO–02/15
23
11.
Ordering Information
Extended Type Number
Package
Remarks
ATA6823C-PHQW-1
QFN32
Pb-free, 4k
12.
Package Information
Top View
D
32
1
technical drawings
according to DIN
specifications
E
PIN 1 ID
A
A1
Side View
A3
Dimensions in mm
Bottom View
D2
9
16
17
COMMON DIMENSIONS
E2
8
1
24
25
Z 32
e
L
Z 10:1
(Unit of Measure = mm)
Symbol
MIN
NOM
MAX
A
0.8
0.85
0.9
A1
A3
0
0.16
0.035
0.21
0.05
0.26
D
6.9
7
7.1
D2
4.6
4.7
4.8
E
6.9
7
7.1
E2
4.6
4.7
4.8
L
0.55
0.6
0.65
b
e
0.25
0.3
0.65
0.35
NOTE
b
05/19/14
TITLE
Package Drawing Contact:
[email protected]
24
ATA6823C [DATASHEET]
9209G–AUTO–02/15
Package: QFN_7x7_32L
Exposed pad 4.7x4.7
GPC
DRAWING NO.
REV.
6.543-5201.01-4
1
13.
Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No.
9209G-AUTO-02/15
History
Section 10 “Ordering Information” on page 24 updated
Section 11 “Package Information” on page 24 updated
9209F-AUTO-06/14
Put datasheet in the latest template
9209E-AUTO-03/12
Section 4 “Absolute Maximum Ratings” on page 13 changed
Figure 3-5 “Definition of Bus Timing Parameters” on page 10 changed
9209D-AUTO-11/11
Section 4 “Absolute Maximum Ratings” on page 15 changed
Section 8 “Electrical Characteristics” numbers 4.8 and 4.12 on pages 19 to 20 changed
9209C-AUTO-01/11
9209B-AUTO-11/10
Section 3.3 “Wake-up and Sleep Mode Strategy” on page 7 changed
Section 8 “Electrical Characteristics” number 4.8b on page 19 added
Table 9-1 “Typical External Components” on page 25 changed
ATA6823C [DATASHEET]
9209G–AUTO–02/15
25
XXXXXX
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© 2015 Atmel Corporation. / Rev.: 9209G–AUTO–02/15
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