AT45BR3214B - Mature

Features
• 32-Mbit DataFlash and 4-Mbit SRAM
• Single 62-ball (8 mm x 12 mm x 1.2 mm) CBGA Package
• 2.7V to 3.3V Operating Voltage
DataFlash
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Single 2.7V to 3.3V Supply
Serial Peripheral Interface (SPI) Compatible
20 MHz Max Clock Frequency
Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 8192 Pages (528 Bytes/Page) Main Memory
Supports Page and Block Erase Operations
Two 528-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming of Nonvolatile Memory
Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
Low Power Dissipation
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
Hardware Data Protection Feature
Industrial Temperature Range
SRAM
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32-megabit
DataFlash®
+ 4-megabit
SRAM
Stack Memory
AT45BR3214B
4-megabit (256K x 16)
2.7V to 3.3V VCC
70 ns Access Time
Fully Static Operation and Tri-state Output
1.2V (Min) Data Retention
Industrial Temperature Range
Rev. 3356B–DFLASH–10/04
1
Pin Configuration
Pin Name
Function
CS
Chip Select
SCK
Serial Clock
SI
Serial Input
SO
Serial Output
WP
Write Protect
RESET
Reset
RDY/BUSY
READY BUSY
VCC
Flash Power Supply
GND
Flash Ground
A0 - A17
SRAM Address Input
I/O0 - I/O15
SRAM Data Inputs/Outputs
SLB
SRAM Lower Byte
SUB
SRAM Upper Byte
SVCC
SRAM Power
SGND
SRAM Ground
SCS1
SRAM Chip Select 1
SCS2
SRAM Chip Select 2
SWE
SRAM Write Enable
SOE
SRAM Output Enable
NC
No Connect
AT45BR3214B
(Top View)
1
2
3
4
5
6
7
8
9
10
NC
SI
A11
A15
A14
A13
A12
GND
NC
NC
A16
A8
A10
A9
I/O15 SWE I/O14
I/O7
I/O13
I/O5
A
B
C
WP RDY/BUSY
I/O6
I/O4
D
SGND RESET
I/O12 SCS2 SVCC VCC
E
NC
NC
NC
SLB
SUB
SOE
SO
A17
A7
NC
A5
A4
I/O11
I/O10
I/O2
I/O3
I/O9
I/O8
I/O0
I/O1
A6
A3
A2
A1
SCS1
A0
CS
GND
SCK
NC
F
G
H
NC
2
NC
AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
Block Diagram
SI WP
ADDRESS
SOE SWE
RESET
CS
SCK
RDY/BUSY
32-Mbit
DataFlash
4-Mbit
SRAM
SCS1
SCS2
SO
DATA (I/O0 - I/O15)
Description
The AT45BR3214B combines a 32-megabit DataFlash (32M x 1) and a 4-megabit
SRAM (organized as 256K x 16) in a stacked 62-ball CBGA package. The stacked module operates at 2.7V to 3.3V in the industrial temperature range.
Absolute Maximum Ratings
Temperature under Bias .................................. -40°C to +85°C
Storage Temperature ..................................... -55°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground .....................................-0.2V to +3.3V
All Output Voltages
with Respect to Ground .....................................-0.2V to +0.2V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC and AC Operating Range
AT45BR3214B
Operating Temperature (Case)
VCC Power Supply
Industrial
-40°C - 85°C
2.7V to 3.3V
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3356B–DFLASH–10/04
32-Mbit DataFlash
Description
The 32-Mbit DataFlash is a 2.7-volt only, serial interface Flash memory ideally suited for
a wide variety of digital voice-, image-, program code- and data-storage applications.
Its 34,603,008 bits of memory are organized as 8192 pages of 528 bytes each. In addition to the main memory, the 32-Mbit DataFlash also contains two SRAM data buffers of
528 bytes each. The buffers allow receiving of data while a page in the main memory is
being reprogrammed, as well as reading or writing a continuous data-stream. EEPROM
emulation (bit or byte alterability) is easily handled with a self-contained three step
Read-Modify-Write operation. Unlike conventional Flash memories that are accessed
randomly with multiple address lines and a parallel interface, the DataFlash uses a SPI
serial interface to sequentially access its data. DataFlash supports SPI mode 0 and
mode 3. The simple serial interface facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size and active pin count. The
device is optimized for use in many commercial and industrial applications where high
density, low pin count, low voltage, and low power are essential. The device operates at
clock frequencies up to 20 MHz with a typical active read current consumption of 4 mA.
To allow for simple in-system reprogrammability, the 32-Mbit DataFlash does not
require high input voltages for programming. The device operates from a single power
supply, 2.7V to 3.3V, for both the program and read operations. The 32-Mbit DataFlash
is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).
All programming cycles are self-timed, and no separate erase cycle is required before
programming. When the device is shipped from Atmel, the most significant page of the
memory array may not be erased. In other words, the contents of the last page may not
be filled with FFH.
DataFlash
Block Diagram
FLASH MEMORY ARRAY
WP
PAGE (528 BYTES)
BUFFER 1 (528 BYTES)
SCK
CS
RESET
VCC
GND
RDY/BUSY
Memory Array
4
BUFFER 2 (528 BYTES)
I/O INTERFACE
SI
SO
To provide optimal flexibility, the memory array of the 32-Mbit DataFlash is divided into
three levels of granularity comprising of sectors, blocks, and pages. The Memory Architecture Diagram illustrates the breakdown of each level and details the number of pages
per sector and block. All program operations to the DataFlash occur on a page-by-page
basis; however, the optional erase operations can be performed at the block or page
level.
AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
Memory Architecture Diagram
SECTOR 0 = 4224 bytes (4K + 128)
BLOCK ARCHITECTURE
SECTOR 0
BLOCK 0
SECTOR 1 = 266,112 bytes (252K + 8064)
SECTOR 2 = 270,336 bytes (256K + 8K)
SECTOR 1
BLOCK 1
BLOCK 2
PAGE ARCHITECTURE
8 Pages
PAGE 0
BLOCK 0
SECTOR ARCHITECTURE
PAGE 8
SECTOR 2
SECTOR 15 = 270,336 bytes (256K + 8K)
BLOCK 1
BLOCK 63
BLOCK 65
PAGE 6
PAGE 7
BLOCK 62
BLOCK 64
PAGE 1
PAGE 9
PAGE 14
PAGE 15
BLOCK 126
PAGE 16
BLOCK 127
PAGE 17
BLOCK 128
PAGE 18
BLOCK 129
PAGE 8189
SECTOR 16 = 270,336 bytes (256K + 8K)
BLOCK 1022
BLOCK 1023
Block = 4224 bytes
(4K + 128)
Device Operation
PAGE 8190
PAGE 8191
Page = 528 bytes
(512 + 16)
The device operation is controlled by instructions from the host processor. The list of
instructions and their associated opcodes are contained in Tables 1 through 4. A valid
instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode
and the desired buffer or main memory address location. While the CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or main
memory address location through the SI (serial input) pin. All instructions, addresses
and data are transferred with the most significant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA9 - BFA0 to
denote the ten address bits required to designate a byte address within a buffer. Main
memory addressing is referenced using the terminology PA12 - PA0 and BA9 - BA0
where PA12 - PA0 denotes the 13 address bits required to designate a page address
and BA9 - BA0 denotes the ten address bits required to designate a byte address within
the page.
Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from
either one of the two data buffers. The DataFlash supports two categories of read
modes in relation to the SCK signal. The differences between the modes are in respect
to the inactive state of the SCK signal as well as which clock cycle data will begin to be
output. The two categories, which are comprised of four modes total, are defined as
Inactive Clock Polarity Low or Inactive Clock Polarity High and SPI Mode 0 or SPI
Mode 3. A separate opcode (refer to Table 1 on page 11 for a complete list) is used to
select which category will be used for reading. Please refer to the “Detailed Bit-level
Read Timing” diagrams in this datasheet for details on the clock cycle sequences for
each mode.
CONTINUOUS ARRAY READ: By supplying an initial starting address for the main
memory array, the Continuous Array Read command can be utilized to sequentially
read a continuous stream of data from the device by simply providing a clock signal; no
additional addressing information or control signals need to be provided. The DataFlash
incorporates an internal address counter that will automatically increment on every clock
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3356B–DFLASH–10/04
cycle, allowing one continuous read operation without the need of additional address
sequences. To perform a continuous read, an opcode of 68H or E8H must be clocked
into the device followed by 24 address bits and 32 don’t care bits. The first bit of the
24-bit address sequence is reserved for upward and downward compatibility to larger
and smaller density devices (see Notes under “Command Sequence for Read/Write
Operations” diagram). The next 13 address bits (PA12 - PA0) specify which page of the
main memory array to read, and the last ten bits (BA9 - BA0) of the 24-bit address
sequence specify the starting byte address within the page. The 32 don’t care bits that
follow the 24 address bits are needed to initialize the read operation. Following the 32
don’t care bits, additional clock pulses on the SCK pin will result in serial data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bits, the don’t
care bits, and the reading of data. When the end of a page in main memory is reached
during a Continuous Array Read, the device will continue reading at the beginning of the
next page with no delays incurred during the page boundary crossover (the crossover
from the end of one page to the beginning of the next page). When the last bit in the
main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will
be incurred when wrapping around from the end of the array to the beginning of the
array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the
SO pin. The maximum SCK frequency allowable for the Continuous Array Read is
defined by the fCAR specification. The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged.
MAIN MEMORY PAGE READ: A Main Memory Page Read allows the user to read data
directly from any one of the 8192 pages in the main memory, bypassing both of the data
buffers and leaving the contents of the buffers unchanged. To start a page read, an
opcode of 52H or D2H must be clocked into the device followed by 24 address bits and
32 don’t care bits. The first bit of the 24-bit address sequence is a reserved bit, the next
13 address bits (PA12 - PA0) specify the page address, and the next ten address bits
(BA9 - BA0) specify the starting byte address within the page. The 32 don’t care bits
which follow the 24 address bits are sent to initialize the read operation. Following the
32 don’t care bits, additional pulses on SCK result in serial data being output on the SO
(serial output) pin. The CS pin must remain low during the loading of the opcode, the
address bits, the don’t care bits, and the reading of data. When the end of a page in
main memory is reached during a Main Memory Page Read, the device will continue
reading at the beginning of the same page. A low-to-high transition on the CS pin will
terminate the read operation and tri-state the SO pin.
BUFFER READ: Data can be read from either one of the two buffers, using different
opcodes to specify which buffer to read from. An opcode of 54H or D4H is used to read
data from buffer 1, and an opcode of 56H or D6H is used to read data from buffer 2. To
perform a Buffer Read, the eight bits of the opcode must be followed by 14 don’t care
bits, ten address bits, and eight don’t care bits. Since the buffer size is 528 bytes, ten
address bits (BFA9 - BFA0) are required to specify the first byte of data to be read from
the buffer. The CS pin must remain low during the loading of the opcode, the address
bits, the don’t care bits, and the reading of data. When the end of a buffer is reached,
the device will continue reading back at the beginning of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin.
STATUS REGISTER READ: The status register can be used to determine the device’s
Ready/Busy status, the result of a Main Memory Page to Buffer Compare operation, or
the device density. To read the status register, an opcode of 57H or D7H must be
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AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
loaded into the device. After the last bit of the opcode is shifted in, the eight bits of the
status register, starting with the MSB (bit 7), will be shifted out on the SO pin during the
next eight clock cycles. The five most significant bits of the status register will contain
device information, while the remaining three least-significant bits are reserved for future
use and will have undefined values. After bit 0 of the status register has been shifted
out, the sequence will repeat itself (as long as CS remains low and SCK is being toggled) starting again with bit 7. The data in the status register is constantly updated, so
each repeating sequence will output new data.
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDY/BUSY
COMP
1
1
0
1
X
X
Ready/Busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the
device is not busy and is ready to accept the next command. If bit 7 is a 0, then the
device is in a busy state. The user can continuously poll bit 7 of the status register by
stopping SCK at a low level once bit 7 has been output. The status of bit 7 will continue
to be output on the SO pin, and once the device is no longer busy, the state of SO will
change from 0 to 1. There are eight operations which can cause the device to be in a
busy state: Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Compare, Buffer to Main Memory Page Program with Built-in Erase, Buffer to Main Memory
Page Program without Built-in Erase, Page Erase, Block Erase, Main Memory Page
Program, and Auto Page Rewrite.
The result of the most recent Main Memory Page to Buffer Compare operation is indicated using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory
page matches the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the
main memory page does not match the data in the buffer.
The device density is indicated using bits 5, 4, 3 and 2 of the status register. For the 32Mbit DataFlash, the four bits are 1, 1, 0 and 1. The decimal value of these four binary
bits does not equate to the device density; the four bits represent a combinational code
relating to differing densities of Serial DataFlash devices, allowing a total of sixteen different density configurations.
Program and Erase
Commands
BUFFER WRITE: Data can be shifted in from the SI pin into either buffer 1 or buffer 2.
To load data into either buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2, must
be followed by 14 don’t care bits and ten address bits (BFA9 - BFA0). The ten address
bits specify the first byte in the buffer to be written. The data is entered following the
address bits. If the end of the data buffer is reached, the device will wrap around back to
the beginning of the buffer. Data will continue to be loaded into the buffer until a low-tohigh transition is detected on the CS pin.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE: Data written
into either buffer 1 or buffer 2 can be programmed into the main memory. To start the
operation, an 8-bit opcode, 83H for buffer 1 or 86H for buffer 2, must be followed by one
reserved bit, 13 address bits (PA12 - PA0) that specify the page in the main memory to
be written, and ten additional don’t care bits. When a low-to-high transition occurs on the
CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. Both the
erase and the programming of the page are internally self-timed and should take place
in a maximum time of tEP. During this time, the status register will indicate that the part is
busy.
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3356B–DFLASH–10/04
BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: A
previously erased page within main memory can be programmed with the contents of
either buffer 1 or buffer 2. To start the operation, an 8-bit opcode, 88H for buffer 1 or
89H for buffer 2, must be followed by the one reserved bit, 13 address bits (PA12 - PA0)
that specify the page in the main memory to be written, and ten additional don’t care
bits. When a low-to-high transition occurs on the CS pin, the part will program the data
stored in the buffer into the specified page in the main memory. It is necessary that the
page in main memory that is being programmed has been previously erased. The programming of the page is internally self-timed and should take place in a maximum time
of tP. During this time, the status register will indicate that the part is busy.
Successive page programming operations without doing a page erase are not recommended. In other words, changing bytes within a page from a “1” to a “0” during multiple
page programming operations without erasing that page is not recommended.
PAGE ERASE: The optional Page Erase command can be used to individually erase
any page in the main memory array allowing the Buffer to Main Memory Page Program
without Built-in Erase command to be utilized at a later time. To perform a Page Erase,
an opcode of 81H must be loaded into the device, followed by one reserved bit,
13 address bits (PA12 - PA0), and ten don’t care bits. The 13 address bits are used to
specify which page of the memory array is to be erased. When a low-to-high transition
occurs on the CS pin, the part will erase the selected page to 1s. The erase operation is
internally self-timed and should take place in a maximum time of tPE. During this time,
the status register will indicate that the part is busy.
BLOCK ERASE: A block of eight pages can be erased at one time allowing the Buffer
to Main Memory Page Program without Built-in Erase command to be utilized to reduce
programming times when writing large amounts of data to the device. To perform a
Block Erase, an opcode of 50H must be loaded into the device, followed by one
reserved bit, ten address bits (PA12 - PA3), and 13 don’t care bits. The ten address bits
are used to specify which block of eight pages is to be erased. When a low-to-high transition occurs on the CS pin, the part will erase the selected block of eight pages to 1s.
The erase operation is internally self-timed and should take place in a maximum time of
tBE. During this time, the status register will indicate that the part is busy.
Block Erase Addressing
8
PA12
PA11
PA10
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Block
0
0
0
0
0
0
0
0
0
0
X
X
X
0
0
0
0
0
0
0
0
0
0
1
X
X
X
1
0
0
0
0
0
0
0
0
1
0
X
X
X
2
0
0
0
0
0
0
0
0
1
1
X
X
X
3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
0
0
X
X
X
1020
1
1
1
1
1
1
1
1
0
1
X
X
X
1021
1
1
1
1
1
1
1
1
1
0
X
X
X
1022
1
1
1
1
1
1
1
1
1
1
X
X
X
1023
AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
MAIN MEMORY PAGE PROGRAM THROUGH BUFFER: This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase
operations. Data is first shifted into buffer 1 or buffer 2 from the SI pin and then programmed into a specified page in the main memory. To initiate the operation, an 8-bit
opcode, 82H for buffer 1 or 85H for buffer 2, must be followed by one reserved bit and
23 address bits. The 13 most significant address bits (PA12 - PA0) select the page in
the main memory where data is to be written, and the next ten address bits
(BFA9 - BFA0) select the first byte in the buffer to be written. After all address bits are
shifted in, the part will take data from the SI pin and store it in one of the data buffers. If
the end of the buffer is reached, the device will wrap around back to the beginning of the
buffer. When there is a low-to-high transition on the CS pin, the part will first erase the
selected page in main memory to all 1s and then program the data stored in the buffer
into the specified page in the main memory. Both the erase and the programming of the
page are internally self-timed and should take place in a maximum of time tEP. During
this time, the status register will indicate that the part is busy.
Additional Commands
MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred
from the main memory to either buffer 1 or buffer 2. To start the operation, an 8-bit
opcode, 53H for buffer 1 and 55H for buffer 2, must be followed by one reserved bit, 13
address bits (PA12 - PA0) which specify the page in main memory that is to be transferred, and ten don’t care bits. The CS pin must be low while toggling the SCK pin to
load the opcode, the address bits, and the don’t care bits from the SI pin. The transfer of
the page of data from the main memory to the buffer will begin when the CS pin transitions from a low to a high state. During the transfer of a page of data (tXFR), the status
register can be read to determine whether the transfer has been completed or not.
MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can
be compared to the data in buffer 1 or buffer 2. To initiate the operation, an 8-bit opcode,
60H for buffer 1 and 61H for buffer 2, must be followed by 24 address bits consisting of
one reserved bit, 13 address bits (PA12 - PA0) which specify the page in the main memory that is to be compared to the buffer, and ten don’t care bits. The CS pin must be low
while toggling the SCK pin to load the opcode, the address bits, and the don’t care bits
from the SI pin. On the low-to-high transition of the CS pin, the 528 bytes in the selected
main memory page will be compared with the 528 bytes in buffer 1 or buffer 2. During
this time (tXFR), the status register will indicate that the part is busy. On completion of the
compare operation, bit 6 of the status register is updated with the result of the compare.
AUTO PAGE REWRITE: This mode is only needed if multiple bytes within a page or
multiple pages of data are modified in a random fashion. This mode is a combination of
two operations: Main Memory Page to Buffer Transfer and Buffer to Main Memory Page
Program with Built-in Erase. A page of data is first transferred from the main memory to
buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed
back into its original page of main memory. To start the rewrite operation, an 8-bit
opcode, 58H for buffer 1 or 59H for buffer 2, must be followed by one reserved bit, 13
address bits (PA12 - PA0) that specify the page in main memory to be rewritten, and ten
additional don’t care bits. When a low-to-high transition occurs on the CS pin, the part
will first transfer data from the page in main memory to a buffer and then program the
data from the buffer back into same page of main memory. The operation is internally
self-timed and should take place in a maximum time of tEP. During this time, the status
register will indicate that the part is busy.
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3356B–DFLASH–10/04
If a sector is programmed or reprogrammed sequentially page-by-page, then the programming algorithm shown in Figure 1 on page 28 is recommended. Otherwise, if
multiple bytes in a page or several pages are programmed randomly in a sector, then
the programming algorithm shown in Figure 2 on page 29 is recommended. Each page
within a sector must be updated/rewritten at least once within every 10,000 cumulative
page erase/program operations in that sector.
Operation Mode
Summary
The modes described can be separated into two groups – modes which make use of the
Flash memory array (Group A) and modes which do not make use of the Flash memory
array (Group B).
Group A modes consist of:
1. Main Memory Page Read
2. Main Memory Page to Buffer 1 (or 2) Transfer
3. Main Memory Page to Buffer 1 (or 2) Compare
4. Buffer 1 (or 2) to Main Memory Page Program with Built-in Erase
5. Buffer 1 (or 2) to Main Memory Page Program without Built-in Erase
6. Page Erase
7. Block Erase
8. Main Memory Page Program through Buffer
9. Auto Page Rewrite
Group B modes consist of:
1. Buffer 1 (or 2) Read
2. Buffer 1 (or 2) Write
3. Status Register Read
If a Group A mode is in progress (not fully completed) then another mode in Group A
should not be started. However, during this time in which a Group A mode is in
progress, modes in Group B can be started.
This gives the Serial DataFlash the ability to virtually accommodate a continuous datastream. While data is being programmed into main memory from buffer 1, data can be
loaded into buffer 2 (or vice versa). See application note AN-4 (“Using Atmel’s Serial
DataFlash”) for more details.
Pin Descriptions
SERIAL INPUT (SI): The SI pin is an input-only pin and is used to shift data into the
device. The SI pin is used for all data input including opcodes and address sequences.
SERIAL OUTPUT (SO): The SO pin is an output-only pin and is used to shift data out
from the device.
SERIAL CLOCK (SCK): The SCK pin is an input-only pin and is used to control the flow
of data to and from the DataFlash. Data is always clocked into the device on the rising
edge of SCK and clocked out of the device on the falling edge of SCK.
CHIP SELECT (CS): The DataFlash is selected when the CS pin is low. When the
device is not selected, data will not be accepted on the SI pin, and the SO pin will
remain in a high-impedance state. A high-to-low transition on the CS pin is required to
start an operation, and a low-to-high transition on the CS pin is required to end an
operation.
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AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
WRITE PROTECT: If the WP pin is held low, the first 256 pages of the main memory
cannot be reprogrammed. The only way to reprogram the first 256 pages is to first drive
the protect pin high and then use the program commands previously mentioned. If this
pin and feature are not utilized it is recommended that the WP pin be driven high
externally.
RESET: A low state on the reset pin (RESET) will terminate the operation in progress
and reset the internal state machine to an idle state. The device will remain in the reset
condition as long as a low level is present on the RESET pin. Normal operation can
resume once the RESET pin is brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions
on the RESET pin during power-on sequences. If this pin and feature are not utilized it is
recommended that the RESET pin be driven high externally.
READY/BUSY: This open drain output pin will be driven low when the device is busy in
an internally self-timed operation. This pin, which is normally in a high state (through
a 1 kΩ external pull-up resistor), will be pulled low during programming operations, compare operations, and during page-to-buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
Power-on/Reset State
When power is first applied to the device, or when recovering from a reset condition, the
device will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance
state, and a high-to-low transition on the CS pin will be required to start a valid instruction. The SPI mode will be automatically selected on every falling edge of CS by
sampling the inactive clock state. After power is applied and Vcc is at the minimum
datasheet value, the system should wait 20 ms before an operational mode is started.
Table 1. Read Commands
Command
SCK Mode
Opcode
Inactive Clock Polarity Low or High
68H
SPI Mode 0 or 3
E8H
Inactive Clock Polarity Low or High
52H
SPI Mode 0 or 3
D2H
Inactive Clock Polarity Low or High
54H
SPI Mode 0 or 3
D4H
Inactive Clock Polarity Low or High
56H
SPI Mode 0 or 3
D6H
Inactive Clock Polarity Low or High
57H
SPI Mode 0 or 3
D7H
Continuous Array Read
Main Memory Page Read
Buffer 1 Read
Buffer 2 Read
Status Register Read
11
3356B–DFLASH–10/04
Table 2. Program and Erase Commands
Command
SCK Mode
Opcode
Buffer 1 Write
Any
84H
Buffer 2 Write
Any
87H
Buffer 1 to Main Memory Page Program with Built-in Erase
Any
83H
Buffer 2 to Main Memory Page Program with Built-in Erase
Any
86H
Buffer 1 to Main Memory Page Program without Built-in Erase
Any
88H
Buffer 2 to Main Memory Page Program without Built-in Erase
Any
89H
Page Erase
Any
81H
Block Erase
Any
50H
Main Memory Page Program through Buffer 1
Any
82H
Main Memory Page Program through Buffer 2
Any
85H
SCK Mode
Opcode
Main Memory Page to Buffer 1 Transfer
Any
53H
Main Memory Page to Buffer 2 Transfer
Any
55H
Main Memory Page to Buffer 1 Compare
Any
60H
Main Memory Page to Buffer 2 Compare
Any
61H
Auto Page Rewrite through Buffer 1
Any
58H
Auto Page Rewrite through Buffer 2
Any
59H
Table 3. Additional Commands
Command
Note:
12
In Tables 2 and 3, an SCK mode designation of “Any” denotes any one of the four modes of operation (Inactive Clock Polarity
Low, Inactive Clock Polarity High, SPI Mode 0, or SPI Mode 3).
AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
Table 4. Detailed Bit-level Addressing Sequence
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
BA9
BA8
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
Additional
Don’t Care
Bytes
Required
50H
0 1 0 1 0 0 0 0 r
P
P
P
P
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
x
x
x
x
N/A
52H
0 1 0 1 0 0 1 0 r
P
P
P
P
P
P
P
P
P
P
P
P
P
B
B
B
B
B
B
B
B
B
B
4 Bytes
53H
0 1 0 1 0 0 1 1 r
P
P
P
P
P
P
P
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
x
N/A
54H
0 1 0 1 0 1 0 0 x
x
x
x
x
x
x
x
x
x
x
x
x
x
B
B
B
B
B
B
B
B
B
B
1 Byte
55H
0 1 0 1 0 1 0 1 r
P
P
P
P
P
P
P
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
x
N/A
56H
0 1 0 1 0 1 1 0 x
x
x
x
x
x
x
x
x
x
x
x
x
x
B
B
B
B
B
B
B
B
B
B
1 Byte
57H
0 1 0 1 0 1 1 1
58H
0 1 0 1 1 0 0 0 r
P
P
P
P
P
P
P
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
x
N/A
59H
0 1 0 1 1 0 0 1 r
P
P
P
P
P
P
P
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
x
N/A
60H
0 1 1 0 0 0 0 0 r
P
P
P
P
P
P
P
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
x
N/A
61H
0 1 1 0 0 0 0 1 r
P
P
P
P
P
P
P
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
x
N/A
68H
0 1 1 0 1 0 0 0 r
P
P
P
P
P
P
P
P
P
P
P
P
P
B
B
B
B
B
B
B
B
B
B
4 Bytes
81H
1 0 0 0 0 0 0 1 r
P
P
P
P
P
P
P
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
x
N/A
82H
1 0 0 0 0 0 1 0 r
P
P
P
P
P
P
P
P
P
P
P
P
P
B
B
B
B
B
B
B
B
B
B
N/A
83H
1 0 0 0 0 0 1 1 r
P
P
P
P
P
P
P
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
x
N/A
84H
1 0 0 0 0 1 0 0 x
x
x
x
x
x
x
x
x
x
x
x
x
x
B
B
B
B
B
B
B
B
B
B
N/A
85H
1 0 0 0 0 1 0 1 r
P
P
P
P
P
P
P
P
P
P
P
P
P
B
B
B
B
B
B
B
B
B
B
N/A
86H
1 0 0 0 0 1 1 0 r
P
P
P
P
P
P
P
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
x
N/A
87H
1 0 0 0 0 1 1 1 x
x
x
x
x
x
x
x
x
x
x
x
x
x
B
B
B
B
B
B
B
B
B
B
N/A
88H
1 0 0 0 1 0 0 0 r
P
P
P
P
P
P
P
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
x
N/A
89H
1 0 0 0 1 0 0 1 r
P
P
P
P
P
P
P
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
x
N/A
D2H
1 1 0 1 0 0 1 0 r
P
P
P
P
P
P
P
P
P
P
P
P
P
B
B
B
B
B
B
B
B
B
B
4 Bytes
D4H
1 1 0 1 0 1 0 0 x
x
x
x
x
x
x
x
x
x
x
x
x
x
B
B
B
B
B
B
B
B
B
B
1 Byte
D6H
1 1 0 1 0 1 1 0 x
x
x
x
x
x
x
x
x
x
x
x
x
x
B
B
B
B
B
B
B
B
B
B
1 Byte
D7H
1 1 0 1 0 1 1 1
E8H
1 1 1 0 1 0 0 0 r
Opcode
Note:
Opcode
Reserved
PA10
Address Byte
PA11
Address Byte
PA12
Address Byte
N/A
N/A
N/A
P
P
P
P
N/A
N/A
P
P
P
P
P
P
P
P
N/A
N/A
P
B
B
B
B
B
B
B
N/A
B
B
B
4 Bytes
r = Reserved Bit
P = Page Address Bit
B = Byte/Buffer Address Bit
x = Don’t Care
13
3356B–DFLASH–10/04
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
*NOTICE:
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC and AC Operating Range
32-Mbit DataFlash
Com.
0°C to 70°C
Operating Temperature (Case)
Ind.
-40°C to 85°C
(1)
VCC Power Supply
Note:
2.7V to 3.3V
1. After power is applied and VCC is at the minimum specified datasheet value, the system should wait 20 ms before an operational mode is started.
DC Characteristics
Symbol
Parameter
Condition
ISB
Standby Current
ICC1(1)
Typ
Max
Units
CS, RESET, WP = VCC, all inputs
at CMOS levels
2
10
µA
Active Current, Read
Operation
f = 20 MHz; IOUT = 0 mA;
VCC = 3.3V
4
10
mA
ICC2
Active Current,
Program/Erase Operation
VCC = 3.3V
15
35
mA
ILI
Input Load Current
VIN = CMOS levels
1
µA
ILO
Output Leakage Current
VI/O = CMOS levels
1
µA
VIL
Input Low Voltage
0.6
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 1.6 mA; VCC = 2.7V
VOH
Output High Voltage
IOH = -100 µA
Note:
14
Min
2.0
V
0.4
VCC - 0.2V
V
V
1. Icc1 during a buffer read is 20mA maximum.
AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
AC Characteristics
32-Mbit DataFlash
Symbol
Parameter
fSCK
Min
Max
Units
SCK Frequency
20
MHz
fCAR
SCK Frequency for Continuous Array Read
20
MHz
tWH
SCK High Time
22
ns
tWL
SCK Low Time
22
ns
tCS
Minimum CS High Time
250
ns
tCSS
CS Setup Time
250
ns
tCSH
CS Hold Time
250
ns
tCSB
CS High to RDY/BUSY Low
tSU
Data In Setup Time
5
ns
tH
Data In Hold Time
10
ns
tHO
Output Hold Time
0
ns
tDIS
Output Disable Time
18
ns
tV
Output Valid
20
ns
tXFR
Page to Buffer Transfer/Compare Time
250
µs
tEP
Page Erase and Programming Time
20
ms
tP
Page Programming Time
14
ms
tPE
Page Erase Time
8
ms
tBE
Block Erase Time
12
ms
tRST
RESET Pulse Width
tREC
RESET Recovery Time
200
10
ns
µs
1
µs
15
3356B–DFLASH–10/04
Input Test Waveforms and Measurement Levels
AC
DRIVING
LEVELS
2.4V
2.0
0.8
0.45V
AC
MEASUREMENT
LEVEL
tR, tF < 3 ns (10% to 90%)
Output Test Load
DEVICE
UNDER
TEST
30 pF
AC Waveforms
Two different timing diagrams are shown below. Waveform 1 shows the SCK signal
being low when CS makes a high-to-low transition, and Waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. Both waveforms show valid
timing diagrams. The setup and hold times for the SI signal are referenced to the low-tohigh transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2
shows timing that is compatible with SPI Mode 3.
Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0
tCS
CS
tWH
tCSS
tWL
tCSH
SCK
tHO
tV
SO
HIGH IMPEDANCE
VALID OUT
tSU
tDIS
HIGH IMPEDANCE
tH
VALID IN
SI
Waveform 2 – Inactive Clock Polarity High and SPI Mode 3
tCS
CS
tCSS
tWL
tWH
tCSH
SCK
tV
SO
HIGH Z
tHO
VALID OUT
tSU
SI
16
tDIS
HIGH IMPEDANCE
tH
VALID IN
AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
Reset Timing (Inactive Clock Polarity Low Shown)
CS
tREC
tCSS
SCK
tRST
RESET
HIGH IMPEDANCE
HIGH IMPEDANCE
SO
SI
Note:
The CS signal should be in the high state before the RESET signal is deasserted.
Command Sequence for Read/Write Operations (except Status Register Read)
SI
MSB
r X X X XXXX
Reserved for
larger densities
Notes:
CMD
8 bits
8 bits
XXXX XXXX
Page Address
(PA12-PA0)
8 bits
XXXX XXXX
LSB
Byte/Buffer Address
(BA9-BA0/BFA9-BFA0)
1. “r” designates bits reserved for larger densities.
2. It is recommended that “r” be a logical “0” for densities of 32M bits or smaller.
3. For densities larger than 32M bits, the “r” bits become the most significant Page Address bit for the appropriate density.
17
3356B–DFLASH–10/04
Write Operations
The following block diagram and waveforms illustrate the various write sequences
available.
FLASH MEMORY ARRAY
PAGE (528 BYTES)
BUFFER 1 TO
MAIN MEMORY
PAGE PROGRAM
MAIN MEMORY
PAGE PROGRAM
THROUGH BUFFER 2
BUFFER 1 (528 BYTES)
BUFFER 2 TO
MAIN MEMORY
PAGE PROGRAM
BUFFER 2 (528 BYTES)
MAIN MEMORY PAGE
PROGRAM THROUGH
BUFFER 1
BUFFER 1
WRITE
BUFFER 2
WRITE
I/O INTERFACE
SI
Main Memory Page Program through Buffers
· Completes writing into selected buffer
· Starts self-timed erase/program operation
CS
SI
r , PA12-6
CMD
PA5-0, BFA9-8
BFA7-0
n
n+1
Last Byte
Buffer Write
· Completes writing into selected buffer
CS
SI
CMD
X
X···X, BFA9-8
BFA7-0
n
Last Byte
n+1
Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)
Starts self-timed erase/program operation
CS
SI
Each transition represents
8 bits and 8 clock cycles
18
CMD
r , PA12-6
PA5-0, XX
X
n = 1st byte read
n+1 = 2nd byte read
AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
Read Operations
The following block diagram and waveforms illustrate the various read sequences
available.
FLASH MEMORY ARRAY
PAGE (528 BYTES)
MAIN MEMORY
PAGE TO
BUFFER 2
MAIN MEMORY
PAGE TO
BUFFER 1
BUFFER 1 (528 BYTES)
BUFFER 2 (528 BYTES)
BUFFER 1
READ
BUFFER 2
READ
MAIN MEMORY
PAGE READ
I/O INTERFACE
SO
Main Memory Page Read
CS
SI
CMD
r , PA12-6
BA7-0
PA5-0, BA9-8
X
X
X
X
SO
n
n+1
Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)
Starts reading page data into buffer
CS
SI
CMD
r , PA12-6
PA5-0, XX
X
SO
Buffer Read
CS
SI
SO
Each transition represents
8 bits and 8 clock cycles
CMD
X
X···X, BFA9-8
BFA7-0
X
n
n+1
n = 1st byte read
n+1 = 2nd byte read
19
3356B–DFLASH–10/04
Detailed Bit-level Read Timing – Inactive Clock Polarity Low
Continuous Array Read (Opcode: 68H)
CS
SCK
1
2
63
64
0
1
X
X
65
66
67
68
tSU
SI
tV
HIGH-IMPEDANCE
SO
DATA OUT
D7
D6
D5
D2
D1
LSB
MSB
D0
D7
BIT 4223
OF
PAGE n
D6
D5
BIT 0
OF
PAGE n+1
Main Memory Page Read (Opcode: 52H)
CS
SCK
1
2
3
4
5
60
61
62
63
64
0
X
X
X
X
X
65
66
67
tSU
COMMAND OPCODE
SI
0
1
0
1
tV
SO
20
HIGH-IMPEDANCE
DATA OUT
D7
MSB
D6
D5
AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
Detailed Bit-level Read Timing – Inactive Clock Polarity Low (Continued)
Buffer Read (Opcode: 54H or 56H)
CS
SCK
1
2
3
4
5
36
37
38
39
40
0
X
X
X
X
X
41
42
43
tSU
COMMAND OPCODE
SI
1
0
1
0
tV
HIGH-IMPEDANCE
SO
DATA OUT
D7
MSB
D6
D5
Status Register Read (Opcode: 57H)
CS
SCK
1
2
0
1
3
4
5
6
7
8
1
1
9
10
11
12
16
17
tSU
COMMAND OPCODE
SI
0
1
0
1
tV
SO
HIGH-IMPEDANCE
STATUS REGISTER OUTPUT
D7
MSB
D6
D5
D1
D0
LSB
D7
MSB
21
3356B–DFLASH–10/04
Detailed Bit-level Read Timing – Inactive Clock Polarity High
Continuous Array Read (Opcode: 68H)
CS
SCK
1
2
63
64
65
66
67
tSU
SI
1
0
X
X
X
tV
HIGH-IMPEDANCE
SO
DATA OUT
D7
D6
D5
D2
D1
LSB
MSB
D0
D7
BIT 4223
OF
PAGE n
D6
D5
BIT 0
OF
PAGE n+1
Main Memory Page Read (Opcode: 52H)
CS
SCK
1
2
3
4
5
61
62
63
64
65
66
68
67
tSU
COMMAND OPCODE
SI
0
1
0
1
0
X
X
X
X
X
tV
SO
22
HIGH-IMPEDANCE
DATA OUT
D7
MSB
D6
D5
D4
AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
Detailed Bit-level Read Timing – Inactive Clock Polarity High (Continued)
Buffer Read (Opcode: 54H or 56H)
CS
SCK
1
2
3
4
5
37
38
39
40
41
42
44
43
tSU
COMMAND OPCODE
SI
1
0
1
0
0
X
X
X
X
X
tV
DATA OUT
HIGH-IMPEDANCE
SO
D7
MSB
D6
D5
D4
Status Register Read (Opcode: 57H)
CS
SCK
1
2
3
4
5
6
7
8
9
10
11
12
17
18
tSU
COMMAND OPCODE
SI
0
1
0
1
0
1
1
1
tV
SO
HIGH-IMPEDANCE
STATUS REGISTER OUTPUT
D7
MSB
D6
D5
D4
D0
LSB
D7
MSB
D6
23
3356B–DFLASH–10/04
Detailed Bit-level Read Timing – SPI Mode 0
Continuous Array Read (Opcode: E8H)
CS
SCK
1
2
62
63
64
1
1
X
X
X
65
66
67
tSU
SI
tV
HIGH-IMPEDANCE
SO
DATA OUT
D7
D6
D5
D2
D1
LSB
MSB
D0
D7
BIT 4223
OF
PAGE n
D6
D5
BIT 0
OF
PAGE n+1
Main Memory Page Read (Opcode: D2H)
CS
SCK
1
2
3
4
5
60
61
62
63
64
0
X
X
X
X
X
65
66
67
tSU
COMMAND OPCODE
SI
1
1
0
1
tV
SO
HIGH-IMPEDANCE
DATA OUT
D7
D6
D5
D4
MSB
24
AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
Detailed Bit-level Read Timing – SPI Mode 0 (Continued)
Buffer Read (Opcode: D4H or D6H)
CS
SCK
1
2
3
4
5
36
37
38
39
40
0
X
X
X
X
X
41
42
43
tSU
COMMAND OPCODE
SI
1
1
1
0
tV
HIGH-IMPEDANCE
SO
DATA OUT
D7
D6
D4
D5
MSB
Status Register Read (Opcode: D7H)
CS
SCK
1
2
3
4
5
6
7
8
1
1
9
10
D7
MSB
D6
11
12
16
17
tSU
COMMAND OPCODE
SI
1
1
0
1
0
1
tV
SO
HIGH-IMPEDANCE
STATUS REGISTER OUTPUT
D5
D4
D1
D0
LSB
D7
MSB
25
3356B–DFLASH–10/04
Detailed Bit-level Read Timing – SPI Mode 3
Continuous Array Read (Opcode: E8H)
CS
SCK
1
2
63
64
65
66
67
tSU
SI
1
1
X
X
X
tV
HIGH-IMPEDANCE
SO
DATA OUT
D7
D6
D5
D2
D1
LSB
MSB
D0
D7
BIT 4223
OF
PAGE n
D6
D5
BIT 0
OF
PAGE n+1
Main Memory Page Read (Opcode: D2H)
CS
SCK
1
2
3
4
5
61
62
63
64
65
66
67
68
tSU
COMMAND OPCODE
SI
1
1
0
1
0
X
X
X
X
X
tV
SO
26
HIGH-IMPEDANCE
DATA OUT
D7
MSB
D6
D5
D4
AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
Detailed Bit-level Read Timing – SPI Mode 3 (Continued)
Buffer Read (Opcode: D4H or D6H)
CS
SCK
1
2
3
4
5
37
38
39
40
41
42
43
44
tSU
COMMAND OPCODE
SI
1
1
1
0
0
X
X
X
X
X
tV
DATA OUT
HIGH-IMPEDANCE
SO
D7
MSB
D6
D5
D4
Status Register Read (Opcode: D7H)
CS
SCK
1
2
3
4
5
6
7
8
9
10
11
12
17
18
tSU
COMMAND OPCODE
SI
1
1
0
1
0
1
1
1
tV
SO
HIGH-IMPEDANCE
STATUS REGISTER OUTPUT
D7
MSB
D6
D5
D4
D0
LSB
D7
MSB
D6
27
3356B–DFLASH–10/04
Figure 1. Algorithm for Sequentially Programming or Reprogramming the Entire Array
START
provide address
and data
BUFFER WRITE
(84H, 87H)
MAIN MEMORY PAGE PROGRAM
THROUGH BUFFER
(82H, 85H)
BUFFER TO MAIN
MEMORY PAGE PROGRAM
(83H, 86H)
END
Notes:
28
1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-bypage.
2. A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer
to Main Memory Page Program operation.
3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page
within the entire array.
AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
Figure 2. Algorithm for Randomly Modifying Data
START
provide address of
page to modify
MAIN MEMORY PAGE
TO BUFFER TRANSFER
(53H, 55H)
If planning to modify multiple
bytes currently stored within
a page of the Flash array
BUFFER WRITE
(84H, 87H)
MAIN MEMORY PAGE PROGRAM
THROUGH BUFFER
(82H, 85H)
BUFFER TO MAIN
MEMORY PAGE PROGRAM
(83H, 86H)
AUTO PAGE REWRITE
(58H, 59H)
(2)
INCREMENT PAGE
(2)
ADDRESS POINTER
END
Notes:
1. To preserve data integrity, each page of a DataFlash sector must be updated/rewritten at least once within every 10,000
cumulative page erase/program operations.
2. A Page Address Pointer must be maintained to indicate which page is to be rewritten. The Auto Page Rewrite command
must use the address specified by the Page Address Pointer.
3. Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000
cumulative page erase/program operations have accumulated before rewriting all pages of the sector. See application note
AN-4 (“Using Atmel’s Serial DataFlash”) for more details.
Sector Addressing
PA12
PA11
PA10
PA9
PA8
PA7
PA6
PA5
PA4
PA3
Sector
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
1
0
0
0
1
X
X
X
X
X
X
2
0
0
1
0
X
X
X
X
X
X
3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
0
0
X
X
X
X
X
X
13
1
1
0
1
X
X
X
X
X
X
14
1
1
1
0
X
X
X
X
X
X
15
1
1
1
1
X
X
X
X
X
X
16
29
3356B–DFLASH–10/04
4-megabit SRAM
Description
The 4-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as
256K words by 16 bits. The SRAM uses high-performance full CMOS process technology and is designed for high-speed and low-power circuit technology. It is particularly
well-suited for the high-density low-power system application. This device has a data
retention mode that guarantees data to remain valid at a minimum power supply voltage
of 1.2V.
Features
• Fully Static Operation and Tri-state Output
• TTL Compatible Inputs and Outputs
• Battery Backup
– 1.2V (Min) Data Retention
Voltage (V)
Speed (ns)
Operation
Current/ICC (mA)
(Max)
2.7 - 3.3
70
3
Standby
Current (µA)
(Max)
Temperature
(°C)
10
-40 - 85
Block Diagram
ROW DECODER
A0
MEMORY ARRAY
256K X 16
WRITE DRIVER
COLUMN
DECODER
DATA I/O BUFFER
SENSE AMP
BLOCK
DECODER
PRE DECODER
ADD INPUT BUFFER
A17
I/O0
I/O7
I/O8
I/O15
SCS1
SCS2
SOE
SLB
SUB
SWE
30
AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
Absolute Maximum Ratings(1)
Symbol
Parameter
Rating
Unit
VIN, VOUT
Input/Output Voltage
-0.3 to 3.6
V
VCC
Power Supply
-0.3 to 3.6
V
TA
Operating Temperature
-40 to 85
°C
TSTG
Storage Temperature
-55 to 150
°C
PD
Power Dissipation
1.0
W
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
stress rating only and the functional operation of the device under these or any other conditions above those indicated in the
operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may
affect reliability.
Truth Table
I/O Pin
SCS1
SCS2
(1)
X
(1)
L
H
X
X
SOE
X
X
X
L(1)
H
L
H
L
Notes:
SWE
H
H
L
H
H
X
L
SLB(2)
SUB(2)
X
X
Mode
I/O0 - I/O7
I/O8 - I/O15
Power
Deselected
High-Z
High-Z
Standby
Output Disabled
High-Z
High-Z
Active
DIN
High-Z
High-Z
DIN
H
H
L
H
H
L
L
L
L
H
H
L
L
L
DIN
DIN
L
H
DOUT
High-Z
H
L
High-Z
DOUT
L
L
DOUT
DOUT
Write
Read
Active
Active
1. H = VIH, L = VIL, X = Don't Care (VIL or VIH)
2. SUB, SLB (Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is
LOW, data is written or read to the lower byte, I/O0 - I/O7. When SUB is LOW, data is written or read to the upper byte, I/O8
- I/O15.
Recommended DC Operating Condition
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
2.7
3.0
3.3
V
VSS
Ground
0
0
0
V
VIH
Input High Voltage
2.2
VCC + 0.3
V
VIL(1)
Input Low Voltage
-0.3(1)
0.6
V
Note:
1. Undershoot: VIL = -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested.
31
3356B–DFLASH–10/04
DC Electrical Characteristics
TA = -40°C to 85°C
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
VSS < VIN < VCC
-1
1
µA
ILO
Output Leakage Current
VSS < VOUT < VCC,
SCS1 = VIH or SCS2=VIL or
SOE = VIH or SWE = VIL or
SUB = VIH, SLB = VIH
-1
1
µA
ICC
Operating Power Supply Current
SCS1 = VIL, SCS2=VIH,
VIN = VIH or VIL, II/O = 0 mA
3
mA
ICC1
Average Operating Current
SCS1 = VIL, SCS2 = VIH,
VIN = VIH or VIL, Cycle Time = Min
100% Duty, II/O = 0 mA
15
mA
SCS1 < 0.2V, SCS2 > VCC - 0.2V
VIN < 0.2V or VIN > VCC - 0.2V,
Cycle Time = 1 µs
100% Duty, II/O = 0 mA
2
mA
ISB
Standby Current (TTL Input)
SCS1 = VIH or SCS2 = VIL or
SUB, SLB = VIH
VIN = VIH or VIL
300
µA
ISB1
Standby Current (CMOS Input)
SCS1 > VCC - 0.2V or
SCS2 < VSS + 0.2V or
SUB, SLB > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < VSS + 0.2V
10
µA
VOL
Output Low
IOL = 2.1 mA
0.4
V
VOH
Output High
IOH = -1.0 mA
2.4
V
Capacitance(1)
(Temp = 25°C, f = 1.0 MHz)
Symbol
Parameter
CIN
COUT
Note:
32
Condition
Max
Unit
Input Capacitance (Add, SCS1,
SCS2, SLB, SUB, SWE, SOE)
VIN = 0 V
8
pF
Output Capacitance (I/O)
VI/O = 0 V
10
pF
1. These parameters are sampled and not 100% tested.
AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
AC Characteristics
TA = -40°C to 85°C, Unless Otherwise Specified
70 ns
#
Symbol
Parameter
Min
Max
1
tRC
Read Cycle Time
2
tAA
Address Access Time
70
ns
3
tACS
Chip Select Access Time
70
ns
4
tOE
Output Enable to Output Valid
35
ns
5
tBA
SLB, SUB Access Time
70
ns
6
tCLZ
Chip Select to Output in Low Z
10
ns
7
tOLZ
Output Enable to Output in Low Z
5
ns
8
tBLZ
SLB, SUB Enable to Output in Low Z
10
ns
9
tCHZ
Chip Deselection to Output in High Z
0
25
ns
10
tOHZ
Out Disable to Output in High Z
0
25
ns
11
tBHZ
SLB, SUB Disable to Output in High Z
0
25
ns
12
tOH
Output Hold from Address Change
10
ns
13
tWC
Write Cycle Time
30
ns
14
tCW
Chip Selection to End of Write
30
ns
15
tAW
Address Valid to End of Write
30
ns
16
tBW
SLB, SUB Valid to End of Write
30
ns
17
tAS
Address Setup Time
0
ns
18
tWP
Write Pulse Width
30
ns
19
tWR
Write Recovery Time
0
ns
20
tWHZ
Write to Output in High Z
0
21
tDW
Data to Write Time Overlap
25
ns
22
tDH
Data Hold from Write Time
0
ns
23
tOW
Output Active from End of Write
5
ns
70
Unit
ns
5
ns
AC Test Conditions
TA = -40°C to 85°C, Unless Otherwise Specified
Parameter
Value
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5 ns
Input and Output Timing Reference Level
1.5V
Output Load
tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW
CL = 5 pF + 1 TTL Load
Others
CL = 30 pF + 1 TTL Load
33
3356B–DFLASH–10/04
AC Test Loads
VTM = 2.8V
1029 Ohm
DOUT
(1)
CL
Note:
34
1728 Ohm
Including jig and scope capacitance.
AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
Timing Diagrams
Read Cycle 1(1),(4)
tRC
ADDRESS
tAA
tOH
tACS
SCS1
SCS2
tCHZ(3)
tBA
SUB, SLB
tBHZ(3)
tOE
SOE
tOLZ(3)
tOHZ (3)
tBLZ(3)
DATA OUT
HIGH-Z
tCLZ(3)
DATA VALID
Read Cycle 2(1),(2),(4)
tRC
ADDRESS
tAA
tOH
tOH
DATA OUT
PREVIOUS DATA
DATA VALID
Read Cycle 3(1),(2),(4)
SCS1
SUB, SLB
SCS2
DATA OUT
Note:
tACS
tCLZ (3)
tCHZ (3)
DATA VALID
1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active
status.
2. SOE = VIL.
3. Transition is measured ± 200 mV from steady state voltage. This parameter is sampled and not 100% tested.
4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the
standby, low for active.
35
3356B–DFLASH–10/04
Write Cycle 1 (SWE Controlled)(1),(4),(8)
tWC
ADDRESS
tWR(2)
tCW
SCS1
SCS2
tAW
tBW
SUB, SLB
tWP
SWE
tAS
DATA IN
tDW
tDH
tAS
HIGH-Z
DATA VALID
tWHZ(3)(7)
tOW
(5)
(5)
DATA OUT
Write Cycle 2 (SCS1, SCS2 Controlled)(1),(4),(8)
tWC
ADDRESS
tWR(2)
tCW
tAS
SCS1
tAW
SCS2
tBW
SUB, SLB
tWP
SWE
tDW
DATA IN
DATA OUT
Notes:
36
HIGH-Z
tDH
DATA VALID
HIGH-Z
1. A write occurs during the overlap of a low SWE, a low SCS1, a high SCS2 and a low SUB and/or SLB.
2. tWR is measured from the earlier of SCS1, SLB, SUB, or SWE going high or SCS2 going low to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be
applied.
4. If the SCS1, SLB and SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after
the SWE transition, outputs remain in a high impedance state.
5. Q (data out) is the same phase with the write data of this write cycle.
6. Q (data out) is the read data of the next address.
7. Transition is measured ± 200 mV from steady state. This parameter is sampled and not 100% tested.
8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the standby,
low for active.
AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
Data Retention Electric Characteristic
TA = -40°C to 85°C
Symbol
Parameter
Test Condition
Min
VDR
VCC for Data Retention
SCS1 > VCC - 0.2V or
SCS2 < VSS + 0.2V or
SUB, SLB > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < VSS + 0.2V
1.2
ICCDR
Data Retention Current
Vcc=1.5V,
SCS1 > VCC - 0.2V or
SCS2 < VSS + 0.2V or
SUB, SLB > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < VSS + 0.2V
tCDR
Chip Deselect to Data
Retention Time
See Data Retention Timing Diagram
tR
Operating Recovery Time
Notes:
Typ
0.2
Max
Unit
3.3
V
6
µA
0
ns
tRC
ns
1. Typical values are under the condition of TA = 25°C. Typical values are sampled and not 100% tested.
2. tRC is read cycle time.
Data Retention Timing Diagram 1
DATA RETENTION MODE
VCC
2.7V
tCDR
tR
IH
VDR
SCS1 > VCC - 0.2V
SCS1
VSS
Data Retention Timing Diagram 2
DATA RETENTION MODE
VCC
2.7V
tCDR
tR
SCS2
VDR
0.4V
VSS
SCS2 < 0.2V
37
3356B–DFLASH–10/04
Ordering Information
DataFlash
fSCK (MHz)
SRAM
tACC(ns)
Ordering Code
DataFlash
SRAM
Package
Operation Range
20
70
AT45BR3214B-C1
32M x 1
256k x 16
62C1
Industrial
(-40°C to 85°C)
Package Type
62C1
38
62-ball, Plastic Chip-scale Ball Grid Array (CBGA)
AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
Packaging Information
62C1 – CBGA
0.12 C
D
C Seating Plane
Marked A1 Identifier
Side View
E
A1
Top View
2.40 REF
A
D1
10
9
8
7
6
A1 Ball Corner
5
4
3
2
1
A
e
B
C
D
E1
E
F
G
COMMON DIMENSIONS
(Unit of Measure = mm)
H
1.20 REF
e
Øb
Bottom View
MIN
NOM
MAX
A
–
–
1.20
A1
0.25
–
–
D
11.90
12.00
12.10
SYMBOL
D1
E
NOTE
7.20 TYP
7.90
8.00
8.10
E1
5.60 TYP
e
0.80 TYP
Øb
0.40 TYP
05/12/03
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
62C1, 62-ball (10 x 8 Array), 12 x 8 x 1.2 mm Body, 0.8 mm Ball
Plastic Chip-scale Ball Grid Array Package (CBGA)
DRAWING NO.
62C1
REV.
A
39
3356B–DFLASH–10/04
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
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Atmel Sarl
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/xM
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