AT27BV4096 - Mature

Features
• Fast Read Access Time – 120 ns
• Dual Voltage Range Operation
•
•
•
•
•
•
•
•
•
– Unregulated Battery Power Supply Range, 2.7V to 3.6V
or Standard 5V ± 10% Supply Range
Pin Compatible with JEDEC Standard AT27C4096
Low Power CMOS Operation
– 20 µA Max (Less than 1 µA Typical) Standby for VCC = 3.6V
– 36 mW Max Active at 5 MHz for VCC = 3.6V
JEDEC Standard Surface Mount Packages
– 44-lead PLCC
– 40-lead VSOP
High Reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latchup Immunity
Rapid Programming algorithm – 100 µs/Word (Typical)
CMOS and TTL Compatible Inputs and Outputs
– JEDEC Standard for LVTTL and LVBO
Integrated Product Identification Code
Industrial Temperature Range
Green (Pb/Halide-free) Packaging Option
1. Description
The AT27BV4096 is a high-performance, low-power, low-voltage 4,194,304-bit onetime programmable read-only memory (OTP EPROM) organized as 256K by 16 bits.
It requires only one supply in the range of 2.7V to 3.6V in normal read mode operation. The by-16 organization makes this part ideal for portable and handheld 16 and
32 bit microprocessor based systems using either regulated or unregulated battery
power.
4-Megabit
(256K x 16)
Unregulated
Battery-Voltage
High-Speed
OTP EPROM
AT27BV4096
Not Recommended
for New Designs.
Atmel’s innovative design techniques provide fast speeds that rival 5V parts while
keeping the low power consumption of a 3V supply. At VCC = 2.7V, any word can be
accessed in less than 120 ns. With a typical power dissipation of only 18 mW at 5 MHz
and VCC = 3V, the AT27BV4096 consumes less than one fifth the power of a standard
5V EPROM.
Standby mode supply current is typically less than 1 µA at 3V. The AT27BV4096 simplifies system design and stretches battery lifetime even further by eliminating the
need for power supply regulation.
The AT27BV4096 is available in industry-standard JEDEC-approved one-time programmable (OTP) plastic PLCC and VSOP packages. All devices feature two-line
control (CE, OE) to give designers the flexibility to prevent bus contention.
The AT27BV4096 operating with VCC at 3.0V produces TTL level outputs that are
compatible with standard TTL logic devices operating at VCC = 5.0V. At VCC = 2.7V,
the part is compatible with JEDEC approved low voltage battery operation (LVBO)
interface specifications. The device is also capable of standard 5-volt operation making it ideally suited for dual supply range systems or card products that are pluggable
in both 3-volt and 5-volt hosts.
0640E–EPROM–8/07
Atmel’s AT27BV4096 has additional features to ensure high quality and efficient production use.
The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 µs/word. The Integrated
Product Identification Code electronically identifies the device and manufacturer. This feature is
used by industry-standard programming equipment to select the proper programming algorithms
and voltages. The AT27BV4096 programs exactly the same way as a standard 5V AT27C4096
and uses the same programming equipment.
2. Pin Configurations
Pin Name
Function
A0 - A17
Addresses
O0 - O15
Outputs
CE
Chip Enable
OE
Output Enable
NC
No Connect
Note:
2.1
Both GND pins must be connected.
40-lead VSOP Top View Type 1
A9
A10
A11
A12
A13
A14
A15
A16
A17
VCC
VPP
CE
O15
O14
O13
O12
O11
O10
O9
O8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
O0
O1
O2
O3
O4
O5
O6
O7
GND
44-lead PLCC Top View
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
7
8
9
10
11
12
13
14
15
16
17
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
O3
O2
O1
O0
OE
NC
A0
A1
A2
A3
A4
O12
O11
O10
O9
O8
GND
NC
O7
O6
O5
O4
6
5
4
3
2
1
44
43
42
41
40
O13
O14
O15
CE
VPP
NC
VCC
A17
A16
A15
A14
2.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Note: PLCC package pins 1 and 23 are Don’t Connect.
2
AT27BV4096
0640E–EPROM–8/07
AT27BV4096
3. System Considerations
Switching between active and standby conditions via the Chip Enable pin may produce transient
voltage excursions. Unless accommodated by the system design, these transients may exceed
datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency,
low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor
should be connected between the VCC and Ground terminals of the device, as close to the
device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards
with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as
possible to the point where the power supply is connected to the array.
4. Block Diagram
5. Absolute Maximum Ratings*
Temperature Under Bias............................... -55° C to +125° C
Storage Temperature .................................... -65° C to +150° C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on A9 with
Respect to Ground ......................................-2.0V to +14.0V(1)
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
VPP Supply Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is
VCC + 0.75V DC which may be exceeded if certain precautions are observed (consult application notes) and which may
overshoot to +7.0V for pulses of less than 20 ns.
3
0640E–EPROM–8/07
6. Operating Modes
Mode/Pin
CE
OE
Ai
VPP
VCC
Outputs
Read(2)
VIL
VIL
Ai
X(1)
VCC
DOUT
X
VIH
X
X
VCC
High Z
VCC
High Z
Output Disable
Standby
(2)
(2)
Rapid Program(3)
X
X
X
VIL
VIH
Ai
VPP
VCC
DIN
(3)
VIH
VIL
Ai
VPP
VCC
DOUT
(3)
VIH
VIH
X
VPP
VCC
High Z
VCC
VCC
Identification Code
PGM Verify
PGM Inhibit
Product Identification(3)(5)
Notes:
VIH
(5)
VH(4)
VIL
VIL
A9 =
A0 = VIH or VIL
A1 - A17 = VIL
1. X can be VIL or VIH.
2. Read, output disable, and standby modes require, 2.7V ≤VCC ≤3.6V, or 4.5V ≤VCC ≤5.5V.
3. Refer to Programming Characteristics. Programming modes require VCC = 6.5V.
4. VH = 12.0 ± 0.5V.
5. Two identifier bytes may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled
low (VIL) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte.
7. DC and AC Operating Conditions for Read Operation
AT27BV4096-12
Industrial Operating Temperature (Case)
-40° C - 85° C
2.7V to 3.6V
VCC Power Supply
4
5V ± 10%
AT27BV4096
0640E–EPROM–8/07
AT27BV4096
8. DC and Operating Characteristics for Read Operation
Symbol
Parameter
Condition
Min
Max
Units
VCC = 2.7V to 3.6V
ILI
ILO
IPP1
(2)
Input Load Current
VIN = 0V to VCC
±1
µA
Output Leakage Current
VOUT = 0V to VCC
±5
µA
VPP = VCC
10
µA
ISB1 (CMOS), CE = VCC ± 0.3V
20
µA
ISB2 (TTL), CE = 2.0 to VCC + 0.5V
100
µA
f = 5 MHz, IOUT = 0 mA, CE = VIL, VCC = 3.6V
10
mA
VPP
(1)
Read/Standby Current
ISB
VCC(1) Standby Current
ICC
VCC Active Current
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
VCC = 3.0 to 3.6V
-0.6
0.8
V
VCC = 2.7 to 3.6V
-0.6
0.2 x VCC
V
VCC = 3.0 to 3.6V
2.0
VCC + 0.5
V
VCC = 2.7 to 3.6V
0.7 x VCC
VCC + 0.5
V
IOL = 2.0 mA
0.4
V
IOL = 100 µA
0.2
V
IOL = 20 µA
0.1
V
IOH = -2.0 mA
2.4
V
IOH = -100 µA
VCC - 0.2
V
IOH = -20 µA
VCC - 0.1
V
VCC = 4.5V to 5.5V
ILI
ILO
IPP1
(2)
Input Load Current
VIN = 0V to VCC
±1
µA
Output Leakage Current
VOUT = 0V to VCC
±5
µA
VPP = VCC
10
µA
ISB1 (CMOS), CE = VCC ± 0.3V
100
µA
ISB2 (TTL), CE = 2.0 to VCC + 0.5V
1
mA
f = 5 MHz, IOUT = 0 mA, CE = VIL
40
mA
VPP
(1)
Read/Standby Current
ISB
VCC(1) Standby Current
ICC
VCC Active Current
VIL
Input Low Voltage
-0.6
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VOL
Output Low Voltage
IOL = 2.1 mA
0.4
V
VOH
Output High Voltage
IOH = -400 µA
Notes:
2.4
V
1. VCC must be applied simultaneously with or before VPP, and removed simultaneously with or after VPP.
2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP.
5
0640E–EPROM–8/07
9. AC Characteristics for Read Operation
VCC = 2.7V to 3.6V and 4.5V to 5.5V
AT27BV4096-12
Symbol
Parameter
Condition
tACC(3)
Address to Output Delay
tCE(2)
tOE
(2)(3)
Max
Units
CE = OE
= VIL
120
ns
CE to Output Delay
OE = VIL
120
ns
OE to Output Delay
CE = VIL
35
ns
30
ns
tDF(4)(5)
OE or CE High to Output Float, Whichever
Occurred First
tOH
Output Hold from Address, CE or OE,
Whichever Occurred First
Min
0
ns
10. AC Waveforms for Read Operation(1)
Notes:
1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE.
3. OE may be delayed up to tACC - tOE after the address is valid without impact on tACC.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
6. When reading a AT27BV4096, a 0.1 µF capacitor is required across VCC and ground to suppress spurious voltage
transients.
6
AT27BV4096
0640E–EPROM–8/07
AT27BV4096
11. Input Test Waveforms and Measurement Levels
tR, tF < 20 ns (10% to 90%)
12. Output Test Load
Note: CL = 100 pF including
jig capacitance.
13. Pin Capacitance
f = 1 MHz T = 25°C(1)
Symbol
CIN
COUT
Note:
Typ
Max
Units
Conditions
4
10
pF
VIN = 0V
8
12
pF
VOUT = 0V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
7
0640E–EPROM–8/07
14. Programming Waveforms(1)
Notes:
1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH.
2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the AT27BV4096 a 0.1 µF capacitor is required across VPP and ground to suppress spurious
voltage transients.
8
AT27BV4096
0640E–EPROM–8/07
AT27BV4096
15. DC Programming Characteristics
TA = 25 ± 5° C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Limits
Symbol
Parameter
Test Conditions
ILI
Input Load Current
VIN = VIL, VIH
VIL
Input Low Level
VIH
Input High Level
VOL
Output Low Voltage
IOL = 2.1 mA
VOH
Output High Voltage
IOH = -400 µA
ICC2
VCC Supply Current (Program and Verify)
IPP2
VPP Supply Current
VID
A9 Product Identification Voltage
Min
Max
Units
±10
mA
-0.6
0.8
V
2.0
VCC + 0.1
V
0.4
V
2.4
V
CE = VIL
11.5
50
mA
30
mA
12.5
V
Max
Units
16. AC Programming Characteristics
TA = 25 ± 5° C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Limits
Test Conditions(1)
Symbol
Parameter
tAS
Address Setup Time
2
µs
tCES
CE Setup Time
2
µs
tOES
OE Setup Time
2
µs
tDS
Data Setup Time
2
µs
tAH
Address Hold Time
0
µs
tDH
Data Hold Time
2
µs
tDFP
OE High to Output Float Delay(2)
tVPS
VPP Setup Time
tVCS
VCC Setup Time
Input Rise and Fall Times:
(10% to 90%) 20 ns
Input Pulse Levels:
0.45V to 2.4V
0
Input Timing Reference Level:
0.8V to 2.0V
Output Timing Reference Level:
0.8V to 2.0V
(3)
tPW
PGM Program Pulse Width
tOE
Data Valid from OE
tPRT
VPP Pulse Rise Time During
Programming
Notes:
Min
130
ns
2
µs
2
µs
47.5
52.5
µs
150
ns
50
ns
1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven –
see timing diagram.
3. Program Pulse width tolerance is 50 µsec ± 5%.
17. Atmel’s AT27BV4096 Integrated Product Identification Code(1)
Pins
A0
O15-O8
O7
O6
O5
O4
O3
O2
O1
O0
Hex
Data
Manufacturer
0
0
0
0
0
1
1
1
1
0
001E
Device Type
1
0
1
1
1
1
0
1
0
0
00F4
Codes
Note:
1. The AT27BV4096 has the same Product Identification Code as the AT27C4096. Both are programming compatible.
9
0640E–EPROM–8/07
18. Rapid Programming Algorithm
A 50 µs CE pulse width is used to program. The address is set to the first location. VCC is raised
to 6.5V and VPP is raised to 13.0V. Each address is first programmed with one 50 µs CE pulse
without verification. Then a verification/reprogramming loop is executed for each address. In the
event a word fails to pass verification, up to 10 successive 50 µs pulses are applied with a verification after each pulse. If the word fails to verify after 10 pulses have been applied, the part is
considered failed. After the word verifies properly, the next address is selected until all have
been checked. VPP is then lowered to 5.0V and VCC to 5.0V. All words are read again and compared with the original data to determine if the device passes or fails.
START
ADDR = FIRST LOCATION
VCC = 6.5V
VPP = 13.0V
PROGRAM ONE 50 µS PULSE
INCREMENT ADDRESS
NO
LAST
ADDR.?
YES
ADDR = FIRST LOCATION
INCREMENT ADDRESS
X=0
NO
LAST
ADDR.?
PASS
VERIFY
WORD
FAIL
INCREMENT X
YES
PROGRAM ONE 50 µS PULSE
X = 10?
YES
VCC = 5.0V
VPP = 5.0V
COMPARE
ALL WORDS
TO ORIGINAL
DATA
NO
FAIL
DEVICE
FAILED
PASS
DEVICE
PASSED
10
AT27BV4096
0640E–EPROM–8/07
AT27BV4096
19. Ordering Information
19.1
Standard Package
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
120
8
0.02
AT27BV4096-12JI
AT27BV4096-12VI
44J
40V
Industrial
(-40° C to 85° C)
Note:
Refer to PCN# SC042702.
19.2
Green Package (Pb/Halide-free)
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
120
8
0.02
AT27BV4096-12JU
44J
Industrial
(-40° C to 85° C)
Package Type
44J
44-lead, Plastic J-leaded Chip Carrier (PLCC)
40V
40-lead, Plastic Thin Small Outline Package (VSOP)
11
0640E–EPROM–8/07
20. Packaging Information
20.1
44J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
D2/E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
17.399
–
17.653
D1
16.510
–
16.662
E
17.399
–
17.653
E1
16.510
–
16.662
D2/E2
14.986
–
16.002
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
12
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
44J
B
AT27BV4096
0640E–EPROM–8/07
AT27BV4096
20.2
40T – VSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
13.80
14.00
14.20
D1
12.30
12.40
12.50
Note 2
E
9.90
10.00
10.10
Note 2
L
0.50
0.60
0.70
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-142, Variation CA.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
L1
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
NOTE
0.50 BASIC
10/18/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
40V, 40-lead (10 x 14 mm Package) Plastic Thin Small Outline
Package, Type I (VSOP)
DRAWING NO.
REV.
40V
B
13
0640E–EPROM–8/07
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
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0640E–EPROM–8/07
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