AT8xC51SND1C - Mature

Features
• MPEG I/II-Layer 3 Hardwired Decoder
•
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– Stand-alone MP3 Decoder
– 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency
– Separated Digital Volume Control on Left and Right Channels (Software Control
using 31 Steps)
– Bass, Medium, and Treble Control (31 Steps)
– Bass Boost Sound Effect
– Ancillary Data Extraction
– CRC Error and MPEG Frame Synchronization Indicators
Programmable Audio Output for Interfacing with Common Audio DAC
– PCM Format Compatible
– I2S Format Compatible
8-bit MCU C51 Core Based (FMAX = 20 MHz)
2304 Bytes of Internal RAM
64K Bytes of Code Memory
– AT89C51SND1C: Flash (100K Erase/Write Cycles)
– AT83SND1C: ROM
4K Bytes of Boot Flash Memory (AT89C51SND1C)
– ISP: Download from USB (standard) or UART (option)
External Code Memory
– AT80C51SND1C: ROMless
USB Rev 1.1 Controller
– Full Speed Data Transmission
Built-in PLL
– MP3 Audio Clocks
– USB Clock
MultiMedia Card® Interface Compatibility
Atmel DataFlash® SPI Interface Compatibility
IDE/ATAPI Interface
2 Channels 10-bit ADC, 8 kHz (8-true bit)
– Battery Voltage Monitoring
– Voice Recording Controlled by Software
Up to 44 Bits of General-purpose I/Os
– 4-bit Interrupt Keyboard Port for a 4 x n Matrix
– SmartMedia® Software Interface
2 Standard 16-bit Timers/Counters
Hardware Watchdog Timer
Standard Full Duplex UART with Baud Rate Generator
Two Wire Master and Slave Modes Controller
SPI Master and Slave Modes Controller
Power Management
– Power-on Reset
– Software Programmable MCU Clock
– Idle Mode, Power-down Mode
Operating Conditions:
– 3V, ±10%, 25 mA Typical Operating at 25°C
– Temperature Range: -40°C to +85°C
Packages
– TQFP80, BGA81, PLCC84 (Development Board)
– Dice
Single-Chip
Flash
Microcontroller
with MP3
Decoder and
Human
Interface
AT83SND1C
AT89C51SND1C
AT80C51SND1C
4109LS–8051–02/08
1. Description
The AT8xC51SND1C are fully integrated stand-alone hardwired MPEG I/II-Layer 3 decoder with
a C51 microcontroller core handling data flow and MP3-player control.
The AT89C51SND1C includes 64K Bytes of Flash memory and allows In-System Programming
through an embedded 4K Bytes of Boot Flash memory.
The AT83SND1C includes 64K Bytes of ROM memory.
The AT80C51SND1C does not include any code memory.
The AT8xC51SND1C include 2304 Bytes of RAM memory.
The AT8xC51SND1C provides the necessary features for human interface like timers, keyboard
port, serial or parallel interface (USB, TWI, SPI, IDE), ADC input, I2S output, and all external
memory interface (NAND or NOR Flash, SmartMedia, MultiMedia, DataFlash cards).
2. Typical Applications
•
MP3-Player
•
PDA, Camera, Mobile Phone MP3
•
Car Audio/Multimedia MP3
•
Home Audio/Multimedia MP3
3. Block Diagram
Figure 3-1.
AT8xC51SND1C Block Diagram
INT0
INT1
3
3
VDD VSS UVDD UVSS AVDD AVSS AREF AIN1:0
Interrupt
Handler Unit
RAM
2304 Bytes
C51 (X2 Core)
Clock and PLL
Unit
Flash
ROM
64 KBytes
Flash Boot
4 KBytes
10-bit A to D
Converter
TXD RXD
T0
T1
SS MISO MOSI SCK
SCL SDA
3
3
3
4
1
3
UART
and
BRG
Timers 0/1
Watchdog
4
4
4
SPI/DataFlash
Controller
1
TWI
Controller
8-Bit Internal Bus
MP3 Decoder
Unit
I2S/PCM
Audio Interface
USB
Controller
MMC
Interface
Keyboard
Interface
I/O
Ports
IDE
Interface
1
FILT
X1
X2
RST
ISP
ALE
DOUT DCLK DSEL SCLK
D+
D-
MCLK MDAT MCMD
KIN3:0
P0-P5
1 Alternate function of Port 1
3 Alternate function of Port 3
4 Alternate function of Port 4
2
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
4. Pin Description
4.1
Pinouts
AT8xC51SND1C 80-pin QFP Package
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P5.1
P5.0
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
VSS
VDD
P0.6/AD6
P0.7/AD7
P4.3/SS
P4.2/SCK
P4.1/MOSI
P4.0/MISO
P2.0/A8
P2.1/A9
P4.7
P4.6
Figure 4-1.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
AT89C51SND1C-RO (FLASH)
AT83SND1C-RO (ROM)
AT80C51SND1C-RO (ROMLESS)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P4.5
P4.4
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
VSS
VDD
MCLK
MDAT
MCMD
RST
SCLK
DSEL
DCLK
DOUT
VSS
VDD
D+
DVDD
VSS
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
AVDD
AVSS
AREFP
AREFN
AIN0
AIN1
P5.2
P5.3
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
ALE
ISP1/PSEN2/NC
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
P1.4
P1.5
P1.6/SCL
P1.7/SDA
VDD
PVDD
FILT
PVSS
VSS
X2
X1
TST
UVDD
UVSS
Notes:
1. ISP pin is only available in AT89C51SND1C product.
Do not connect this pin on AT83SND1C product.
2. PSEN pin is only available in AT80C51SND1C product.
3
4109LS–8051–02/08
Figure 4-2.
9
Notes:
4
AT8xC51SND1C 81-pin BGA Package
8
7
6
5
4
P4.6
P2.0/
A8
P4.0/
MISO
P4.4
P4.7
P2.5/
A13
3
2
1
P4.2/
SCK
VDD
P0.2/
AD2
P0.3/
AD3
P5.0
ALE
A
P4.1/
MOSI
P4.3/
SS
P0.1/
AD1
P0.4/
AD4
P0.0/
AD0
ISP1/
PSEN2
NC
P1.1
B
P2.2/
A10
P2.1/
A9
P0.6
VSS
P5.1
P1.0/
KIN0
P1.3/
KIN3
P1.2/
KIN2
C
P2.4/
A12
P2.6/
A14
P4.5
P0.7/
AD7
P0.5/
AD5
P1.6/
SCL
P1.7/
SDA
P1.5
P1.4
D
VDD
P2.3/
A11
VSS
P2.7/
A15
FILT
PVDD
X1
VDD
E
RST
MCMD
MCLK
MDAT
AVDD
P3.4/
T0
UVSS
PVSS
X2
F
DSEL
SCLK
DOUT
P5.3
P3.7/
RD
P3.5/
T1
VDD
TST
VSS
G
DCLK
VSS
AIN1
AVSS
AIN0
P3.3/
INT1
P3.1/
TXD
D-
UVDD
H
VDD
P5.2
AREFP
AREFN
P3.6/
WR
P3.2/
INT0
P3.0/
RXD
VSS
D+
J
1. ISP pin is only available in AT89C51SND1C product.
Do not connect this pin on AT83SND1C and AT80C51SND1C product.
2. PSEN pin is only available in AT80C51SND1C product.
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
AT8xC51SND1C 84-pin PLCC Package
11
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
76
75
NC
P5.1
P5.0
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
VSS
VDD
P0.6/AD6
P0.7/AD7
P4.3/SS
P4.2/SCK
P4.1/MOSI
P4.0/MISO
P2.0/A8
P2.1/A9
P4.7
P4.6
Figure 4-3.
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AT89C51SND1C-SR (FLASH)
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
NC
P4.5
P4.4
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
VSS
VDD
MCLK
MDAT
MCMD
RST
SCLK
DSEL
DCLK
DOUT
VSS
VDD
D+
DVDD
VSS
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
AVDD
AVSS
AREFP
AREFN
AIN0
AIN1
P5.2
P5.3
NC
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
ALE
ISP
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
P1.4
P1.5
P1.6/SCL
P1.7/SDA
VDD
PAVDD
FILT
PAVSS
VSS
X2
NC
X1
TST
UVDD
UVSS
4.2
Signals
All the AT8xC51SND1C signals are detailed by functionality in Table 1 to Table 14.
Table 1. Ports Signal Description
Signal
Name
Type
Description
Alternate
Function
P0.7:0
I/O
Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. To
avoid any parasitic current consumption, floating P0 inputs must be
polarized to VDD or VSS.
P1.7:0
I/O
Port 1
P1 is an 8-bit bidirectional I/O port with internal pull-ups.
KIN3:0
SCL
SDA
P2.7:0
I/O
Port 2
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
A15:8
AD7:0
5
4109LS–8051–02/08
Signal
Name
Type
Alternate
Function
Description
RXD
TXD
INT0
INT1
T0
T1
WR
RD
I/O
Port 3
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
P4.7:0
I/O
Port 4
P4 is an 8-bit bidirectional I/O port with internal pull-ups.
MISO
MOSI
SCK
SS
P5.3:0
I/O
Port 5
P5 is a 4-bit bidirectional I/O port with internal pull-ups.
-
P3.7:0
Table 2. Clock Signal Description
Signal
Name
Type
Alternate
Function
Description
X1
I
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to
this pin. If an external oscillator is used, its output is connected to this
pin. X1 is the clock source for internal timing.
X2
O
Output of the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to
this pin. If an external oscillator is used, leave X2 unconnected.
-
FILT
I
PLL Low Pass Filter input
FILT receives the RC network of the PLL low pass filter.
-
-
Table 3. Timer 0 and Timer 1 Signal Description
Signal
Name
Type
Alternate
Function
Description
Timer 0 Gate Input
INT0 serves as external run control for timer 0, when selected by
GATE0 bit in TCON register.
INT0
I
External Interrupt 0
INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set,
bit IE0 is set by a falling edge on INT0. If bit IT0 is cleared, bit IE0 is set
by a low level on INT0.
P3.2
Timer 1 Gate Input
INT1 serves as external run control for timer 1, when selected by
GATE1 bit in TCON register.
INT1
6
I
External Interrupt 1
INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set,
bit IE1 is set by a falling edge on INT1. If bit IT1 is cleared, bit IE1 is set
by a low level on INT1.
P3.3
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
Signal
Name
Type
T0
I
Timer 0 External Clock Input
When timer 0 operates as a counter, a falling edge on the T0 pin
increments the count.
P3.4
T1
I
Timer 1 External Clock Input
When timer 1 operates as a counter, a falling edge on the T1 pin
increments the count.
P3.5
Description
Alternate
Function
Table 4. Audio Interface Signal Description
Signal
Name
Type
DCLK
O
DAC Data Bit Clock
-
DOUT
O
DAC Audio Data
-
DSEL
O
DAC Channel Select Signal
DSEL is the sample rate clock output.
-
SCLK
O
DAC System Clock
SCLK is the oversampling clock synchronized to the digital audio data
(DOUT) and the channel selection signal (DSEL).
-
Description
Alternate
Function
Table 5. USB Controller Signal Description
Signal
Name
Type
D+
I/O
USB Positive Data Upstream Port
This pin requires an external 1.5 KΩ pull-up to VDD for full speed
operation.
-
D-
I/O
USB Negative Data Upstream Port
-
Description
Alternate
Function
Table 6. MutiMediaCard Interface Signal Description
Signal
Name
Type
MCLK
O
MMC Clock output
Data or command clock transfer.
-
MCMD
I/O
MMC Command line
Bidirectional command channel used for card initialization and data
transfer commands. To avoid any parasitic current consumption,
unused MCMD input must be polarized to VDD or VSS.
-
MDAT
I/O
MMC Data line
Bidirectional data channel. To avoid any parasitic current consumption,
unused MDAT input must be polarized to VDD or VSS.
-
Description
Alternate
Function
7
4109LS–8051–02/08
Table 7. UART Signal Description
Signal
Name
Type
Alternate
Function
RXD
I/O
Receive Serial Data
RXD sends and receives data in serial I/O mode 0 and receives data in
serial I/O modes 1, 2 and 3.
P3.0
TXD
O
Transmit Serial Data
TXD outputs the shift clock in serial I/O mode 0 and transmits data in
serial I/O modes 1, 2 and 3.
P3.1
Description
Table 8. SPI Controller Signal Description
Signal
Name
Type
Alternate
Function
MISO
I/O
SPI Master Input Slave Output Data Line
When in master mode, MISO receives data from the slave peripheral.
When in slave mode, MISO outputs data to the master controller.
P4.0
MOSI
I/O
SPI Master Output Slave Input Data Line
When in master mode, MOSI outputs data to the slave peripheral.
When in slave mode, MOSI receives data from the master controller.
P4.1
SCK
I/O
SPI Clock Line
When in master mode, SCK outputs clock to the slave peripheral. When
in slave mode, SCK receives clock from the master controller.
P4.2
SS
I
SPI Slave Select Line
When in controlled slave mode, SS enables the slave mode.
P4.3
Description
Table 9. TWI Controller Signal Description
Signal
Name
Type
Alternate
Function
Description
SCL
I/O
TWI Serial Clock
When TWI controller is in master mode, SCL outputs the serial clock to
the slave peripherals. When TWI controller is in slave mode, SCL
receives clock from the master controller.
SDA
I/O
TWI Serial Data
SDA is the bidirectional Two Wire data line.
P1.6
P1.7
Table 10. A/D Converter Signal Description
8
Signal
Name
Type
AIN1:0
I
A/D Converter Analog Inputs
-
AREFP
I
Analog Positive Voltage Reference Input
-
AREFN
I
Analog Negative Voltage Reference Input
This pin is internally connected to AVSS.
-
Description
Alternate
Function
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
Table 11. Keypad Interface Signal Description
Signal
Name
Type
KIN3:0
I
Description
Keypad Input Lines
Holding one of these pins high or low for 24 oscillator periods triggers a
keypad interrupt.
Alternate
Function
P1.3:0
Table 12. External Access Signal Description
Notes:
Signal
Name
Type
A15:8
I/O
Address Lines
Upper address lines for the external bus.
Multiplexed higher address and data lines for the IDE interface.
P2.7:0
AD7:0
I/O
Address/Data Lines
Multiplexed lower address and data lines for the external memory or the
IDE interface.
P0.7:0
ALE
O
Address Latch Enable Output
ALE signals the start of an external bus cycle and indicates that valid
address information is available on lines A7:0. An external latch is used
to demultiplex the address from address/data bus.
-
PSEN
I/O
Program Store Enable Output (AT80C51SND1C Only)
This signal is active low during external code fetch or external code
read (MOVC instruction).
-
ISP
I/O
ISP Enable Input (AT89C51SND1C Only)
This signal must be held to GND through a pull-down resistor at the
falling reset to force execution of the internal bootloader.
-
RD
O
Read Signal
Read signal asserted during external data memory read operation.
P3.7
WR
O
Write Signal
Write signal asserted during external data memory write operation.
P3.6
EA(1)(2)
I
External Access Enable (Dice Only)
EA must be externally held low to enable the device to fetch code from
external program memory locations 0000h to FFFFh.
Description
Alternate
Function
-
1. For ROM/Flash Dice product versions: pad EA must be connected to VCC.
2. For ROMless Dice product versions: pad EA must be connected to VSS.
Table 13. System Signal Description
Signal
Name
Type
Description
RST
I
Reset Input
Holding this pin high for 64 oscillator periods while the oscillator is
running resets the device. The Port pins are driven to their reset
conditions when a voltage lower than VIL is applied, whether or not the
oscillator is running.
This pin has an internal pull-down resistor which allows the device to be
reset by connecting a capacitor between this pin and VDD.
Asserting RST when the chip is in Idle mode or Power-Down mode
returns the chip to normal operation.
TST
I
Test Input
Test mode entry signal. This pin must be set to VDD.
Alternate
Function
-
-
9
4109LS–8051–02/08
Table 14. Power Signal Description
10
Signal
Name
Type
Description
Alternate
Function
VDD
PWR
Digital Supply Voltage
Connect these pins to +3V supply voltage.
-
VSS
GND
Circuit Ground
Connect these pins to ground.
-
AVDD
PWR
Analog Supply Voltage
Connect this pin to +3V supply voltage.
-
AVSS
GND
Analog Ground
Connect this pin to ground.
-
PVDD
PWR
PLL Supply voltage
Connect this pin to +3V supply voltage.
-
PVSS
GND
PLL Circuit Ground
Connect this pin to ground.
-
UVDD
PWR
USB Supply Voltage
Connect this pin to +3V supply voltage.
-
UVSS
GND
USB Ground
Connect this pin to ground.
-
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
4.3
Internal Pin Structure
Table 15. Detailed Internal Pin Structure
Circuit(1)
Type
Pins
Input
TST
Input/Output
RST
Input/Output
P1(2)
P2(3)
P3
P4
P53:0
RTST
VDD
VDD
P
RRST
Watchdog Output
VSS
2 osc
periods
Latch Output
VDD
VDD
VDD
P1
P2
P3
N
VSS
VDD
P
Input/Output
P0
MCMD
MDAT
ISP
N
PSEN
VSS
ALE
SCLK
DCLK
VDD
P
Output
N
DOUT
DSEL
MCLK
VSS
D+
Input/Output
D+
D-
D-
Notes:
1. For information on resistors value, input/output levels, and drive capability, refer to the
Section “DC Characteristics”, page 18.
2. When the Two Wire controller is enabled, P1, P2, and P3 transistors are disabled allowing
pseudo open-drain structure.
3. In Port 2, P1 transistor is continuously driven when outputting a high level bit address (A15:8).
11
4109LS–8051–02/08
5. Application Information
RST
VDD
AVDD
Ref.
VREFP
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
P0.0
P0.1
P0.2
P0.3
AIN1
P1.6/SCL
P1.7/SDA
LCD
VREFN
Battery
AT8xC51SND1C Typical Application with On-Board Atmel DataFlash and 2-wire
LCD
AIN0
Figure 5-1.
MCLK
MDAT
MCMD
AT8xC51SND1C
D+
D-
DataFlash
Memories
USB PORT
AVSS
VSS
P1.5
P1.4
DOUT
DCLK
DSEL
SCLK
P4.0/SI
UVSS
P4.1/SO
P4n
FILT
P4.2/SCK
X2
12
MMC2
UVDD
X1
PVSS
MMC1
Audio DAC
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
RST
AVDD
VDD
Ref.
VREFP
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P0.0
P0.1
P0.2
P0.3
AIN1
P1.3
P0.4
P0.5
P0.6
P0.7
P1.6/SCL
P1.7/SDA
LCD
VREFN
Battery
AT8xC51SND1C Typical Application with On-Board Atmel DataFlash and // LCD
AIN0
Figure 5-2.
AT8xC51SND1C
D+
D-
X2
DataFlash
Memories
USB PORT
AVSS
VSS
P1.5
P1.4
DOUT
DCLK
DSEL
SCLK
P4.0/SI
P4.1/SO
P4.n
FILT
P4.2/SCK
UVSS
Audio DAC
RST
AVDD
VDD
Ref.
VREFP
AIN1
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
P0.0
P0.1
P0.2
P0.3
P4.0
P4.1
P4.2
P4.4
P4.5
P4.6
P4.7
LCD
VREFN
Battery
AT8xC51SND1C Typical Application with On-Board SSFDC Flash
AIN0
Figure 5-3.
MMC2
UVDD
X1
PVSS
MMC1
MCLK
MDAT
MCMD
MCLK
MDAT
MCMD
AT8xC51SND1C
MMC2
UVDD
D+
D-
X1
X2
USB PORT
AVSS
VSS
P3.5
P3.4
DOUT
DCLK
DSEL
SCLK
P3.7/RD#
P0
P2
FILT
P3.6/WR#
UVSS
PVSS
MMC1
Audio DAC
SSFDC Memories
or SmartMedia Cards
SmartMedia
13
4109LS–8051–02/08
RST
VDD
AVDD
Ref.
VREFP
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P0.0
P0.1
P0.2
P0.3
AIN1
P4.0
P4.1
P4.2
P4.4
P4.5
P4.6
P4.7
P1.6/SCL
P1.7/SDA
LCD
VREFN
Battery
AT8xC51SND1C Typical Application with IDE CD-ROM Drive
AIN0
Figure 5-4.
MCLK
MDAT
MCMD
AT8xC51SND1C
MMC2
UVDD
X1
D+
D-
USB PORT
AVSS
VSS
P3.5
P3.4
UVSS
DOUT
DCLK
DSEL
SCLK
P3.7/RD#
P0
P2
FILT
P3.6/WR#
X2
PVSS
MMC1
Audio DAC
IDE CD-ROM
14
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
6. Peripherals
The AT8xC51SND1C peripherals are briefly described in the following sections. For further
details on how to interface (hardware and software) to these peripherals, please refer to the
AT8xC51SND1C design guide.
6.1
Clock Generator System
The AT8xC51SND1C internal clocks are extracted from an on-chip PLL fed by an on-chip oscillator. Four clocks are generated respectively for the C51 core, the MP3 decoder, the audio
interface, and the other peripherals. The C51 and peripheral clocks are derived from the oscillator clock. The MP3 decoder clock is generated by dividing the PLL output clock. The audio
interface sample rates are also obtained by dividing the PLL output clock.
6.2
Ports
The AT8xC51SND1C implements five 8-bit ports (P0 to P4) and one 4-bit port (P5). In addition
to performing general-purpose I/O, some ports are capable of external data memory operations;
others allow for alternate functions. All I/O Ports are bidirectional. Each Port contains a latch, an
output driver and an input buffer. Port 0 and Port 2 output drivers and input buffers facilitate
external memory operations. Some Port 1, Port 3 and Port 4 pins serve for both general-purpose
I/O and alternate functions.
6.3
Timers/Counters
The AT8xC51SND1C implements the two general-purpose, 16-bit Timers/Counters of a standard C51. They are identified as Timer 0, Timer 1, and can independently be configured each to
operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, a
Timer/Counter runs for a programmed length of time, then issues an interrupt request. When
operating as a Counter, a Timer/Counter counts negative transitions on an external pin. After a
preset number of counts, the Counter issues an interrupt request.
6.4
Watchdog Timer
The AT8xC51SND1C implements a hardware Watchdog Timer that automatically resets the
chip if it is allowed to time out. The WDT provides a means of recovering from routines that do
not complete successfully due to software or hardware malfunctions.
6.5
MP3 Decoder
The AT8xC51SND1C implements a MPEG I/II audio layer 3 decoder (known as MP3 decoder).
In MPEG I (ISO 11172-3) three layers of compression have been standardized supporting three
sampling frequencies: 48, 44.1, and 32 KHz. Among these layers, layer 3 allows highest compression rate of about 12:1 while still maintaining CD audio quality. For example, 3 minutes of
CD audio (16-bit PCM, 44.1 KHz) data, which needs about 32 MBytes of storage, can be
encoded into only 2.7 MBytes of MPEG I audio layer 3 data.
In MPEG II (ISO 13818-3), three additional sampling frequencies: 24, 22.05, and 16 KHz are
supported for low bit rates applications.
The AT8xC51SND1C can decode in real-time the MPEG I audio layer 3 encoded data into a
PCM audio data, and also supports MPEG II audio layer 3 additional frequencies.
Additional features are supported by the AT8xC51SND1C MP3 decoder such as volume, bass,
medium, and treble controls, bass boost effect and ancillary data extraction.
15
4109LS–8051–02/08
6.6
Audio Output Interface
The AT8xC51SND1C implements an audio output interface allowing the decoded audio bitstream to be output in various formats. It is compatible with right and left justification PCM and
I2S formats and thanks to the on-chip PLL (see Section 6.1) allows connection of almost all of
the commercial audio DAC families available on the market.
6.7
Universal Serial Bus Interface
The AT8xC51SND1C implements a full speed Universal Serial Bus Interface. It can be used for
the following purposes:
6.8
•
Download of MP3 encoded audio files by supporting the USB mass storage class.
•
In System Programming by supporting the USB firmware upgrade class.
MultiMediaCard Interface
The AT8xC51SND1C implements a MultiMediaCard (MMC) interface compliant to the V2.2
specification in MultiMediaCard Mode. The MMC allows storage of MP3 encoded audio files in
removable flash memory cards that can be easily plugged or removed from the application. It
can also be used for In System Programming.
6.9
IDE/ATAPI interface
The AT8xC51SND1C provides an IDE/ATAPI interface allowing connexion of devices such as
CD-ROM reader, CompactFlash cards, Hard Disk Drive… It consists in a 16-bit bidirectional bus
part of the low-level ANSI ATA/ATAPI specification. It is provided for mass storage interface but
could be used for In System Programming using CD-ROM.
6.10
Serial I/O Interface
The AT8xC51SND1C implements a serial port with its own baud rate generator providing one
single synchronous communication mode and three full-duplex Universal Asynchronous
Receiver Transmitter (UART) communication modes. It is provided for the following purposes:
6.11
•
In System Programming.
•
Remote control of the AT8xC51SND1C by a host.
Serial Peripheral Interface
The AT8xC51SND1C implements a Serial Peripheral Interface (SPI) supporting master and
slave modes. It is provided for the following purposes:
6.12
•
Interfacing DataFlash memory for MP3 encoded audio files storage.
•
Remote control of the AT8xC51SND1C by a host.
•
In System Programming.
2-wire Controller
The AT8xC51SND1C implements a 2-wire controller supporting the four standard master and
slave modes with multimaster capability. It is provided for the following purposes:
16
•
Connection of slave devices like LCD controller, audio DAC…
•
Remote control of the AT8xC51SND1C by a host.
•
In System Programming.
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
6.13
A/D Controller
The AT8xC51SND1C implements a 2-channel 10-bit (8 true bits) analog to digital converter
(ADC). It is provided for the following purposes:
6.14
•
Battery monitoring.
•
Voice recording.
•
Corded remote control.
Keyboard Interface
The AT8xC51SND1C implements a keyboard interface allowing connection of 4 x n matrix keyboard. It is based on 4 inputs with programmable interrupt capability on both high or low level.
These inputs are available as alternate function of P1.3:0 and allow exit from idle and power
down modes.
17
4109LS–8051–02/08
7. Electrical Characteristics
7.1
Absolute Maximum Rating
Storage Temperature ......................................... -65 to +150°C
Voltage on any other Pin to VSS
.................................... -0.3
*NOTICE:
to +4.0 V
IOL per I/O Pin ................................................................. 5 mA
Power Dissipation ............................................................. 1 W
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond
the “operating conditions” is not recommended
and extended exposure beyond the “Operating
Conditions” may affect device reliability.
Operating Conditions
Ambient Temperature Under Bias........................ -40 to +85°C
VDD ........................................................................................................................ 4.0V
7.2
DC Characteristics
7.2.1
Digital Logic
Table 16. Digital DC Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
VIL
VIH1
(2)
Min
Input Low Voltage
Input High Voltage (except RST, X1)
Typ(1)
Max
Units
-0.5
0.2·VDD - 0.1
V
0.2·VDD + 1.1
VDD
V
0.7·VDD
VDD + 0.5
V
Test Conditions
VIH2
Input High Voltage (RST, X1)
VOL1
Output Low Voltage
(except P0, ALE, MCMD, MDAT, MCLK,
SCLK, DCLK, DSEL, DOUT)
0.45
V
IOL= 1.6 mA
VOL2
Output Low Voltage
(P0, ALE, MCMD, MDAT, MCLK, SCLK,
DCLK, DSEL, DOUT)
0.45
V
IOL= 3.2 mA
VOH1
Output High Voltage
(P1, P2, P3, P4 and P5)
VDD - 0.7
V
IOH= -30 µA
VOH2
Output High Voltage
(P0, P2 address mode, ALE, MCMD,
MDAT, MCLK, SCLK, DCLK, DSEL,
DOUT, D+, D-)
VDD - 0.7
V
IOH= -3.2 mA
IIL
Logical 0 Input Current (P1, P2, P3, P4
and P5)
-50
µA
VIN= 0.45 V
ILI
Input Leakage Current (P0, ALE, MCMD,
MDAT, MCLK, SCLK, DCLK, DSEL,
DOUT)
10
µA
0.45< VIN< VDD
ITL
Logical 1 to 0 Transition Current
(P1, P2, P3, P4 and P5)
-650
µA
VIN= 2.0 V
200
kΩ
RRST
CIO
VRET
18
Parameter
Pull-Down Resistor
Pin Capacitance
VDD Data Retention Limit
50
90
10
pF
1.8
TA= 25°C
V
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
Table 16. Digital DC Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Parameter
Min
AT89C51SND1C
Operating Current
IDD
Typ(1)
Max
(3)
X1 / X2 mode
6.5 / 10.5
8 / 13.5
9.5 / 17
AT83SND1C
Operating Current
X1 / X2 mode
6.5 / 10.5
8 / 13.5
9.5 / 17
AT80C51SND1C
Idle Mode Current
X1 / X2 mode
6.5 / 10.5
8 / 13.5
9.5 / 17
AT89C51SND1C
(3)
Idle Mode Current
IDL
IPD
IFP
X1 / X2 mode
5.3 / 8.1
6.4 / 10.3
7.5 / 13
Units
Test Conditions
VDD < 3.3 V
mA
12 MHz
16 MHz
20 MHz
VDD < 3.3 V
mA
12 MHz
16 MHz
20 MHz
VDD < 3.3 V
mA
12 MHz
16 MHz
20 MHz
VDD < 3.3 V
mA
12 MHz
16 MHz
20 MHz
VDD < 3.3 V
AT83SND1C
Idle Mode Current
X1 / X2 mode
5.3 / 8.1
6.4 / 10.3
7.5 / 13
AT80C51SND1C
Idle Mode Current
X1 / X2 mode
5.3 / 8.1
6.4 / 10.3
7.5 / 13
mA
mA
12 MHz
16 MHz
20 MHz
VDD < 3.3 V
12 MHz
16 MHz
20 MHz
AT89C51SND1C
Power-Down Mode Current
20
500
µA
VRET < VDD < 3.3 V
AT83SND1C
Power-Down Mode Current
20
500
µA
VRET < VDD < 3.3 V
AT80C51SND1C
Power-Down Mode Current
20
500
µA
VRET < VDD < 3.3 V
15
mA
VDD < 3.3 V
AT89C51SND1C
Flash Programming Current
Notes:
1. Typical values are obtained using VDD= 3 V and TA= 25°C. They are not tested and there is no
guarantee on these values.
2. Flash retention is guaranteed with the same formula for VDD min down to 0V.
3. See Table 17 for typical consumption in player mode.
Table 17. Typical Reference Design AT89C51SND1C Power Consumption
Player Mode
IDD
Test Conditions
Stop
10 mA
AT89C51SND1C at 16 MHz, X2 mode, VDD= 3 V
No song playing
Playing
30 mA
AT89C51SND1C at 16 MHz, X2 mode, VDD= 3 V
MP3 Song with Fs= 44.1 KHz, at any bit rates (Variable Bit Rate)
19
4109LS–8051–02/08
7.2.1.1
IDD, IDL and IPD Test Conditions
Figure 7-1.
IDD Test Condition, Active Mode
VDD
VDD
RST
(NC)
Clock Signal
VDD
PVDD
UVDD
AVDD
X2
X1
IDD
VDD
P0
VSS
PVSS
UVSS
AVSS
VSS
Figure 7-2.
TST
All other pins are unconnected
IDL Test Condition, Idle Mode
VDD
RST
VSS
(NC)
Clock Signal
VDD
PVDD
UVDD
AVDD
X2
X1
IDL
VDD
P0
VSS
PVSS
UVSS
AVSS
VSS
Figure 7-3.
TST
All other pins are unconnected
IPD Test Condition, Power-Down Mode
VDD
RST
VSS
(NC)
X2
X1
VSS
PVSS
UVSS
AVSS
VSS
20
VDD
PVDD
UVDD
AVDD
IPD
VDD
P0
MCMD
MDAT
TST
All other pins are unconnected
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
7.2.2
A to D Converter
Table 18. A to D Converter DC Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Typ
2.7
Max
Units
Test Conditions
3.3
V
600
µA
AVDD= 3.3V
AIN1:0= 0 to AVDD
ADEN= 1
2
µA
AVDD= 3.3V
ADEN= 0 or PD= 1
V
Analog Supply Voltage
AIDD
Analog Operating Supply Current
AIPD
Analog Standby Current
AVIN
Analog Input Voltage
AVSS
AVDD
Reference Voltage
AREFN
AREFP
AVSS
2.4
AVDD
10
30
KΩ
TA= 25°C
10
pF
TA= 25°C
RREF
AREF Input Resistance
CIA
7.2.3.1
Min
AVDD
AVREF
7.2.3
Parameter
V
Analog Input capacitance
Oscillator & Crystal
Schematic
Figure 7-4.
Crystal Connection
X1
C1
Q
C2
VSS
Note:
7.2.3.2
X2
For operation with most standard crystals, no external components are needed on X1 and X2. It
may be necessary to add external capacitors on X1 and X2 to ground in special cases (max 10
pF). X1 and X2 may not be used to drive other circuits.
Parameters
Table 19. Oscillator & Crystal Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Parameter
Min
Typ
Max
Unit
CX1
Internal Capacitance (X1 - VSS)
10
pF
CX2
Internal Capacitance (X2 - VSS)
10
pF
CL
Equivalent Load Capacitance (X1 - X2)
5
pF
DL
Drive Level
50
µW
Crystal Frequency
20
MHz
RS
Crystal Series Resistance
40
Ω
CS
Crystal Shunt Capacitance
6
pF
F
21
4109LS–8051–02/08
7.2.4
7.2.4.1
Phase Lock Loop
Schematic
Figure 7-5.
PLL Filter Connection
FILT
R
C2
C1
VSS
7.2.4.2
VSS
Parameters
Table 20. PLL Filter Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
7.2.5
7.2.5.1
Parameter
Min
Typ
Max
Unit
R
Filter Resistor
100
Ω
C1
Filter Capacitance 1
10
nF
C2
Filter Capacitance 2
2.2
nF
USB Connection
Schematic
Figure 7-6.
USB Connection
VDD
VBUS
To Power
Supply
D+
RFS
D+
RUSB
D-
D-
RUSB
GND
VSS
7.2.5.2
Parameters
Table 21. USB Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
22
Parameter
Min
Typ
Max
Unit
RUSB
USB Termination Resistor
27
Ω
RFS
USB Full Speed Resistor
1.5
KΩ
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
7.2.6
7.2.6.1
MMC Controller
Schematic
Figure 7-7.
MMC Connection
VDD
RDAT
RCMD
7.2.6.2
MDAT
MCMD
Parameters
Table 22. MMC Components Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
7.2.7
7.2.7.1
Parameter
RCMD
MMC/SD Command Line Pull-Up Resistor
RDAT
MMC/SD Data Line Pull-Up Resistor
Min
Typ
Max
Unit
1OO
KΩ
10
KΩ
In System Programming
Schematic
Figure 7-8.
ISP Pull-Down Connection
ISP
RISP
VSS
7.2.7.2
Parameters
Table 23. ISP Pull-Down Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
RISP
Parameter
ISP Pull-Down Resistor
Min
Typ
2.2
Max
Unit
KΩ
23
4109LS–8051–02/08
7.3
7.3.1
7.3.1.1
AC Characteristics
External Program Bus Cycles
Definition of Symbols
Table 24. External Program Bus Cycles Timing Symbol Definitions
Signals
7.3.1.2
Conditions
A
Address
H
High
I
Instruction In
L
Low
L
ALE
V
Valid
P
PSEN
X
No Longer Valid
Z
Floating
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 25. External Program Bus Cycle - Read AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
24
Parameter
TCLCL
Clock Period
TLHLL
ALE Pulse Width
TAVLL
Min
Max
Min
Max
Unit
50
50
ns
2·TCLCL-15
TCLCL-15
ns
Address Valid to ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLAX
Address hold after ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLIV
ALE Low to Valid Instruction
4·TCLCL-35
2·TCLCL-35
ns
TPLPH
PSEN Pulse Width
3·TCLCL-25
1.5·TCLCL-25
ns
TPLIV
PSEN Low to Valid Instruction
TPXIX
Instruction Hold After PSEN High
TPXIZ
Instruction Float After PSEN High
TCLCL-10
0.5·TCLCL-10
ns
TAVIV
Address Valid to Valid Instruction
5·TCLCL-35
2.5·TCLCL-35
ns
TPLAZ
PSEN Low to Address Float
10
10
ns
3·TCLCL-35
0
1.5·TCLCL-35
0
ns
ns
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
7.3.1.3
Waveforms
Figure 7-9.
External Program Bus Cycle - Read Waveforms
ALE
TLHLL
TPLPH
TLLPL
PSEN
TPLIV
TPLAZ
TAVLL TLLAX
P0
D7:0
TPXAV
TPXIZ
TPXIX
A7:0
D7:0
A7:0
D7:0
Instruction In
P2
7.3.2
7.3.2.1
Instruction In
A15:8
A15:8
External Data 8-bit Bus Cycles
Definition of Symbols
Table 26. External Data 8-bit Bus Cycles Timing Symbol Definitions
Signals
7.3.2.2
Conditions
A
Address
H
High
D
Data In
L
Low
L
ALE
V
Valid
Q
Data Out
X
No Longer Valid
R
RD
Z
Floating
W
WR
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 27. External Data 8-bit Bus Cycle - Read AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Variable Clock
Standard Mode
Symbol
Parameter
TCLCL
Clock Period
TLHLL
ALE Pulse Width
TAVLL
Min
Max
Variable Clock
X2 Mode
Min
Max
Unit
50
50
ns
2·TCLCL-15
TCLCL-15
ns
Address Valid to ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLAX
Address hold after ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLRL
ALE Low to RD Low
3·TCLCL-30
1.5·TCLCL-30
ns
25
4109LS–8051–02/08
Variable Clock
Standard Mode
Symbol
Parameter
TRLRH
RD Pulse Width
TRHLH
RD high to ALE High
TAVDV
Address Valid to Valid Data In
TAVRL
Address Valid to RD Low
TRLDV
RD Low to Valid Data
TRLAZ
RD Low to Address Float
TRHDX
Data Hold After RD High
TRHDZ
Data Float After RD High
Min
Max
6·TCLCL-25
TCLCL-20
Variable Clock
X2 Mode
Min
Max
3·TCLCL-25
TCLCL+20
0.5·TCLCL-20
9·TCLCL-65
4·TCLCL-30
Unit
ns
0.5·TCLCL+20
ns
4.5·TCLCL-65
ns
2·TCLCL-30
ns
5·TCLCL-30
2.5·TCLCL-30
ns
0
0
ns
0
0
2·TCLCL-25
ns
TCLCL-25
ns
Table 28. External Data 8-bit Bus Cycle - Write AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Variable Clock
Standard Mode
Symbol
26
Parameter
TCLCL
Clock Period
TLHLL
ALE Pulse Width
TAVLL
Min
Max
Variable Clock
X2 Mode
Min
Max
Unit
50
50
ns
2·TCLCL-15
TCLCL-15
ns
Address Valid to ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLAX
Address hold after ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLWL
ALE Low to WR Low
3·TCLCL-30
1.5·TCLCL-30
ns
TWLWH
WR Pulse Width
6·TCLCL-25
3·TCLCL-25
ns
TWHLH
WR High to ALE High
TAVWL
Address Valid to WR Low
4·TCLCL-30
2·TCLCL-30
ns
TQVWH
Data Valid to WR High
7·TCLCL-20
3.5·TCLCL-20
ns
TWHQX
Data Hold after WR High
TCLCL-15
0.5·TCLCL-15
ns
TCLCL-20
TCLCL+20
0.5·TCLCL-20
0.5·TCLCL+20
ns
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
7.3.2.3
Waveforms
Figure 7-10. External Data 8-bit Bus Cycle - Read Waveforms
ALE
TLHLL
TLLRL
TRLRH
TRHLH
RD
TRLDV
TRHDZ
TRLAZ
TAVLL
P0
TLLAX
TRHDX
A7:0
D7:0
TAVRL
Data In
TAVDV
P2
A15:8
Figure 7-11. External Data 8-bit Bus Cycle - Write Waveforms
ALE
TLHLL
TLLWL
TWLWH
TWHLH
WR
TAVWL
TAVLL
P0
TLLAX
TQVWH
A7:0
TWHQX
D7:0
Data Out
P2
7.3.3
7.3.3.1
A15:8
External IDE 16-bit Bus Cycles
Definition of Symbols
Table 29. External IDE 16-bit Bus Cycles Timing Symbol Definitions
Signals
Conditions
A
Address
H
High
D
Data In
L
Low
L
ALE
V
Valid
Q
Data Out
X
No Longer Valid
R
RD
Z
Floating
W
WR
27
4109LS–8051–02/08
7.3.3.2
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 30. External IDE 16-bit Bus Cycle - Data Read AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Variable Clock
Standard Mode
Symbol
Parameter
TCLCL
Clock Period
TLHLL
ALE Pulse Width
TAVLL
Min
Max
Variable Clock
X2 Mode
Min
Max
Unit
50
50
ns
2·TCLCL-15
TCLCL-15
ns
Address Valid to ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLAX
Address hold after ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLRL
ALE Low to RD Low
3·TCLCL-30
1.5·TCLCL-30
ns
TRLRH
RD Pulse Width
6·TCLCL-25
3·TCLCL-25
ns
TRHLH
RD high to ALE High
TAVDV
Address Valid to Valid Data In
TAVRL
Address Valid to RD Low
TRLDV
RD Low to Valid Data
TRLAZ
RD Low to Address Float
TRHDX
Data Hold After RD High
TRHDZ
Data Float After RD High
TCLCL-20
TCLCL+20
0.5·TCLCL-20
9·TCLCL-65
4·TCLCL-30
0.5·TCLCL+20
ns
4.5·TCLCL-65
ns
2·TCLCL-30
ns
5·TCLCL-30
2.5·TCLCL-30
ns
0
0
ns
0
0
2·TCLCL-25
ns
TCLCL-25
ns
Table 31. External IDE 16-bit Bus Cycle - Data Write AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Variable Clock
Standard Mode
Symbol
28
Parameter
TCLCL
Clock Period
TLHLL
ALE Pulse Width
TAVLL
Min
Max
Variable Clock
X2 Mode
Min
Max
Unit
50
50
ns
2·TCLCL-15
TCLCL-15
ns
Address Valid to ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLAX
Address hold after ALE Low
TCLCL-20
0.5·TCLCL-20
ns
TLLWL
ALE Low to WR Low
3·TCLCL-30
1.5·TCLCL-30
ns
TWLWH
WR Pulse Width
6·TCLCL-25
3·TCLCL-25
ns
TWHLH
WR High to ALE High
TAVWL
Address Valid to WR Low
4·TCLCL-30
2·TCLCL-30
ns
TQVWH
Data Valid to WR High
7·TCLCL-20
3.5·TCLCL-20
ns
TWHQX
Data Hold after WR High
TCLCL-15
0.5·TCLCL-15
ns
TCLCL-20
TCLCL+20
0.5·TCLCL-20
0.5·TCLCL+20
ns
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
7.3.3.3
Waveforms
Figure 7-12. External IDE 16-bit Bus Cycle - Data Read Waveforms
ALE
TLHLL
TLLRL
TRLRH
TRHLH
RD
TRLDV
TRHDZ
TRLAZ
TAVLL
P0
TLLAX
TRHDX
A7:0
D7:0
TAVRL
Data In
TAVDV
P2
D15:8(1)
A15:8
Data In
Note:
1. D15:8 is written in DAT16H SFR.
Figure 7-13. External IDE 16-bit Bus Cycle - Data Write Waveforms
ALE
TLHLL
TLLWL
TWLWH
TWHLH
WR
TAVWL
TAVLL
P0
TLLAX
TQVWH
A7:0
TWHQX
D7:0
Data Out
P2
A15:8
D15:8(1)
Data Out
Note:
7.4
7.4.0.4
1. D15:8 is the content of DAT16H SFR.
SPI Interface
Definition of Symbols
Table 32. SPI Interface Timing Symbol Definitions
Signals
Conditions
C
Clock
H
High
I
Data In
L
Low
O
Data Out
V
Valid
X
No Longer Valid
Z
Floating
29
4109LS–8051–02/08
7.4.0.5
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 33. SPI Interface Master AC Timing
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Parameter
Min
Max
Unit
Slave Mode
TCHCH
Clock Period
2
TPER
TCHCX
Clock High Time
0.8
TPER
TCLCX
Clock Low Time
0.8
TPER
TSLCH, TSLCL
SS Low to Clock edge
100
ns
TIVCL, TIVCH
Input Data Valid to Clock Edge
40
ns
TCLIX, TCHIX
Input Data Hold after Clock Edge
40
ns
TCLOV, TCHOV
Output Data Valid after Clock Edge
TCLOX, TCHOX
Output Data Hold Time after Clock Edge
0
ns
TCLSH, TCHSH
SS High after Clock Edge
0
ns
TSLOV
SS Low to Output Data Valid
50
ns
TSHOX
Output Data Hold after SS High
50
ns
TSHSL
SS High to SS Low
TILIH
Input Rise Time
2
µs
TIHIL
Input Fall Time
2
µs
TOLOH
Output Rise time
100
ns
TOHOL
Output Fall Time
100
ns
40
ns
(1)
Master Mode
Note:
30
TCHCH
Clock Period
2
TPER
TCHCX
Clock High Time
0.8
TPER
TCLCX
Clock Low Time
0.8
TPER
TIVCL, TIVCH
Input Data Valid to Clock Edge
20
ns
TCLIX, TCHIX
Input Data Hold after Clock Edge
20
ns
TCLOV, TCHOV
Output Data Valid after Clock Edge
TCLOX, TCHOX
Output Data Hold Time after Clock Edge
TILIH
Input Data Rise Time
2
µs
TIHIL
Input Data Fall Time
2
µs
TOLOH
Output Data Rise time
50
ns
TOHOL
Output Data Fall Time
50
ns
40
0
ns
ns
1. Value of this parameter depends on software.
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
7.4.0.6
Waveforms
Figure 7-14. SPI Slave Waveforms (SSCPHA= 0)
SS
(input)
TSLCH
TSLCL
TCHCH
SCK
(SSCPOL= 0)
(input)
TCHCX
TSHSL
TCLCX
TCHCL
SCK
(SSCPOL= 1)
(input)
TCLOX
TCHOX
TCLOV
TCHOV
TSLOV
MISO
(output)
TCLCH
TCLSH
TCHSH
SLAVE MSB OUT
BIT 6
TSHOX
SLAVE LSB OUT
(1)
TIVCH TCHIX
TIVCL TCLIX
MOSI
(input)
Note:
MSB IN
BIT 6
LSB IN
1. Not Defined but generally the MSB of the character which has just been received.
Figure 7-15. SPI Slave Waveforms (SSCPHA= 1)
SS
(input)
TSLCH
TSLCL
SCK
(SSCPOL= 0)
(input)
TCHCH
TCHCX
TSHSL
TCLCX
TCHCL
SCK
(SSCPOL= 1)
(input)
TCHOV
TCLOV
TSLOV
MISO
(output)
TCLCH
TCLSH
TCHSH
(1)
SLAVE MSB OUT
BIT 6
TCHOX
TCLOX
TSHOX
SLAVE LSB OUT
TIVCH TCHIX
TIVCL TCLIX
MOSI
(input)
Note:
MSB IN
BIT 6
LSB IN
1. Not Defined but generally the LSB of the character which has just been received.
31
4109LS–8051–02/08
Figure 7-16. SPI Master Waveforms (SSCPHA= 0)
SS
(output)
TCHCH
SCK
(SSCPOL= 0)
(output)
TCHCX
TCLCH
TCLCX
TCHCL
SCK
(SSCPOL= 1)
(output)
TIVCH TCHIX
TIVCL TCLIX
MOSI
(input)
MSB IN
BIT 6
LSB IN
TCLOX
TCLOV
TCHOV
MISO
(output)
Note:
Port Data
MSB OUT
TCHOX
BIT 6
LSB OUT
Port Data
1. SS handled by software using general purpose port pin.
Figure 7-17. SPI Master Waveforms (SSCPHA= 1)
SS(1)
(output)
TCHCH
SCK
(SSCPOL= 0)
(output)
TCHCX
TCLCH
TCLCX
TCHCL
SCK
(SSCPOL= 1)
(output)
TIVCH TCHIX
TIVCL TCLIX
MOSI
(input)
MISO
(output)
Note:
7.4.1
7.4.1.1
MSB IN
BIT 6
TCLOV
TCLOX
TCHOX
TCHOV
Port Data
MSB OUT
BIT 6
LSB IN
LSB OUT
Port Data
1. SS handled by software using general purpose port pin.
Two-wire Interface
Timings
Table 34. TWI Interface AC Timing
32
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
INPUT
Min
Max
OUTPUT
Min
Max
Start condition hold time
14·TCLCL(4)
4.0 µs(1)
TLOW
SCL low time
16·TCLCL(4)
4.7 µs(1)
THIGH
SCL high time
14·TCLCL(4)
4.0 µs(1)
TRC
SCL rise time
1 µs
-(2)
TFC
SCL fall time
0.3 µs
0.3 µs(3)
TSU; DAT1
Data set-up time
250 ns
20·TCLCL(4)- TRD
TSU; DAT2
SDA set-up time (before repeated START condition)
250 ns
1 µs(1)
TSU; DAT3
SDA set-up time (before STOP condition)
250 ns
8·TCLCL(4)
THD; DAT
Data hold time
0 ns
8·TCLCL(4) - TFC
TSU; STA
Repeated START set-up time
14·TCLCL(4)
4.7 µs(1)
TSU; STO
STOP condition set-up time
14·TCLCL(4)
4.0 µs(1)
TBUF
Bus free time
14·TCLCL(4)
4.7 µs(1)
TRD
SDA rise time
1 µs
-(2)
TFD
SDA fall time
0.3 µs
0.3 µs(3)
Symbol
THD; STA
Notes:
7.4.1.2
Parameter
1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this
must be < 1 µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered out. Maximum capacitance on bus-lines SDA and
SCL= 400 pF.
4. TCLCL= TOSC= one oscillator clock period.
Waveforms
Figure 7-18. Two Wire Waveforms
Repeated START condition
START or Repeated START condition
START condition
STOP condition
Trd
Tsu;STA
0.7 VDD
0.3 VDD
SDA
(INPUT/OUTPUT)
Tsu;STO
Tfd
Trc
Tfc
Tbuf
Tsu;DAT3
0.7 VDD
0.3 VDD
SCL
(INPUT/OUTPUT)
Thd;STA
Tlow Thigh Tsu;DAT1
Thd;DAT
Tsu;DAT2
33
4109LS–8051–02/08
7.4.2
7.4.2.1
MMC Interface
Definition of symbols
Table 35. MMC Interface Timing Symbol Definitions
Signals
7.4.2.2
Conditions
C
Clock
H
High
D
Data In
L
Low
O
Data Out
V
Valid
X
No Longer Valid
Timings
Table 36. MMC Interface AC timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C, CL ≤ 100pF (10 cards)
Symbol
7.4.2.3
Parameter
Min
Max
Unit
TCHCH
Clock Period
50
ns
TCHCX
Clock High Time
10
ns
TCLCX
Clock Low Time
10
ns
TCLCH
Clock Rise Time
10
ns
TCHCL
Clock Fall Time
10
ns
TDVCH
Input Data Valid to Clock High
3
ns
TCHDX
Input Data Hold after Clock High
3
ns
TCHOX
Output Data Hold after Clock High
5
ns
TOVCH
Output Data Valid to Clock High
5
ns
Waveforms
Figure 7-19. MMC Input-Output Waveforms
TCHCH
TCHCX
TCLCX
MCLK
TCHCL
TCHIX
TCLCH
TIVCH
MCMD Input
MDAT Input
TCHOX
TOVCH
MCMD Output
MDAT Output
34
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
7.4.3
7.4.3.1
Audio Interface
Definition of symbols
Table 37. Audio Interface Timing Symbol Definitions
Signals
7.4.3.2
Conditions
C
Clock
H
High
O
Data Out
L
Low
S
Data Select
V
Valid
X
No Longer Valid
Timings
Table 38. Audio Interface AC timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C, CL≤ 30pF
Symbol
Note:
7.4.3.3
Parameter
Min
Max
Unit
325.5(1)
ns
TCHCH
Clock Period
TCHCX
Clock High Time
30
ns
TCLCX
Clock Low Time
30
ns
TCLCH
Clock Rise Time
10
ns
TCHCL
Clock Fall Time
10
ns
TCLSV
Clock Low to Select Valid
10
ns
TCLOV
Clock Low to Data Valid
10
ns
1. 32-bit format with Fs= 48 KHz.
Waveforms
Figure 7-20. Audio Interface Waveforms
TCHCH
TCHCX
TCLCX
DCLK
TCHCL
TCLCH
TCLSV
DSEL
Right
Left
TCLOV
DDAT
35
4109LS–8051–02/08
7.4.4
7.4.4.1
Analog to Digital Converter
Definition of symbols
Table 39. Analog to Digital Converter Timing Symbol Definitions
Signals
7.4.4.2
Conditions
C
Clock
H
High
E
Enable (ADEN bit)
L
Low
S
Start Conversion
(ADSST bit)
Characteristics
Table 40. Analog to Digital Converter AC Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Notes:
36
Parameter
TCLCL
Clock Period
TEHSH
Start-up Time
TSHSL
Min
Max
4
Unit
µs
4
µs
Conversion Time
11·TCLCL
µs
DLe
Differential nonlinearity error(1)(2)
1
LSB
ILe
Integral nonlinearity errorss(1)(3)
2
LSB
OSe
Offset error(1)(4)
4
LSB
Ge
Gain error(1)(5)
4
LSB
1. AVDD= AVREFP= 3.0 V, AVSS= AVREFN= 0 V. ADC is monotonic with no missing code.
2. The differential non-linearity is the difference between the actual step width and the ideal step
width (see Figure 7-22).
3. The integral non-linearity is the peak difference between the center of the actual step and the
ideal transfer curve after appropriate adjustment of gain and offset errors (see Figure 7-22).
4. The offset error is the absolute difference between the straight line which fits the actual transfer curve (after removing of gain error), and the straight line which fits the ideal transfer curve
(see Figure 7-22).
5. The gain error is the relative difference in percent between the straight line which fits the actual
transfer curve (after removing of offset error), and the straight line which fits the ideal transfer
curve (see Figure 7-22).
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
7.4.4.3
Waveforms
Figure 7-21. Analog to Digital Converter Internal Waveforms
CLK
TCLCL
ADEN Bit
TEHSH
ADSST Bit
TSHSL
Figure 7-22. Analog to Digital Converter Characteristics
Offset Gain
Error Error
OSe
Ge
Code Out
1023
1022
1021
1020
1019
1018
Ideal Transfer curve
7
Example of an actual transfer curve
6
5
Center of a step
4
Integral non-linearity (ILe)
3
Differential non-linearity (DLe)
2
1
0
0
1 LSB
(ideal)
1
2
3
4
5
6
7
1018 1019 1020 1021 1022 1023 1024
AVIN
(LSB ideal)
Offset
Error OSe
37
4109LS–8051–02/08
7.4.5
7.4.5.1
Flash Memory
Definition of symbols
Table 41. Flash Memory Timing Symbol Definitions
Signals
7.4.5.2
Conditions
S
ISP
L
Low
R
RST
V
Valid
B
FBUSY flag
X
No Longer Valid
Timings
Table 42. Flash Memory AC Timing
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
7.4.5.3
Parameter
Min
Typ
Max
Unit
TSVRL
Input ISP Valid to RST Edge
50
ns
TRLSX
Input ISP Hold after RST Edge
50
ns
TBHBL
FLASH Internal Busy (Programming) Time
NFCY
Number of Flash Write Cycles
TFDR
Flash Data Retention Time
10
ms
100K
Cycle
10
Years
Waveforms
Figure 7-23. FLASH Memory - ISP Waveforms
RST
TSVRL
ISP
Note:
TRLSX
(1)
1. ISP must be driven through a pull-down resistor (see Section “In System Programming”,
page 23).
Figure 7-24. FLASH Memory - Internal Busy Waveforms
FBUSY bit
38
TBHBL
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
7.4.6
7.4.6.1
External Clock Drive and Logic Level References
Definition of symbols
Table 43. External Clock Timing Symbol Definitions
Signals
C
7.4.6.2
Conditions
Clock
H
High
L
Low
X
No Longer Valid
Timings
External Clock AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Parameter
Max
Unit
TCLCL
Clock Period
50
ns
TCHCX
High Time
10
ns
TCLCX
Low Time
10
ns
TCLCH
Rise Time
3
ns
TCHCL
Fall Time
3
ns
Cyclic Ratio in X2 mode
40
TCR
7.4.6.3
Min
60
%
Waveforms
Figure 7-25. External Clock Waveform
TCLCH
VDD - 0.5
VIH1
TCHCX
TCLCX
VIL
0.45 V
TCHCL
TCLCL
Figure 7-26. AC Testing Input/Output Waveforms
INPUTS
VDD - 0.5
0.45 V
Note:
OUTPUTS
0.7 VDD
VIH min
0.3 VDD
VIL max
1. During AC testing, all inputs are driven at VDD -0.5 V for a logic 1 and 0.45 V for a logic 0.
2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0.
Figure 7-27. Float Waveforms
VLOAD
VLOAD + 0.1 V
VLOAD - 0.1 V
Timing Reference Points
VOH - 0.1 V
VOL + 0.1 V
39
4109LS–8051–02/08
Note:
40
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loading VOH/VOL level occurs with
IOL/IOH= ±20 mA.
AT8xC51SND1C
4109LS–8051–02/08
AT8xC51SND1C
8. Ordering Information
Part Number
Memory
Size
Supply
Voltage
Temperature
Range
Max
Frequency
Package(2)
Packing
Product
Marking
AT89C51SND1C-ROTIL
AT89C51SND1C-7HTIL
AT89C51SND1C-DDV
AT83SND1Cxxx(1)-ROTIL
AT83SND1Cxxx(1)-7HTIL
OBSOLETE
AT83SND1Cxxx-DDV
AT80C51SND1C-ROTIL
AT80C51SND1C-7HTIL
AT80C51SND1C-DDV
Industrial &
Green
40 MHz
TQFP80
Tray
89C51SND1C-IL
3V
Industrial
40 MHz
BGA81
Tray
89C51SND1C-IL
40 MHz
TQFP80
Tray
89C51SND1C-IL
AT89C51SND1C-ROTUL
64K Flash
3V
AT89C51SND1C-7HTJL
64K Flash
AT83SND1Cxxx(1)-ROTUL
64K ROM
3V
Industrial &
Green
AT83SND1Cxxx(1)-7HTJL
64K ROM
3V
Industrial &
Green
40 MHz
BGA81
Tray
89C51SND1C-IL
AT80C51SND1C-ROTUL
ROMless
3V
Industrial &
Green
40 MHz
TQFP80
Tray
89C51SND1C-IL
AT80C51SND1C-7HTJL
ROMless
3V
Industrial &
Green
40 MHz
BGA81
Tray
89C51SND1C-IL
Notes:
1. Refers to ROM code.
2. PLCC84 package only available for development board.
41
4109LS–8051–02/08
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4109LS–8051–02/08
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