AT17F16 FPGA Configuration Flash Memory DATASHEET Features Programmable 16,777,216 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) 3.3V Output Capability 5.0V Tolerant I/O Pins Program Support using the Atmel ATDH2200E System, ATDH2225 ISP Cable, or Third-party Programmers In-System Programmable (ISP) via 2-wire Bus Simple Interface to SRAM FPGAs Compatible with Atmel AT40K and AT94K Devices, Altera® FLEX®, APEX™ Devices, Lucent® ORCA® FPGAs, Xilinx® XC3000, XC4000, XC5200, Spartan®, Virtex® FPGAs, Motorola® MPA1000 FPGAs Cascadable Read-back to Support Additional Configurations or Higher-density Arrays Low-power CMOS FLASH Process Available in 8-pad LAP (Pin-compatible with 8-lead SOIC/VOIC Footprint Packages) and 20-lead PLCC Packages Emulation of the Atmel AT24C Serial EEPROMs Low-power Standby Mode Single Device Capable of Holding Four Bitstream Files Allowing Simple System Reconfiguration Fast Serial Download Speeds up to 33MHz Endurance: 10,000 Write Cycles Typical Green (Pb/Halide-free/RoHS Compliant) Packages Description The Atmel® AT17F16 In-System Programmable Configuration PROMs (Configurators) provide an easy-to-use, cost-effective configuration memory solutions for FPGAs. The AT17F16 is packaged in the 8-pad LAP and 20-lead PLCC packages (Table 1). The AT17F16 uses a simple serial-access procedure to configure one or more FPGA devices. The AT17F16 can be programmed with industry-standard programmers, the Atmel ATDH2200E Programming Kit, or the Atmel ATDH2225 ISP Cable. Table 1. AT17F16 Packages Package AT17F16 8-pad LAP Yes 20-lead PLCC Yes Atmel-3392G-CNFG-AT17F16-Datasheet_012015 1. Pin Configurations Table 1-1. Pin Description DATA(1) Three-state DATA output for FPGA Configuration. Open-collector bi-directional pin for configuration programming. CLK(1) Clock Input. Used to increment the internal address and bit counter for reading and programming. PAGE_EN(2) Enable Page Download Mode Input. When PAGE_EN is high, the configuration download address space is partitioned into four equal pages. This gives users the ability to easily store and retrieve multiple configuration bitstreams from a single configuration device. This input works in conjunction with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired. When SER_EN is Low (ISP mode) this pin has no effect. PAGESEL[1:0](2) Page Select Inputs. Used to determine which of the four memory pages are targeted during a serial configuration download. The address space for each of the pages is shown in Table 1-2. When SER_EN is Low (ISP mode) these pins have no effect. RESET/OE(1) Output Enable (Active High) and RESET (Active Low) when SER_EN is High. A Low level on RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data output driver. CE(1) Chip Enable Input (Active Low). A Low level (with OE High) allows CLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the 2-wire Serial Programming mode (SER_EN Low). GND Ground. A 0.2μF decoupling capacitor between VCC and GND is recommended. CEO Chip Enable Output (when SER_EN is High). This output goes Low when the internal address counter has reached its maximum value. If the PAGE_EN input is set High, the maximum value is the highest address in the selected partition. The PAGESEL[1:0] inputs are used to make the four partition selections. If the PAGE_EN input is set Low, the device is not partitioned and the address maximum value is the highest address in the device (Table 1-2). In a daisy chain of AT17F Series devices, the CEO pin of one device must be connected to the CE input of the next device in the chain. It will stay Low as long as CE is Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay High until the entire EEPROM is read again. A2(1) Device Selection Input, (when SER_EN Low). The input is used to enable (or chip select) the device during programming (i.e., when SER_EN is Low). Refer to the AT17F(A) Programming Specification available at www.atmel.com for additional details. READY Open Collector Reset State Indicator. Driven Low during power-up reset, released when power-up is complete. (Recommend 4.7k pull-up on this pin if used). SER_EN(1) Serial Enable Input. Must remain High during FPGA configuration operations. Bringing SER_EN Low enables the 2-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC. VCC Device Power Supply. +3.3V (±10%) Notes: 2 Pin Descriptions 1. 2. Internal 20K pull-up resistor Internal 30K pull-up resistor AT17F16 [DATASHEET] Atmel-3392G-CNFG-AT17F16-Datasheet_012015 Table 1-2. Address Space PAGESEL[1:0] Paging Decodes AT17F16 (16Mb) PAGESEL = 00, PAGE_EN = 1 00000 – 3FFFFh PAGESEL = 01, PAGE_EN = 1 40000 – 7FFFFh PAGESEL = 10, PAGE_EN = 1 80000 – BFFFFh PAGESEL = 11, PAGE_EN = 1 C0000 – FFFFFh PAGESEL = XX, PAGE_EN = 0 00000 – FFFFFh Table 1-3. Pin Configurations Name I/O 8-pad LAP 20-lead PLCC DATA I/O 1 2 CLK I 2 4 PAGE_EN I — 16 PAGESEL0 I — 11 PAGESEL1 I — 7 RESET/OE I 3 6 CE I 4 8 GND — 5 10 CEO O 6 14 A2 I 6 14 READY O – 15 SER_EN I 7 17 — 8 20 VCC Figure 1-1. Pinouts NC VCC NC 19 4 18 NC NC 5 17 SER_EN RESET/OE 6 16 PAGE_EN PAGESEL1 7 15 READY CE 8 14 CEO (A2) 13 Drawings are not to scale. CLK NC Note: 20 GND 12 5 NC 4 DATA CE 1 CEO (A2) 11 6 PAGESEL0 3 10 SER_EN RESET/OE 9 7 1 NC VCC 2 GND 8 CLK DATA NC (Top View) 2 20-lead PLCC (Top View) 3 8-pad LAP AT17F16 [DATASHEET] Atmel-3392G-CNFG-AT17F16-Datasheet_012015 3 2. Block Diagram Figure 2-1. READY PAGE_EN PAGESEL0 PAGESEL1 Block Diagram Power-on Reset Reset Clock/Oscillator Logic CEO (A2) Configuration Page Select Serial Download Logic 2-wire Serial Programming Flash Memory CLK CE/WE/OE Data Address DATA CE Control Logic RESET/OE SER_EN 4 AT17F16 [DATASHEET] Atmel-3392G-CNFG-AT17F16-Datasheet_012015 3. Device Description The control signals for the configuration memory device (CE, RESET/OE and CLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration device without requiring an external intelligent controller. The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven Low, the configuration device resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the AT17F16. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE. When the configurator has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset. 4. FPGA Master Serial Mode Summary The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory. The AT17F16 Serial Configuration PROM has been designed for compatibility with the Master Serial mode. This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xilinx applications. 5. Control of Configuration Most connections between the FPGA device and the AT17F16 Serial Configurator PROM are simple and selfexplanatory. 6. The DATA output of the AT17F16 Configurator drives DIN of the FPGA devices. The master FPGA CCLK output drives the CLK input of the AT17F16 Configurator. The CEO output of any AT17F16 Configurator drives the CE input of the next Configurator in a cascade chain of configurator devices. SER_EN must be connected to VCC or allowed to float to logic High via the internal pull-up resistor (except during ISP). The READY pin is available as an open-collector indicator of the device’s reset status; it is driven Low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete. PAGE_EN must be held Low if download paging is not desired. The PAGESEL[1:0] inputs must be tied off High or Low. If paging is desired, PAGE_EN must be High and the PAGESEL pins must be set to High or Low such that the desired page is selected, see Table 1-2. Cascading Serial Configuration Devices For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded configurators provide additional memory. After the last bit from the first configurator is read, the clock signal to the configurator asserts its CEO output Low and disables its DATA line driver. The second configurator recognizes the Low level on its CE input and enables its DATA output. After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE on each configurator is driven to its active (Low) level. If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to its inactive (High) level. AT17F16 [DATASHEET] Atmel-3392G-CNFG-AT17F16-Datasheet_012015 5 7. Programming Mode The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. The AT17F16 is read/write at 3.3V nominal. Refer to the AT17F16(A) Programming Specification available on www.atmel.com for more programming details. The AT17F16 is supported by the Atmel ATDH2200E programming system along with many third party programmers. 8. Standby Mode The AT17F16 enters a low-power standby mode whenever SER_EN is High and CE is asserted High. In this mode, the AT17F16 consumes less than 2mA of current at 3.6V. The output remains in a high-impedance state regardless of the state of the OE input. 6 AT17F16 [DATASHEET] Atmel-3392G-CNFG-AT17F16-Datasheet_012015 9. Electrical Specifications 9.1 Absolute Maximum Ratings* Operating Temperature . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C Voltage on Any Pin with Respect to Ground . . . . . . . . . . . . . . . . .-0.1V to VCC +0.5V Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.0V Maximum Soldering Temp. (10 sec. @ 1/16in.) . . . . . . . . .260C ESD (RZAP = 1.5K, CZAP = 100pF) . . . . . . . . . . . . . . . . . . 2000V 9.2 Operating Conditions Table 9-1. 9.3 *Notice: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Operating Conditions Symbol Description Min Max Units VCC Supply voltage relative to GND -40C to +85C 2.97 3.63 V DC Characteristics Table 9-2. DC Characteristics Symbol Description Min Max Units VIH High-level Input Voltage 2.0 VCC V VIL Low-level Input Voltage 0 0.8 V VOH High-level Output Voltage (IOH = -2.5mA) VOL Low-level Output Voltage (IOL = +3.0mA) VOH High-level Output Voltage (IOH = -2.0mA) VOL Low-level Output Voltage (IOL = +3.0mA) 0.4 V ICCA Supply Current, Active Mode (3.6V 33MHz) 40 mA IL Input or Output Leakage Current (VIN = VCC or GND) 10 μA ICCS Supply Current, Standby Mode 2 mA 2.4 V 0.4 2.4 -10 V V AT17F16 [DATASHEET] Atmel-3392G-CNFG-AT17F16-Datasheet_012015 7 9.4 AC Characteristics Table 9-3. Symbol Description TOE(1) Max Units OE to Data Delay 55 ns TCE(1) CE to Data Delay 60 ns TCAC(1) CLK to Data Delay 30 ns TOH Data Hold from CE, OE, or CLK TDF (2) Min Typ 0 ns CE or OE to Data Float Delay 15 ns TLC CLK Low Time 15 ns THC CLK High Time 15 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 25 ns THCE CE Hold Time from CLK (to guarantee proper counting) 0 ns THOE RESET/OE Low Time (guarantees counter is reset) 20 ns FMAX Maximum Input Clock Frequency SEREN = 0 10 MHz FMAX Maximum Input Clock Frequency SEREN = 1 33 MHz (3) TWR Write Cycle Time TEC Erase Cycle Time(3) Notes: 1. 2. 3. Table 9-4. 12 μs 33 s AC test lead = 50pF. Float delays are measured with 5pF AC loads. Transition is measured ±200mV from steady-state active levels. See the AT17F(A) Programming Specification for procedural information. AC Characteristics When Cascading Symbol Description Max Units TCDF(2) CLK to Data Float Delay 50 ns TOCK(1) CLK to CEO Delay 55 ns TOCE(1) CE to CEO Delay 40 ns TOOE(1) RESET/OE to CEO Delay 35 ns FMAX Maximum Input Clock Frequency 33 MHz Notes: 8 AC Characteristics 1. 2. Min AC test load = 50pF. Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels. AT17F16 [DATASHEET] Atmel-3392G-CNFG-AT17F16-Datasheet_012015 Figure 9-1. AC Waveforms CE TSCE TSCE THCE RESET/OE TLC THOE THC CLK TOE TOH TCAC TDF TCE DATA TOH Figure 9-2. AC Waveforms when Cascading RESET/OE CE CLK TCDF DATA FIRST BIT LAST BIT TOCK TOCE TOOE CEO TOCE AT17F16 [DATASHEET] Atmel-3392G-CNFG-AT17F16-Datasheet_012015 9 10. Ordering Information 10.1 Ordering Code Detail AT 1 7 F 1 6 - 3 0 C U Package Device Grade Atmel Designator U = Green, Sn Lead Finish Industrial Temperature Range (-40°C to +85°C) Product Family 17F = FPGA Flash Configuration Memory Package Option Device Density C = 8-pad LAP J = 20-lead PLCC 16 = 16 megabit Product Variation 30 = Default Value 10.2 Ordering Codes Memory Size 16-Mbit Atmel Ordering Code Lead Finish Package AT17F16-30CU Sn (Lead-free/Halogen-free) 8CN4 AT17F16-30JU 20J Package Type 10 8CN4 8-pad, 6.00mm x 6.00mm x 1.04mm, Leadless Array Package (LAP) Pin-compatible with 8-lead SOIC/VOIC Packages 20J 20-lead, Plastic J-leaded Chip Carrier (PLCC) AT17F16 [DATASHEET] Atmel-3392G-CNFG-AT17F16-Datasheet_012015 Voltage Operation Range 3.3V Industrial (-40C to 85C) 11. Packaging Information 11.1 8CN4 — 8-pad LAP Marked Pin1 Indentifier E A A1 D Side View Top View Pin1 Corner L1 0.10 mm TYP 8 1 e 7 2 COMMON DIMENSIONS (Unit of Measure = mm) 3 6 b 5 4 e1 L Bottom View SYMBOL MIN TYP MAX A 0.94 1.04 1.14 A1 0.30 0.34 0.38 D 5.89 5.99 6.09 E 5.89 5.99 6.09 e 1.27 BSC e1 Note: 1. Metal Pad Dimensions. 2. All exposed metal area shall have the following finished platings. Ni: 0.0005 to 0.015 mm Au: 0.0005 to 0.001 mm NOTE 1.10 REF L 0.95 1.00 1.05 1 L1 1.25 1.30 1.35 1 b 0.45 0.50 0.55 1 12/22/14 Package Drawing Contact: [email protected] TITLE GPC DRAWING NO. REV. 8CN4, 8-pad 6x6x1.04mm Body, 1.27mm pitch Leadless Array Package (LAP) DMH 8CN4 E AT17F16 [DATASHEET] Atmel-3392G-CNFG-AT17F16-Datasheet_012015 11 11.2 20J — 20-lead PLCC PIN NO. 1 1.14(0.045) X 45° 1.14(0.045) X 45° 0.318(0.0125) 0.191(0.0075) IDENTIFIER e E1 E D2/E2 B1 B A2 D1 A1 D A 0.51(0.020)MAX 45° MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102mm) maximum SYMBOL MIN NOM MAX A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 9.779 – 10.033 D1 8.890 – 9.042 E 9.779 – 10.033 E1 8.890 – 9.042 D2/E2 7.366 – 8.382 B 0.660 – 0.813 B1 0.330 – 0.533 e NOTE Note 2 Note 2 1.270 TYP 10/04/01 Package Drawing Contact: [email protected] 12 AT17F16 [DATASHEET] Atmel-3392G-CNFG-AT17F16-Datasheet_012015 TITLE 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. REV. 20J B 12. Revision History Doc Rev Date Comments Removed commercial and 32-lead TQFP package options. 3392G 01/2015 Updated the 8CN4 package outline drawing, template, Atmel logos, and disclaimer page. Added an ordering code detail. 3392F 02/2008 3392E 08/2007 3392D 03/2006 Removed -30JC, -30JI, -30BJC and -30BJI devices from ordering information. Removed -30CC and -30CI devices from ordering information. Announced last-time buy for -30JC, -30BJC, -30JI, and -30BJI devices. Added last-time buy for AT17F16-30CC and AT17F16-30CI. AT17F16 [DATASHEET] Atmel-3392G-CNFG-AT17F16-Datasheet_012015 13 XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2015 Atmel Corporation. / Rev.: Atmel-3392G-CNFG-AT17F16-Datasheet_012015. Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. 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