ATF1508AS(L) - Datasheet

Features
• High-density, High-performance, Electrically-erasable Complex
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Programmable Logic Device
– 128 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 84, 100, 160 Pins
– 7.5 ns Maximum Pin-to-pin Delay
– Registered Operation up to 125 MHz
– Enhanced Routing Resources
Flexible Logic Macrocell
– D/T/Latch Configured Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register within a COM Output
Advanced Power Management Features
– Automatic 10 µA Standby for “L” Version
– Pin-controlled 1 mA Standby Mode
– Programmable Pin-keeper Inputs and I/Os
– Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 84-lead PLCC, 100-lead PQFP, 100-lead TQFP and 160-lead PQFP Packages
Advanced EE Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
Fast In-System Programmability (ISP) via JTAG
PCI-compliant
3.3 or 5.0V I/O Pins
Security Fuse Feature
Green (Pb/Halide-free/RoHS Compliant) Package Options
Highperformance
EE PLD
ATF1508AS
ATF1508ASL
Enhanced Features
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Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
Transparent-latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
VCC Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
– Edge-controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts
Rev. 0784P–PLD–7/05
1
100-lead PQFP
Top View
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I/O
I/O
I/O/PD1
I/O
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
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I/O
I/O
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD2
I/O
GND
I/O
I/O
I/O
I/O
I/O
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I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD2
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O/PD1
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
GND
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I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
84-lead PLCC
Top View
160-lead PQFP
Top View
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD2
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
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N/C
N/C
N/C
N/C
N/C
N/C
GND
I/O/TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O/TCK
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N/C
N/C
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N/C
N/C
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N/C
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I/O/PD1
I/O
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N/C
N/C
N/C
N/C
N/C
N/C
N/C
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O/TMS
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N/C
N/C
N/C
N/C
N/C
N/C
N/C
I/O
GND
I/O
N/C
N/C
N/C
N/C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD1
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N/C
N/C
N/C
N/C
I/O
VCCIO
I/O
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I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O/PD2
I/O
N/C
N/C
N/C
N/C
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
N/C
N/C
N/C
N/C
I/O
I/O
I/O
100-lead TQFP
Top View
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
Block Diagram
8 to 12
16
3
0784P–PLD–7/05
Description
The ATF1508AS is a high-performance, high-density complex programmable logic device
(CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 128 logic macrocells
and up to 100 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic
PLDs. The ATF1508AS’s enhanced routing switch matrices increase usable gate count and
increase odds of successful pin-locked design modifications.
The ATF1508AS has up to 96 bi-directional I/O pins and four dedicated input pins, depending
on the type of device package selected. Each dedicated pin can also serve as a global control
signal, register clock, register reset or output enable. Each of these control signals can be
selected for use individually within each macrocell.
Each of the 128 macrocells generates a buried feedback that goes to the global bus. Each
input and I/O pin also feeds into the global bus. The switch matrix in each logic block then
selects 40 individual signals from the global bus. Each macrocell also generates a foldback
logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1508AS
allows fast, efficient generation of complex logic functions. The ATF1508AS contains eight
such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product
terms.
The ATF1508AS macrocell, shown in Figure 1, is flexible enough to support highly-complex
logic functions operating at high speed. The macrocell consists of five sections: product terms
and product term select multiplexer; OR/XOR/CASCADE logic, a flip-flop, output select and
enable, and logic array inputs.
Unused macrocells are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF1508AS. Two bytes
(16 bits) of User Signature are accessible to the user for purposes such as storing project
name, part number, revision or date. The User Signature is accessible regardless of the state
of the security fuse.
The ATF1508AS device is an in-system programmable (ISP) device. It uses the industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundaryscan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also
allows design modifications to be made in the field via software.
Product Terms and
Select Mux
Each ATF1508AS macrocell has five product terms. Each product term receives as its inputs
all signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as needed to
the macrocell logic gates and control signals. The PTMUX programming is determined by the
design compiler, which selects the optimum macrocell configuration.
OR/XOR/
CASCADE Logic
The ATF1508AS’s logic structure is designed to efficiently support all types of logic. Within a
single macrocell, all the product terms can be routed to the OR gate, creating a 5-input
AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be
expanded to as many as 40 product terms with a little small additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a
product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input
allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. The XOR gate is also used to emulate T- and JK-type flip-flops.
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ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
Flip-flop
The ATF1508AS’s flip-flop has very flexible data and control functions. The data input can
come from either the XOR gate, from a separate product term or directly from the I/O pin.
Selecting the separate product term allows creation of a buried registered feedback within a
combinatorial output macrocell. (This feature is automatically implemented by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flowthrough latch. In this mode, data passes through when the clock is high and is latched when
the clock is low.
The clock itself can be either the Global CLK Signal (GCK) or an individual product term. The
flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the clock,
one of the macrocell product terms can be selected as a clock enable. When the clock enable
function is active and the enable signal (product term) is low, all clock edges are ignored. The
flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product
term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product term or always off.
Extra Feedback
The ATF15xxSE Family macrocell output can be selected as registered or combinatorial. The
extra buried feedback signal can be either combinatorial or a registered signal regardless of
whether the output is combinatorial or registered. (This enhancement function is automatically
implemented by the fitter software.) Feedback of a buried combinatorial output allows the creation of a second latch within a macrocell.
I/O Control
The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be individually configured as an input, output or for bi-directional operation. The output enable for
each macrocell can be selected from the true or compliment of the two output enable pins, a
subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done
by the fitter software when the I/O is configured as an input, all macrocell resources are still
available, including the buried feedback, expander and cascade logic.
Global Bus/Switch
Matrix
The global bus contains all input and I/O pin signals as well as the buried feedback signal from
all 128 macrocells. The switch matrix in each logic block receives as its inputs all signals from
the global bus. Under software control, up to 40 of these signals can be selected as inputs to
the logic block.
Foldback Bus
Each macrocell also generates a foldback product term. This signal goes to the regional bus
and is available to 16 macrocells. The foldback is an inverse polarity of one of the macrocell’s
product terms. The 16 foldback terms in each region allows generation of high fan-in sum
terms (up to 21 product terms) with a little additional delay.
3.3V or 5.0V I/O
Operation
The ATF1508AS device has two sets of VCC pins viz, VCCINT and VCCIO. VCCINT pins must
always be connected to a 5.0V power supply. VCCINT pins are for input buffers and are “compatible” with both 3.3V and 5.0V inputs. V CCIO pins are for I/O output drives and can be
connected for 3.3/5.0V power supply.
Open-collector
Output Option
This option enables the device output to provide control signals such as an interrupt that can
be asserted by any of the several devices.
5
0784P–PLD–7/05
Figure 1. ATF1508AS Macrocell
Programmable
Pin-keeper
Option for
Inputs and I/Os
The ATF1508AS offers the option of programming all input and I/O pins so that “pin-keeper”
circuits can be utilized. When any pin is driven high or low and then subsequently left floating,
it will stay at that previous high- or low-level. This circuitry prevents unused input and I/O lines
from floating to intermediate voltage levels, which causes unnecessary power consumption
and system noise. The keeper circuits eliminate the need for external pull-up resistors and
eliminate their DC power consumption.
Input Diagram
6
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
Speed/Power
Management
The ATF1508AS has several built-in speed and power management features. The
ATF1508AS contains circuitry that automatically puts the device into a low-power stand-by
mode when no logic transitions are occurring. This not only reduces power consumption during inactive periods, but also provides proportional power-savings for most applications
running at system speeds below 5 MHz.
To further reduce power, each ATF1508AS macrocell has a Reduced-power bit feature. This
feature allows individual macrocells to be configured for maximum power savings. This feature
may be selected as a design option.
I/O Diagram
All ATF1508 also have an optional power-down mode. In this mode, current drops to below 10
mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used to
power down the part. The power-down option is selected in the design source file. When
enabled, the device goes into power-down when either PD1 or PD2 is high. In the power-down
mode, all internal logic signals are latched and held, as are any enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is
enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s
macrocell may still be used to generate buried foldback and cascade logic signals.
All power-down AC characteristic parameters are computed from external input or I/O pins,
with Reduced-power Bit turned on. For macrocells in reduced-power mode (Reduced-power
bit turned on), the reduced-power adder, tRPA, must be added to the AC parameters, which
include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP.
Each output also has individual slew rate control. This may be used to reduce system noise by
slowing down outputs that do not need to operate at maximum speed. Outputs default to slow
switching, and may be specified as fast switching in the design file.
7
0784P–PLD–7/05
Design
Software
Support
ATF1508AS designs are supported by several third-party tools. Automated fitters allow logic
synthesis using a variety of high level description languages and formats.
Power-up Reset
The ATF1508AS is designed with a power-up reset, a feature critical for state machine initialization. At a point delayed slightly from VCC crossing VRST, all registers will be initialized, and
the state of each output will depend on the polarity of its buffer. However, due to the asynchronous nature of reset and uncertainty of how VCC actually rises in the system, the following
conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving the
clock pin high, and,
3. The clock must remain stable during TD.
The ATF1508AS has two options for the hysteresis about the reset level, VRST, Small and
Large. During the fitting process users may configure the device with the Power-up Reset hysteresis set to Large or Small. Atmel POF2JED users may select the Large option by including
the flag “-power_reset” on the command line after “filename.POF”. To allow the registers to be
properly reinitialized with the Large hysteresis option selected, the following condition is
added:
4. If VCC falls below 2.0V, it must shut off completely before the device is turned on again.
When the Large hysteresis option is active, ICC is reduced by several hundred microamps as
well.
Security Fuse
Usage
A single fuse is provided to prevent unauthorized copying of the ATF1508AS fuse patterns.
Once programmed, fuse verify is inhibited. However, User Signature and device ID remains
accessible.
Programming
ATF1508AS devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for programming and
facilitates rapid design iterations and field changes.
Atmel provides ISP hardware and software to allow programming of the ATF1508AS via the
PC. ISP is performed by using either a download cable or a comparable board tester or a simple microprocessor interface.
To allow ISP programming support by the Automated Test Equipment (ATE) vendors, Serial
Vector Format (SVF) files can be created by the Atmel ISP Software. Conversion to other ATE
tester format beside SVF is also possible
ATF1508AS devices can also be programmed using standard third-party programmers. With
third-party programmer, the JTAG ISP port can be disabled thereby allowing four additional
I/O pins to be used for logic.
Contact your local Atmel representatives or Atmel PLD applications for details.
8
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
ISP
Programming
Protection
The ATF1508AS has a special feature that locks the device and prevents the inputs and I/O
from driving if the programming process is interrupted for any reason. The inputs and I/O
default to high-Z state during such a condition. In addition the pin-keeper option preserves the
former state during device programming.
All ATF1508AS devices are initially shipped in the erased state thereby making them ready to
use for ISP.
Note:
JTAG-BST
Overview
For more information refer to the “Designing for In-System Programmability with Atmel CPLDs”
application note.
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the
ATF1508AS. The boundary-scan technique involves the inclusion of a shift-register stage
(contained in a boundary-scan cell) adjacent to each component so that signals at component
boundaries can be controlled and observed using scan testing principles. Each input pin and
I/O pin has its own boundary-scan cell (BSC) in order to support boundary-scan testing. The
ATF1508AS does not currently include a Test Reset (TRST) input pin because the TAP controller is automatically reset at power-up. The six JTAG BST modes supported include:
SAMPLE/PRELOAD, EXTEST, BYPASS and IDCODE. BST on the ATF1508AS is implemented using the Boundary-scan Definition Language (BSDL) described in the JTAG
specification (IEEE Standard 1149.1). Any third-party tool that supports the BSDL format can
be used to perform BST on the ATF1508AS.
The ATF1508AS also has the option of using four JTAG-standard I/O pins for In-System programming (ISP). The ATF1508AS is programmable through the four JTAG pins using
programming compatible with the IEEE JTAG Standard 1149.1. Programming is performed by
using 5V TTL-level programming signals from the JTAG ISP interface. The JTAG feature is a
programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are
available as I/O pins.
JTAG
Boundary-scan
Cell (BSC)
Testing
The ATF1508AS contains up to 96 I/O pins and four input pins, depending on the device type
and package type selected. Each input pin and I/O pin has its own boundary-scan cell (BSC)
in order to support boundary-scan testing as described in detail by IEEE Standard 1149.1. A
typical BSC consists of three capture registers or scan registers and up to two update registers. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The
BSCs in the device are chained together through the (BST) capture registers. Input to the capture register chain is fed in from the TDI pin while the output is directed to the TDO pin.
Capture registers are used to capture active device data signals, to shift data in and out of the
device and to load data into the update registers. Control signals are generated internally by
the JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells are
shown below.
9
0784P–PLD–7/05
BSC
Configuration
Pins and
Macrocells
(Except JTAG
TAP Pins)
Note:
The ATF1508AS has a pull-up option on TMS and TDI pins. This feature is selected as a design
option.
BSC
Configuration
for Macrocell
TDO
OEJ
0
0
1
D Q
D Q
1
OUTJ
0
0
Pin
1
D Q
D Q
Capture
DR
Update
DR
1
Mode
TDI
Shift
Clock
Macrocell BSC
Boundary Scan
Definition
Language
(BSDL) Models
for the ATF1508
10
These are now available in all package types via the Atmel Web Site. These models can be
used for Boundary-scan Test Operation in the ATF1508AS and have been scheduled to conform to the IEEE 1149.1 standard.
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
PCI Voltage-tocurrent Curves
for +5V
Signaling in
Pull-up Mode
The ATF1508AS also supports the growing need in the industry to support the new Peripheral
Component Interconnect (PCI) interface standard in PCI-based designs and specifications.
The PCI interface calls for high current drivers, which are much larger than the traditional TTL
drivers.
Pull Up
VCC
Test Point
Voltage
PCI Compliance
2.4
DC
drive point
1.4
AC drive
point
-44 Current (mA) -178
-2
Pull Down
VCC
AC drive
point
Voltage
PCI Voltage-tocurrent Curves
for +5V
Signaling in
Pull-down Mode
2.2
DC
drive point
0.55
Test Point
3,6
95
Current (mA)
380
11
0784P–PLD–7/05
PCI DC Characteristics
Symbol
Parameter
Conditions
Min
Max
Units
VCC
Supply Voltage
4.75
5.25
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VIL
Input Low Voltage
-0.5
0.8
V
VIN = 2.7V
70
µA
VIN = 0.5V
-70
µA
Input High Leakage Current
IIH
(1)
(1)
IIL
Input Low Leakage Current
VOH
Output High Voltage
IOUT = -2 mA
VOL
Output Low Voltage
IOUT = 3 mA, 6 mA
CIN
2.4
V
0.55
V
Input Pin Capacitance
10
pF
CCLK
CLK Pin Capacitance
12
pF
CIDSEL
IDSEL Pin Capacitance
8
pF
Pin Inductance
20
nH
LPIN
Note:
1. Leakage current is without pin-keeper off.
PCI AC Characteristics
Symbol
Parameter
Conditions
Min
IOH(AC)
Switching
0 < VOUT ≤ 1.4
-44
mA
1.4 < VOUT < 2.4
-44+(VOUT - 1.4)/0.024
mA
Current High
IOL(AC)
Max
Units
3.1 < VOUT < VCC
Equation A(1)
mA
(Test High)
VOUT = 3.1V
-142
µA
Switching
VOUT > 2.2V
95
2.2 > VOUT > 0
VOUT/0.023
Current Low
mA
mA
(2)
0.1 > VOUT > 0
Equation B
(Test Point)
VOUT = 0.71
ICL
Low Clamp Current
-5 < VIN ≤ -1
-25+(VIN + 1)/0.015
SLEWR
Output Rise Slew Rate
0.4V to 2.4V load
0.5
3.0
V/ns
Output Fall Slew Rate
2.4V to 0.4V load
0.5
3.0
V/ns
SLEWF
Notes:
12
206
mA
mA
mA
1. Equation A: IOH = 11.9 (VOUT - 5.25) * (VOUT + 2.45) for VCC > VOUT > 3.1V.
2. Equation B: IOL = 78.5 * VOUT * (4.4 - VOUT) for 0V < VOUT < 0.71V.
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
Power-down
Mode
The ATF1508AS includes two pins for optional pin-controlled power-down feature. When this
mode is enabled, the PD pin acts as the power-down pin. When the PD1 and PD2 pin is high,
the device supply current is reduced to less than 10 mA. During power-down, all output data
and internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any outputs that were in a high-Z state at the onset will remain at highZ. During power-down, all input signals except the power-down pin are blocked. Input and I/O
hold latches remain active to ensure that pins do not float to indeterminate levels, further
reducing system power. The power-down pin feature is enabled in the logic design file.
Designs using either power-down pin may not use the PD pin logic array input. However, buried logic resources in this macrocell may still be used.
Power-down AC Characteristics(1)(2)
-7
Symbol
tIVDH
Parameter
Valid I, I/O before PD High
(2)
tGVDH
Valid OE
tCVDH
Valid Clock(2) before PD High
tDHIX
I, I/O Don’t Care after PD High
(2)
before PD High
Min
-10
Max
Min
-15
Max
Min
-20
Max
Min
-25
Max
Min
Max
Units
7
10
15
20
25
ns
7
10
15
20
25
ns
7
10
15
20
25
ns
12
15
25
30
35
ns
OE
Don’t Care after PD High
12
15
25
30
35
ns
tDHCX
Clock
(2)
12
15
25
30
35
ns
tDLIV
PD Low to Valid I, I/O
1
1
1
1
1
µs
tDLGV
PD Low to Valid OE (Pin or Term)
1
1
1
1
1
µs
tDLCV
PD Low to Valid Clock (Pin or Term)
1
1
1
1
1
µs
tDLOV
PD Low to Valid Output
1
1
1
1
1
µs
tDHGX
Notes:
Don’t Care after PD High
1. For slow slew outputs, add tSSO.
2. Pin or product term.
Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C
*NOTICE:
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Note:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
13
0784P–PLD–7/05
DC and AC Operating Conditions
Commercial
Industrial
Operating Temperature (Ambient)
0°C - 70°C
-40°C - 85°C
VCCINT or VCCIO (5V) Power Supply
5V ± 5%
5V ± 10%
2.7V - 3.6V
2.7V - 3.6V
VCCIO (3.3V) Power Supply
DC Characteristics(1)
Symbol
Parameter
Condition
IIL
Input or I/O Low
Leakage Current
IIH
Input or I/O High
Leakage Current
IOZ
Tri-state Output
Off-state Current
VO = VCC or GND
ICC1
Power Supply
Current, Standby
VCC = Max
VIN = 0, VCC
VIN = VCC
Std Mode
“L” Mode
ICC2
Power Supply Current,
Power-down Mode
VCC = Max
VIN = 0, VCC
“PD” Mode
ICC3(2)
Reduced-power Mode
Supply Current
VCC = Max
VIN = 0, VCC
Std Mode
VCCIO
Supply Voltage
Min
5.0V Device Output
Typ
Max
Units
-2
-10
µA
2
10
µA
40
µA
-40
Com.
160
mA
Ind.
180
mA
Com.
10
µA
Ind.
10
1
Com.
µA
10
mA
65
Ind.
mA
85
mA
Com.
4.75
5.25
V
Ind.
4.5
5.5
V
3.0
3.6
V
VCCIO
Supply Voltage
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
2.0
VCCIO + 0.3
V
VOL
VOH
Notes:
14
3.3V Device Output
Output Low Voltage (TTL)
VIN = VIH or VIL
VCCIO = MIN, IOL = 12 mA
Com.
0.45
V
Ind.
0.45
V
Output Low Voltage (CMOS)
VIN = VIH or VIL
VCC = MIN, IOL = 0.1 mA
Com.
0.2
V
Ind.
0.2
V
Output High Voltage (TTL)
VIN = VIH or VIL
VCCIO = MIN, IOH = -4.0 mA
2.4
V
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. ICC3 refers to the current in the reduced-power mode when macrocell reduced-power is turned ON.
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
Pin Capacitance(1)
Typ
Max
Units
Conditions
CIN
8
10
pF
VIN = 0V; f = 1.0 MHz
CI/O
8
10
pF
VOUT = 0V; f = 1.0 MHz
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage
pin during programming) has a maximum capacitance of 12 pF.
Timing Model
U
Input Test Waveforms and Measurement Levels
rR, tF = 1.5 ns typical
Output AC Test Loads
(3.0V)*
(703 )*
(8060 )*
Note:
*Numbers in parenthesis refer to 3.0V operating conditions (preliminary).
15
0784P–PLD–7/05
SUPPLY CURRENT VS. FREQUENCY
LOW-POWER ("L") VERSION
(TA = 25°C)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
(TA = 25°C, F = 0)
200.0
250.0
STANDARD POWER
150.0
STANDARD POWER
ICC (mA)
ICC (mA)
200.0
150.0
REDUCED POWER MODE
100.0
REDUCED POWER MODE
50.0
100.0
0.0
0.00
50.0
4.50
4.75
5.00
VCC (V)
5.25
5.50
5.00
10.00
FREQUENCY (MHz)
15.00
20.00
OUTPUT SOURCE CURRENT
VS. SUPPLY VOLTAGE (VOH = 2.4V, TA = 25°C)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
LOW-POWER ("L") VERSION
(TA = 25°C, F = 0)
0
30.0
-10
IOH (mA)
-20
ICC ( A)
20.0
-30
-40
10.0
-50
0.0
4.50
4.75
5.00
VCC (V)
5.25
-60
4.50
5.50
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
INPUT CLAMP CURRENT
VS. INPUT VOLTAGE (VCC = 5V, TA = 25°C)
SUPPLY CURRENT VS. FREQUENCY
STANDARD POWER
(TA = 25°C, F = 0)
0
-20
INPUT CURRENT (mA)
300.0
250.0
STANDARD POWER
200.0
ICC ( A)
4.75
150.0
100.0
REDUCED POWER MODE
-40
-60
-80
-100
-120
-140
50.0
0.0
0.00
-160
20.00
40.00
60.00
FREQUENCY (MHz)
80.00
-1.4
100.00
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
INPUT VOLTAGE (V)
OUTPUT SINK CURRENT
VS. SUPPLY VOLTAGE (VOL = 0.5V, TA = 25°C)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
PIN-CONTROLLED POWER-DOWN MODE
(TA = 25°C, F = 0)
43
1100.0
42
41
IOL (mA)
1000.0
ICC ( A)
STANDARD POWER
900.0
40
39
38
800.0
37
REDUCED POWER MODE
700.0
4.50
16
4.75
5.00
VCC (V)
5.25
5.50
36
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
NORMALIZED TCO
VS. SUPPLY VOLTAGE (TA = 25°C)
OUTPUT SOURCE CURRENT
VS. SUPPLY VOLTAGE (VCC = 5V, TA = 25°C)
1.20
-10
NORMALIZED TPD
IOH (mA)
-30
-50
-70
-90
-110
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1.10
1.00
0.90
0.80
4.50
5.0
4.75
5.00
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE (V)
5.50
NORMALIZED TSU
VS. SUPPLY VOLTAGE (TA = 25°C)
INPUT CURRENT
VS. INPUT VOLTAGE (VCC = 5V, TA = 25°C)
1.20
40
5.25
1.10
20
NORMALIZED TSU
INPUT CURRENT ( A)
30
10
0
-10
1.00
0.90
-20
-30
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0.80
4.50
5.0
4.75
5.00
SUPPLY VOLTAGE (V)
INPUT VOLTAGE (V)
5.25
5.50
NORMALIZED TPD
VS. TEMPERATURE (VCC = 5.0V)
OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25°C)
140
1.20
120
NORMALIZED TPD
IOL (mA)
100
80
60
40
1.10
1.00
0.90
20
0
0.80
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-40
0
1.20
1.20
1.10
NORMALIZED TCO
NORMALIZED TPD
75
NORMALIZED TCO
VS. TEMPERATURE (VCC = 5.0V)
NORMALIZED TPD
VS. SUPPLY VOLTAGE (TA = 25°C)
1.00
0.90
0.80
4.50
25
TEMPERATURE (C)
OUTPUT VOLTAGE (V)
1.10
1.00
0.90
0.80
4.75
5.00
SUPPLY VOLTAGE (V)
5.25
5.50
-40
0
25
75
TEMPERATURE (C)
17
0784P–PLD–7/05
NORMALIZED TSU
VS. TEMPERATURE (VCC = 5.0V)
NORMALIZED TSU
1.20
1.10
1.00
0.90
0.80
-40
0
25
75
TEMPERATURE (C)
18
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
AC Characteristics (1)
-7
Min
-10
Max
Min
-15
-20
Max
Min
Max
7.5
10
3
15
7
9
3
12
Symbol
Parameter
tPD1
Input or Feedback to
Non-registered Output
tPD2
I/O Input or Feedback to
Non-registered Feedback
tSU
Global Clock Setup Time
6
7
11
16
20
ns
tH
Global Clock Hold Time
0
0
0
0
0
ns
tFSU
Global Clock Setup Time of
Fast Input
3
3
3
3
3
ns
tFH
Global Clock Hold Time of
Fast Input
0.5
0.5
1.0
1.5
2
MHz
tCOP
Global Clock to Output Delay
tCH
Global Clock High Time
3
4
5
6
7
ns
tCL
Global Clock Low Time
3
4
5
6
7
ns
tASU
Array Clock Setup Time
3
3
4
4
5
ns
tAH
Array Clock Hold Time
2
3
4
5
6
ns
tACOP
Array Clock Output Delay
tACH
Array Clock High Time
3
4
6
8
10
ns
tACL
Array Clock Low Time
3
4
6
8
10
ns
tCNT
Minimum Clock Global Period
fCNT
Maximum Internal Global
Clock Frequency
tACNT
Minimum Array Clock Period
fACNT
Maximum Internal Array
Clock Frequency
fMAX
Maximum Clock Frequency
tIN
Input Pad and Buffer Delay
0.5
0.5
2
2
2
ns
tIO
I/O Input Pad and Buffer Delay
0.5
0.5
2
2
2
ns
tFIN
Fast Input Delay
1
1
2
2
2
ns
tSEXP
Foldback Term Delay
4
5
8
10
12
ns
tPEXP
Cascade Logic Delay
0.8
0.8
1
1
1.2
ns
tLAD
Logic Array Delay
3
5
6
7
8
ns
tLAC
Logic Control Delay
3
5
6
7
8
ns
tIOE
Internal Output Enable Delay
2
2
3
3
4
ns
tOD1
Output Buffer and Pad Delay
(Slow slew rate = OFF;
VCCIO = 5V; CL = 35 pF)
2
1.5
4
5
6
ns
4.5
5
7.5
125
8
10
8
8
10
Min
Max
Units
20
25
ns
16
20
ns
13
20
13
76.9
Max
10
15
10
100
Min
-25
25
17
66
13
22
50
17
ns
ns
ns
MHz
22
ns
125
100
76.9
66
50
MHz
166.7
125
100
41.7
33.3
MHz
19
0784P–PLD–7/05
AC Characteristics (Continued)(1)
-7
Symbol
Parameter
Min
tOD2
Output Buffer and Pad Delay
(Slow slew rate = OFF;
VCCIO = 3.3V; CL = 35 pF)
tOD3
Output Buffer and Pad Delay
(Slow slew rate = ON;
VCCIO = 5V or 3.3V; CL = 35 pF)
tZX1
-10
Max
Min
-15
Max
Min
-20
Max
Min
-25
Max
Min
Max
Units
2.5
2.0
5
6
7
ns
5
5.5
8
10
12
ns
Output Buffer Enable Delay
(Slow slew rate = OFF;
VCCIO = 5.0V; CL = 35 pF)
4.0
5.0
7
9
10
ns
tZX2
Output Buffer Enable Delay
(Slow slew rate = OFF;
VCCIO = 3.3V; CL = 35 pF)
4.5
5.5
7
9
10
ns
tZX3
Output Buffer Enable Delay
(Slow slew rate = ON;
VCCIO = 5.0V/3.3V; CL = 35 pF)
9
9
10
11
12
ns
tXZ
Output Buffer Disable Delay
(CL = 5 pF)
4
5
6
7
8
ns
tSU
Register Setup Time
3
2
4
5
6
ns
tH
Register Hold Time
2
3
4
5
6
ns
tFSU
Register Setup Time of Fast
Input
3
3
2
2
3
ns
tFH
Register Hold Time of Fast
Input
0.5
0.5
2
2
2.5
ns
tRD
Register Delay
1
2
1
2
2
ns
tCOMB
Combinatorial Delay
1
2
1
2
2
ns
tIC
Array Clock Delay
3
5
6
7
8
ns
tEN
Register Enable Time
3
5
6
7
8
ns
tGLOB
Global Control Delay
1
1
1
1
1
ns
tPRE
Register Preset Time
2
3
4
5
6
ns
tCLR
Register Clear Time
2
3
4
5
6
ns
tUIM
Switch Matrix Delay
1
1
2
2
2
ns
10
11
13
14
15
ns
tRPA
Notes:
20
Reduced-power Adder
(2)
1. See ordering information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reducedpower mode.
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
ATF1508AS Dedicated Pinouts
Dedicated Pin
84-lead J-lead
100-lead PQFP
100-lead TQFP
160-lead PQFP
INPUT/OE2/GCLK2
2
92
90
142
INPUT/GCLR
1
91
89
141
INPUT/OE1
84
90
88
140
INPUT/GCLK1
83
89
87
139
I/O /GCLK3
81
87
85
137
12,45
3,43
1,41
63,159
I/O / TDI(JTAG)
14
6
4
9
I/O / TMS(JTAG)
23
17
15
22
I/O / TCK(JTAG)
62
64
62
99
I/O / TDO(JTAG)
71
75
73
112
7,19,32,42,
47,59,72,82
13,28,40,45,
61,76,88,97
11,26,38,43,
59,74,86,95
17,42,60,66,95,
113,138,148
VCCINT
3,43
41,93
39,91
61,143
VCCIO
13,26,38,
53,66,78
5,20,36,53,68,84
3,18,34,51,66,82
8,26,55,79,104,133
N/C
–
–
–
1,2,3,4,5,6,7,34,35,36,
37,38,39,40,44,45,46,
47,74,75,76,77,81,82,
83,84,85,86,87,114,
115,116,117,118,119,
120,124,125,126,127,
154,155,156,157
# of SIGNAL PINS
68
84
84
100
# USER I/O PINS
64
80
80
96
I/O / PD (1, 2)
GND
OE (1, 2)
Global OE Pins
GCLR
Global Clear Pin
GCLK (1, 2, 3)
Global Clock Pins
PD (1, 2)
Power-down pins
TDI, TMS, TCK, TDO
JTAG pins used for boundary scan testing or in-system programming
GND
Ground Pins
VCCINT
VCC pins for the device (+5V - Internal)
VCCIO
VCC pins for output drivers (for I/O pins) (+5V or 3.3V - I/Os)
21
0784P–PLD–7/05
ATF1508AS I/O Pinouts
MC
PLB
84-lead
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
MC
PLB
84-lead
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
1
A
–
4
2
160
33
C
–
27
25
41
2
A
–
–
–
–
34
C
–
–
–
–
3
A/
PD1
12
3
1
159
35
C
31
26
24
33
4
A
–
–
–
158
36
C
–
–
–
32
5
A
11
2
100
153
37
C
30
25
23
31
6
A
10
1
99
152
38
C
29
24
22
30
7
A
–
–
–
–
39
C
–
–
–
–
8
A
9
100
98
151
40
C
28
23
21
29
9
A
–
99
97
150
41
C
–
22
20
28
10
A
–
–
–
–
42
C
–
–
–
–
11
A
8
98
96
149
43
C
27
21
19
27
12
A
–
–
–
147
44
C
–
–
–
25
13
A
6
96
94
146
45
C
25
19
17
24
14
A
5
95
93
145
46
C
24
18
16
23
15
A
–
–
–
–
47
C
–
–
–
–
16
A
4
94
92
144
48
C/
TMS
23
17
15
22
17
B
22
16
14
21
49
D
41
39
37
59
18
B
–
–
–
–
50
D
–
–
–
–
19
B
21
15
13
20
51
D
40
38
36
58
20
B
–
–
–
19
52
D
–
–
–
57
21
B
20
14
12
18
53
D
39
37
35
56
22
B
–
12
10
16
54
D
–
35
33
54
23
B
–
–
–
–
55
D
–
–
–
–
24
B
18
11
9
15
56
D
37
34
32
53
25
B
17
10
8
14
57
D
36
33
31
52
26
B
–
–
–
–
58
D
–
–
–
–
27
B
16
9
7
13
59
D
35
32
30
51
28
B
–
–
–
12
60
D
–
–
–
50
29
B
15
8
6
11
61
D
34
31
29
49
30
B
–
7
5
10
62
D
–
30
28
48
31
B
–
–
–
–
63
D
–
–
–
–
32
B/
TDI
14
6
4
9
64
D
33
29
27
43
65
E
44
42
40
62
97
G
63
65
63
100
22
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
ATF1508AS I/O Pinouts (Continued)
MC
PLB
84-lead
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
MC
PLB
84-lead
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
66
E
–
–
–
–
98
G
–
–
–
–
67
E/
PD2
45
43
41
63
99
G
64
66
64
101
68
E
–
–
–
64
100
G
–
–
–
102
69
E
46
44
42
65
101
G
65
67
65
103
70
E
–
46
44
67
102
G
–
69
67
105
71
E
–
–
–
–
103
G
–
–
–
–
72
E
48
47
45
68
104
G
67
70
68
106
73
E
49
48
46
69
105
G
68
71
69
107
74
E
–
–
–
–
106
G
–
–
–
–
75
E
50
49
47
70
107
G
69
72
70
108
76
E
–
–
–
71
108
G
–
–
–
109
77
E
51
50
48
72
109
G
70
73
71
110
78
E
–
51
49
73
110
G
–
74
72
111
79
E
–
–
–
–
111
G
–
–
–
–
80
E
52
52
50
78
112
G/
TDO
71
75
73
112
81
F
–
54
52
80
113
H
–
77
75
121
82
F
–
–
–
–
114
H
–
–
–
–
83
F
54
55
53
88
115
H
73
78
76
122
84
F
–
–
–
89
116
H
–
–
–
123
85
F
55
56
54
90
117
H
74
79
77
128
86
F
56
57
55
91
118
H
75
80
78
129
87
F
–
–
–
–
119
H
–
–
–
–
88
F
57
58
56
92
120
H
76
81
79
130
89
F
–
59
57
93
121
H
–
82
80
131
90
F
–
–
–
–
122
H
–
–
–
–
91
F
58
60
58
94
123
H
77
83
81
132
92
F
–
–
–
96
124
H
–
–
–
134
93
F
60
62
60
97
125
H
79
85
83
135
94
F
61
63
61
98
126
H
80
86
84
136
95
F
–
–
–
–
127
H
–
–
–
–
96
F/
TCK
62
64
62
99
128
H/
GCLK3
81
87
85
137
23
0784P–PLD–7/05
Ordering Information
ATF1508AS Standard Package Options
tPD
(ns)
7.5
10
10
15
15
Notes:
tCO1
(ns)
4.5
5
fMAX
(MHz)
166.7
125
5
125
5
100
8
100
Ordering Code
Package
ATF1508AS-7 JC84
84J
ATF1508AS-7 QC100
100Q1
ATF1508AS-7 AC100
100A
ATF1508AS-7 QC160
160Q1
ATF1508AS-10 JC84
84J
ATF1508AS-10 QC100
100Q1
ATF1508AS-10 AC100
100A
ATF1508AS-10 QC160
160Q1
ATF1508AS-10 Jl84
ATF1508AS-10 Ql100
ATF1508AS-10 Al100
ATF1508AS-10 Ql160
84J
100Q1
100A
160Q1
ATF1508AS-15 JC84
84J
ATF1508AS-15 QC100
100Q1
ATF1508AS-15 AC100
100A
ATF1508AS-15 QC160
160Q1
ATF1508AS-15 JI84
ATF1508AS-15 QI100
84J
100Q1
ATF1508AS-15 AI100
100A
ATF1508AS-15 QI160
160Q1
Operation Range
Commercial
(0°C to 70°C)
Commercial
(0°C to 70°C)
Industrial
(-40°C to +85°C)
Commercial
(0°C to 70°C)
Industrial
(-40°C to +85°C)
1. The last time buy is Sept. 30, 2005 for shaded parts.
2. The recommended replacement package for QC160 is the AU100.
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
ATF1508AS Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD
(ns)
tCO1
(ns)
fMAX
(MHz)
Ordering Code
Package
7.5
4.5
166.7
ATF1508AS-7 JX84
ATF1508AS-7 AX100
84J
100A
10
5
125
ATF1508AS-10 JU84
ATF1508AS-10 QU100
ATF1508AS-10 AU100
84J
100Q1
100A
Operation Range
Commercial
(0°C to 70°C)
Industrial
(-40°C to +85°C)
Package Type
84J
84-lead, Plastic J-leaded Chip Carrier (PLCC)
100Q1
100-lead, Plastic Quad Pin Flat Package (PQFP)
100A
100-lead, Very Thin Plastic Gull Wing Quad Flat Package (TQFP)
160Q1
160-lead, Plastic Quad Pin Flat Package (PQFP)
24
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
ATF1508ASL Standard Package Options
tPD
(ns)
tCO1
(ns)
fMAX
(MHz)
Ordering Code
Package
ATF1508ASL-20 JC84
20
12
83.3
25
Note:
15
70
84J
ATF1508ASL-20 QC100
100Q1
ATF1508ASL-20 AC100
100A
ATF1508ASL-20 QC160
160Q1
ATF1508ASL-25 JI84
Operation Range
Commercial
(0°C to 70°C)
84J
ATF1508ASL-25 QI100
100Q1
ATF1508ASL-25 AI100
100A
ATF1508ASL-25 QI160
160Q1
Industrial
(-40°C to +85°C)
1. The last time buy is Sept. 30, 2005 for shaded parts.
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
ATF1508ASL Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD
(ns)
tCO1
(ns)
fMAX
(MHz)
25
15
70
Ordering Code
Package
ATF1508ASL-25 JU84
ATF1508ASL-25 AU100
84J
100A
Operation Range
Industrial
(-40°C to +85°C)
Package Type
84J
84-lead, Plastic J-leaded Chip Carrier (PLCC)
100Q1
100-lead, Plastic Quad Pin Flat Package (PQFP)
100A
100-lead, Very Thin Plastic Gull Wing Quad Flat Package (TQFP)
160Q1
160-lead, Plastic Quad Pin Flat Package (PQFP)
25
0784P–PLD–7/05
Package Information
84J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
D2/E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AF.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
30.099
–
30.353
D1
29.210
–
29.413
E
30.099
–
30.353
E1
29.210
–
29.413
D2/E2
27.686
–
28.702
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
26
2325 Orchard Parkway
San Jose, CA 95131
TITLE
84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
84J
B
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
100Q1 – PQFP
E
PIN 1 ID
PIN 1
e
D1
B
D
E1
COMMON DIMENSIONS
(Unit of Measure = mm)
JEDEC STANDARD MS-022, GC-1
A
0º~7º
C
L
A1
SYMBOL
MIN
NOM
MAX
A
–
3.04
3.4
A1
0.25
0.33
0.5
D
23.20 BSC
E
17.20 BSC
E1
14.00 BSC
B
0.22
C
0.11
D1
L
e
NOTE
–
0.40
–
0.23
20 BSC
0.73
–
1.03
0.65 BSC
07/6/2005
R
DRAWING NO.
TITLE
2325 Orchard Parkway
100Q1, 100-lead, 14 x 20 mm Body, 3.2 mm Footprint, 0.65 mm Pitch,
100Q1
San Jose, CA 95131
Plastic Quad Flat Package (PQFP)
REV.
C
27
0784P–PLD–7/05
100A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
e
E
D1
D
C
0˚~7˚
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AED.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.08 mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
15.75
16.00
16.25
D1
13.90
14.00
14.10
E
15.75
16.00
16.25
E1
13.90
14.00
14.10
B
0.17
–
0.27
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.50 TYP
10/5/2001
R
28
2325 Orchard Parkway
San Jose, CA 95131
TITLE
100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
100A
REV.
C
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
160Q1 – PQFP
D1
D
E
E1
Top View
Bottom View
A2
A1
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
L1
SYMBOL
Side View
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing
MS-022, Variation DD-1, for additional information.
2. To be determined at seating plane.
3. Regardless of the relative size of the upper and lower body sections,
dimensions D1 and E1 are determined at the largest feature of the body
exclusive of mold Flash and gate burrs, but including any mismatch
between the upper and lower sections of the molded body.
4. Dimension b does not include Dambar protrusion. The Dambar
protrusion(s) shall not cause the lead width to exceed b maximum by more
than 0.08 mm. Dambar cannot be located on the lower radius or the lead
foot.
5. A1 is defined as the distance from the seating plane to the lowest point of
the package body.
MIN
NOM
MAX
A1
0.25
–
0.50
A2
3.20
3.40
3.60
D
NOTE
5
31.20 BSC
2
D1
28.00 BSC
3
E
31.20 BSC
2
E1
28.00 BSC
3
e
0.65 BSC
b
0.22
L1
–
0.40
4
1.60 REF
3/28/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
160Q1, 160-lead, 28 x 28 mm Body, 3.2 Form Opt.,
Plastic Quad Flat Pack (PQFP)
DRAWING NO.
160Q1
REV.
A
29
0784P–PLD–7/05
Revision History
30
Revision
Comments
0784P
Green package options added.
0784O
The ATF1508ASL-25 commercial speed offering was obsoleted in 2002
and replaced by the ATF1508ASL-20 commercial speed grade.
ATF1508AS(L)
0784P–PLD–7/05
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
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Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
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0784P–PLD–7/05
xM
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