ATF22LV10C - Complete

Features
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3.0V to 5.5V Operating Range
Advanced Low-voltage Electrically-erasable Programmable Logic Device
User-controlled Power-down Pin Option
Pin-controlled Standby Power (10µA Typical)
Well-suited for Battery Powered Systems
10ns Maximum Propagation Delay
CMOS and TTL Compatible Inputs and Outputs
Latch Feature Hold Inputs to Previous Logic States
Advanced Electrically-erasable Technology
– Reprogrammable
– 100% Tested
High-reliability CMOS Process
– 20 year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200mA Latchup Immunity
Industrial Temperature Ranges
Dual-in-line and Surface Mount Packages in Standard Pinouts
Inputs are 5V Tolerant
Green Package Options (Pb/Halide-free/RoHS Compliant) Available
Applcations include Glue logic for 3.3V systems, DMA Control, State Machine Control,
Graphics processing
1.
High-performance
Electrically
Erasable
Programmable
Logic Device
Atmel ATF22LV10C
See separate datasheet for Atmel
ATF22LV10C(Q)Z option
Description
The Atmel® ATF22LV10C is a high-performance CMOS (electrically erasable) programmable logic device (PLD) that utilizes the Atmel proven electrically erasable
Flash memory technology. Speeds down to 10ns and power dissipation as low as
10mA are offered. All speed ranges are specified over the 3.0V to 5.5V range for
industrial and commercial temperature ranges.
The ATF22LV10C provides a low-voltage and user controlled “zero” power CMOS
PLD solution. A user-controlled power-down feature offers “zero” (10 µA typical)
standby power. This feature allows the user to manage total system power to meet
specific application requirements and enhance reliability, all without sacrificing speed.
(The Atmel ATF22LV10CQZ provides edge-sensing “zero” standby power (3µA typical), as well as low voltage operation. See the ATF22LV10CQZ datasheet.)
The ATF22LV10C is capable of operating at supply voltages down to 3.0V. When the
power-down pin is active, the device is placed into a zero standby power-down mode.
When the power-down pin is not used or active, the device operates in a full power
low voltage mode. Pin “keeper” circuits on input and output pins hold pins to their previous logic levels when idle, which eliminate static power consumed by pull-up
resistors.
The ATF22LV10C macrocell incorporates a variable product term architecture. Each
output is allocated from 8 to 16 product terms which allows highly-complex logic functions to be realized. Two additional product terms are included to provide synchronous
reset and asynchronous reset. These additional product terms are common to all ten
registers and are automatically cleared upon power-up. Register preload simplifies
testing. A security fuse prevents unauthorized copying of programmed fuse patterns.
0780M–PLD–7/10
Figure 1-1.
Block Diagram
Figure 1-2. Pin Configurations
Pin Configurations (All Pinouts Top View)
Pin Name
Function
CLK
Clock
IN
Logic Inputs
I/O
Bi-directional Buffers
VCC
(3V to 5.5V) Supply
PD
Programmable Power-down
Figure 1-3.
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
CLK/IN
IN
IN
IN/PD
IN
IN
IN
IN
IN
IN
IN
GND
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
DIP/SOIC
CLK/IN
IN
IN
IN/PD
IN
IN
IN
IN
IN
IN
IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
PLCC
25
24
23
22
21
20
19
12
13
14
15
16
17
18
5
6
7
8
9
10
11
I/O
I/O
I/O
GND*
I/O
I/O
I/O
IN
IN
GND
GND*
IN
I/O
I/O
IN/PD
IN
IN
GND*
IN
IN
IN
4
3
2
1
28
27
26
IN
IN
CLK/IN
VCC*
VCC
I/O
I/O
Figure 1-5.
Figure 1-4.
Note:
2
For PLCC, pins 1, 8, 15, and 22 can be left unconnected. For superior performance, connect
VCC to pin 1 and GND to 8, 15, and 22
Atmel ATF22LV10C
0780M–PLD–7/10
Atmel ATF22LV10C
2.
Absolute Maximum Ratings*
Temperature Under Bias .................. -40°C to +85°C
*NOTICE:
Storage Temperature...................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground...........................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming......................-2.0V to +14.0V(1)
Note:
Programming Voltage with
Respect to Ground.........................-2.0V to +14.0V(1)
3.
Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
1. Minimum voltage is -0.6V DC, which may undershoot to 2.0V for pulses of less than 20ns. Maximum output pin voltage is VCC + 0.75V DC, which may overshoot to 7.0V for
pulses of less than 20ns.
DC and AC Operating Conditions
Commercial
Industrial
Operating Temperature (Ambient)
0°C - 70°C
-40°C - 85°C
VCC Power Supply
3.0V - 5.5V
3.0V - 5.5V
3.1
DC Characteristics
Symbol
Parameter
Condition(2)
IIL
Input or I/O Low Leakage Current
IIH
Max
Units
0 VIN VIL(Max)
-10
µA
Input or I/O High Leakage Current
(VCC - 0.2)V VIN VCC
10
µA
ICC
Power Supply Current
VCC = Max, VIN = Max
Outputs Open
Com.
Ind.
85
90
mA
mA
ICC2
Clocked Power Supply Current
VCC = Max
Outputs Open, f = 15MHz
Com.
Ind.
100
105
mA
mA
IPD
Power Supply Current,
Power-down Mode
VCC = 3.6V, Max
VIN = 0, Outputs Open
Com.
Ind.
100
120
µA
µA
IOS(1)
Output Short Circuit Current
VOUT = 0.5V
-130
mA
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.75
V
0.5
V
VOL
Output Low Voltage
VIN = VIH or VIL
VCC = Min
IOL = 16mA
VOH
Output High Voltage
VIN = VIH or VIL
VCC = Min
IOH = -2.0mA
VOH
Output High Voltage
IOH = -100µA
Notes:
Min
Typ
55
60
10
10
2.4
V
VCC - 0.2V
V
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec
2. For DC characteristics, the test condition of VCC = Max corresponds to 3.6V
3
0780M–PLD–7/10
3.2
AC Waveforms
3.3
AC Characteristics(1)
-10
Symbol
Parameter
tPD
Input or Feedback to Non-Registered Output
tCF
Clock to Feedback
tCO
Clock to Output
tS
Input or Feedback Setup Time
tH
-15
Min
Max
Min
Max
Units
3
10
3
15
ns
8
ns
10
ns
5
2
6.5
2
7.5
12
ns
Input Hold Time
0
0
ns
tP
Clock Period
12
16
ns
tW
Clock Width
6
8
ns
fMAX
External Feedback 1/(tS+ tCO)
71.4
45.5
MHz
Internal Feedback 1/(tS + tCF)
80
50
MHz
83.3
62.5
MHz
No Feedback 1/(tP)
tEA
Input to Output Enable
3
12
3
15
ns
tER
Input to Output Disable
2
12
2
15
ns
tAP
Input or I/O to Asynchronous Reset of Register
3
13
3
15
ns
tSP
Setup Time, Synchronous Preset
10
10
ns
tAW
Asychronous Reset Width
8
8
ns
tAR
Asychronous Reset Recovery Time
6
6
ns
tSPR
Synchronous Preset to Clock Recovery Time
10
10
ns
Note:
4
1. See ordering information for valid part numbers
Atmel ATF22LV10C
0780M–PLD–7/10
Atmel ATF22LV10C
3.4
Power-down AC Characteristics
-10
Symbol
Parameter
tIVDH
Valid Input before PD High
10
15
ns
tGVDH
Valid OE before PD High
0
0
ns
tCVDH
Valid Clock before PD High
0
0
ns
tDHIX
Input Don't Care after PD High
10
15
ns
tDHGX
OE Don't Care after PD High
10
15
ns
tDHCX
Clock Don't Care after PD High
10
15
ns
tDLIV
PD Low to Valid Input
10
15
ns
tDLGV
PD Low to Valid OE
25
30
ns
tDLCV
PD Low to Valid Clock
25
30
ns
tDLOV
PD Low to Valid Output
30
35
ns
3.5
Min
-15
Max
Min
Max
Units
Input Test Waveforms and Measurement Levels
tR, tF < 1.5ns
3.6
Output Test Loads
3.3V
R1 = 316
OUTPUT
PIN
R2 = 348
Note:
Similar competitors devices are specified with slightly different loads. These load differences may affect output signals’
delay and slew rate. Atmel® devices are tested with sufficient margins to meet compatible device
specification conditions.
Table 3-1.
Note:
CL = 35 pF
Pin Capacitance (f = 1MHz, T = 25°C(1)
Typ
Max
Units
Conditions
CIN
5
8
pF
VIN = 0V
COUT
6
8
pF
VOUT = 0V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested
5
0780M–PLD–7/10
3.7
Power-up Reset
The registers in the Atmel® ATF22LV10C are designed to reset during power-up. At a point delayed slightly from
VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the
buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the following conditions are required:
1. The VCC rise must be monotonic and start below 0.7V
2. The clock must remain stable during TPR
3. After TPR, all input and feedback setup times must be met before driving the clock pin high
3.8
Preload of Register Outputs
The ATF22LV10C registers are provided with circuitry to allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC
file preload sequence will be done automatically by most of the approved programmers after the programming.
4.
Electronic Signature Word
There are 64-bits of programmable memory that are always available to the user, even if the device is secured.
These bits can be used for user-specific data.
5.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF22LV10C fuse patterns. Once programmed,
fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible.
The security fuse should be programmed last, as its effect is immediate.
6.
Programming/Erasing
Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware &
Software Support for information on software/programming.
Table 6-1.
7.
Programming/Erasing
Parameter
Description
Typ
Max
Units
TPR
Power-up Reset Time
600
1,000
ns
VRST
Power-up Reset Voltage
2.5
3.0
V
Input and I/O Pin-keeper
All ATF22V10C family members have internal input and I/O pin-keeper circuits. Therefore, whenever inputs or
I/Os are not being driven externally, they will maintain their last driven state. This ensures that all logic array inputs
and device outputs are at known states. These are relatively weak active circuits that can be easily overridden by
TTL-compatible drivers (see Input and I/O diagrams on page 7).
6
Atmel ATF22LV10C
0780M–PLD–7/10
Atmel ATF22LV10C
8.
Power-down Mode
The Atmel® ATF22LV10C includes an optional pin controlled power-down feature. When this mode is enabled, the
PD pin acts as the power-down pin (Pin 4 on the DIP/SOIC packages and Pin 5 on the PLCC package). When the
PD pin is high, the device supply current is reduced to less than 100mA. During power-down, all output data and
internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any
outputs which were in an undetermined state at the onset of power-down will remain at the same state. During
power-down, all input signals except the power-down pin are blocked. Input and I/O hold latches remain active to
insure that pins do not float to indeterminate levels, further reducing system power. The power-down pin feature is
enabled in the logic design file. Designs using the power-down pin may not use the PD pin logic array input.
However, all other PD pin macrocell resources may still be used, including the buried feedback and foldback
product term array inputs.
PD pin configuration is controlled by the design file, and appears as a separate fuse bit in the JEDEC file. When
the power-down feature is not specified in the design file, the IN/PD pin will be configured as a regular logic input.
Note:
Some programmers list the 22V10 JEDEC-compatible 22V10C (no PD used) separately from the non-22V10 JEDECcompatible 22V10CEX (with PD used).
Figure 8-1.
Input Diagram
VCC
100K
INPUT
ESD
PROTECTION
CIRCUIT
Figure 8-2.
I/O Diagram
VCC
OE
I/O
DATA
VCC
INPUT
100K
7
0780M–PLD–7/10
9.
Compiler Mode Selection
Table 9-1.
Compiler Mode Selection
PAL Mode
(5828 Fuses)
Power-down Mode(1)
(5893 Fuses)
Synario
Atmel ATF22C10C (DIP)
Atmel ATF22V10C (PLCC)
Atmel ATF22C10C DIO (UES)
Atmel ATF22V10C PLCC (UES)
Atmel ATF22C10C DIP (PWD)
Atmel ATF22C10V PLCC (PWD)
WINCUPL
P22V10
P22V10LCC
G22V10
G22V10LCC
G22V10CP
G22V10CPLCC
Note:
10.
GAL Mode
(5892 Fuses)
1. These device types will create a JEDEC file which when programmed in an Atmel ATF22V10C device will enable
the power-down mode feature. All other devices have this feature disabled.
Functional Logic Diagram Description
The functional logic diagram describes the Atmel® ATF22LV10C architecture.
The ATF22LV10C has twelve inputs and ten I/O macrocells. Each macrocell can be configured into one of four
output configurations: active high/low, registered/combinatorial output.The universal architecture of the
ATF22LV10C can be programmed to emulate most 24-pin PAL devices.
Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse,
when programmed, protects the contents of the ATF22LV10C. Eight bytes (64-fuses) of User Signature are
accessible to the user for purposes such as storing project name, part number, revision or date. The User
Signature is accessible regardless of the state of the security fuse.
8
Atmel ATF22LV10C
0780M–PLD–7/10
Atmel ATF22LV10C
Figure 10-1. Functional Logic Diagram Atmel ATF22LV10C
Note:
1. *Input not available if the power-down (PD) option is utilized
9
0780M–PLD–7/10
ATMEL ATF22LV10C
SUPPLY CURRENT VS. SUPPLY VOLTAGE (TA = 25°C)
ATMEL ATF22LV10C
NORMALIZED ICC VS. TEMP.
1.10
70.00
NORMALIZED ICC
ICC (mA)
60.00
50.00
40.00
30.00
20.00
10.00
0.00
1.00
0.90
0.80
3.00
3.30
3.60
-40.00
0.00
SUPPLY VOLTAGE (V)
25.00
75.00
TEMPERATURE (DEG. C)
ATMEL ATF22LV10C SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 3.3V, TA = 25°C)
ICC (mA)
75.00
50.00
25.00
0.00
0.00
10.00
20.00
50.00
FREQUENCY (MHz)
ATMEL ATF22LV10C OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE (VCC = 3.3V, TA = 25°C)
0.00
0.00
-2.00
-2.00
IOH (mA)
IOH (mA)
ATMEL ATF22LV10C OUTPUT SOURCE
CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V)
-4.00
-6.00
-8.00
-6.00
-8.00
-10.00
-10.00
3.00
-4.00
-12.00
3.15
3.30
3.45
3.60
2.00
2.20
2.40
SUPPLY VOLTAGE (V)
2.80
3.00
3.20
3.30
ATMEL ATF22LV10C OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE (VCC = 3.3V, TA = 25°C)
40.00
90.00
39.00
80.00
38.00
70.00
60.00
37.00
IOL (mA)
IOL (mA)
2.70
VOH (V)
ATMEL ATF22LV10C
OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V)
36.00
35.00
50.00
40.00
30.00
34.00
20.00
33.00
10.00
0.00
32.00
3.00
3.15
3.30
3.45
SUPPLY VOLTAGE (V)
10
2.60
3.60
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.30
OUTPUT VOLTAGE (V)
Atmel ATF22LV10C
0780M–PLD–7/10
Atmel ATF22LV10C
ATMEL ATF22LV10C INPUT CLAMP CURRENT VS.
INPUT VOLTAGE (VCC = 3.3V, TA = 25°C)
ATMEL ATF22LV10C INPUT CURRENT VS.
INPUT VOLTAGE (VCC = 3.3V, TA = 25°C)
15.00
0.00
INPUT CURRENT (µA)
INPUT CURRENT (mA)
20.00
-20.00
-40.00
-60.00
-80.00
-100.00
0.00
-0.20
-0.40
-0.60
-0.80
10.00
5.00
0.00
-5.00
-1.00
0.00
INPUT VOLTAGE (V)
1.50
2.00
2.50
3.00
3.50
4.00
NORMALIZED TPD VS. TEMP
1.15
1.20
1.10
1.15
NORMALIZED TPD
NORMALIZED TPD
1.00
INPUT VOLTAGE (V)
NORMALIZED TPD VS. VCC
1.05
1.00
0.95
0.90
0.85
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.80
3.00
0.50
3.15
3.30
3.45
-0.40
3.60
0.00
25.00
75.00
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
NORMALIZED TCO VS. TEMP
1.15
1.20
1.10
1.15
NORMALIZED TCO
NORMALIZED TCO
NORMALIZED TCO VS. VCC
1.05
1.00
0.95
0.90
0.85
1.05
1.00
0.95
0.90
0.85
0.80
0.80
3.00
1.10
3.15
3.30
3.45
-0.40
3.60
0.00
25.00
75.00
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
NORMALIZED TSU VS. TEMP
1.10
1.10
1.05
1.05
NORMALIZED TSU
NORMALIZED TSU
NORMALIZED TSU VS. VCC
1.00
0.95
0.90
0.85
0.80
3.00
1.00
0.95
0.90
0.85
0.80
3.15
3.30
SUPPLY VOLTAGE (V)
3.45
3.60
-0.40
0.00
25.00
75.00
TEMPERATURE (C)
11
0780M–PLD–7/10
ATMEL ATF22LV10C
DELTA TCO VS. OUTPUT LOADING
14.00
14.00
12.00
12.00
10.00
10.00
DELTA TCO (ns)
DELTA TPD (ns)
ATMEL ATF22LV10C
DELTA TPD VS. OUTPUT LOADING
8.00
6.00
4.00
2.00
0.00
-2.00
6.00
4.00
2.00
0.00
-2.00
-4.00
0.00
8.00
-4.00
50.00
100.00
150.00
200.00
250.00
300.00
0.00
50.00
OUTPUT LOADING (PF)
0.00
-0.10
-0.10
DELTA TCO (ns)
DELTA TPD (ns)
200.00
250.00
300.00
ATMEL ATF22LV10C DELTA TCO VS.
NUMBER OF OUTPUT SWITCHING
0.00
-0.20
-0.30
-0.40
-0.50
-0.20
-0.30
-0.40
-0.50
2.00
3.00
4.00
5.00
6.00
7.00
8.00
NUMBER OF OUTPUTS SWITCHING
12
150.00
OUTPUT LOADING (PF)
ATMEL ATF22LV10C DELTA TPD VS.
NUMBER OF OUTPUT SWITCHING
1.00
100.00
9.00 10.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
9.00 10.00
NUMBER OF OUTPUTS SWITCHING
Atmel ATF22LV10C
0780M–PLD–7/10
Atmel ATF22LV10C
11.
Ordering Information
11.1
Ordering Code Detail
tPD
(ns)
10
10
tS
(ns)
7.5
7.5
12
tCO
(ns)
Ordering Code
Package
Operation Range
7.5
ATF22LV10C-10JC
ATF22LV10C-10PC
ATF22LV10C-10SC
ATF22LV10C-10XC
28J
24P3
24S
24X
Commercial
(0C to 70C)
7.5
ATF22LV10C-10JI
ATF22LV10C-10PI
ATF22LV10C-10SI
ATF22LV10C-10XI
28J
24P3
24S
24X
Industrial
(0C to 85C)
10
ATF22LV10C-15JC
ATF22LV10C-15PC
ATF22LV10C-15SC
ATF22LV10C-15XC
28J
24P3
24S
24X
Commercial
(0C to 70C)
10
ATF22LV10C-15JI
ATF22LV10C-15PI
ATF22LV10C-15SI
ATF22LV10C-15XI
28J
24P3
24S
24X
Industrial
(-40C to +85C)
15
12
Note:
11.2
Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD
(ns)
10
11.3
Lead based packages will become obsolete, and are not recommended for new designs
tS
(ns)
7.5
tCO
(ns)
7.5
Ordering Code
ATF22LV10C-10JU
ATF22LV10C-10PU
ATF22LV10C-10SU
ATF22LV10C-10XU
Package
Operation Range
28J
24P3
24S
24X
Industrial
(0C to +85C)
Using “C” Product for Industrial
To use commercial product for industrial temperature ranges, simply de-rate ICC by 15% on the “C” device. No
speed de-rating is necessary.
Package Type
28J
28-lead, Plastic J-leaded Chip Carrier (PLCC)
24P3
24-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
24S
24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
24X
24-lead, 4.4mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
13
0780M–PLD–7/10
12.
Package Information
12.1
28J – PLCC
1.14(0.045) X 45°
PIN NO. 1
1.14(0.045) X 45°
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
E
D2/E2
B1
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45° MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AB.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102mm) maximum.
MIN
MAX
NOM
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
12.319
–
12.573
D1
11.430
–
11.582
E
12.319
–
12.573
E1
11.430
–
11.582
D2/E2
9.906
–
10.922
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
Package Drawing Contact:
[email protected]
14
TITLE
28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
28J
B
Atmel ATF22LV10C
0780M–PLD–7/10
Atmel ATF22LV10C
12.2
24P3 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
C
eC
eB
Notes:
1.
2.
This package conforms to JEDEC reference MS-001, Variation AF.
Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25mm (0.010").
SYMBOL
MIN
NOM
MAX
A
–
–
5.334
A1
0.381
–
–
D
31.623
–
32.131
E
7.620
–
8.255
E1
6.096
–
7.112
B
0.356
–
0.559
B1
1.270
–
1.651
L
2.921
–
3.810
C
0.203
–
0.356
eB
–
–
10.922
eC
0.000
–
1.524
e
NOTE
Note 2
Note 2
2.540 TYP
6/1/04
Package Drawing Contact:
[email protected]
TITLE
24P3, 24-lead (0.300"/7.62mm Wide) Plastic Dual
Inline Package (PDIP)
DRAWING NO.
24P3
REV.
D
15
0780M–PLD–7/10
12.3
24S – SOIC
B
D1
D
PIN 1 ID
PIN 1
e
E
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A1
0
8
L1
L
MIN
NOM
MAX
A
–
–
2.65
A1
0.10
–
0.30
D
10.00
–
10.65
D1
7.40
–
7.60
E
15.20
–
15.60
B
0.33
–
0.51
L
0.40
–
1.27
L1
0.23
–
0.32
e
NOTE
1.27 BSC
06/17/2002
Package Drawing Contact:
[email protected]
16
TITLE
24S, 24-lead (0.300" body) Plastic Gull Wing Small
Outline (SOIC)
DRAWING NO.
REV.
24S
B
Atmel ATF22LV10C
0780M–PLD–7/10
Atmel ATF22LV10C
12.4
24X – TSSOP
Dimensions in Millimeter and (Inches)*
JEDEC STANDARD MO-153 AD
Controlling dimension: millimeters
0.30(0.012)
0.19(0.007)
4.48(0.176)
6.50(0.256)
4.30(0.169)
6.25(0.246)
PIN 1
0.65(0.0256)BSC
7.90(0.311)
1.20(0.047)MAX
7.70(0.303)
0.15(0.006)
0.05(0.002)
0
0.20(0.008)
8
0.09(0.004)
0.75(0.030)
0.45(0.018)
04/11/2001
Package Drawing Contact:
[email protected]
TITLE
24X, 24-lead (4.4mm body width) Plastic Thin Shrink
Small Outline Package (TSSOP)
DRAWING NO.
REV.
24X
A
17
0780M–PLD–7/10
13.
18
Revision History
Doc. Rev.
Date
Comments
0780M
07/2010
Update the standby current parameters for Powerdown mode from 100µA to 120µA.
Shade Ordering Package Option table and add note, “Lead based packages will become
obsolete and are not recommended for new designs.”
0780L
12/2005
Add Green Package options
Atmel ATF22LV10C
0780M–PLD–7/10
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0780M–PLD–7/10
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