ATA6662C - Complete

ATA6662C
LIN Transceiver
DATASHEET
Features
● Operating range from 5V to 27V
● Baud rate up to 20Kbaud
● Improved slew rate control according to LIN specification 2.0, 2.1 and SAEJ2602-2
● Fully compatible with 3.3V and 5V devices
● Dominant time-out function at transmit data (TXD)
● Normal and Sleep Mode
● Wake-up capability via LIN Bus (90µs dominant)
● External wake-up via WAKE pin (35µs low level)
● Control of external voltage regulator via INH pin
● Very low standby current during sleep mode (10µA)
● Wake-up source recognition
● Bus pin short-circuit protected versus GND and battery
● LIN input current < 2µA if VBAT is disconnected
● Overtemperature protection
● High EMC level
● Interference and damage protection according to ISO/CD 7637
● Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications
Rev.1.0”
4916S-AUTO-09/14
1.
Description
The Atmel® ATA6662C is a fully integrated LIN transceiver complying with the LIN specification 2.0, 2.1 and SAEJ2602-2. It
interfaces the LIN protocol handler and the physical layer. The device is designed to handle the low-speed data
communication in vehicles, for example, in convenience electronics. Improved slope control at the LIN driver ensures secure
data communication up to 20Kbaud. Sleep Mode guarantees minimal current consumption. The Atmel ATA6662C has
advanced EMI and ESD performance.
Figure 1-1. Block Diagram
RXD
7
VS
6
LIN
5
GND
Receiver
1
+
Filter
Wake up bus timer
TXD
4
TXD
Time-Out
timer
Short circuit and
overtemperature
protection
Slew rate control
VS
VS
Control unit
WAKE
3
Wake-up
timer
Standby mode
2
EN
2
ATA6662C [DATASHEET]
4916S–AUTO–09/14
8
INH
2.
Pin Configuration
Figure 2-1. Pinning SO8
RXD
EN
WAKE
TXD
Table 2-1.
1
2
3
4
8
7
6
5
INH
VS
LIN
GND
Pin Description
Pin
Symbol
1
RXD
Function
Receive data output (open drain)
2
EN
Enables Normal Mode; when the input is open or low, the device is in Sleep Mode
3
WAKE
High voltage input for local wake-up request. If not needed, connect directly to VS
4
TXD
Transmit data input; active low output (strong pull-down) after a local wake-up request
5
GND
Ground, heat sink
6
LIN
LIN bus line input/output
7
VS
Battery supply
8
INH
Battery-related inhibit output for controlling an external voltage regulator; active high after a
wake-up request
ATA6662C [DATASHEET]
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3
3.
Functional Description
3.1
Physical Layer Compatibility
Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical
layer according to revision 2.x can be mixed with LIN physical layer nodes, which, according to older versions (i.e., LIN 1.0,
LIN 1.1, LIN 1.2, LIN 1.3), are without any restrictions.
3.2
Supply Pin (VS)
Undervoltage detection is implemented to disable transmission if VS falls to a value below 5V in order to avoid false bus
messages. After switching on VS, the IC switches to Fail-safe Mode and INHIBIT is switched on. The supply current in Sleep
Mode is typically 10µA.
3.3
Ground Pin (GND)
The Atmel® ATA6662C does not affect the LIN Bus in the case of a GND disconnection. It is able to handle a ground shift up
to 11.5% of VS.
3.4
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown and an internal pull-up resistor are implemented as
specified for LIN 2.x. The voltage range is from –27V to +40V. This pin exhibits no reverse current from the LIN bus to VS,
even in the case of a GND shift or VBatt disconnection. The LIN receiver thresholds are compatible to the LIN protocol
specification.The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope controlled.
The output has a self-adapting short circuit limitation; that is, during current limitation, as the chip temperature increases, the
current is reduced.
3.5
Input/Output Pin (TXD)
In Normal Mode the TXD pin is the microcontroller interface to control the state of the Lin output. TXD must be at Low- level
in order to have a low LIN Bus. If TXD is high, the LIN output transistor is turned off and the Bus is in recessive state. The
TXD pin is compatible to both a 3.3V or 5V supply. During fail-safe Mode, this pin is used as output and is signalling the
wake-up source (see Section 3.14 “Wake-up Source Recognition” on page 7). It is current limited to < 8mA.
3.6
TXD Dominant Time-out Function
The TXD input has an internal pull-down resistor. An internal timer prevents the bus line from being driven permanently in
dominant state. If TXD is forced to low longer than tDOM > 6ms, the pin LIN will be switched off (Recessive Mode). To reset
this mode, switch TXD to high (> 10µs) before switching LIN to dominant again.
3.7
Output Pin (RXD)
This pin reports to the microcontroller the state of the LIN bus. LIN high (recessive) is reported by a high level at RXD, LIN
low (dominant) is reported by a low voltage at RXD. The output is an open drain, therefore, it is compatible to a 3.3V or 5V
power supply. The AC characteristics are defined with a pull-up resistor of 5k to 5V and a load capacitor of 20pF. The
output is short-protected. In Unpowered Mode (VS = 0V), RXD is switched off. For ESD protection a Zener diode is
integrated, with VZ = 6.1V.
3.8
Enable Input Pin (EN)
This pin controls the Operation Mode of the interface. If EN = 1, the interface is in Normal Mode, with the transmission path
from TXD to LIN and from LIN to RXD both active. At a falling edge on EN, while TXD is already set to high, the device is
switched to Sleep Mode and no transmission is possible. In Sleep Mode, the LIN bus pin is connected to VS with a weak pullup current source. The device can transmit only after being woken up (see Section 3.9 “Inhibit Output Pin (INH)” on page 5).
During Sleep Mode the device is still supplied from the battery voltage. The supply current is typically 10µA. The pin EN
provides a pull-down resistor in order to force the transceiver into Sleep Mode in case the pin is disconnected.
4
ATA6662C [DATASHEET]
4916S–AUTO–09/14
3.9
Inhibit Output Pin (INH)
This pin is used to control an external switchable voltage regulator having a wake-up input. The inhibit pin provides an
internal switch towards pin VS. If the device is in Normal Mode, the inhibit high-side switch is turned on and the external
voltage regulator is activated. When the device is in Sleep Mode, the inhibit switch is turned off and disables the voltage
regulator.
A wake-up event on the LIN bus or at pin WAKE will switch the INH pin to the VS level. After a system power-up (VS rises
from zero), the pin INH switches automatically to the VS level.
3.10
Wake-up Input Pin (WAKE)
This pin is a high-voltage input used to wake the device up from Sleep Mode. It is usually connected to an external switch in
the application to generate a local wake-up. A pull-up current source with typically –10µA is implemented. The voltage
threshold for a wake-up signal is 3V below the VS voltage with an output current of typically –3µA.
If you do not need a local wake-up in your application, connect pin WAKE directly to pin VS.
3.11
Operation Modes
1.
Normal Mode
This is the normal transmitting and Receiving Mode. All features are available.
2.
Sleep Mode
In this mode the transmission path is disabled and the device is in low power mode. Supply current from VBatt is
typically 10µA. A wake-up signal from the LIN bus or via pin WAKE will be detected and will switch the device to
Fail-safe Mode. If EN then switches to high, Normal Mode is activated. Input debounce timers at pin WAKE
(tWAKE), LIN (tBUS) and EN (tsleep,tnom) prevent unwanted wake-up events due to automotive transients or EMI. In
Sleep Mode the INH pin is left floating. The internal termination between pin LIN and pin VS is disabled. Only a
weak pull-up current (typical 10µA) between pin LIN and pin VS is present. The Sleep Mode can be activated independently from the actual level on pin LIN or WAKE.
3.
Fail-safe Mode
At system power-up or after a wake-up event, the device automatically switches to Fail- safe Mode. It switches the
INH pin to a high state, to the VS level. LIN communication is switched off. The microcontroller of the application
will then confirm the Normal Mode by setting the EN pin to high.
4.
Unpowered Mode
If you connect battery voltage to the application circuit, the voltage at the VS pin increases according to the block
capacitor. After VS is higher than the VS undervoltage threshold VSth, the IC mode changes from Unpowered
Mode to Fail-safe Mode. Then the LIN driver is switched off, but the LIN receiver is active, if the TXD pin is at low
level.
Figure 3-1. Mode of Operation
a: VS > 5V
b: VS < 5V
c: Bus wake-up event
d: Wake-up from wake switch
Unpowered Mode
VBatt = 0V
b
a
Fail-safe Mode
INH: high (INH internal high-side switch ON)
Communication: OFF
b
b
c
EN = 1
d
Go to sleep command
EN = 0; after 1 → 0 while TXD = 1
Normal Mode
INH: high (INH HS switch ON)
Communication: ON
Sleep Mode
EN = 1
Local wake-up event
INH: high impedence (INH HS switch OFF)
Communication: OFF
ATA6662C [DATASHEET]
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Table 3-1.
Table of Modes
Mode of Operation
Transceiver
INH
RXD
LIN
Fail-safe
Off
On
High, except after
wake up
Recessive
Normal
On
On
LIN depending
TXD depending
Sleep
Off
Off
High ohmic
Recessive
Wake-up events from Sleep Mode:
● LIN bus
●
●
●
EN pin
WAKE pin
VS undervoltage
Figure 3-1 on page 5, Figure 3-2 and Figure 3-3 on page 7 show details of wake-up operations.
3.12
Remote Wake-up via Dominant Bus State
A voltage less than the LIN pre-wake detection VLINL at pin LIN activates the internal LIN receiver and switches on the
internal slave termination between the LIN pin and the VS pin.
A falling edge at pin LIN, followed by a dominant bus level VBUSdom maintained for a certain time period (tBUS) and a rising
edge at pin LIN results in a remote wake-up request. The device switches to Fail-safe Mode. Pin INH is activated (switches
to VS) and the internal termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD
to interrupt the microcontroller (see Figure 3-2 on page 6).
Figure 3-2. LIN Wake-up Waveform Diagram
Bus wake-up filtering time
(tBUS)
LIN bus
High
INH
Low or floating
RXD
High or floating
Low
External
voltage
regulator
Off state
Regulator wake-up time delay
EN High
EN
Node in sleep state
Microcontroller start-up
delay time
6
ATA6662C [DATASHEET]
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Normal
Mode
3.13
Local Wake-up via Pin WAKE
A falling edge at pin WAKE, followed by a low level maintained for a certain time period (tWAKE), results in a local wake-up
request. The wake-up time (tWAKE) ensures that no transient, according to ISO7637, creates a wake-up. The device switches
to Fail-safe Mode. Pin INH is activated (switches to VS) and the internal termination resistor is switched on. The local wakeup request is indicated by a low level at pin RXD to interrupt the microcontroller and a strong pull-down at pin TXD (see
Figure 3-3). The voltage threshold for a wake-up signal is 3V below the VS voltage with an output current of typical –3µA.
Even in the case of a continuous low at pin WAKE it is possible to switch the IC into Sleep Mode via a low at pin EN. The IC
will stay in Sleep Mode for an unlimited time. To generate a new wake up at pin WAKE it needs first a high signal > 6µs
before a negative edge starts the wake-up filtering time again.
Figure 3-3. Wake-up from Wake-up Switch
Wake pin
INH
State change
Low or floating
RXD
High or floating
TXD
TXD weak pull-down resistor
High
Low
High
TXD strong pull-down
Weak
pull-down
Wake filtering time
tWAKE
Voltage
regulator
On state
Off state
Regulator wake-up time delay
EN
Node in
operation
EN High
Node in sleep state
Microcontroller start-up
delay time
3.14
Wake-up Source Recognition
The device can distinguish between a local wake-up request (pin WAKE) and a remote wake-up request (LIN bus). The
wake-up source can be read on pin TXD in Fail-safe Mode. If an external pull-up resistor (typically 5k) has been added on
pin TXD to the power supply of the microcontroller, a high level indicates a remote wake-up request (weak pull-down at pin
TXD) and a low level indicates a local wake-up request (strong pull-down at pin TXD).
The wake-up request flag (signalled on pin RXD) as well as the wake-up source flag (signalled on pin TXD) are reset
immediately if the microcontroller sets pin EN to high (see Figure 3-2 on page 6 and Figure 3-3).
ATA6662C [DATASHEET]
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3.15
8
Fail-safe Features
●
The reverse current is < 2µA at pin LIN during loss of VBAT; this is optimal behavior for bus systems where some slave
nodes are supplied from battery or ignition.
●
●
●
●
Pin EN provides a pull-down resistor to force the transceiver into Sleep Mode if EN is disconnected.
●
The implemented hysteresis, Thys, enables the LIN output again after the temperature has been decreased.
Pin RXD is set floating if VBAT is disconnected.
Pin TXD provides a pull-down resistor to provide a static low if TXD is disconnected.
The LIN output driver has a current limitation, and if the junction temperature Tj exceeds the thermal shut-down
temperature Toff, the output driver switches off.
ATA6662C [DATASHEET]
4916S–AUTO–09/14
4.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Typ.
Max.
Unit
VS
- Continuous supply voltage
–0.3
+40
V
Wake DC and transient voltage (with 33-k serial resistor)
- Transient voltage due to ISO7637 (coupling 1nF)
–1
–150
+40
+100
V
V
Logic pins (RXD, TXD, EN)
–0.3
+5.5
V
LIN
- DC voltage
- Transient voltage due to ISO7637 (coupling 1nF)
–27
–150
+40
+100
V
V
INH
- DC voltage
–0.3
VS + 0.3
V
ESD according to IBEE LIN EMC
Test specification 1.0 following IEC 61000-4-2
- Pin VS, LIN to GND
- Pin WAKE (33k serial resistor)
±6
±5
KV
KV
ESD HBM following STM5.1
with 1.5k/100pF
- Pin VS, LIN, WAKE, INH to GND
±6
KV
±3
KV
CDM ESD STM 5.3.1
±750
V
Machine Model ESD
AEC-Q100-RevF(003)
±100
V
HBM ESD
ANSI/ESD-STM5.1
JESD22-A114
AEC-Q100 (002)
Junction temperature
Tj
–40
+150
°C
Storage temperature
Tstg
–55
+150
°C
Symbol
Min.
Max.
Unit
145
K/W
5.
Thermal Characteristics
Parameters
Thermal resistance junction ambient
RthJA
Special heat sink at GND (pin 5) on PCB (fused lead
frame to pin 5)
RthJA
Typ.
80
K/W
Thermal shutdown
Toff
150
165
180
°C
Thermal shutdown hysteresis
Thys
5
10
20
°C
ATA6662C [DATASHEET]
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9
6.
Electrical Characteristics
5V < VS < 27V, Tj = –40°C to +150°C
No.
1
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
7
VS
5
13.5
27
V
A
Sleep Mode
VLIN > VS – 0.5V
VS < 14V
7
IVSsleep
10
20
µA
A
Bus recessive
VS < 14V
7
IVSrec
0.9
1.3
mA
A
1.2
2
mA
A
VS Pin
1.1
DC voltage range nominal
1.2
Supply current in Sleep Mode
1.3
1.4
Supply current in Normal Mode Bus dominant
VS < 14V
Total bus load > 500
7
IVSdom
1.5
Supply current in Fail-safe
Mode
7
IVSfail
0.5
1.1
mA
A
1.6
VS undervoltage threshold on
VSth
4
4.95
V
A
1.7
VS undervoltage threshold off
VSth
4.05
5
V
A
1.8
VS undervoltage threshold
hysteresis
7
VSth_hys
50
500
mV
A
1.3
8
mA
A
0.4
V
A
Bus recessive
VS < 14V
2
RXD Output Pin (Open Drain)
2.1
Low-level output sink current
Normal Mode
VLIN = 0V, VRXD = 0.4V
1
IRXDL
2.2
RXD saturation voltage
5-k pull-up resistor to 5V
1
VsatRXD
2.3
High-level leakage current
Normal Mode
VLIN = VBAT, VRXD = 5V
1
IRXDH
–3
+3
µA
A
2.4
ESD zener diode
IRXD = 100µA
1
VZRXD
5.8
8.6
V
A
3
2.5
TXD Input Pin
3.1
Low-level voltage input
4
VTXDL
–0.3
+0.8
V
A
3.2
High-level voltage input
4
VTXDH
2
5.5
V
A
3.3
Pull-down resistor
VTXD = 5V
4
RTXD
125
600
k
A
3.4
Low-level leakage current
VTXD = 0V
4
ITXD_leak
–3
+3
µA
A
Low-level output sink current
Fail-safe Mode, local wake up
VTXD = 0.4V
VLIN = VBAT
4
ITXD
1.3
8
mA
A
3.5
4
250
2.5
EN Input Pin
4.1
Low-level voltage input
2
VENL
–0.3
+0.8
V
A
4.2
High-level voltage input
2
VENH
2
5.5
V
A
4.3
Pull-down resistor
VEN = 5V
2
REN
125
600
k
A
4.4
Low-level input current
VEN = 0V
2
IEN
–3
+3
µA
A
5
250
INH Output Pin
5.1
High-level voltage
Normal Mode
IINH = –2mA
8
VINHH
VS – 3
VS
V
A
5.2
Leakage current
Sleep Mode
VINH = 0V/27V, VS = 27V
8
IINHL
–3
+3
µA
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
10
ATA6662C [DATASHEET]
4916S–AUTO–09/14
6.
Electrical Characteristics (Continued)
5V < VS < 27V, Tj = –40°C to +150°C
No.
6
Parameters
Test Conditions
Pin
Symbol
Min.
3
VWAKEH
Typ.
Max.
Unit
Type*
VS –
1V
VS +
0.3V
V
A
VS –
3.3V
V
A
WAKE Pin
6.1
High-level input voltage
6.2
Low-level input voltage
IWAKE = Typically –3µA
3
VWAKEL
–1V
6.3
Wake pull-up current
VS < 27V
3
IWAKE
–30
µA
A
6.4
High-level leakage current
VS = 27V, VWAKE = 27V
3
IWAKE
–5
+5
µA
A
0.9 VS
VS
V
A
7
–10
LIN Bus Driver
7.1
Driver recessive output voltage RLOAD = 500 / 1k
6
VBUSrec
7.2
Driver dominant voltage
VBUSdom_DRV_LoSUP
VVS = 7V, Rload = 500
6
V_LoSUP
1.2
V
A
7.3
Driver dominant voltage
VBUSdom_DRV_HiSUP
VVS = 18V, Rload = 500
6
V_HiSUP
2
V
A
7.4
Driver dominant voltage
VBUSdom_DRV_LoSUP
VVS = 7V, Rload = 1000
6
V_LoSUP_1k
0.6
V
A
7.5
Driver dominant voltage
VBUSdom_DRV_HiSUP
VVS = 18V, Rload = 1000
6
V_HiSUP_1k_
0.8
V
A
7.6
Pull-up resistor to VS
The serial diode is mandatory
6
RLIN
20
60
k
A
7.7
Voltage drop at the serial
diodes
In pull-up path with Rslave
ISerDiode = 10mA
6
VSerDiode
0.4
1.0
V
D
7.8
LIN current limitation
VBUS = VBAT_max
6
IBUS_LIM
40
200
mA
A
7.9
Input leakage current at the
receiver, including pull-up
resistor as specified
6
IBUS_PAS_dom
–1
mA
A
7.10
Driver off
8V < VBAT < 18V
Leakage current LIN recessive
8V < VBUS < 18V
VBUS ≥ VBAT
6
IBUS_PAS_rec
7.11
Leakage current at ground loss;
Control unit disconnected from
GNDDevice = VS
ground; Loss of local ground
VBAT =12V
must not affected
0V < VBUS < 18V
communication in the residual
network
6
IBUS_NO_gnd
7.12
Leakage current at loss of
battery; Node has to substain
VBAT disconnected
the current that can flow under VSUP_Device = GND
this condition; Bus must remain 0V < VBUS < 18V
operational under this condition
6
IBUS_NO_bat
7.13
Capacitance on pin LIN to GND
6
CLIN
Input leakage current
Driver off
VBUS = 0V, VS = 12V
–10
30
120
10
20
µA
A
+0.5
+10
µA
A
0.1
2
µA
A
20
pF
D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA6662C [DATASHEET]
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11
6.
Electrical Characteristics (Continued)
5V < VS < 27V, Tj = –40°C to +150°C
No.
8
Parameters
Test Conditions
Pin
Symbol
Min.
Max.
Unit
Type*
0.525
VS
V
A
0.4 
VS
V
A
LIN Bus Receiver
0.475  0.5
VS
VS
8.1
Center of receiver threshold
VBUS_CNT =
(Vth_dom + Vth_rec) / 2
6
VBUS_CNT
8.2
Receiver dominant state
VEN = 5V
6
VBUSdom
–27
8.3
Receiver recessive state
VEN = 5V
6
VBUSrec
0.6 VS
6
VBUShys
0.028 
VS
6
VLINH
Switches the LIN receiver on
6
8.4
Receiver input hysteresis
8.5
Pre-wake detection LIN
High-level input voltage
8.6
Pre-wake detection LIN
Low-level input voltage
9
Typ.
VHYS = Vth_rec – Vth_dom
40
V
A
0.175
VS
V
A
VS –
2V
VS +
0.3V
V
A
VLINL
–27V
VS –
3.3V
V
A
0.1 
VS
Internal Timers
9.1
Dominant time for wake-up via
LIN bus
VLIN = 0V
6
tBUS
30
90
150
µs
A
9.2
Time of low pulse for wake-up
via pin WAKE
VWAKE = 0V
3
tWAKE
7
35
50
µs
A
9.3
Time delay for mode change
from Fail-safe Mode to Normal
Mode via pin EN
VEN = 5V
2
tnorm
2
7
15
µs
A
9.4
Time delay for mode change
from Normal Mode into Sleep
Mode via pin EN
VEN = 0V
2
tsleep
2
7
12
µs
A
9.5
TXD dominant time out time
VTXD = 0V
4
tdom
6
9
20
ms
A
9.6
Power-up delay between
VS = 5V until INH switches to
high
VVS = 5V
200
µs
A
tVS
LIN Bus Driver AC Parameter with Different Bus Loads
10
10.1
10.2
10.3
Load 1 (small): 1nF, 1k ; Load 2 (large): 10nF, 500 ; RRXD = 5k ; CRXD = 20pF;
Load 3 (medium): 6.8nF, 660 characterized on samples; 10.1 and 10.2 specifies the timing parameters for proper
operation at 20Kbit/s, 10.3 and 10.4 at 10.4Kbit/s.
Duty cycle 1
THRec(max) = 0.744  VS
THDom(max) = 0.581  VS
VS = 7.0V to 18V
tBit = 50µs
D1 = tbus_rec(min) / (2  tBit)
6
D1
Duty cycle 2
THRec(min) = 0.422  VS
THDom(min) = 0.284  VS
VS = 7.0V to 18V
tBit = 50µs
D2 = tbus_rec(max) / (2  tBit)
6
D2
Duty cycle 3
THRec(max) = 0.778  VS
THDom(max) = 0.616  VS
VS = 7.0V to 18V
tBit = 96µs
D3 = tbus_rec(min) / (2  tBit)
6
D3
0.396
A
0.581
0.417
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
12
ATA6662C [DATASHEET]
4916S–AUTO–09/14
A
A
6.
Electrical Characteristics (Continued)
5V < VS < 27V, Tj = –40°C to +150°C
No.
10.4
11
Parameters
Test Conditions
Duty cycle 4
THRec(min) = 0.389  VS
THDom(min) = 0.251  VS
VS = 7.0V to 18V
tBit = 96µs
D4 = tbus_rec(max) / (2  tBit)
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
6
D4
0.590
6
µs
A
+2
µs
A
A
Receiver Electrical AC Parameters of the LIN Physical Layer
LIN receiver, RXD load conditions: CRXD = 20pF, Rpull-up = 5k
11.1
Propagation delay of receiver
(see Figure 6-1)
trec_pd = max(trx_pdr, trx_pdf)
VS = 7.0V to 18V
1
trx_pd
11.2
Symmetry of receiver
propagation delay rising edge
minus falling edge
trx_sym = trx_pdr – trx_pdf
VS = 7.0V to 18V
1
trx_sym
–2
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Figure 6-1. Definition of Bus Timing Parameter
tBit
tBit
tBit
TXD
(Input to transmitting node)
tBus_dom(max)
tBus_rec(min)
Thresholds of
receiving node 1
THRec(max)
VS
(Transceiver supply
of transmitting node)
THDom(max)
LIN Bus Signal
Thresholds of
THRec(min)
receiving node 2
THDom(min)
tBus_dom(min)
tBus_rec(max)
RXD
(Output of receiving node 1)
trx_pdf(1)
trx_pdr(1)
RXD
(Output of receiving node 2)
trx_pdr(2)
trx_pdf(2)
ATA6662C [DATASHEET]
4916S–AUTO–09/14
13
Figure 6-2. Application Circuit
Master node
pull-up
VBATTERY
22μF
100nF
12V
1k
7
ATA6662C
5kΩ
VDD
VS
Receiver
1
LIN sub bus
5V
RXD
Filter
Microcontroller
LIN
Wake-up bus timer
4
TXD
Time-out
timer
TXD
GND IO
33kΩ
14
ATA6662C [DATASHEET]
4916S–AUTO–09/14
3
WAKE
Slew rate control
Short-circuit and
overtemperature
protection
220pF
VS
VS
Control unit
10kΩ
External
switch
6
Wake-up
timer
5
Sleep mode
GND
2
8
EN
INH
7.
Ordering Information
Extended Type Number
Package
ATA6662C-GAQW
LIN transceiver, Pb-free, 4k, taped and reeled
Package Information
E1
L
A
b
A2
C
D
A1
8.
SO8
Remarks
e
8
E
5
technical drawings
according to DIN
specifications
Dimensions in mm
1
4
COMMON DIMENSIONS
Pin 1 identity
(Unit of Measure = mm)
Symbol
MIN
NOM
MAX
A
1.5
1.65
1.8
A1
A2
0.1
1.4
0.15
1.47
0.25
1.55
D
4.8
4.9
5
E
5.8
6
6.2
E1
3.8
3.9
4
L
0.4
0.65
0.9
C
0.15
0.2
0.25
b
e
0.3
0.4
0.5
NOTE
1.27 BSC
05/08/14
TITLE
Package Drawing Contact:
[email protected]
Package: SO8
GPC
DRAWING NO.
REV.
6.543-5185.01-4
1
ATA6662C [DATASHEET]
4916S–AUTO–09/14
15
9.
Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No.
4916S-AUTO-09/14
History
● Section 7 “Ordering Information” on page 15 updated
● Section 8 “Package Information” on page 15 updated
4916R-AUTO-04/14
● Put datasheet in the latest template
4916Q-AUTO-02/13
● Section 7 “Ordering Information” on page 15 updated
4916P-AUTO-10/11
● Section 3.11 “Operation Modes” on page 5 changed
4916O-AUTO-05/10
● Features on page 1 changed
● Heading 3.6: text changed
● Features on page 1 changed
4916N-AUTO-03/10
● Section 4 “Absolute Maximum Ratings” on page 9 changed
● Section 6 “Electrical Characteristics” number 7.13 on page 11 added
● Section 7 “Ordering Information” on page 16 changed
● Figure 1-1 “Block Diagram” on page 1 changed
4916M-AUTO-09/09
● Section 4 “Absolute Maximum Ratings” on page 8 changed
● Figure 6-2 “Application Circuit” on page 14 changed
4916L-AUTO-02/09
● Section 6 “El.Characteristics” numbers 3.2 and 4.2 on page 9 changed
● Figure 2-1 “Pinning SO8” on page 2 changed
● Section 3.2 “Supply Pin (VS)” on page 3 changed
● Section 3.8 “Enable Input Pin (EN)” on page 4 changed
● Section 3.11 “Operation Modes” on page 5 changed
● Section 3.12 “Remote Wake-up via Dominant Bus State” on page 5 changed
4916K-AUTO-12/08
● Section 3.14 “Wake-up Source Recognition” on page 6 changed
● Figure 3.2 “LIN Wake-up Waveform Diagram” on page 7 changed
● Figure 3.3 “Wake-up from Wake-up Switch” on page 7 changed
● Section 4 “Absolute Maximum Ratings” on page 8 changed
● Section 5 “Thermal Resistance” on page 8 changed
● Section 6 “Electrical Characteristics” on pages 9 to 12 changed
● Figure 6-2 “Application Circuit” on page 13 changed
● “Pre-normal Mode” in “Fail-safe Mode” changed
4916J-AUTO-02/08
● Section 3.9 “Inhibit Output Pin (INH) on page 4 changed
● Section 4 “Absolute Maximum Ratings” on page 8 changed
● Section 6 “Electrical Characteristics” number 5.1 on page 9 changed
4916I-AUTO-12/07
4916H-AUTO-10/07
4916G-AUTO-07/07
16
● Section 3.1 “Physical Layer Compatibility” on page 3 added
● Section 6 “El.Characteristics” numbers 1.5, 1.6 and 1.7 on page 9 changed
● Section 7 “Ordering Information” on page 14 changed
● Put datasheet in a new template
● Capital T for time generally changed in a lower case t
ATA6662C [DATASHEET]
4916S–AUTO–09/14
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document. (Continued)
Revision No.
History
● Figure 1-1 “Block Diagram” on page 1 changed
4916F-AUTO-05/07
● Figure 6-2 “Application Circuit” on page 13 changed
● Features on page 1 changed
● Section 6 “El.Characteristics” numbers 10.1 to 10.4 and 11.1, 11.2 changed
4916E-AUTO-02/07
● Section 4 “Absolute Maximum Ratings” on page 8 changed
● Section 2 “Electrical Characteristics” on pages 9 to 11 changed
● Features on page 1 changed
● Section 1 “Description” on page 1 changed
● Table 2-1 “Pin Description” on page 2 changed
● Section 3.2 “Ground Pin (GND) on page 3 changed
4916D-AUTO-02/07
● Section 3.7 “Enable Input Pin (EN)” on page 4 changed
● Section 3.11 “Remote Wake-up via Dominant Bus State” on page 5 changed
● Figure 3-1 “Mode of Operation” on page 6 changed
● Section 3-14 “Fail-safe Features” on page 6 changed
● Section 4 “Absolute Maximum Ratings” on page 8 changed
● Section 6 “Electrical Characteristics” on pages 9 to 11 changed
ATA6662C [DATASHEET]
4916S–AUTO–09/14
17
XXXXXX
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