AT24C01D and AT24C02D I2C-Compatible (2-wire) Serial EEPROM 1-Kbit (128 x 8) or 2-Kbit (256 x 8) DATASHEET Features Low Voltage Operation ̶ 1.7V (VCC = 1.7V to 3.6V) Internally Organized 128 x 8 (1K) or 256 x 8 (2K) I2C-Compatible (2-wire) Serial Interface ̶ 100kHz Standard Mode, 1.7V to 3.6V 400kHz Fast Mode, 1.7V to 3.6V 1MHz Fast Mode Plus (FM+), 2.5V to 3.6V ̶ ̶ Schmitt Triggers, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol Write Protect Pin for Full Array Hardware Data Protection Ultra Low Active Current (1mA max) and Standby Current (0.8μA max) 8-byte Page Write Mode ̶ Partial Page Writes Allowed Random and Sequential Read Modes Self-timed Write Cycle Within 5ms max High Reliability ̶ Endurance: 1,000,000 Write Cycles Data Retention: 100 Years ̶ Green Package Options (Lead-free/Halide-free/RoHS Compliant) ̶ 8-lead SOIC, 8-lead TSSOP, 8-pad UDFN, 8-lead PDIP(1), 5-lead SOT23, and 8-ball VFBGA Die Sale Options: Wafer Form and Tape and Reel Description The Atmel® AT24C01D/02D provides 1,024/2,048 bits of Serial Electrically Erasable and Programmable Read-Only Memory (EEPROM) organized as 128/256 words of eight bits each. The device’s cascadable feature allows up to eight devices to share a common 2-wire bus. These device are optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. Both devices are available in space-saving 8-lead SOIC, 8-lead TSSOP, 8-pad UDFN, 8-lead PDIP(1), 5-lead SOT23, and 8-ball VFBGA packages. The entire family of packages operates from 1.7V to 3.6V. Note: 1. Contact Atmel Sales for availability of this package. Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 1. Pin Descriptions and Pinouts Table 1-1. Pin Number 1, 2, 3 Pin Descriptions Pin Symbol Pin Name and Functional Description Asserted State Pin Type — Input — Power — Input/ Output — Input High Input — Power Device Address Inputs: The A0, A1, and A2 pins are used to select the hardware device address and correspond to the seventh, sixth, and fifth bit of the I2C seven bit slave address. These pins can be directly connected to VCC or GND, allowing up to eight devices on the same bus. A0, A1, A2 Refer to Note 1 for behavior of the pin when not connected. 4 Ground: The ground reference for the power supply. GND should be connected to the system ground. GND Serial Data: The SDA pin is an open-drain bidirectional input/output pin used to serially transfer data to and from the device. 5 SDA 6 The SDA pin must be pulled-high using an external pull-up resistor (not to exceed 10K in value) and may be wire-ORed with any number of other open-drain or open-collector pins from other devices on the same bus. Serial Clock: The SCL pin is used to provide a clock to the device and to control the flow of data to and from the device. Command and input data present on the SDA pin is always latched in on the rising edge of SCL, while output data on the SDA pin is clocked out on the falling edge of SCL. SCL The SCL pin must either be forced high when the serial bus is idle or pulled-high using an external pull-up resistor. 7 Write Protect: Connecting the WP pin to GND will ensure normal write operations.When the WP pin is connected to VCC, all write operations to the memory are inhibited. WP Refer to Note 1 for behavior of the pin when not connected. 8 Note: Device Power Supply: The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted. VCC 1. If the A0, A1, A2, or WP pins are not driven, they are internally pulled down to GND. In order to operate in a wide variety of application environments, the pull-down mechanism is intentionally designed to be somewhat strong. Once these pins are biased above the CMOS input buffer’s trip point (~0.5 x VCC), the pull-down mechanism disengages. Atmel recommends connecting these pins to a known state whenever possible. 8-lead SOIC A0 1 8 VCC A1 2 7 WP A2 3 6 SCL GND 5 4 8-pad UDFN 8-lead TSSOP SDA A0 A1 A2 GND 1 2 3 4 VCC WP SCL SDA 8 7 6 5 A0 1 8 VCC A1 2 7 WP A2 3 6 SCL GND 4 5 SDA Top View Top View 5-lead SOT23 8-lead PDIP A0 1 8 VCC A1 2 7 WP A2 3 6 SCL GND 4 5 SDA Top View SCL 1 GND 2 SDA 3 5 4 Top View Top View (1) WP VCC 8-ball VFBGA A0 1 8 VCC A1 2 7 WP A2 3 6 SCL GND 4 5 SDA Top View Note: Package drawings are not to scale. Note: 2 1. Refer to Section 4.1, “Device Addressing” on page 7 for details addressing the SOT23 version of the device. AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 Device Block Diagram and System Configuration Figure 2-1. Block Diagram Hardware Address Comparator A0 Memory System Control Module Power On Reset Generator VCC High Voltage Generation Circuit A1 Write Protection Control Row Decoder 2. EEPROM Array WP Address Register and Counter 1 page Column Decoder A2 SCL Data Register DOUT Start Stop Detector Data & ACK Input/Output Control DIN GND Figure 2-2. SDA System Configuration Using 2-Wire Serial EEPROMs VCC RPUP(max) = VCC RPUP(min) = tR(max) 0.8473 x CL VCC - VOL(max) IOL SCL SDA WP I2C Bus Master: Microcontroller A0 VCC A0 VCC A0 VCC A1 Slave 0 WP AT24Cxxx SDA A1 Slave 1 WP AT24Cxxx SDA A1 Slave 7 WP AT24Cxxx SDA A2 GND GND SCL A2 GND SCL A2 GND AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 SCL 3 3. Device Operation and Communication The AT24C01D/02D operates as a slave device and utilizes a simple I2C-compatible 2-wire digital serial interface to communicate with a host controller, commonly referred to as the bus Master. The Master initiates and controls all Read and Write operations to the slave devices on the serial bus, and both the Master and the slave devices can transmit and receive data on the bus. The serial interface is comprised of just two signal lines: Serial Clock (SCL) and Serial Data (SDA). The SCL pin is used to receive the clock signal from the Master, while the bidirectional SDA pin is used to receive command and data information from the Master as well as to send data back to the Master. Data is always latched into the AT24C01D/02D on the rising edge of SCL and always output from the device on the falling edge of SCL. Both the SCL and SDA pin incorporate integrated spike suppression filters and Schmitt Triggers to minimize the effects of input spikes and bus noise. All command and data information is transferred with the Most-Significant Bit (MSB) first. During bus communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data have been transferred, the receiving device must respond with either an acknowledge (ACK) or a no-acknowledge (NACK) response bit during a ninth clock cycle (ACK/NACK clock cycle) generated by the Master; Therefore, nine clock cycles are required for every one byte of data transferred. There are no unused clock cycles during any Read or Write operation, so there must not be any interruptions or breaks in the data stream during each data byte transfer and ACK or NACK clock cycle. During data transfers, data on the SDA pin must only change while SCL is low, and the data must remain stable while SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop condition will occur. Start and Stop conditions are used to initiate and end all serial bus communication between the Master and the slave devices. The number of data bytes transferred between a Start and a Stop condition is not limited and is determined by the Master. In order for the serial bus to be idle, both the SCL and SDA pins must be in the logic-high state at the same time. 3.1 Clock and Data Transition Requirements The SDA pin is an open drain terminal and therefore must be pulled high with an external pull-up resistor. Data on the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will indicate a Start or Stop condition as defined below. 3.2 Start and Stop Conditions 3.2.1 Start Condition A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is at a stable Logic 1 state and will bring the device out of standby mode. The Master uses a Start condition to initiate any data transfer sequence; therefore, every command must begin with a Start condition. The device will continuously monitor the SDA and SCL pins for a Start condition but will not respond unless one is detected. See Figure 3-1 for more details. 3.2.2 Stop Condition A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable in the Logic 1 state. The Master can use the Stop condition to end a data transfer sequence with the AT24C01D/02D which will subsequently return to standby mode. The Master can also utilize a repeated Start condition instead of a Stop condition to end the current data transfer if the Master will perform another operation. See Figure 3-1 for more details. 4 AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 3.3 Acknowledge and No-Acknowledge After every byte of data is received, the receiving device must confirm to the Master that it has successfully received the data byte by responding with what is known as an acknowledge (ACK). An ACK is accomplished by the transmitting device first releasing the SDA line at the falling edge of the eighth clock cycle followed by the receiving device responding with a Logic 0 during the entire high period of the ninth clock cycle. When the AT24C01D/02D is transmitting data to the Master, the Master can indicate that it is done receiving data and wants to end the operation by sending a Logic 1 response to the AT24C01D/02D instead of an ACK response during the ninth clock cycle. This is known as a no-acknowledge (NACK) and is accomplished by the Master sending a Logic 1 during the ninth clock cycle, at which point the AT24C01D/02D will release the SDA line so the Master can then generate a Stop condition. The transmitting device, which can be the bus Master or the Serial EEPROM, must release the SDA line at the falling edge of the eighth clock cycle to allow the receiving device to drive the SDA line to a Logic 0 to ACK the previous 8-bit word. The receiving device must release the SDA line at the end of the ninth clock cycle to allow the transmitter to continue sending new data. A timing diagram has been provided in Figure 3-1 to better illustrate these requirements. Figure 3-1. Start Condition, Data Transitions, Stop Condition and Acknowledge SCL SDA Must Be Stable SDA Must Be Stable 1 2 Acknowledge Window 8 9 Stop Condition SDA Acknowledge Valid Start Condition SDA Change Allowed 3.4 SDA Change Allowed The transmitting device (Master or Slave) must release the SDA line at this point to allow the receiving device (Master or Slave) to drive the SDA line low to ACK the previous 8-bit word. The receiver (Master or Slave) must release the SDA line at this point to allow the transmitter to continue sending new data. Standby Mode The AT24C01D/02D features a low power standby mode which is enabled when any one of the following occurs: A valid power-up sequence is performed (see Section 8.6, “Power-Up Requirements and Reset Behavior”). A Stop condition is received by the device unless it initiates an internal write cycle (see Section 5.). At the completion of an internal write cycle (see Section 5., “Write Operations”). An unsuccessful match of the device type identifier or hardware address in the Device Address byte occurs (see Section 4.1, “Device Addressing”). The bus Master does not ACK the receipt of data read out from the device; instead it sends a NACK response (see Section 6., “Read Operations”). AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 5 3.5 Software Reset After an interruption in protocol, power loss, or system reset, any 2-wire part can be protocol reset by following these steps: 1. 2. 3. Create a Start condition (if possible). Clock nine cycles. Create another Start condition followed by a Stop condition as seen in Figure 3-2. The device should be ready for the next communication after above steps have been completed. In the event that the device is still non-responsive or remains active on the SDA bus, a power cycle must be used to reset the device (see Section 8.6.1, “Device Reset”). Figure 3-2. Software Reset Dummy Clock Cycles SCL 1 2 Start Condition SDA 6 AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 3 8 9 Start Condition Stop Condition 4. Memory Organization The AT24C01D is internally organized as 16 pages of 8 bytes each while the AT24C02D is organized as 32 pages of 8 bytes each. 4.1 Device Addressing Accessing the device requires an 8-bit Device Address word following a Start condition to enable the device for a Read or Write operation. Since multiple slave devices can reside on the serial bus, each slave device must have its own unique address so that the Master can access each device independently. The most significant four bits of the Device Address word is referred to as the device type identifier. The device type identifier ‘1010’ (Ah) is required in bits seven through four of the Device Address byte (see Table 4-1.) Following the 4-bit device type identifier are the hardware slave address bits, A2, A1, and A0. These bits can be used to expand the address space by allowing up to eight other Serial EEPROM devices on the same bus. The A2, A1, and A0 values must correlate with the voltage level on the corresponding hardwired input pins, A2, A1, and A0. These hardwired address pins use an internal proprietary circuit that automatically biases each pin to a Logic 0 state if the pin is allowed to float. In order to operate in a wide variety of application environments, the pull-down mechanism is intentionally designed to be somewhat strong. Once the pin is biased above the CMOS input buffer’s trip point (~0.5 x VCC), the pull-down mechanism disengages. Atmel recommends connecting the A2, A1, and A0 pins to a known state whenever possible. When using the SOT23 package, the A2, A1, and A0 signals are not accessible and are left floating. The previously mentioned automatic pull-down circuit will set these signals to a Logic 0 state. As a result, to properly communicate with the device in the SOT23 package, the A2, A1, and A0 software bits must always be set to Logic 0 for any operation. This requirement has been shown in Table 4-1. The eighth bit of the Device Address (bit 0) is the Read/Write operation select bit. A Read operation is initiated if this bit is high and a Write operation is initiated if this bit is low. Upon the successful comparison of the Device Address, the EEPROM will return an ACK. If a valid comparison is not made, the device will NACK and return to a standby state. Table 4-1. Device Address Byte Device Type Identifier Hardware Slave Address Bits Read/ Write Package Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SOIC, TSSOP, UDFN, PDIP, VFBGA 1 0 1 0 A2 A1 A0 R/W SOT23 1 0 1 0 0 0 0 R/W For all operations except the Current Address Read, a Word Address byte must be transmitted to the device immediately following the Device Address byte. The Word Address byte contains a 7-bit (in the case of the AT24C01D) or 8-bit (in the case of the AT24C02D) memory array address, and is used to specify which location in the EEPROM to start reading or writing. Please refer to Table 4-2 to review these bit positions. Table 4-2. Word Address Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A7(1) A6 A5 A4 A3 A2 A1 A0 Note: 1. The A7 bit is a don’t care bit for the AT24C01D. The relationship of the AC timing parameters with respect to SCL and SDA for the AT24C01D/02D are shown in the timing waveform in Figure 8-1. The AC timing characteristics and specifications are outlined in Section 8.4 “AC Characteristics” on page 14. AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 7 5. Write Operations All Write operations for the AT24C01D/02D begin with the Master sending a Start condition, followed by a Device Address byte with the R/W bit set to ‘0’, and then by the Word Address byte. The data value(s) to be written to the device immediately follow the Word Address byte. 5.1 Byte Write The AT24C01D/02D supports the writing of single 8-bit bytes. Selecting a data word in the 1-Kbit memory requires a 7-bit word address while selecting a data word in the 2-Kbit memory requires an 8-bit word address. Upon receipt of the proper Device Address and Word Address bytes, the EEPROM will send an Acknowledge. The device will then be ready to receive the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will respond with an Acknowledge. The addressing device, such as a bus Master, must then terminate the Write operation with a Stop condition. At that time the EEPROM will enter an internally self-timed write cycle, which will complete within a time of tWR, while the data is being programmed into the nonvolatile EEPROM. All inputs are disabled during this write cycle, and the EEPROM will not respond until the Write is complete. Figure 5-1. Byte Write 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 D2 D1 D0 0 SCL Device Address Byte SDA 1 0 1 0 A2 A1 A0 0 0 MSB Start by Master 5.2 Data Word Word Address Byte A7 A6 A5 A4 A3 A2 A1 A0 0 ACK from Slave D7 D6 D5 D4 D3 MSB MSB ACK from Slave ACK from Slave Stop by Master Page Write A Page Write operation allows up to eight bytes to be written in the same write cycle, provided all bytes are in the same row of the memory array (where address bits A7 through A3 are the same). Partial Page Writes of less than eight bytes are also allowed. A Page Write is initiated the same way as a Byte Write, but the bus Master does not send a Stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the bus Master can transmit up to seven additional data words. The EEPROM will respond with an ACK after each data word is received. Once all data to be written has been sent to the device, the bus Master must issue a Stop condition (see Figure 5-2) at which time the internally self-timed write cycle will begin. The lower three bits of the word address are internally incremented following the receipt of each data word. The higher order address bits are not incremented and retains the memory page row location. Page Write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. When the incremented word address reaches the page boundary, the address counter will “roll-over” to the beginning of the same page. Nevertheless, creating a roll-over event should be avoided as previously loaded data in the page could become unintentionally altered. 8 AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 Figure 5-2. Page Write 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 A1 A0 0 SCL Device Address Byte SDA 1 0 1 0 A2 A1 Word Address Byte A0 0 A7 0 MSB A6 A5 A4 A3 A2 MSB Start by Master ACK from Slave ACK from Slave 1 2 3 4 5 6 7 8 9 D6 D5 D4 D3 2 3 4 5 D2 D1 D0 0 MSB 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 0 MSB ACK from Slave 5.3 6 Data Word (n+x), max of 8 without rollover Data Word (n) D7 1 ACK from Slave Stop by Master Acknowledge Polling An Acknowledge Polling routine can be implemented to optimize time sensitive applications that would prefer not to wait the fixed maximum write cycle time (tWR). This method allows the application to know immediately when the Serial EEPROM write cycle has completed, so a subsequent operation can be started. Once the internally self-timed write cycle has started, an Acknowledge Polling routine can be initiated. This involves repeatedly sending a Start condition followed by a valid Device Address byte with the R/W bit set at Logic 0. The device will not respond with an ACK while the write cycle is ongoing. Once the internal write cycle has completed, the EEPROM will respond with an ACK, allowing a new Read or Write operation to be immediately initiated. A flow chart has been included below in Figure 5-3 to better illustrate this technique. Figure 5-3. Acknowledge Polling Flow Chart Send any Write protocol Send Stop condition to initiate the write cycle Send Start condition followed by a valid Device Address byte with R/W = 0 Did the device ACK? YES Proceed to next Read or Write operation NO 5.4 Write Cycle Timing The length of the self-timed write cycle, or tWR, is defined as the amount of time from the Stop condition that begins the internal Write operation, to the Start condition of the first Device Address byte sent to the AT24C01D/02D which it subsequently responds to with an ACK. Figure 5-4 has been included to show this measurement. During the internally self-timed write cycle, any attempts to read or write to the memory array will not be processed. AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 9 Figure 5-4. Write Cycle Timing SCL 8 9 9 ACK ACK Data Word n SDA D0 First Acknowledge from the device to a valid device address sequence after write cycle is initiated. The minumum tWR can only be determined through the use of an ACK Polling routine. tWR Stop Condition 5.5 Start Condition Stop Condition Write Protection The AT24C01D/02D utilizes a hardware data protection scheme that allows the user to write protect the entire memory contents when the WP pin is at VCC (or a valid VIH). No write protection will be set if the WP pin is at GND or left floating. Table 5-1. AT24C01D/02D Write Protect Behavior WP Pin Voltage Part of the Array Protected VCC Full Array GND None — Write Protection Not Enabled The status of the WP pin is sampled at the Stop condition for every Byte Write or Page Write command prior to the start of an internally self-timed Write operation. Changing the WP pin state after the Stop condition has been sent will not alter or interrupt the execution of the write cycle. The WP pin state must be valid with respect to the associated setup (tSU.WP) and hold (tHD.WP) as shown in the Figure 5-5 below. The WP setup time is the amount of time that the WP state must be stable before the Stop condition is issued. The WP hold time is the amount of time after the Stop condition that the WP state must remain stable. If an attempt is made to write to the device while the WP pin has been asserted, the device will acknowledge the Device Address, Word address, and Data bytes but no write cycle will occur when the Stop condition is issued, and the device will immediately be ready to accept a new Read or Write command. Figure 5-5. SCL Write Protect Setup and Hold Timing 1 2 7 8 9 Stop by Master Data Word Input Sequence Page/Byte Write Operation SDA IN D7 D6 D1 D0 ACK by Slave tSU.WP WP 10 AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 tHD.WP 6. Read Operations Read operations are initiated the same way as Write operations with the exception the read/write select bit in the Device Address word must be a Logic 1. There are three Read operations: 6.1 Current Address Read Random Address Read Sequential Read Current Address Read The internal data word address counter maintains the last address accessed during the last Read or Write operation, incremented by one. This address stays valid between operations as long as the VCC is maintained to the part. The address roll-over during read is from the last byte of the last page to the first byte of the first page of the memory. A Current Address Read operation will output data according to the location of the internal data word address counter. This is initiated with a Start condition, followed by a valid Device Address byte with the R/W bit set to Logic 1. The device will ACK this sequence and the current address data word is serially clocked out on the SDA line. All types of Read operations will be terminated if the bus Master does not respond with an ACK (it NACKs) during the ninth clock cycle, which will force the device into standby mode. After the NACK response, the Master may send a Stop condition to complete the protocol, or it can send a Start condition to begin the next sequence. Figure 6-1. Current Address Read 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 D2 D1 D0 1 SCL Device Address Byte SDA 1 0 1 0 A2 A1 Data Word (n) A0 1 0 MSB Start by Master 6.2 D7 D6 D5 D4 D3 MSB ACK from Slave NACK from Master Stop by Master Random Read A Random Read begins in the same way as a Byte Write operation does to load in a new data word address. This is known as a “dummy write” sequence. However, the Data Byte and the Stop condition of the Byte Write must be omitted to prevent the part from entering an internal write cycle. Once the Device Address and Word Address are clocked in and acknowledged by the EEPROM, the bus Master must generate another Start condition. The bus Master now initiates a Current Address Read by sending a Start condition, followed by a valid Device Address byte with the R/W bit set to Logic 1. The EEPROM will ACK the Device Address and serially clock out the data word on the SDA line. All types of Read operations will be terminated if the bus Master does not respond with an ACK (it NACKs) during the ninth clock cycle, which will force the device into standby mode. After the NACK response, the Master may send a Stop condition to complete the protocol, or it can send a Start condition to begin the next sequence. AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 11 Figure 6-2. Random Read 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 A1 A0 0 SCL Device Address Byte SDA 1 0 1 0 A1 A2 Word Address Byte A0 0 0 A7 MSB A6 A5 A4 A3 A2 MSB Start by Master ACK from Slave ACK from Slave Dummy Write 1 2 3 4 5 6 7 8 9 1 2 3 0 1 0 A1 A2 A0 1 0 D7 MSB 6 7 8 9 D6 D5 D4 D3 D2 D1 D0 1 MSB Start by Master 6.3 5 Data Word (n) Device Address Byte 1 4 ACK from Slave Stop by Master NACK from Master Sequential Read Sequential Reads are initiated by either a Current Address Read or a Random Read. After the bus Master receives a data word, it responds with an acknowledge. As long as the EEPROM receives an ACK, it will continue to increment the word address and serially clock out sequential data words. Figure 6-3 depicts a Sequential Read sequence that was initiated as a Current Address Read. When the maximum memory address is reached, the data word address will “roll over” and the sequential read will continue from the beginning of the memory array. All types of Read operations will be terminated if the bus Master does not respond with an ACK (it NACKs) during the ninth clock cycle, which will force the device into standby mode. After the NACK response, the Master may send a Stop condition to complete the protocol, or it can send a Start condition to begin the next sequence. Figure 6-3. Sequential Read, Initiated by a Current Address Read 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 D2 D1 D0 0 SCL Device Address Byte SDA 1 0 1 0 A1 A2 Data Word (n) A0 1 0 D7 MSB Start by Master 1 D5 D4 2 3 4 5 6 7 8 9 ACK from Master 1 2 D6 D5 D4 D3 D2 3 4 5 6 7 8 9 1 2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 MSB ACK from Master 3 4 5 6 7 8 9 D1 D0 1 Data Word (n+x) Data Word (n+2) MSB 7. D3 ACK from Slave Data Word (n+1) D7 D6 MSB D7 D6 D5 D4 D3 D2 MSB ACK from Master NACK from Master Stop by Master Device Default Condition from Atmel The AT24C01D/02D is delivered with the EEPROM array set to Logic 1, resulting in FFh data in all locations. 12 AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 8. Electrical Specifications 8.1 Absolute Maximum Ratings Functional operation at the “Absolute Maximum Ratings” or any other conditions beyond those indicated in Section 8.2 “DC and AC Operating Range” is not implied or guaranteed. Stresses beyond those listed under “Absolute Maximum Ratings” and/or exposure to the “Absolute Maximum Ratings” for extended periods may affect device reliability and cause permanent damage to the device. Temperature under Bias. . . . . -55C to +125C Storage Temperature . . . . . . . -65C to +150C Supply Voltage with respect to ground . . . . . . . -0.5V to +4.10V The voltage extremes referenced in the “Absolute Maximum Ratings” are intended to accommodate short duration undershoot/overshoot pulses that the device may be subjected to during the course of normal operation and does not imply or guarantee functional device operation at these levels for any extended period of time. Voltage on any pin with respect to ground . . . . -0.6V to VCC + 0.5V DC Output Current . . . . . . . . . . . . . . . . . 5.0mA 8.2 DC and AC Operating Range Table 8-1. DC and AC Operating Range AT24C01D and AT24C02D 8.3 Operating Temperature (Case) Industrial Temperature Range VCC Power Supply Low Voltage Grade -40C to +85C 1.7V to 3.6V DC Characteristics Table 8-2. DC Characteristics Parameters are applicable over the operating range in Section 8.2, unless otherwise noted. Symbol Parameter VCC Supply Voltage Test Condition Min Typical(1) 1.7 (2) ICC1 Supply Current, Read ICC2 Supply Current, Write ISB Standby Current ILI Input Leakage Current ILO Output Leakage Current VIL Input Low Level(2) Max Units 3.6 V VCC = 1.8V Read at 400kHz 0.08 0.3 mA VCC = 3.6V Read at 1MHz 0.15 0.5 mA VCC = 3.6V Write at 1MHz 0.20 1.0 mA 0.08 0.4 μA 0.10 0.8 μA VIN = VCC or VSS 0.10 3.0 μA VOUT = VCC or VSS 0.05 3.0 μA -0.6 VCC x 0.3 V VCC x 0.7 VCC + 0.5 V VCC = 1.8V(2) VCC = 3.6V VIN = VCC or VSS (2) VIH Input High Level VOL1 Output Low Level VCC = 1.7V IOL = 0.15mA 0.2 V VOL2 Output Low Level VCC = 3.0V IOL = 2.1mA 0.4 V Notes: 1. 2. Typical values characterized at TA = +25°C unless otherwise noted. This parameter is characterized but is not 100% tested in production. AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 13 8.4 AC Characteristics Table 8-3. AC Characteristics Parameters are applicable over operating range in Section 8.2, unless otherwise noted. Test conditions shown in Note 2. Symbol Parameter fSCL Clock Frequency, SCL tLOW Clock Pulse Width Low tHIGH Clock Pulse Width High Standard Mode Fast Mode Fast Mode Plus VCC1.7V to 3.6V VCC1.7V to 3.6V VCC 2.5V to 3.6V Min Max Min 100 tI Input Filter Spike Suppression (SCL,SDA) tAA Clock Low to Data Out Valid Min 400 Max Units 1000 kHz 4,700 1,300 500 ns 4,000 600 400 ns (1) (1) Max 100 100 100 ns 4,500 900 450 ns tBUF Bus Free Time between Stop and Start 4,700 1,300 500 ns tHD.STA Start Hold Time 4,000 600 250 ns tSU.STA Start Set-up Time 4,700 600 250 ns tHD.DAT Data In Hold Time 0 0 0 ns tSU.DAT Data In Set-up Time 200 100 100 ns tR Inputs Rise Time (1) (1) 1,000 300 100 ns 300 300 100 ns tF Inputs Fall Time tSU.STO Stop Set-up Time 4,700 600 250 ns tSU.WP Write Protect Setup Time 4,000 600 100 ns tHD.WP Write Protect Hold Time 4,000 600 400 ns tDH Data Out Hold Time 100 50 50 ns tWR Write Cycle Time Notes: 5 5 5 1. These parameters are determined through product characterization and are not tested 100% in production. 2. AC measurement conditions: CL : 100pF RPUP (bus line pull-up resistor to VCC): 1.3 k (1000kHz), 4k (400kHz), 10k (100kHz) Input pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall times: 50ns Input and output timing reference voltages: 0.5 x VCC Figure 8-1. Bus Timing tHIGH tF tR tLOW SCL tSU.STA tHD.STA tHD.DAT tSU.DAT tSU.STO SDA IN tAA SDA OUT 14 AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 tDH tBUF ms 8.5 Pin Capacitance Pin Capacitance(1) Table 8-4. Applicable over recommended operating range from TA = 25C, f = 1.0MHz, VCC = 3.6V Symbol Test Condition CI/O CIN Note: 8.6 1. Max Units Conditions Input/Output Capacitance (SDA) 8 pF VI/O = 0V Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V This parameter is characterized but is not 100% tested in production. Power-Up Requirements and Reset Behavior During a power-up sequence, the VCC supplied to the AT24C01D/02D should monotonically rise from GND to the minimum VCC level as specified in Section 8.2 with no greater than a slew rate of 1V/μs. 8.6.1 Device Reset To prevent inadvertent write operations or other spurious events from happening during a power-up sequence, the AT24C01D/02D includes a Power-On-Reset (POR) circuit. Upon power-up, the device will not respond to any commands until the VCC level crosses the internal voltage threshold (VPOR) that brings the device out of reset and into standby mode. The system designer must ensure that instructions are not sent to the device until the VCC supply has reached a stable value greater than or equal to the minimum VCC level. Additionally, once the VCC is greater than or equal to the minimum VCC level, the bus Master must wait at least tPUP before sending the first command to the device. See Table 8-5 for the values associated with these power-up parameters. Table 8-5. Power-up Conditions(1) Symbol Parameter Min tPUP Time required after VCC is stable before the device can accept commands. 100 VPOR Power-On Reset Threshold Voltage tPOFF Minimum time at VCC = 0V between power cycles. Note: 1. Max Units μs 1.5 V 1 ms These parameters are characterized but they are not 100% tested in production. If an event occurs in the system where the VCC level supplied to the AT24C01D/02D drops below the maximum VPOR level specified, it is recommended that a full power cycle sequence be performed by first driving the VCC pin to GND, waiting at least the minimum tPOFF time, and then performing a new power-up sequence in compliance with the requirements defined in this section. 8.7 EEPROM Cell Performance Characteristics Table 8-6. EEPROM Cell Performance Characteristics Operation Test Condition Write Endurance(1) TA = 25°C, VCC(min)< VCC <VCC(max) Byte or Page Write Mode Data Retention(2) TA = 55°C Notes: 1. 2. Min Max Units 1,000,000 — Write Cycles 100 — Years Write endurance performance is determined through characterization and the qualification process. The data retention capability is determined through qualification and checked on each device in production. AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 15 9. Ordering Code Detail AT2 4 C 0 1 D - S S H M x x - T Atmel Designator Product Family 24C = Standard I2C-compatible Serial EEPROM Device Density 01 = 1 Kilobit 02 = 2 Kilobit Device Revision Shipping Carrier Option T = Tape and Reel, Standard Quantity Option E = Tape and Reel, Expanded Quantity Option B = Bulk (Tubes) Product Variation HY = Applies to select packages only. See ordering code table for variation details. Operating Voltage M = 1.7V to 3.6V Package Device Grade or Wafer/Die Thickness H = Green, NiPdAu Lead Finish Industrial Temperature Range (-40°C to +85°C) U = Green, Matte Tin Lead Finish or SnAgCu Ball Industrial Temperature Range (-40°C to +85°C) 11 = 11mil Wafer Thickness Package Option SS = JEDEC SOIC X = TSSOP MA = 2.0mm x 3.0mm UDFN P = PDIP ST = SOT23 C = VFBGA WWU = Wafer Unsawn 16 AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 10. Ordering Information Delivery Information Atmel Ordering Code Lead Finish Package AT24C01D-SSHM-T 8S1 AT24C01D-SSHM-B AT24C01D-XHM-T NiPdAu AT24C01D-XHM-B (Lead-free/Halogen-free) AT24C01D-MAHM-T AT24C01D-STUM-T AT24C01D-CUM-T AT24C01D-WWU11M(1) Quantity Tape and Reel 4,000 per Reel Bulk (Tubes) 100 per Tube Tape and Reel 5,000 per Reel Bulk (Tubes) 100 per Tube Tape and Reel Matte Tin 8P3 Bulk (Tubes) 50 per Tube (Lead-free/Halogen-free) 5TS1 Tape and Reel 5,000 per Reel 8U3-1 Tape and Reel 5,000 per Reel SnAgCu Ball (Lead-free/Halogen-free) N/A Wafer Sale AT24C02D-SSHM-T AT24C02D-SSHMHY-T 8S1 NiPdAu (Lead-free/Halogen-free) 8X AT24C02D-XHM-B AT24C02D-MAHM-T Tape and Reel 4,000 per Reel Bulk (Tubes) 100 per Tube Tape and Reel 5,000 per Reel Bulk (Tubes) 100 per Tube AT24C02D-STUM-T AT24C02D-CUM-T AT24C02D-WWU11M(1) Note: 1. 5,000 per Reel 8MA2 Tape and Reel Matte Tin 8P3 Bulk (Tubes) 50 per Tube (Lead-free/Halogen-free) 5TS1 Tape and Reel 5,000 per Reel 8U3-1 Tape and Reel 5,000 per Reel AT24C02D-MAHM-E AT24C02D-PUM 15,000 per Reel SnAgCu Ball (Lead-free/Halogen-free) N/A Operation Range Industrial Temperature (-40C to 85C) Note 1 AT24C02D-SSHM-B AT24C02D-XHM-T 5,000 per Reel 8MA2 AT24C01D-MAHM-E AT24C01D-PUM 8X Form Wafer Sale 15,000 per Reel Industrial Temperature (-40C to 85C) Note 1 For wafer sales, please contact Atmel Sales. Package Type 8S1 8-lead, 0.15” wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8X 8-lead, 4.40mm body, Plastic Thin Shrink Small Outline Package (TSSOP) 8MA2 8-pad, 2.00mm x 3.00mm body, 0.50mm Pitch, Ultra Thin Dual Flat No Lead (UDFN) 8P3 8-lead, 0.30” wide, Plastic Dual Inline Package (PDIP) 5TS1 5-lead, 2.90mm x 1.60mm body, Plastic Thin Shrink Small Outline (SOT23) 8U3-1 8-ball, 1.50mm x 2.00mm body, 0.5mm pitch, Very thin Fine Ball Grid Array (VFBGA) AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 17 11. Part Markings AT24C01D and AT24C02D: Package Marking Information 8-lead TSSOP 8-lead SOIC 8-pad UDFN 2.0 x 3.0 mm Body ### H%@ YXX ATHYWW ###% @ AAAAAAA ATMLHYWW ###% @ AAAAAAAA 8-lead PDIP 5-lead SOT-23 8-ball VFBGA 1.5 x 2.0 mm Body ###%U ATMLUYWW ###% @ AAAAAAAA Note 1: Top Mark ###U YMXX YMXX Bottom Mark PIN 1 designates pin 1 Note 2: Package drawings are not to scale Catalog Number Truncation AT24C01D Truncation Code ###: 01D AT24C02D Truncation Code ###: 02D Date Codes Y = Year 3: 2013 4: 2014 5: 2015 6: 2016 Voltages 7: 2017 8: 2018 9: 2019 0: 2020 M = Month A: January B: February ... L: December WW = Work Week of Assembly 02: Week 2 04: Week 4 ... 52: Week 52 Country of Assembly Lot Number @ = Country of Assembly AAA...A = Atmel Wafer Lot Number Trace Code % = Minimum Voltage M: 1.7V min Grade/Lead Finish Material H: Industrial/NiPdAu U: Industrial/Matte Tin/SnAgCu Atmel Truncation XX = Trace Code (Atmel Lot Numbers Correspond to Code) Example: AA, AB.... YZ, ZZ AT: Atmel ATM: Atmel ATML: Atmel 12/20/13 Package Mark Contact: [email protected] 18 TITLE DRAWING NO. REV. 24C01-02DSM, AT24C01D and AT24C02D Package Marking Information 24C01-02DSM D AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 12. Packaging Information 12.1 8S1 — 8-lead JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. MIN NOM MAX – – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 SYMBOL A D 4.90 BSC E 6.00 BSC E1 3.90 BSC e 1.27 BSC L 0.40 – 1.27 Ø 0° – 8° NOTE 3/6/2015 Package Drawing Contact: [email protected] TITLE 8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) GPC SWB DRAWING NO. REV. 8S1 H AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 19 12.2 8X — 8-lead TSSOP C 1 Pin 1 indicator this corner E1 E L1 N L Top View End View A b A1 e COMMON DIMENSIONS (Unit of Measure = mm) A2 D SYMBOL Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07mm. 5. Dimension D and E1 to be determined at Datum Plane H. MIN NOM MAX A - - 1.20 A1 0.05 - 0.15 NOTE A2 0.80 1.00 1.05 D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5 b 0.19 0.25 0.30 4 e L 0.65 BSC 0.45 L1 C 0.60 0.75 1.00 REF 0.09 - 0.20 2/27/14 TITLE Package Drawing Contact: [email protected] 20 8X, 8-lead 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 GPC TNR DRAWING NO. 8X REV. E 12.3 8MA2 — 8-pad UDFN E 1 8 Pin 1 ID 2 7 3 6 4 5 D C TOP VIEW A2 SIDE VIEW A A1 E2 b (8x) 8 7 1 D2 6 3 5 4 e (6x) K L (8x) BOTTOM VIEW Notes: COMMON DIMENSIONS (Unit of Measure = mm) 2 Pin#1 ID 1. This drawing is for general information only. Refer to Drawing MO-229, for proper dimensions, tolerances, datums, etc. 2. The Pin #1 ID is a laser-marked feature on Top View. 3. Dimensions b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 4. The Pin #1 ID on the Bottom View is an orientation feature on the thermal pad. SYMBOL MIN NOM MAX A 0.50 0.55 0.60 A1 0.0 0.02 0.05 A2 - - 0.55 D 1.90 2.00 2.10 D2 1.40 1.50 1.60 E 2.90 3.00 3.10 E2 1.20 1.30 1.40 b 0.18 0.25 0.30 C L 3 1.52 REF 0.30 e K NOTE 0.35 0.40 0.50 BSC 0.20 - - 11/26/14 Package Drawing Contact: [email protected] TITLE 8MA2, 8-pad 2 x 3 x 0.6mm Body, Thermally Enhanced Plastic Ultra Thin Dual Flat No-Lead Package (UDFN) GPC DRAWING NO. REV. YNZ 8MA2 G AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 21 12.4 8P3 — 8-lead PDIP E 1 E1 .381 Gage Plane N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = mm) D e D1 A2 A A1 b2 b3 b v 4 PLCS L 0.254 m C Side View MIN NOM MAX A - - 5.334 A1 0.381 A2 2.921 3.302 4.953 b 0.356 0.457 0.559 5 b2 1.143 1.524 1.778 6 b3 0.762 0.991 1.143 6 c 0.203 0.254 0.356 D 9.017 9.271 10.160 3 D1 0.127 0.000 0.000 3 E 7.620 7.874 8.255 4 E1 6.096 6.350 7.112 3 3.810 2 SYMBOL - e Notes: 2 - 2.540 BSC eA L NOTE 7.620 BSC 2.921 3.302 4 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 07/31/14 Package Drawing Contact: [email protected] 22 TITLE GPC DRAWING NO. 8P3, 8-lead, 0.300” Wide Body, Plastic Dual In-line Package (PDIP) PTC 8P3 AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 REV. E 12.5 5ST1 — 5-lead SOT23 e1 C 4 5 E1 C L E L1 1 3 2 END VIEW TOP VIEW b A2 SEATING PLANE e A A1 D SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) 1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per end. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.15 mm per side. 2. The package top may be smaller than the package bottom. Dimensions D and E1 are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 3. These dimensions apply to the flat section of the lead between 0.08 mm and 0.15 mm from the lead tip. 4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08 mm total in excess of the "b" dimension at maximum material condition. The dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and an adjacent lead shall not be less than 0.07 mm. This drawing is for general information only. Refer to JEDEC Drawing MO-193, Variation AB for additional information. SYMBOL MIN A A1 A2 c D E E1 L1 e e1 b 0.00 0.70 0.08 NOM 0.90 2.90 BSC 2.80 BSC 1.60 BSC 0.60 REF 0.95 BSC 1.90 BSC 0.30 - MAX 1.00 0.10 1.00 0.20 0.50 NOTE 3 1,2 1,2 1,2 3,4 5/31/12 Package Drawing Contact: [email protected] TITLE GPC 5TS1, 5-lead 1.60mm Body, Plastic Thin Shrink Small Outline Package (Shrink SOT) TSZ DRAWING NO. 5TS1 AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 REV. D 23 12.6 8U3-1 — 8-ball VFBGA E D 2. b PIN 1 BALL PAD CORNER A1 A2 TOP VIEW A SIDE VIEW PIN 1 BALL PAD CORNER 3 1 2 4 d (d1) 8 7 6 5 COMMON DIMENSIONS (Unit of Measure - mm) e (e1) SYMBOL MIN NOM MAX BOTTOM VIEW A 0.73 0.79 0.85 8 SOLDER BALLS A1 0.09 0.14 0.19 A2 0.40 0.45 0.50 Notes: b 0.20 0.25 0.30 1. This drawing is for general information only. D 2. Dimension ‘b’ is measured at maximum solder ball diameter. 3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu. NOTE 2 1.50 BSC E 2.0 BSC e 0.50 BSC e1 0.25 REF d 1.00 BSC d1 0.25 REF 6/11/13 Package Drawing Contact: [email protected] 24 TITLE GPC DRAWING NO. 8U3-1, 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) GXU 8U3-1 AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 REV. F 13. Revision History Doc. No. Date Comments 8871D 10/2015 Added AT24C02D-SSHMHY-T ordering code option and updated the 8S1 package drawing. 8871C 01/2015 Added the 100kHz timing set for reference, the UDFN extended quantity option, and the figure for “System Configuration Using 2-Wire Serial EEPROMs”. Updated 8X, 8MA2, and 8P3 package outline drawings and the ordering information. 8871B 03/2014 Corrected pinouts from bottom to top view and grammatical changes. No changes to functional specification. 8871A 12/2013 Initial document release. AT24C01D and AT24C02D [DATASHEET] Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015 25 XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2015 Atmel Corporation. / Rev.: Atmel-8871D-SEEPROM-AT24C01D-02D-Datasheet_102015. Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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