AT24C32C/64C - Mature

(Features
• Low-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
•
•
•
•
•
– 1.8 (VCC = 1.8 to 5.5V)
Internally Organized 4096 x 8, 8192 x 8
2-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bi-directional Data Transfer Protocol
1 MHz (5.0V) and 400 KHz (1.8V Compatibility)
Write Protect Pin for Hardware Data Protection
32-Byte Page Write Mode (Partial Page Writes Allowed)
Self-Timed Write Cycle (5 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
Lead-free/Halogen-free Devices
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead
TSSOP, 8-lead Ultra Thin Mini-MAP (MLP2x3), and 8-ball dBGA2 Packages.
Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Description
2-Wire
Serial EEPROM
32K (4096 x 8)
64K (8192 x 8)
AT24C32C
AT24C64C
The AT24C32C/64C provides 32,768/65,536 bits of serial electrically erasable and
programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits
each. The device’s cascadable feature allows up to 8 devices to share a common 2wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C32C/64C is
available in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Lead Frame
Land Grid Array (ULA), 8-lead TSSOP, 8-lead Ultra Thin Mini-MAP (MLP2x3) and, 8ball dBGA2 packages and is accessed via a 2-wire serial interface. In addition, the
entire family is available in 1.8V (1.8 to 5.5V) version.
Pin Configurations
Pin Name
Function
A0 - A2
Address Inputs
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
8-lead Ultra Thin
Mini-MAP (MLP 2x3)
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
A0
A1
A2
GND
8-lead Ultra Lead Frame
Land Grid Array (ULA)
VCC
WP
SCL
SDA
Bottom View
Bottom View
8-ball dBGA2
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
Not Recommended
for New Design
A0
A1
A2
GND
1
2
3
4
8
7
6
5
8-lead TSSOP
A0
A1
A2
GND
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
Bottom View
8-lead PDIP
8-lead SOIC
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
5298A–SEEPR–1/08
Absolute Maximum Ratings*
Operating Temperature ..................................... -55 to +125°C
*NOTICE:
Storage Temperature......................................... -65 to +150°C
Voltage on Any Pin
with Respect to Ground ....................................... -1.0 to +7.0V
Maximum Operating Voltage .......................................... 6.25V
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
DC Output Current........................................................ 5.0 mA
1. Block Diagram
VCC
GND
WP
START
STOP
LOGIC
SERIAL
CONTROL
LOGIC
LOAD
DEVICE
ADDRESS
COMPARATOR
A2
A1
A0
R/W
EN
H.V. PUMP/TIMING
COMP
LOAD
DATA RECOVERY
INC
DATA WORD
ADDR/COUNTER
Y DEC
X DEC
SCL
SDA
EEPROM
SERIAL MUX
DOUT/ACK
LOGIC
DIN
DOUT
2
AT24C32C/64C
5298A–SEEPR–1/08
AT24C32C/64C
2. Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM
device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain
driven and may be wire-ORed with any number of other open-drain or open collector devices.
DEVICE/ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are
hard wired or left not connected for hardware compatibility with other AT24CXX devices. When
the pins are hardwired, as many as eight 32K/64K devices may be addressed on a single bus
system (device addressing is discussed in detail under the Device Addressing section). If the
pins are left floating, the A2, A1 and A0 pins will be internally pulled down to GND if the capacitive coupling to the circuit board VCC plane is <3pF. If coupling is >3pF, Atmel® recommends
connecting the address pins to GND.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write
operations. When WP is connected high to VCC, all write operations to the memory are inhibited.
If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive coupling to the circuit board VCC plane is <3pF. If coupling is >3pF, Atmel recommends connecting
the pin to GND.
3
5298A–SEEPR–1/08
3. Memory Organization
AT24C32C/64C, 32/64K SERIAL EEPROM: The 32K/64K is internally organized as 128/256
pages of 32 bytes each. Random word addressing requires a 12/13 bit data word address.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V to 5.5V
Symbol
Test Condition
CI/O
CIN
Note:
Max
Units
Conditions
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
Input Capacitance (A0, A1, A2, SCL)
6
pF
VIN = 0V
1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40 to +85°C, VCC = +1.8 to +5.5V (unless otherwise noted)
Symbol
Parameter
VCC1
Supply Voltage
ICC1
Supply Current
VCC = 5.0V
READ at 400 kHz
ICC2
Supply Current
VCC = 5.0V
WRITE at 400 kHz
ISB1
Standby Current
(1.8V option)
VCC = 1.8V
ILI
Input Leakage
Current VCC = 5.0V
VIN = VCC or VSS
ILO
Output Leakage
Current VCC = 5.0V
VOUT = VCC or VSS
VIL
Input Low Level(1)
VIH
Input High Level
(1)
VOL2
Output Low Level
VCC = 3.0V
VOL1
Output Low Level
VCC = 1.8V
Note:
4
Test Condition
Min
Typ
Max
Units
5.5
V
0.4
1.0
mA
2.0
3.0
mA
1.0
µA
6.0
µA
0.10
3.0
µA
0.05
3.0
µA
−0.6
VCC x 0.3
V
VCC x 0.7
VCC + 0.5
V
IOL = 2.1 mA
0.4
V
IOL = 0.15 mA
0.2
V
1.8
VCC = 5.5V
VIN = VCC or VSS
1. VIL min and VIH max are reference only and are not tested.
AT24C32C/64C
5298A–SEEPR–1/08
AT24C32C/64C
AC Characteristics
Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
1.8-volt
Symbol
Parameter
Min
fSCL
Clock Frequency, SCL
tLOW
Clock Pulse Width Low
tHIGH
Clock Pulse Width High
Max
5.0-volt
Min
400
Max
Units
1000
kHz
1.3
0.4
µs
0.6
0.4
µs
(1)
ti
Noise Suppression Time
tAA
Clock Low to Data Out Valid
0.05
tBUF
Time the bus must be free before a new
transmission can start(1)
1.3
0.5
µs
tHD.STA
Start Hold Time
0.6
0.25
µs
tSU.STA
Start Set-up Time
0.6
0.25
µs
tHD.DAT
Data In Hold Time
0
0
µs
tSU.DAT
Data In Set-up Time
100
100
ns
Inputs Rise Time
tR
100
(1)
(1)
0.9
0.05
50
ns
0.55
µs
0.3
0.3
µs
300
100
ns
tF
Inputs Fall Time
tSU.STO
Stop Set-up Time
0.6
0.25
µs
tDH
Data Out Hold Time
50
50
ns
tWR
Write Cycle Time
Endurance(1)
25°C, Page Mode, 3.3V
Notes:
5
5
1,000,000
ms
Write
Cycles
1. This parameter is ensured by characterization.
2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.5V, 5.0V), 10 kΩ (1.8V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 50 ns
Input and output timing reference voltages: 0.5 VCC
5
5298A–SEEPR–1/08
4. Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition
as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (refer to Start and Stop Definition timing diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (refer to
Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.
STANDBY MODE: The AT24C32C/64C features a low power standby mode which is enabled:
a) upon power-up and b) after the receipt of the Stop bit and the completion of any internal
operations.
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, and 2-wire
part can be protocol reset by following these steps:
(a) Create a start bit condition, (b) clock 9 cycles, (c) create another start bit followed by stop bit
condition as shown below. The device is ready for next communication after above steps have
been completed.
Figure 4-1.
Software Reset
Dummy Clock Cycles
Start bit
SCL
1
2
3
Start bit
8
Stop bit
9
SDA
6
AT24C32C/64C
5298A–SEEPR–1/08
AT24C32C/64C
5. Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
tHIGH
tF
tR
tLOW
SCL
tSU.STA
tLOW
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA IN
tAA
tDH
tBUF
SDA OUT
6. Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th BIT
ACK
WORDn
(1)
twr
STOP
CONDITION
Note:
START
CONDITION
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
7
5298A–SEEPR–1/08
7. Data Validity
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
8. Start and Stop Definition
SDA
SCL
START
STOP
9. Output Acknowledge
1
SCL
8
9
DATA IN
DATA OUT
START
8
ACKNOWLEDGE
AT24C32C/64C
5298A–SEEPR–1/08
AT24C32C/64C
10. Device Addressing
The 32K/64K EEPROM requires an 8-bit device address word following a start condition to
enable the chip for a read or write operation (see Figure 12-1 on page 11). The device address
word consists of a mandatory one, zero sequence for the first four most significant bits as
shown. This is common to all 2-wire EEPROM devices.
The 32K/64K uses the three device address bits A2, A1, A0 to allow as many as eight devices
on the same bus. These bits must compare to their corresponding hardwired input pins. The A2,
A1, and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the
pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not
made, the device will return to standby state.
DATA SECURITY: The AT24C32C/64C has a hardware data protection scheme that allows the
user to write protect the entire memory when the WP pin is at VCC.
11. Write Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a zero and the addressing device, such as a microcontroller,
must terminate the write sequence with a stop condition. At this time the EEPROM enters an
internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this
write cycle and the EEPROM will not respond until the write is complete (see Figure 12-2 on
page 11).
PAGE WRITE: The 32K/64K EEPROM is capable of 32-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a
stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to 31 more data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 12-3 on page 11).
The data word address lower 5 bits are internally incremented following the receipt of each data
word. The higher data word address bits are not incremented, retaining the memory page row
location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32 data words are transmitted
to the EEPROM, the data word address will “roll over” and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond with
a zero, allowing the read or write sequence to continue.
9
5298A–SEEPR–1/08
12. Read Operations
Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to one. There are three read operations:
current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address “roll over”
during read is from the last byte of the last memory page, to the first byte of the first page. The
address “roll over” during write is from the last byte of the current page to the first byte of the
same page.
Once the device address with the read/write select bit set to one is clocked in and acknowledged
by the EEPROM, the current address data word is serially clocked out. The microcontroller does
not respond with an input zero but does generate a following stop condition (see Figure 12-4 on
page 12).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition. The
microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (see Figure 12-5 on page 12).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory address
limit is reached, the data word address will “roll over” and the sequential read will continue. The
sequential read operation is terminated when the microcontroller does not respond with a zero
but does generate a following stop condition (see Figure 12-6 on page 12).
Figure 12-1. Device Address
Figure 12-2. Byte Write
10
AT24C32C/64C
5298A–SEEPR–1/08
AT24C32C/64C
Figure 12-3. Page Write
t
Note:
1. * = DON’T CARE bits
2. t = DON’T CARE bit for AT24C32C
Figure 12-4. Current Address Read
Figure 12-5. Random Read
Note:
1. * = DON’T CARE bits
11
5298A–SEEPR–1/08
Figure 12-6. Sequential Read
12
AT24C32C/64C
5298A–SEEPR–1/08
AT24C32C/64C
AT24C32C Ordering Information
Ordering Code
Voltage
Package
AT24C32C-PU (Bulk form only)
AT24C32CN-SH-B(1) (NiPdAu Lead Finish)
AT24C32CN-SH-T(2) (NiPdAu Lead Finish)
AT24C32C-TH-B(1) (NiPdAu Lead Finish)
AT24C32C-TH-T(2) (NiPdAu Lead Finish)
AT24C32CY6-YH-T(2) (NiPdAu Lead Finish)
AT24C32CD3-DH-T(2) (NiPdAu Lead Finish)
AT24C32CU2-UU-T(2)
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
8P3
8S1
8S1
8A2
8A2
8Y6
8D3
8U2-1
AT24C32C-W-11(3)
1.8
Die Sale
Notes:
Operation Range
Lead-free/Halogen-free
Industrial Temperature
(-40°C to 85°C)
Industrial Temperature
(-40°C to 85°C)
1. “-B” denotes Bulk.
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP and dBGA2 = 5K per reel.
3. Available in waffle pack, tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon
request. Please contact Serial Interface Marketing.
Package Type
8Y6
8-lead, 2.00mm x 3.00mm Body, 0.50mm Pitch, Ultra Thin Mini-MAP, Dual no Lead Package (DFN), (MLP 2x3)
8P3
8-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2
8-lead, 4.4 mm Body, Plastic, Thin Shrink Small Outline Package (TSSOP)
8U2-1
8-ball, die Ball Grid Array Package (dBGA2)
8D3
8-lead, 1.80 mm x 2.20 mm Body, Ultra Lead Frame Land Grid Array (ULA)
Options
-1.8
Low Voltage (1.8V to 5.5V)
13
5298A–SEEPR–1/08
AT24C64C Ordering Information
Ordering Code
Voltage
Package
AT24C64C-PU (Bulk form only)
AT24C64CN-SH-B(1) (NiPdAu Lead Finish)
AT24C64CN-SH-T(2) (NiPdAu Lead Finish)
AT24C64C-TH-B(1) (NiPdAu Lead Finish)
AT24C64C-TH-T(2) (NiPdAu Lead Finish)
AT24C64CY6-YH-T(2) (NiPdAu Lead Finish)
AT24C64CD3-DH-T(2) (NiPdAu Lead Finish)
AT24C64CU2-UU-T(2)
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
8P3
8S1
8S1
8A2
8A2
8Y6
8D3
8U2-1
AT24C64C-W-11(3)
1.8
Die Sale
Notes:
Operation Range
Lead-free/Halogen-free
Industrial Temperature
(-40°C to 85°C)
Industrial Temperature
(-40°C to 85°C)
1. “-B” denotes Bulk.
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP and dBGA2 = 5K per reel.
3. Available in waffle pack, tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon
request. Please contact Serial Interface Marketing.
Package Type
8Y6
8-lead, 2.00mm x 3.00mm Body, 0.50mm Pitch, Ultra Thin Mini-MAP, Dual no Lead Package (DFN), (MLP 2x3)
8P3
8-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2
8-lead, 4.4 mm Body, Plastic, Thin Shrink Small Outline Package (TSSOP)
8U2-1
8-ball, die Ball Grid Array Package (dBGA2)
8D3
8-lead, 1.80 mm x 2.20 mm Body, Ultra Lead Frame Land Grid Array (ULA)
Options
-1.8
14
Low Voltage (1.8V to 5.5V)
AT24C32C/64C
5298A–SEEPR–1/08
AT24C32C/64C
13. Part Marking Scheme
13.1
8-PDIP
TOP MARK
Seal Year
| Seal Week
|
|
|
|---|---|---|---|---|---|---|---|
A
T
M
L
U
Y
W
W
Y = SEAL YEAR
6: 2006
0: 2010
7: 2007
8: 2008
9: 2009
1: 2011
2: 2012
3: 2013
|---|---|---|---|---|---|---|---|
3
2
C
04 = Week 4
:: : :::: :
:: : :::: ::
50 = Week 50
1
52 = Week 52
|---|---|---|---|---|---|---|---|
*
Lot Number
|---|---|---|---|---|---|---|---|
|
Pin 1 Indicator (Dot)
13.2
WW = SEAL WEEK
02 = Week 2
Lot Number to Use ALL Characters in Marking
BOTTOM MARK
No Bottom Mark
8-SOIC
Seal Year
| Seal Week
TOP MARK
|
|
|
|---|---|---|---|---|---|---|---|
A
T
M
L
H
Y
W
W
Y = SEAL YEAR
6: 2006
0: 2010
7: 2007
8: 2008
9: 2009
1: 2011
2: 2012
3: 2013
|---|---|---|---|---|---|---|---|
3
2
C
04 = Week 4
:: : :::: :
:: : :::: ::
50 = Week 50
1
|---|---|---|---|---|---|---|---|
*
Lot Number
|---|---|---|---|---|---|---|---|
|
Pin 1 Indicator (Dot)
WW = SEAL WEEK
02 = Week 2
52 = Week 52
Lot Number to Use ALL Characters in Marking
BOTTOM MARK
No Bottom Mark
15
5298A–SEEPR–1/08
13.3
8-TSSOP
TOP MARK
Pin 1 Indicator (Dot)
|
|---|---|---|---|
*
H
Y
W
W
|---|---|---|---|---|
3
2
C
Y = SEAL YEAR
6:
7:
8:
9:
2006
2007
2008
2009
0:
1:
2:
3:
WW = SEAL WEEK
2010
2011
2012
2013
1
02
04
::
::
=
=
:
:
Week
Week
::::
::::
2
4
:
::
50 = Week 50
|---|---|---|---|---|
52 = Week 52
BOTTOM MARK
|---|---|---|---|---|---|---|
P
H
|---|---|---|---|---|---|---|
A
A
A
A
A
A
A
|---|---|---|---|---|---|---|
<- Pin 1 Indicator
13.4
8-Ultra Thin Mini MAP
TOP MARK
Y = YEAR OF ASSEMBLY
|---|---|---|
3
2
C
|---|---|---|
H
1
XX = ATMEL LOT NUMBER TO COORESPOND WITH
NSEB TRACE CODE LOG BOOK.
(e.g. XX = AA, AB, AC,...AX, AY, AZ)
|---|---|---|
Y
X
X
|---|---|---|
*
|
Pin 1 Indicator (Dot)
Y =
6:
7:
8:
SEAL YEAR
2006
0: 2010
2007
1: 2011
2008
2: 2012
9: 2009
16
3: 2013
AT24C32C/64C
5298A–SEEPR–1/08
AT24C32C/64C
13.5
8-ULA
TOP MARK
Y = YEAR OF ASSEMBLY
|---|---|---|
2
B C
|---|---|---|
Y
X
XX = ATMEL LOT NUMBER TO COORESPOND WITH
NSEB TRACE CODE LOG BOOK.
(e.g. XX = AA, AB, AC,...AX, AY, AZ)
X
|---|---|---|
*
|
Pin 1 Indicator (Dot)
Y =
6:
7:
8:
BUILD YEAR
2006
2007
2008
Etc...
17
5298A–SEEPR–1/08
14. Part Marking Scheme
14.1
8-PDIP
TOP MARK
Seal Year
| Seal Week
|
|
|
|---|---|---|---|---|---|---|---|
A
T
M
L
U
Y
W
W
Y = SEAL YEAR
6: 2006
0: 2010
7: 2007
8: 2008
9: 2009
1: 2011
2: 2012
3: 2013
|---|---|---|---|---|---|---|---|
6
4
C
52 = Week 52
|
Pin 1 Indicator (Dot)
Lot Number to Use ALL Characters in Marking
BOTTOM MARK
No Bottom Mark
8-SOIC
Seal Year
| Seal Week
TOP MARK
|
|
|
|---|---|---|---|---|---|---|---|
A
T
M
L
H
Y
W
W
Y = SEAL YEAR
6: 2006
0: 2010
7: 2007
8: 2008
9: 2009
1: 2011
2: 2012
3: 2013
|---|---|---|---|---|---|---|---|
6
4
C
WW = SEAL WEEK
02 = Week 2
04 = Week 4
:: : :::: :
:: : :::: ::
50 = Week 50
1
|---|---|---|---|---|---|---|---|
*
Lot Number
|---|---|---|---|---|---|---|---|
|
Pin 1 Indicator (Dot)
18
04 = Week 4
:: : :::: :
:: : :::: ::
50 = Week 50
1
|---|---|---|---|---|---|---|---|
*
Lot Number
|---|---|---|---|---|---|---|---|
14.2
WW = SEAL WEEK
02 = Week 2
52 = Week 52
Lot Number to Use ALL Characters in Marking
BOTTOM MARK
No Bottom Mark
AT24C32C/64C
5298A–SEEPR–1/08
AT24C32C/64C
14.3
8-TSSOP
TOP MARK
Pin 1 Indicator (Dot)
|
|---|---|---|---|
*
H
Y
W
W
|---|---|---|---|---|
6
4
C
Y = SEAL YEAR
6:
7:
8:
9:
2006
2007
2008
2009
0:
1:
2:
3:
WW = SEAL WEEK
2010
2011
2012
2013
1
02
04
::
::
=
=
:
:
Week
Week
::::
::::
2
4
:
::
50 = Week 50
|---|---|---|---|---|
52 = Week 52
BOTTOM MARK
|---|---|---|---|---|---|---|
P
H
|---|---|---|---|---|---|---|
A
A
A
A
A
A
A
|---|---|---|---|---|---|---|
<- Pin 1 Indicator
14.4
8-Ultra Thin Mini MAP
TOP MARK
Y = YEAR OF ASSEMBLY
|---|---|---|
6
4
C
|---|---|---|
H
1
XX = ATMEL LOT NUMBER TO COORESPOND WITH
NSEB TRACE CODE LOG BOOK.
(e.g. XX = AA, AB, AC,...AX, AY, AZ)
|---|---|---|
Y
X
X
|---|---|---|
*
|
Pin 1 Indicator (Dot)
Y =
6:
7:
8:
SEAL YEAR
2006
0: 2010
2007
1: 2011
2008
2: 2012
9: 2009
3: 2013
19
5298A–SEEPR–1/08
14.5
8-ULA
TOP MARK
Y = YEAR OF ASSEMBLY
|---|---|---|
2
C C
|---|---|---|
Y
X
XX = ATMEL LOT NUMBER TO COORESPOND WITH
NSEB TRACE CODE LOG BOOK.
(e.g. XX = AA, AB, AC,...AX, AY, AZ)
X
|---|---|---|
*
|
Pin 1 Indicator (Dot)
Y =
6:
7:
8:
BUILD YEAR
2006
2007
2008
Etc...
20
AT24C32C/64C
5298A–SEEPR–1/08
AT24C32C/64C
15. Packaging Information
8Y6 - MLP
D2
A
b
(8X)
E
E2
Pin 1
Index
Area
Pin 1 ID
L (8X)
D
A2
e (6X)
A1
1.50 REF.
COMMON DIMENSIONS
(Unit of Measure = mm)
A3
SYMBOL
MIN
D
2.00 BSC
E
3.00 BSC
MAX
D2
1.40
1.50
1.60
E2
-
-
1.40
A
-
-
0.60
A1
0.0
0.02
0.05
A2
-
-
0.55
A3
L
b
NOTE
0.20 REF
0.20
e
Notes:
NOM
0.30
0.40
0.50 BSC
0.20
0.25
0.30
2
1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
3. Soldering the large thermal pad is optional, but not recommended. No electrical connection is accomplished to the
device through this pad, so if soldered it should be tied to ground
10/16/07
R
2325 Orchard Parkway
San Jose, CA 95131
DRAWING NO.
TITLE
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,
8Y6
Dual No Lead Package (DFN) ,(MLP 2x3)
REV.
D
21
5298A–SEEPR–1/08
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
SYMBOL
MIN
NOM
A
A2
b2
b3
b
4 PLCS
Side View
L
NOTE
0.210
0.115
0.130
2
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
D1
0.005
E
0.300
E1
0.240
e
3
3
0.310
0.325
4
0.250
0.280
3
0.150
2
0.100 BSC
eA
L
Notes:
MAX
0.300 BSC
0.115
0.130
4
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
22
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
AT24C32C/64C
5298A–SEEPR–1/08
AT24C32C/64C
8S1 – JEDEC SOIC
C
1
E
E1
L
N
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
SYMBOL
MIN
NOM
MAX
A1
0.10
–
0.25
NOTE
D
SIDE VIEW
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
3/17/05
R
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8S1, 8-lead (0.150 Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
REV.
8S1
C
23
5298A–SEEPR–1/08
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
b
D
MIN
NOM
MAX
NOTE
2.90
3.00
3.10
2, 5
4.50
3, 5
E
E1
e
A2
D
6.40 BSC
4.30
A
–
–
1.20
A2
0.80
1.00
1.05
b
0.19
–
0.30
e
Side View
L
0.60
0.75
1.00 REF
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and ad acent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
R
24
4
0.65 BSC
0.45
L1
Notes:
4.40
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
8A2
REV.
B
AT24C32C/64C
5298A–SEEPR–1/08
AT24C32C/64C
8U2-1 - dBGA2
D
A1 BALL PAD CORNER
5.
b
E
A1
TOP VIEW
A2
A1 BALL PAD CORNER
2
A
SIDE VIEW
1
A
B
e
C
D
(e1)
d
(d1)
BOTTOM VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
8 SOLDER BALLS
SYMBOL
A
A1
A2
b
D
E
e
e1
d
5. Dimension 'b' is measured at the maximum solder ball diameter.
d1
MIN
0.81
0.15
0.40
0.25
NOM
MAX
NOTE
0.91 1.00
0.20 0.25
0.45 0.50
0.30 0.35
2.35 BSC
3.73 BSC
0.75 BSC
0.74 REF
0.75 BSC
0.80 REF
This drawing is for general information only.
6/17/03
TITLE
R
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch,
Small Die Ball Grid Array Package (dBGA2)
DRAWING NO.
REV.
PO8U2-1
A
25
5298A–SEEPR–1/08
8D3 - ULA
D
8
7
e1
6
b
5
L
E
PIN #1 ID
0.10
PIN #1 ID
0.15
1
2
3
4
A1
A
TOP VIEW
b
e
BOTTOM VIEW
SIDE VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
A
–
–
0.40
A1
0.00
–
0.05
D
1.70
1.80
1.90
E
2.10
2.20
2.30
b
0.15
0.20
0.25
e
0.40 TYP
e1
L
NOTE
1.20 REF
0.25
0.30
0.35
11/15/05
R
26
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8D3, 8-lead (1.80 x 2.20 mm Body) Ultra Leadframe
Land Grid Array (ULLGA) D3
DRAWING NO.
REV.
8D3
0
AT24C32C/64C
5298A–SEEPR–1/08
AT24C32C/64C
Revision History
Doc. Rev.
Date
Comments
5298A
1/2008
AT24C32C/64C product with date code 2008 work week 14 (814) or later
supports 5Vcc operation
Initial document release
27
5298A–SEEPR–1/08
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International
Atmel Corporation
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USA
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Literature Requests
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5298A–SEEPR–1/08
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