ATF2500C - Complete

Features
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High-performance, High-density, Electrically-erasable Programmable Logic Device
Fully Connected Logic Array with 416 Product Terms
15 ns Maximum Pin-to-pin Delay for 5V Operation
24 Flexible Output Macrocells
– 48 Flip-flops – Two per Macrocell
– 72 Sum Terms
– All Flip-flops, I/O Pins Feed in Independently
D- or T-type Flip-flops
Product Term or Direct Input Pin Clocking
Registered or Combinatorial Internal Feedback
Backward Compatible with ATV2500B/BQ and ATV2500H Software
Advanced Electrically-erasable Technology
– Reprogrammable
– 100% Tested
44-lead Surface Mount Package and 40-pin DIP Package
Flexible Design: Up to 48 Buried Flip-flops and 24 Combinatorial Outputs
Simultaneously
8 Synchronous Product Terms
Individual Asynchronous Reset per Macrocell
OE Control per Macrocell
Functionality Equivalent to ATV2500B/BQ and ATV2500H
2000V ESD Protection
Security Fuse Feature to Protect the Code
Commercial, Industrial and Military Temperature Range Offered
10 Year Data Retention
Pin Keeper Option
200 mA Latch-up Immunity
Green Package Options (Pb/Halide-free/RoHS Compliant) Available
ATF2500C
CPLD Family
Datasheet
ATF2500C
1. Description
The ATF2500C is the highest-density PLD available in a 44-pin surface mount package. With its fully connected logic array and flexible macrocell structure, high gate
utilization is easily obtainable. The ATF2500C is a high-performance CMOS (electrically-erasable) programmable logic device (PLD) that utilizes Atmel’s proven
electrically-erasable technology. This PLD is now available in a fully Green or LHF
(lead and halide-free) packages.
Figure 1-1.
Block Diagram
0777K–PLD–1/24/08
The ATF2500C is organized around a single universal array. All pins and feedback terms are
always available to every macrocell. Each of the 38 logic pins are array inputs, as are the outputs of each flip-flop.
In the ATF2500C, four product terms are input to each sum term. Furthermore, each macrocell’s
three sum terms can be combined to provide up to 12 product terms per sum term with no performance penalty. Each flip-flop is individually selectable to be either D- or T-type, providing
further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal combinatorial feedback to the logic array.
Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip-flops
may also be individually configured to have direct input pin clocking. Each output has its own
enable product term. Eight synchronous preset product terms serve local groups of either four or
eight flip-flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up.
2. Pin Configurations
Pin Configurations
Pin Name
Function
IN
Logic Inputs
CLK/IN
Pin Clock and Input
I/O
Bi-directional Buffers
I/O 0,2,4...
Even I/O Buffers
I/O 1,3,5...
Odd I/O Buffers
GND
Ground
VCC
+5V Supply
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
IN
IN
IN
IN
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
GND
I/O23
I/O22
I/O21
I/O20
I/O19
I/O18
IN
IN
IN
PLCC
I/O1
I/O0
GND
IN
IN
CLK/IN
IN
IN
IN
IN
I/O6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Figure 2-2.
I/O2
I/O3
I/O4
I/O5
VCC
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
6
5
4
3
2
1
44
43
42
41
40
CLK/IN
IN
IN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
IN
IN
IN
IN
DIP
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
I/O7
I/O8
I/O9
I/O10
I/O11
GND
GND
I/O23
I/O22
I/O21
I/O20
I/O12
IN
IN
IN
IN
IN
IN
IN
GND
I/O18
I/O19
Figure 2-1.
18
19
20
21
22
23
24
25
26
27
28
Table 2-1.
Note:
(PLCC package) pin 4 and pin 26 GND connections are
not required, but are recommended for improved noise
immunity.
ATF2500C
0777K–PLD–1/24/08
ATF2500C
3. Using the ATF2500C Family’s Many Advanced Features
The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs.
Some of the ATF2500Cs key features are:
• Fully Connected Logic Array – Each array input is always available to every product term.
This makes logic placement a breeze.
• Selectable D- and T-Type Registers – Each ATF2500C flip-flop can be individually
configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also
easily created. These options allow more efficient product term usage.
• Buried Combinatorial Feedback – Each macrocell’s Q2 register may be bypassed to feed
its input (D/T2) directly back to the logic array. This provides further logic expansion capability
without using precious pin resources.
• Selectable Synchronous/Asynchronous Clocking – Each of the ATF2500Cs flip-flops has
a dedicated clock product term. This removes the constraint that all registers use the same
clock. Buried state machines, counters and registers can all coexist in one device while
running on separate clocks. Individual flip-flop clock source selection further allows mixing
higher performance pin clocking and flexible product term clocking within one design.
• A Total of 48 Registers – The ATF2500C provides two flip-flops per macrocell – a total of 48.
Each register has its own clock and reset terms, as well as its own sum term.
• Independent I/O Pin and Feedback Paths – Each I/O pin on the ATF2500C has a dedicated
input path. Each of the 48 registers has its own feedback term into the array as well. These
features, combined with individual product terms for each I/O’s output enable, facilitate true
bi-directional I/O design.
• Combinable Sum Terms – Each output macrocell’s three sum terms may be combined into
a single term. This provides a fan in of up to 12 product terms per sum term with no speed
penalty.
• Programmable Pin-keeper Circuits – These weak feedback latches are useful for bus
interfacing applications. Floating pins can be set to a known state if the Pin-keepers are
enabled.
• User Row (64 bits) – Use to store information such as unit history.
3
0777K–PLD–1/24/08
4. Power-up Reset
The registers in the ATF2500Cs are designed to reset during power-up. At a point delayed
slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will
depend on the polarity of the output buffer.
This feature is critical for state as nature of reset and the uncertainty of how VCC actually rises in
the system, the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving the
clock pin or terms high, and
3. The clock pin, and any signals from which clock terms are derived, must remain stable
during tPR.
4
Figure 4-1.
Power-up Reset Waveform
Table 4-1.
Power-up Reset
Parameter
Description
Typ
Max
Units
tPR
Power-up Reset Time
600
1000
ns
VRST
Power-up Reset Voltage
3.8
4.5
V
ATF2500C
0777K–PLD–1/24/08
ATF2500C
5. Preload and Observability of Registered Outputs
The ATF2500Cs registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. This feature will simplify testing since any state can be forced
into the registers to control test sequencing. A VIH level on the odd I/O pins will force the appropriate register high; a VIL will force it low, independent of the polarity or other configuration bit
settings.
The PRELOAD state is entered by placing an 10.25V to 10.75V signal on SMP lead 42. When
the preload clock SMP lead 23 is pulsed high, the data on the I/O pins is placed into the 12 registers chosen by the Q select and even/odd select pins.
Register 2 observability mode is entered by placing an 10.25V to 10.75V signal on pin/lead 2. In
this mode, the contents of the buried register bank will appear on the associated outputs when
the OE control signals are active.
Figure 5-1.
Preload Waveforms
Table 5-1.
Preload Levels
Level Forced on Odd
I/O Pin during
PRELOAD Cycle
Q Select
Pin State
Even/Odd
Select
Even Q1
State after
Cycle
Even Q2
State after
Cycle
Odd Q1
State after
Cycle
Odd Q2
State after
Cycle
VIH/VIL
Low
Low
High/Low
X
X
X
VIH/VIL
High
Low
X
High/Low
X
X
VIH/VIL
Low
High
X
X
High/Low
X
VIH/VIL
High
High
X
X
X
High/Low
5
0777K–PLD–1/24/08
6. Software Support
All family members of the ATF2500C can be designed with Atmel-WinCUPL.
Additionally, the ATF2500C may be programmed to perform the ATV2500Hs functional subset
(no T-type flip-flops, pin clocking or D/T2 feedback) using the ATV2500H JEDEC file. In this
case, the ATF2500C becomes a direct replacement or speed upgrade for the ATV2500H. The
ATF2500C are direct replacements for the ATV2500B/BQ and the ATV2500H, including the lack
of extra grounds on P4 and P26.
6.1
Software Compiler Mode Selection
Table 6-1.
6.2
Software Compiler Mode Selection
Device
Atmel - WinCupL Device Mnemonic
Pin-keeper
ATF2500C-DIP
V2500C
V2500CPPK
Disabled
Enabled
ATF2500C-PLCC
V2500LCC
V2500CPPKLCC
Disabled
Enabled
Third Party Programmer Support
Table 6-2.
Third Party Programmer Support
Major Third Party Device Programmers support three types of JEDEC files.
Device
ATF2500C (V2500)
V2500 Cross-programming. JEDEC file compatible with standard V2500
JEDEC file (Total fuses in JEDEC file = 71648). The Programmer will
automatically disable the User row fuses and also disable the pin-keeper
feature. The Fuse checksum will be the same as the old ATV2500H/L file.
This Device type is recommended for customers that are directly migrating
from an ATV2500H/L device to an ATF2500C device.
ATF2500C (V2500B)
V2500B Cross-programming. JEDEC file compatible with standard
V2500B JEDEC file (Total fuses in JEDEC file = 71745). The Programmer
will automatically disable the User row fuses and also disable the pin-keeper
feature. The Fuse checksum will be the same as the old
ATV2500B/BQ/BQL/BL file. This Device type is recommended for customers
that are directly migrating from an ATV2500B/BQ/BQL/BL device to an
ATF2500C device.
ATF2500C
Programming of User Row bits supported and Pin keeper bit is userprogrammable. (Total fuses in JEDEC file = 71816). This is the default device
type and is recommended for users that have Re-compiled their Source
Design files to specifically target the ATF2500C device.
Note:
6
Description
The ATF2500C has 71816 Jedec fuses.
ATF2500C
0777K–PLD–1/24/08
ATF2500C
7. Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of ATF2500C fuse patterns. Once programmed, the outputs will read programmed during verify.
The security fuse should be programmed last, as its effect is immediate.
The security fuse also inhibits Preload and Q2 observability.
8. Bus-friendly Pin-keeper Input and I/O
All ATF2500C family members have programmable internal input and I/O pin-keeper circuits.
The default condition, including when using the AT2500C/CQ family to replace the AT2500B/BQ
or AT2500H, is that the pin-keepers are not activated.
When pin-keepers are active, inputs or I/Os not being driven externally will maintain their last
driven state. This ensures that all logic array inputs and device outputs are known states. Pinkeepers are relatively weak active circuits that can be easily overridden by TTL-compatible drivers (see input and I/O diagrams below).
Enabling or disabling of the pin-keeper circuits is controlled by the device type chosen in the
logic compiler device selection menu. Please refer to the Software Compiler Mode Selection
table for more details. Once the pin-keeper circuits are disabled, normal termination procedures
required for unused inputs and I/Os.
Figure 8-1.
Input Diagram
PROGRAMMABLE
OPTION
7
0777K–PLD–1/24/08
Figure 8-2.
I/O Diagram
INPUT
PROGRAMMABLE
OPTION
9. Functional Logic Diagram Description
The ATF2500C functional logic diagram describes the interconnections between the input, feedback pins and logic cells. All interconnections are routed through the single global bus.
The ATF2500Cs are straightforward and uniform PLDs. The 24 macrocells are numbered 0
through 23. Each macrocell contains 17 AND gates. All AND gates have 172 inputs. The five
lower product terms provide AR1, CK1, CK2, AR2, and OE. These are: one asynchronous reset
and clock per flip-flop, and an output enable. The top 12 product terms are grouped into three
sum terms, which are used as shown in the macrocell diagrams.
Eight synchronous preset terms are distributed in a 2/4 pattern. The first four macrocells share
Preset 0, the next two share Preset 1, and so on, ending with the last two macrocells sharing
Preset 7.
The 14 dedicated inputs and their complements use the numbered positions in the global bus as
shown. Each macrocell provides six inputs to the global bus: (left to right) feedback F2(1) true
and false, flip-flop Q1 true and false, and the pin true and false. The positions occupied by these
signals in the global bus are the six numbers in the bus diagram next to each macrocell.
Note:
8
1. Either the flip-flop input (D/T2) or output (Q2) may be fed back in the ATF2500Cs.
ATF2500C
0777K–PLD–1/24/08
ATF2500C
9.1
Functional Logic Diagram ATF2500C
Notes:
1. Pin 4 and Pin 26 are “ground” connections and are not required for PLCC, LCC and JLCC versions of ATF2500C, making
them compatible with ATV2500H, ATV2500B and ATV2500BQ pinouts.
2. For DIP package, VCC = P10 and GND = P30. For, PLCC, LCC and JLCC packages, VCC = P11 and P12, GND = P33 and
P34, and GND = P4, P26 (See Note 1, above).
9
0777K–PLD–1/24/08
9.2
Output Logic, Registered(1)
S2 = 0
Terms in
S1
S0
D/T1
D/T2
0
0
8
4
Registered (Q1); Q2 FB
1
0
12
4(1)
Registered (Q1); Q2 FB
1
1
8
4
S3
Output Configuration
Registered (Q1); D/T2 FB
Output
Configuration
S6
0
Active Low
0
CK1
1
Active High
1
CK1 • PIN1
S4
Register 1 Type
0
D
0
CK2
1
T
1
CK2 • PIN1
S2 = 1
Output Logic, Combinatorial(1)
0
D
1
T
Terms in
S1
S0
D/T1
D/T2
X
0
0
4(1)
4
Combinatorial (8 Terms);
Q2 FB
X
0
1
4
4
Combinatorial (4 Terms);
Q2 FB
X
1
0
4(1)
4(1)
Combinatorial (12 Terms);
Q2 FB
1
1
1
4(1)
4
Combinatorial (8 Terms);
D/T2 FB
0
1
1
4
4
Combinatorial (4 Terms);
D/T2 FB
Output Configuration
1. These four terms are shared with D/T1.
Figure 9-1.
10
Register 2 Type
S5
Note:
Note:
Q2 CLOCK
S7
S5
9.3
Q1 CLOCK
Clock Option
1. These diagrams show equivalent logic functions, not
necessarily the actual circuit implementation.
ATF2500C
0777K–PLD–1/24/08
ATF2500C
10. Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Junction Temperature ............................................. 150°C Max
Note:
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is VCC + 0.75V DC
which may overshoot to +7.0V for pulses of less
than 20 ns.
11. DC and AC Operating Conditions
Operating Temperature
Commercial
Industrial
Military
0°C - 70°C
(Ambient)
-40°C - 85°C
(Ambient)
-55°C - 125°C
(Case)
5V ± 5%
5V ± 10%
5V ± 10%
VCC Power Supply
11.1
ATF2500C DC Characteristics
Symbol
Parameter
Condition
IIL
Input Load Current
ILO
ICC
Max
Units
VIN = -0.1V to VCC + 1V
10
µA
Output Leakage
Current
VOUT = -0.1V to VCC + 0.1V
10
µA
Power Supply
Current Standby
VCC = MAX,
VIN = GND or
VCC f = 0 MHz,
Outputs Open
VIL
Input Low Voltage
MIN ≤VCC ≤MAX
VIH
Input High Voltage
VOL
Output Low
Voltage
VIN = VIH or VIL,
VCC = 4.5V
VOH
Output High
Voltage
VCC = MIN
Note:
Min
Typ
Com.
80
110
mA
Ind., Mil.
80
130
mA
-0.6
0.8
V
2.0
VCC + 0.75
V
ATF2500C
IOL = 8 mA
Com., Ind.
0.5
V
IOL = 6 mA
Mil.
0.5
V
IOH = -100 µA
VCC - 0.3
IOH = -4.0 mA
2.4
V
1. See ICC versus frequency characterization curves.
11
0777K–PLD–1/24/08
11.2
AC Waveforms(1) Input Pin Clock
11.3
AC Waveforms(1) Product Term Clock
11.4
AC Waveforms(1) Combinatorial Outputs and Feedback
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
12
ATF2500C
0777K–PLD–1/24/08
ATF2500C
11.5
ATF2500C AC Characteristics
-15
Symbol
Parameter
tPD1
Input to Non-registered Output
tPD2
Max
Units
15
20
ns
Feedback to Non-registered Output
15
20
ns
tPD3
Input to Non-registered Feedback
11
15
ns
tPD4
Feedback to Non-registered Feedback
11
15
ns
tEA1
Input to Output Enable
15
20
ns
tER1
Input to Output Disable
15
20
ns
tEA2
Feedback to Output Enable
15
20
ns
tER2
Feedback to Output Disable
15
20
ns
tAW
Asynchronous Reset Width
tAP
Asynchronous Reset to Registered Output
18
22
ns
tAPF
Asynchronous Reset to Registered Feedback
15
19
ns
11.6
Min
-20
Max
Min
8
12
ns
ATF2500C Register AC Characteristics, Input Pin Clock
-15
-20
Symbol
Parameter
tCOS
Clock to Output
tCFS
Clock to Feedback
0
tSIS
Input Setup Time
9
14
ns
tSFS
Feedback Setup Time
9
14
ns
tHS
Hold Time
0
0
ns
tWS
Clock Width
6
7
ns
tPS
Clock Period
12
14
ns
FMAXS
tARS
Min
Max
Min
10
5
0
Max
Units
11
ns
6
ns
External Feedback 1/(tSIS + tCOS)
52
40
MHz
Internal Feedback 1/(tSFS + tCFS)
71
50
MHz
No Feedback 1/(tPS)
83
71
MHz
Asynchronous Reset/Preset Recovery Time
12
15
ns
13
0777K–PLD–1/24/08
11.7
ATF2500C Register AC Characteristics, Product Term Clock
-15
Symbol
Parameter
tCOA
Clock to Output
tCFA
Clock to Feedback
5
tSIA
Input Setup Time
5
10
ns
tSFA
Feedback Setup Time
5
8
ns
tHA
Hold Time
5
10
ns
tWA
Clock Width
7.5
11
ns
tPA
Clock Period
15
22
ns
FMAXA
tARA
11.8
Min
-20
Max
Min
15
12
10
Max
Units
20
ns
16
ns
External Feedback 1/(tSIA + tCOA)
50
33
MHz
Internal Feedback 1/(tSFA + tCFA)
58
38
MHz
No Feedback 1/(tPS)
66
45
MHz
Asynchronous Reset/Preset Recovery Time
8
12
ns
Pin Capacitance
f = 1 MHz, T = 25°C (1)
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
11.9
Test Waveforms and Measurement Levels
11.10 Output Test Load
14
ATF2500C
0777K–PLD–1/24/08
ATF2500C
12. ATF2500C Characterization Data
STAND-BY ICC VS. TEMPERATURE (VCC = 5.0V)
90.0
ICC (mA)
-10
IOH (mA)
100.0
ATF2500C OUTPUT SOURCE CURRENT VS.
SUPPLY VOLTAGE (VOH = 2.4V, TA = 25°C)
-20
80.0
70.0
-30
60.0
-40
4.50
4.75
5.00
5.25
SUPPLY VOLTAGE (V)
50.0
-40.0
5.50
SUPPLY VOLTAGE (TA = 25°C)
100.0
14
90.0
13
ICC (mA)
IOL (mA)
85.0
STAND-BY ICC VS.
ATF2500C OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (V O L = 0.5V, T A = 25°C)
15
25.0
TEMPERATURE (°C)
12
11
10
4.50
4.75
5.00
5.25
SUPPLY VOLTAGE (V)
80.0
70.0
60.0
5.50
50.0
4.5
4.8
5.0
5.3
5.5
SUPPLY VOLTAGE (V)
ATF2500C OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0.0
50
-20.0
INPUT
CURRENT (mA)
IOH (mA)
-10.0
-30.0
-40.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
ATF2500C INPUT CLAMP CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0
-50
-100
-150
-200
-1.4
OUTPUT VOLTAGE (V)
-1.2
-1.0
-0.8
-0.6
-0.4
INPUT VOLTAGE (V)
-0.2
0.0
ATF2500C OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE (V CC = 5.0V, T A = 25°C)
50
A TF2500C IN PU T C U R R EN T VS.
IN PU T VOLTA GE (V CC = 5.0V, T A = 25°C )
40
30
20
ICC (mA)
IOL (mA)
40
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT VOLTAGE (V)
3.5
4.0
4.5
5.0
30
20
10
0
-10
-20
-30
0.0
0.5
1.0
1.5 2.0 2.5 3.0 3.5
INPUT VOLTAGE (V )
4.0
4.5
5.0
15
0777K–PLD–1/24/08
NORMALIZED TPD VS. SUPPLY VOLTAGE
ATF2500C OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
-2
I OH (mA)
(TA = 25°C)
1.2
TPD NORMALIZED
0
-4
-6
1.1
1.0
0.9
-8
4.5
4.6
4.7
4.8
4.9
5.0
0.8
4.50
Output Voltage (V)
TPD NORMALIZED
1.1
30
IOL (mA)
25
20
15
10
5
1.0
0.9
0.8
-40.0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
5.50
NORMALIZED TPD VS. AMBIENT TEMP (VCC = 5V)
ATF2500C OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0.0
4.75
5.00
5.25
SUPPLY VOLTAGE (V)
0.9
25.0
AMBIENT TEMPERATURE (°C)
1.0
85.0
OUTPUT VOLTAGE (V)
NORMALIZED TCOS VS. SUPPLY VOLTAGE
1.1
100
TCOS NORMALIZED
ATF2500C SUPPLY CURRENT VS. SUPPLY
VOLTAGE (Freq. = 0 MHz, TA = 25°C)
ICC (mA)
90
80
70
1.0
0.9
4.50
60
50
4.50
4.75
5.00
5.25
(TA = 25°C)
4.75
5.00
5.25
SUPPLY VOLTAGE (V)
5.50
5.50
Supply Voltage (V)
NORMALIZED TCOS VS. AMBIENT TEMP
(VCC = 5V)
100
80
1.0
0.9
0.8
-40.0
60
0
16
1.1
TCOS NORMALIZED
ICC (mA)
120
ATF2500C SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
10
20
30
40
50
60
FREQUENCY (MHz)
70
80
90
25.0
AMBIENT TEMPERATURE (°C)
85.0
ATF2500C
0777K–PLD–1/24/08
ATF2500C
NORMALIZED TCOA VS. SUPPLY VOLTAGE
1.3
TCOA NORMALIZED
NORMALIZED TSIS VS. AMBIENT TEMP
(TA = 25°C)
TSIS NORMALIZED
1.2
1.1
1.0
0.9
0.8
4.50
4.75
5.00
SUPPLY VOLTAGE (V)
5.25
1.1
1.0
0.9
0.8
-40.0
5.50
TSIA NORMALIZED
TCOA NORMALIZED
1.0
0.9
25.0
1.1
1.0
0.9
0.8
4.50
85.0
AMBIENT TEMPERATURE (°C)
NORMALIZED TSIS VS. SUPPLY VOLTAGE
TSIA NORMALIZED
1.2
1.0
0.9
4.75
5.00
SUPPLY VOLTAGE (V)
5.25
4.75
5.00
SUPPLY VOLTAGE (V)
5.25
5.50
NORMALIZED TSIA VS. AMBIENT TEMP
(TA = 25°C)
1.1
0.8
4.50
(TA = 25°C)
1.2
1.1
1.2
85.0
NORMALIZED TSIA VS. SUPPLY VOLTAGE
(VCC = 5V)
0.8
-40.0
25.0
AMBIENT TEMPERATURE (°C)
NORMALIZED TCOA VS. AMBIENT TEMP
TSIS NORMALIZED
(VCC = 5V)
1.2
5.50
(VCC = 5V)
1.1
1.0
0.9
0.8
-40.0
25.0
85.0
AMBIENT TEMPERATURE (°C)
17
0777K–PLD–1/24/08
13. Ordering Information
13.1
tPD
(ns)
15
20
13.2
Standard Package Options
tCOS
(ns)
10
11
Ext. fMAXS
(MHz)
Package
Operation Range
ATF2500C-15JC
44J
Commercial
(0° C to 70° C)
ATF2500C-15JI
44J
Industrial
(-40° C to 85° C)
ATF2500C-20JC
ATF2500C-20PC
44J
40P6
Commercial
(0° C to 70° C)
ATF2500C-20JI
ATF2500C-20PI
44J
40P6
Industrial
(-40° C to 85° C)
Package
Operation Range
ATF2500C-20KM
44K
ATF2500C-20GM
40D6
Military
(-55° C to 125° C)
52
40
Military Temperature Grade Standard Package Options
tPD
(ns)
tCOS
(ns)
Ext. fMAXS
(MHz)
20
11
40
13.3
Ordering Code
Ordering Code
Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD
(ns)
tCOS
(ns)
Ext. fMAXS
(MHz)
Ordering Code
Package
Operation Range
15
10
52
ATF2500C-15JU
44J
20
11
40
ATF2500C-20PU
40P6
Industrial
(-40° C to 85° C)
Package Type
40D6
40-lead, Non-windowed, Ceramic Dual Inline Package (Cer DIP)
40P6
40-pin, 0.600" Wide, Plastic, Dual Inline Package (PDIP)
44J
44-lead, Plastic J-leaded Chip Carrier (PLCC)
44K
44-lead, Non-windowed, Ceramic J-leaded Chip Carrier (JLCC)
18
ATF2500C
0777K–PLD–1/24/08
ATF2500C
14. Packaging Information
14.1
40D6 – DIP (CerDIP)
Dimensions in Millimeters and (Inches).
Controlling dimension: Inches.
MIL-STD 1835 D-5 Config A (Glass Sealed)
53.09(2.090)
51.82(2.040)
PIN
1
15.49(0.610)
12.95(0.510)
48.26(1.900) REF
5.72(0.225)
MAX
0.127(0.005)MIN
SEATING
PLANE
1.78(0.070)
5.08(0.200)
0.38(0.015)
3.18(0.125)
0.66(0.026)
1.65(0.065)
2.54(0.100)BSC
0.36(0.014)
1.14(0.045)
15.70(0.620)
15.00(0.590)
0.46(0.018)
0º~ 15º REF
0.20(0.008)
17.80(0.700) MAX
10/23/03
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
40D6, 40-lead, 0.600" Wide, Non-windowed,
Ceramic Dual Inline Package (Cerdip)
DRAWING NO.
40D6
REV.
B
19
0777K–PLD–1/24/08
14.2
40P6 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
0º ~ 15º
C
COMMON DIMENSIONS
(Unit of Measure = mm)
REF
MIN
NOM
MAX
A
–
–
4.826
A1
0.381
–
–
D
52.070
–
52.578
E
15.240
–
15.875
E1
13.462
–
13.970
B
0.356
–
0.559
B1
1.041
–
1.651
L
3.048
–
3.556
C
0.203
–
0.381
eB
15.494
–
17.526
SYMBOL
eB
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
e
NOTE
Note 2
Note 2
2.540 TYP
09/28/01
R
20
2325 Orchard Parkway
San Jose, CA 95131
TITLE
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
DRAWING NO.
40P6
REV.
B
ATF2500C
0777K–PLD–1/24/08
ATF2500C
14.3
44J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
D2/E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
17.399
–
17.653
D1
16.510
–
16.662
E
17.399
–
17.653
E1
16.510
–
16.662
D2/E2
14.986
–
16.002
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
44J
B
21
0777K–PLD–1/24/08
14.4
44K – JLCC
D
0.89 X 45˚
1.14 X 45˚
D1
C
E2
b1
E
E1
b
e
A2
A1
A
0.20 C
D2
c
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
.025(.635) RADIUS MAX (3X)
MIN
NOM
MAX
A
3.93
4.36
4.57
A1
2.28
2.66
3.04
NOTE
A2
0.89
-
1.14
D
17.40
17.52
17.65
D1
16.38
16.63
16.89
D2
15.00
15.50
16.00
E
17.40
17.52
17.65
E1
16.38
16.63
16.89
E2
15.00
15.50
16.00
b
0.66
0.73
0.81
b1
c
0.43
-
0.58
-
0.30
0.15
e
1.27 TYP
Note : Refer to MIL-STD-1835C-J1
R
2325 Orchard Parkway
San Jose, CA 95131
09/18/01
TITLE
44K, 44-lead, Non-windowed, Ceramic J-leaded Chip Carrier (JLCC)
DRAWING NO.
44K
REV.
A
15. Revision History
22
ATF2500C
0777K–PLD–1/24/08
ATF2500C
Revision Level –
Release Date
History
J – May 2005
Added fully Green and Military temperatures packages in Section 13. ”Ordering Information”
on page 18.
K – Jan. 2008
Added 40-pin CerDIP Package Option.
23
0777K–PLD–1/24/08
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
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France
Tel: (33) 1-30-60-70-00
Fax: (33) 1-30-60-71-11
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Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Technical Support
[email protected]
Sales Contact
www.atmel.com/contacts
Product Contact
Web Site
www.atmel.com
Literature Requests
www.atmel.com/literature
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0777K–PLD–1/24/08
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