ATA6826C Triple Half-bridge DMOS Output Driver with Serial Input Control DATASHEET Features ● Supply voltage up to 40V ● RDSon typically 0.8 at 25°C, Maximum 1.5 at 150°C ● Up to 1.0A output current ● Three half-bridge outputs formed by three high-side and three low-side drivers ● Capable of switching all kinds of loads such as DC motors, bulbs, resistors, capacitors and inductors ● No shoot-through current ● Very low quiescent current IS < 2µA in Standby Mode versus total temperature range ● Outputs short-circuit protected ● Overtemperature protection for each switch and overtemperature prewarning ● Undervoltage protection ● Various diagnostic functions such as shorted output, open-load, overtemperature and power-supply fail detection ● Serial data interface, daisy chain capable, up to 2MHz clock frequency ● SO14 power package 9213F-AUTO-08/15 1. Description The Atmel® ATA6826C is a fully protected triple half-bridge designed in smart power SOI Technology, used to control up to three different loads by a microcontroller in automotive and industrial applications. Each of the three high-side and three low-side drivers is capable of driving currents up to 1.0A. The drivers are internally connected to form three half-bridges and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC design especially supports the application of H-bridges to drive DC motors. Protection is guaranteed regarding short-circuit conditions, overtemperature and undervoltage. Various diagnostic functions and a very low quiescent current in standby mode opens a wide range of applications. Automotive qualification gives added value and enhanced quality for exacting requirements of automotive applications. Figure 1-1. Block Diagram n. u. n. u. O C S n. u. n. u. n. u. n. u. n. u. n. u. H S 3 Input register Output register DI 5 P S F O P L S C D n. u. n. u. L S 3 H S 2 L S 2 H S 1 L S 1 S R R 3 Serial interface n. u. n. u. n. u. n. u. H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 VS Charge pump T P CLK 6 CS Fault detect INH UV protection 4 Fault detect Fault detect 11 10 Control logic DO 9 VCC Power-on reset 1 7 Fault detect Fault detect 2 OUT3 2 ATA6826C [DATASHEET] 9213F–AUTO–08/15 Fault detect 12 OUT2 Thermal protection 13 OUT1 8 14 GND GND GND GND 2. Pin Configuration Figure 2-1. Pinning SO14 GND OUT3 VS CS DI CLK GND Table 2-1. 1 2 3 4 5 6 7 14 13 12 11 10 9 8 GND OUT1 OUT2 VCC INH DO GND Pin Description Pin Symbol 1 GND Function Ground; reference potential; internal connection to pin 7, 8 and 14; cooling tab 2 OUT3 Half-bridge output 3; formed by internally connected power MOS high-side switch 3 and lowside switch 3 with internal reverse diodes; short-circuit protection; overtemperature protection; diagnosis for short and open load 3 VS Power supply for output stages OUT1, OUT2 and OUT3, internal supply 4 CS Chip select input; 5V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled 5 DI Serial data input; 5V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first 6 CLK Serial clock input; 5V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2MHz) 7 GND Ground; see pin 1 8 GND Ground; see pin 1 9 DO Serial data output; 5V CMOS logic level tristate output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate on only one data output line. 10 INH Inhibit input; 5V logic input with internal pull down; low = standby, high = normal operation 11 VCC Logic supply voltage (5V) 12 OUT2 Half-bridge output 2; see pin 2 13 OUT1 Half-bridge output 1; see pin 2 14 GND Ground; see pin 1 ATA6826C [DATASHEET] 9213F–AUTO–08/15 3 3. Functional Description 3.1 Serial Interface Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and is accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3-1. Data Transfer CS DI SRR 0 LS1 1 HS1 2 LS2 3 HS2 LS3 HS3 n. u. n. u. n. u. 4 5 6 7 8 9 S2H S3L S3H n. u. n. u. n. u. n. u. 10 n. u. 11 n. u. 12 OCS 13 n. u. 14 n. u. 15 CLK DO Table 3-1. 4 TP S1L S1H S2L n. u. n. u. n. u. SCD OPL PSF Input Data Protocol Bit Input Register 0 SRR Status register reset (high = reset; the bits PSF, OPL and SCD in the output data register are set to low) 1 LS1 Controls output LS1 (high = switch output LS1 on) 2 HS1 Controls output HS1 (high = switch output HS1 on) 3 LS2 See LS1 4 HS2 See HS1 5 LS3 See LS1 6 HS3 See HS1 7 n. u. Not used 8 n. u. Not used 9 n. u. Not used 10 n. u. Not used 11 n. u. Not used 12 n. u. Not used 13 OCS Overcurrent shutdown (high = overcurrent shutdown is active) 14 n. u. Not used 15 n. u. Not used ATA6826C [DATASHEET] 9213F–AUTO–08/15 Function Table 3-2. Output Data Protocol Bit Output (Status) Register 0 TP Function Temperature prewarning: high = warning 1 Status LS1 High = output is on, low = output is off; not affected by SRR 2 Status HS1 High = output is on, low = output is off; not affected by SRR 3 Status LS2 Description see LS1 4 Status HS2 Description see HS1 5 Status LS3 Description see LS1 6 Status HS3 Description see HS1 7 n. u. Not used 8 n. u. Not used 9 n. u. Not used 10 n. u. Not used 11 n. u. Not used 12 n. u. Not used 13 SCD Short circuit detected: set high when at least one high-side or low-side switch is switched off by a short-circuit condition. Bits 1 to 6 can be used to detect the shorted switch. 14 OPL Open load detected: set high, when at least one active high-side or low-side switch sinks/sources a current below the open load threshold current. 15 PSF Power-supply fail: undervoltage at pin VS detected After power-on reset, the input register has the following status: Bit 15 Bit 14 x x Bit 13 (OCS) H Bit 12 Bit 11 x x Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 (HS3) Bit 5 (LS3) Bit 4 (HS2) x x x x L L L Bit 3 Bit 2 Bit 1 (LS2) (HS1) (LS1) L L L Bit 0 (SRR) L The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during normal operation. Bit 15 Bit 14 Bit 13 (OCS) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 (HS3) Bit 5 (LS3) Bit 4 (HS2) Bit 3 Bit 2 Bit 1 (LS2) (HS1) (LS1) Bit 0 (SRR) L L L L L L L L L H H H H H L L H H H L L H H L L L L L L L L L H H H L L L L H H L L L L L L L ATA6826C [DATASHEET] 9213F–AUTO–08/15 5 3.2 Power-supply Fail In case of undervoltage at pin VS, the Power-Supply Fail bit (PSF) in the output register is set and all outputs are disabled. To detect an undervoltage, its duration has to be longer than the undervoltage detection delay time tdUV. The outputs are enabled immediately when supply voltage recovers to a normal operating value. The PSF bit stays high until it is reset by the SRR (Status Register Reset) bit in the input register. 3.3 Open-load Detection If the current through a high-side or low-side switch in the ON-state stays below the open-load detection threshold, the openload detection bit (OPL) in the output register is set. The OPL bit stays high until it is reset by the SRR bit in the input register. To detect an open load, its duration has to be longer than the open-load detection delay time tdOL. 3.4 Overtemperature Protection If the junction temperature of one or more output stages exceeds the thermal prewarning threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word. The status of TP is available at pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the status of input and output registers. If the junction temperature of one or more output stages exceeds the thermal shutdown threshold, Tj switch off, all outputs are disabled and the corresponding bits in the output register are set to low. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold, Tjswitch on and the SRR bit in the input register is set to high. Hysteresis of thermal pre-warning and shutdown threshold avoids oscillations. 3.5 Short-circuit Protection The output currents are limited by a current regulator. Overcurrent detection is activated by writing a high to the OCS (Overcurrent Shutdown) bit in the input register. When the current in an output stage exceeds the overcurrent limitation and shutdown threshold, it is switched off after a delay time (tdSd). The short-circuit detection bit (SCD) is set and the corresponding status bit in the output register is set to low. For OCS = low the overcurrent shutdown is inactive. The SCD bit is also set if the current exceeds the overcurrent limitation and shutdown threshold, but the outputs are not affected. By writing a high to the SRR bit in the input register the SCD bit is reset and the disabled outputs are enabled. 3.6 Inhibit Applying 0V to pin 10 (INH) inhibits the Atmel® ATA6826C. All output switches are then turned off and switched to tri-state. The data in the output register is deleted. The current consumption is reduced to less than 2µA at pin VS and less than 25µA at pin VCC. The output switches can be activated again by switching pin 10 (INH) to 5V which initiates an internal power-on reset. 6 ATA6826C [DATASHEET] 9213F–AUTO–08/15 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All values refer to GND pins. Parameters Pin Symbol Value Unit Supply voltage 3 VVS –0.3 to +40 V Supply voltage t < 0.5s; IS > –2A 3 VVS –1 V Logic supply voltage 11 VVCC –0.3 to +7 V 4 to 6, 10 VCS,VDI, VCLK, VINH –0.3 to VVCC + 0.3 V 9 VDO –0.3 to VVCC + 0.3 V 4 to 6, 10 ICS,IDI, ICLK, IINH –10 to +10 mA Output current 9 IDO –10 to +10 mA Output current 2, 12 and 13 IOut3, IOut2, IOut1 Internally limited, see output specification Output voltage 2, 12 and 13 IOut3, IOut2, IOut1 –0.3 to +40 V Reverse conducting current (tpulse = 150µs) 2, 12 and 13 towards pin 3 IOut3, IOut2, IOut1 17 A Junction temperature range TJ –40 to +150 °C Storage temperature range TSTG –55 to +150 °C Logic input voltage Logic output voltage Input current 5. Thermal Resistance Parameters Test Conditions Junction pin Measured to GND Pins 1, 7, 8 and 14 Junction ambient 6. Symbol Value Unit RthJP 30 K/W RthJA 65 K/W Operating Range Parameters Symbol Value Unit Supply voltage VVS VUV(1) to 40 V Logic supply voltage VVCC 4.75 to 5.25 V VCS,VDI, VCLK, VINH –0.3 to VVCC V fCLK 2 MHz Tj –40 to +150 °C Logic input voltage Serial interface clock frequency Junction temperature range Note: Threshold for undervoltage detection ATA6826C [DATASHEET] 9213F–AUTO–08/15 7 7. Noise and Surge Immunity Parameters Test Conditions Conducted interferences ISO 7637-1 Interference suppression VDE 0879 Part 2 Value Level 4(1) Level 5 ESD (human body model); pins 2, 12, 13 vs. GND HBM: AEC-Q100-002-Ref-D CEI/IEC 60749-26:2006 ESD (human body model), all other pins ESDA/JEDEC JS-001-2010 8kV CDM (charged device model) ANSI/ESD S5.3.1-2009 1kV MM (machine model) AEC Q100-003-REV-E ANSI/ESD S5.2-2009 250V Note: 8. 5kV Test pulse 5: Vsmax = 40V Electrical Characteristics 7.5V < VVS < 40V; 4.75V < VVCC < 5.25V; INH = High; –40°C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 1 Current Consumption 1.1 Quiescent current VS VVS < 20V, INH = low 3 IVS 1 2 µA A 1.2 Quiescent current VCC 4.75V < VVCC < 5.25V, INH = low 11 IVCC 15 25 µA A 1.3 Supply current VS VVS < 20V normal operating, all outputs off 3 IVS 4 6 mA A 1.4 Supply current VCC 4.75V < VVCC < 5.25V, normal operating 11 IVCC 350 500 µA A 1.5 Discharge current VS VVS = 32.5V, INH = low 3 IVS 0.5 5.5 mA A 1.6 Discharge current VS VVS = 40V, INH = low 3 IVS 2.5 10 mA A 11 VVCC 3.2 3.9 4.4 V A tdPor 30 95 190 µs A 2 Undervoltage Detection, Power-on Reset 2.1 Power-on reset threshold 2.2 Power-on reset delay time 2.3a Undervoltage-detection VCC = 5V threshold (down) 3 VUv 5.6 6.5 V A 2.3b Undervoltage-detection VCC = 5V threshold (up) 3 VUv 6.0 7.0 V A 2.4 Undervoltage-detection VCC = 5V hysteresis 3 VUv V A 2.5 Undervoltage-detection delay time µs A After switching on VCC tdUV 0.6 10 40 *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of the input signal at pin CS after data transmission and switch on output stages to 90% of final level. Device not in standby for t > 1ms 8 ATA6826C [DATASHEET] 9213F–AUTO–08/15 8. Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.75V < VVCC < 5.25V; INH = High; –40°C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. 3 Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Thermal Prewarning and Shutdown 3.1 Thermal prewarning set TjPW set 120 145 170 °C B 3.2 Thermal prewarning reset TjPW reset 105 130 155 °C B 3.3 Thermal prewarning hysteresis TjPW °C B 3.4 Thermal shutdown off Tj switch off 150 175 200 °C B 3.5 Thermal shutdown on Tj switch on 135 160 185 °C B 3.6 Thermal shutdown hysteresis Tj switch off K B 3.7 Ratio thermal shutdown off/thermal prewarning set Tj switch off/ TjPW set 1.05 1.2 B 3.8 Ratio thermal shutdown on/thermal prewarning reset Tj switch on/ TjPW reset 1.05 1.2 B 4 15 15 Output Specification (OUT1-OUT3) 4.1 IOut 1-3 = –0.9A 2, 12, 13 RDSOn1-3 0.8 1.5 A IOut 1-3 = +0.9A 2, 12, 13 RDSOn1-3 0.8 1.5 A µA A 200 µA A 2 V A V A On resistance 4.2 4.3 High-side output leakage current VOut 1-3 = 0V, output stages off 2, 12, 13 IOut1-3 4.4 Low-side output leakage current VOut 1-3 = VVS, output stages off 2, 12, 13 IOut1-3 4.5 High-side switch reverse diode forward voltage IOut 1-3 = 1.5A 2, 12, VOut1-3 – VVS 13 4.6 Low-side switch reverse diode forward voltage IOut 1-3 = –1.5A 2, 12, 13 VOut 1-3 –2 4.7 High-side overcurrent 7.5V < VS < 20V limitation and shutdown 20V ≤ VS < 40V threshold 2, 12, 13 IOut1-3 –1.7 –2.0 –1.3 –1.3 –1.0 –1.0 A A A 4.8 Low-side overcurrent 7.5V < VS < 20V limitation and shutdown 20V ≤ VS < 40V threshold 2, 12, 13 IOut1-3 1 1 1.3 1.3 1.7 2.0 A A A 4.9 Overcurrent shutdown delay time tdSd 10 40 µs A 4.10 High-side open-load detection threshold 2, 12, 13 IOut1-3 –50 –30 –10 mA A 4.11 Low-side open-load detection threshold 2, 12, 13 IOut1-3 10 30 50 mA A –15 *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of the input signal at pin CS after data transmission and switch on output stages to 90% of final level. Device not in standby for t > 1ms ATA6826C [DATASHEET] 9213F–AUTO–08/15 9 8. Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.75V < VVCC < 5.25V; INH = High; –40°C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. Parameters 4.12 Symbol Min. Max. Unit Type* Open-load detection delay time tdOL 200 600 µs A 4.13 High-side output switch VVS = 13V on delay(1) RLoad = 30 tdon 20 µs A 4.14 Low-side output switch VVS = 13V on delay(1) RLoad = 30 tdon 20 µs A 4.15 High-side output switch VVS = 13V off delay(1) RLoad = 30 tdoff 20 µs A 4.16 Low-side output switch VVS = 13V off delay(1) RLoad = 30 tdoff 3 µs A 4.17 Dead time between corresponding highand low-side switches 5 Test Conditions Pin VVS = 13V RLoad = 30 Typ. tdon – tdoff 1 µs A 0.3 VVCC V A 0.7 VVCC V A Logic Inputs DI, CLK, CS, INH 5.1 Input voltage low-level threshold 4-6, 10 VIL 5.2 Input voltage high-level threshold 4-6, 10 VIH 5.3 Hysteresis of input voltage 4-6, 10 VI 50 700 mV B 5.4 Pull-down current pin DI, CLK, INH VDI, VCLK, VINH = VCC 5, 6, 10 IPD 10 65 µA A 5.5 Pull-up current pin CS VCS = 0V 4 IPU –65 –10 µA A 0.4 V A V A 10 µA A 100 µs A 6 Serial Interface – Logic Output DO 6.1 Output-voltage low level IDOL = 2mA 9 VDOL 6.2 Output-voltage high level IDOL = –2mA 9 VDOH VVCC – 0.7V 6.3 Leakage current (tri-state) VCS = VCC 0V < VDO < VVCC 9 IDO –10 7 7.1 Inhibit Input - Timing Delay time from standby to normal operation tdINH *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of the input signal at pin CS after data transmission and switch on output stages to 90% of final level. Device not in standby for t > 1ms 10 ATA6826C [DATASHEET] 9213F–AUTO–08/15 9. Serial Interface – Timing Pin Timing Chart No.(1) Symbol CDO = 100pF 9 1 DO disable after CS rising edge CDO = 100pF 9 8.3 DO fall time CDO = 100pF 8.4 DO rise time 8.5 DO valid time 8.6 CS setup time 8.7 No. Parameters Test Conditions 8.1 DO enable after CS falling edge 8.2 Min. Typ. Max. Unit Type* tENDO 200 ns D 2 tDISDO 200 ns D 9 - tDOf 100 ns D CDO = 100pF 9 - tDOr 100 ns D CDO = 100pF 9 10 tDOVal 200 ns D 4 4 tCSSethl 225 ns D CS setup time 4 8 tCSSetlh 225 ns D 8.8 CS high time 4 9 tCSh 500 ns D 8.9 CLK high time 6 5 tCLKh 225 ns D 8.10 CLK low time 6 6 tCLKl 225 ns D 8.11 CLK period time 6 - tCLKp 500 ns D 8.12 CLK setup time 6 7 tCLKSethl 225 ns D 8.13 CLK setup time 6 3 tCLKSetlh 225 ns D 8.14 DI setup time 5 11 tDIset 40 ns D 8.15 DI hold time 5 12 tDIHold 40 ns D *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. See Figure 9-1 on page 12 “Serial Interface Timing with Chart Numbers” ATA6826C [DATASHEET] 9213F–AUTO–08/15 11 Figure 9-1. Serial Interface Timing with Chart Numbers 1 2 CS DO 9 CS 4 7 CLK 5 3 6 8 DI 11 CLK 10 12 DO Inputs DI, CLK, CS: High level = 0.7 x VCC, low level = 0.3 x VCC Output DO: High level = 0.8 x VCC, low level = 0.2 x VCC 12 ATA6826C [DATASHEET] 9213F–AUTO–08/15 10. Application Circuit Figure 10-1. Application Circuit VCC Enable Trigger Reset Atmel U5021M Watchdog VS n. u. n. u. O C S n. u. n. u. n. u. n. u. n. u. n. u. H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R BYT41D 3 VS VBatt Microcontroller CLK CS 5 P S F O P L S C D n. u. n. u. DO n. u. n. u. n. u. n. u. H S 3 L S 3 H S 2 L S 2 H S 1 13V Charge pump L T S P 1 6 Fault detect Fault detect VCC UV protection 4 Fault detect INH Serial interface 11 10 Control logic VCC VCC 5V Power-on reset 9 1 GND + DI + Input register Output register 7 GND Fault detect Fault detect Fault detect Thermal protection 2 12 OUT3 8 14 GND GND 13 OUT1 OUT2 VCC M 11. M Application Notes It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. Recommended value for capacitors at VS: Electrolytic capacitor C > 22µF in parallel with a ceramic capacitor C = 100nF. The value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting current IOut1,2,3 (see Section 4. “Absolute Maximum Ratings” on page 7). Recommended value for capacitors at VCC: Electrolytic capacitor C > 10µF in parallel with a ceramic capacitor C = 100nF. To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as possible to the GND pins. ATA6826C [DATASHEET] 9213F–AUTO–08/15 13 12. Ordering Information Extended Type Number Package ATA6826C-TUQW 13. SO14 Remarks Power package, taped and reeled, 4k, green Package Information 1 7 14 technical drawings according to DIN specifications 8 Dimensions in mm A C D A2 A1 b e E1 L E COMMON DIMENSIONS Note1): Dimensions “D” and “E1” do not include Moldflash or protrusion. (MAX. 0.15mm per side) Bemerkung: ASE (Unit of Measure = mm) Symbol MIN NOM MAX A 1.35 1.55 1.75 A1 0.10 0.18 0.25 A2 1.25 1.38 1.50 b 0.33 0.42 0.51 C 0.19 0.22 0.25 D1) 8.55 8.65 8.75 E1) 3.80 3.90 4.00 E 5.80 6.00 6.20 e L 1.27 BSC 0.40 0.84 1.27 04/13/12 TITLE Package Drawing Contact: [email protected] 14 ATA6826C [DATASHEET] 9213F–AUTO–08/15 Package: SO14 GPC DRAWING NO. REV. 6.541-5053.01-4 1 14. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 9213F-AUTO-08/15 Section 12 “Ordering Information” on page 14 updated 9213E-AUTO-06/14 Put datasheet in the latest template 9213D-AUTO-09/12 Section 7 “Noise and Surge Immunity” on page 8 changed 9213C-AUTO-05/12 Section 13 “Package Information” on page 14 changed 9213B-BCD-01/11 Section 3.6 “Inhibit” on page 6 changed ATA6826C [DATASHEET] 9213F–AUTO–08/15 15 XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2015 Atmel Corporation. / Rev.: 9213F–AUTO–08/15 Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. 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