AT25P1024 - Mature

Features
•
•
•
•
•
•
•
•
•
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Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
2.1 MHz Clock Rate
128-byte Page Mode Only for Write Operations
Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
Self-Timed Write Cycle (5 ms Typical)
High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: >40 Years
20-lead JEDEC SOIC and 8-lead Leadless Array Package
SPI Serial
EEPROMs
1M (131,072 x 8)
Description
The AT25P1024 provides 1,048,576 bits of serial electrically erasable programmable
read only memory (EEPROM) organized as 131,072 words of 8 bits each. The device
is optimized for use in many industrial and commercial applications where low power
and low voltage operation are essential. The AT25P1024 is available in space saving
20-lead JEDEC SOIC and 8-lead LAP packages.
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
NC
No Connect
Note:
Not Recommended for new
design; Please refer to
AT25FS010 datasheet.
20-lead SOIC
Table 1. Pin Configurations
Pin Name
AT25P1024
CS
SO
NC
NC
NC
NC
NC
NC
WP
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
HOLD
NC
NC
NC
NC
NC
NC
SCK
SI
8-lead Leadless Array
VCC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
CS
SO
WP
GND
Bottom View
The AT25P1024 is enabled through the Chip Select pin (CS) and accessed via a 3wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial
Clock (SCK). All programming cycles are completely self-timed, and no separate
erase cycle is required before write.
1082I–SEEPR–7/06
1
Block Write protection is enabled by programming the status register with top ¼, top ½ or entire array of write protection.
Separate Program Enable and Program Disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be
used to suspend any serial communication without resetting the serial sequence.
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
131,072 x 8
2
AT25P1024
1082I–SEEPR–7/06
AT25P1024
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol
Test Conditions
COUT
Output Capacitance (SO)
CIN
Note:
Max
Units
Conditions
8
pF
VOUT = 0V
6
pF
VIN = 0V
Input Capacitance (CS, SCK, SI, WP, HOLD)
1. This parameter is characterized and is not 100% tested.
Table 3. DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +2.7V to +5.5V,
TAC = 0°C to +70°C, VCC = +2.7V to +5.5V (unless otherwise noted)
Symbol
Parameter
Max
Units
VCC1
Supply Voltage
2.7
5.5
V
VCC2
Supply Voltage
4.5
5.5
V
ICC1
Supply Current
VCC = 5.0V at 1 MHz, SO = Open Read
2.0
5.0
mA
ICC2
Supply Current
VCC = 5.0V at 2 MHz, SO = Open Write
4.0
7.0
mA
ISB1
Standby Current
VCC = 2.7V, CS = VCC
0.2
3.0
µA
ISB2
Standby Current
VCC = 5.0V, CS = VCC
2.0
7.0
µA
IIL
Input Leakage
VIN = 0V to VCC
-3.0
3.0
µA
IOL
Output Leakage
VIN = 0V to VCC, TAC = 0°C to 70°C
-3.0
3.0
µA
Input Low Voltage
-0.6
VCC x 0.3
V
Input High Voltage
VCC x 0.7
VCC + 0.5
V
0.4
V
VIL(1)
VIH
(1)
VOL1
VOH1
Note:
Output Low Voltage
Output High Voltage
Test Condition
4.5V ≤ VCC ≤ 5.5V
Min
IOL = 3.0 mA
IOH = -1.6 mA
VCC - 0.8
Typ
V
1. VIL and VIH max are reference only and are not tested.
3
1082I–SEEPR–7/06
Table 4. AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min
Max
Units
fSCK
SCK Clock Frequency
4.5 - 5.5
2.7 - 5.5
0
0
2.1
1.0
MHz
tRI
Input Rise Time
4.5 - 5.5
2.7 - 5.5
2
2
µs
tFI
Input Fall Time
4.5 - 5.5
2.7 - 5.5
2
2
µs
tWH
SCK High Time
4.5 - 5.5
2.7 - 5.5
200
400
ns
tWL
SCK Low Time
4.5 - 5.5
2.7 - 5.5
200
400
ns
tCS
CS High Time
4.5 - 5.5
2.7 - 5.5
250
500
ns
tCSS
CS Setup Time
4.5 - 5.5
2.7 - 5.5
100
250
ns
tCSH
CS Hold Time
4.5 - 5.5
2.7 - 5.5
150
250
ns
tSU
Data In Setup Time
4.5 - 5.5
2.7 - 5.5
30
50
ns
tH
Data In Hold Time
4.5 - 5.5
2.7 - 5.5
50
50
ns
tHD
Hold Setup Time
4.5 - 5.5
2.7 - 5.5
100
100
ns
tCD
Hold Hold Time
4.5 - 5.5
2.7 - 5.5
200
300
ns
tV
Output Valid
4.5 - 5.5
2.7 - 5.5
0
0
tHO
Output Hold Time
4.5 - 5.5
2.7 - 5.5
0
0
tLZ
Hold to Output Low Z
4.5 - 5.5
2.7 - 5.5
0
0
tHZ
Hold to Output High Z
tDIS
200
400
ns
ns
100
200
ns
4.5 - 5.5
2.7 - 5.5
100
200
ns
Output Disable Time
4.5 - 5.5
2.7 - 5.5
200
250
ns
tWC
Write Cycle Time
4.5 - 5.5
2.7 - 5.5
5
10
ms
Endurance(1)
5.0V, 25°C, Page Mode
4.5 - 5.5
2.7 - 5.5
Note:
4
100K
Write Cycles
1. This parameter is characterized and is not 100% tested.
AT25P1024
1082I–SEEPR–7/06
AT25P1024
Serial Interface
Description
MASTER:
The device that generates the serial clock.
SLAVE: Because the serial clock pin (SCK) is always an input, the AT25P1024
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25P1024 has separate pins designated for data
transmission (SO) and reception (SI).
MSB:
The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will
be received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25P1024, and the serial output pin (SO) will remain in a high impedance state until
the falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25P1024 is selected when the CS pin is low. When the device is
not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will
remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25P1024.
When the device is selected and a serial sequence is underway, HOLD can be used to
pause the serial communication with the master device without resetting the serial
sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought high while the SCK pin is low
(SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin
is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations
when held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a
write to the status register. If the internal write cycle has already been initiated, WP
going low will have no effect on any write operation to the status register. The WP pin
function is blocked when the WPEN bit in the status register is “0”. This will allow the
user to install the AT25P1024 in a system with the WP pin tied to ground and still be
able to write to the status register. All WP pin functions are enabled when the WPEN bit
is set to “1”.
5
1082I–SEEPR–7/06
Figure 2. SPI Serial Interface
MASTER:
MICROCONTROLLER
DATA OUT (MOSI)
DATA IN (MISO)
SERIAL CLOCK (SPI CK)
SS0
SS1
SS2
SS3
SLAVE:
AT25P1024
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
6
AT25P1024
1082I–SEEPR–7/06
AT25P1024
Functional
Description
The AT25P1024 is designed to interface directly with the synchronous serial peripheral
interface (SPI) of the 6800 type series of microcontrollers.
The AT25P1024 utilizes an 8-bit instruction register. The list of instructions and their
operation codes are contained in Table 5. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low transition.
Table 5. Instruction Set for the AT25P1024
Instruction Name
Instruction Format
Operation
WREN
0000 X110
Set Write Enable Latch
WRDI
0000 X100
Reset Write Enable Latch
RDSR
0000 X101
Read Status Register
WRSR
0000 X001
Write Status Register
READ
0000 X011
Read Data from Memory Array
WRITE
0000 X010
Write Data to Memory Array
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC
is applied. All programming instructions must therefore be preceded by a Write Enable
instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write
Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides
access to the status register. The Ready/Busy and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the block write protection bits
indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 6. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
7
1082I–SEEPR–7/06
Table 7. Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = “0” (RDY) indicates the device is ready. Bit 0 = “1” indicates the write cycle
is in progress.
Bit 1 (WEN)
Bit 1 = “0” indicates the device is not write enabled. Bit 1 = “1” indicates the device
is write enabled.
Bit 2 (BP0)
See Table 8.
Bit 3 (BP1)
See Table 8.
Bits 4-6 are “0”s when device is not in an internal write cycle.
Bit 7 (WPEN)
See Table 9.
Bits 0-7 are “1”s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select
one of four levels of protection. The AT25P1024 is divided into four array segments. Top
quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of the
data within any selected segment will therefore be read only. The block write protection
levels and corresponding status register control bits are shown in Table 8.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties
and functions as the regular memory cells (e.g. WREN, tWC, RDSR).
Table 8. Block Write Protect Bits
Status Register Bits
Level
Array Addresses Protected
BP1
BP0
AT25P1024
0
0
0
None
1(1/4)
0
1
01800 - 01FFFF
2(1/2)
1
0
010000 - 01FFFF
3(All)
1
1
0000 - 01FFFF
The WRSR instruction also allows the user to enable or disable the write protect (WP)
pin through the use of the write protect enable (WPEN) bit. Hardware write protection is
enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is
disabled when either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected, writes to the Status Register, including the block protect bits and
the WPEN bit, and the block-protected sections in the memory array are disabled.
Writes are only allowed to sections of the memory which are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to
“0”, as long as the WP pin is held low.
Table 9. WPEN Operation
8
WPEN
WP
WEN
Protected
Blocks
Unprotected Blocks
Status Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
AT25P1024
1082I–SEEPR–7/06
AT25P1024
Table 9. WPEN Operation (Continued)
WPEN
WP
WEN
Protected
Blocks
Unprotected Blocks
Status Register
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
READ SEQUENCE (READ): Reading the AT25P1024 via the SO (Serial Output) pin
requires the following sequence. After the CS line is pulled low to select a device, the
READ op-code is transmitted via the SI line followed by the byte address to be read
(Refer to Table 10). Upon completion, any data on the SI line will be ignored. The data
(D7-D0) at the specified address is then shifted out onto the SO line. If only one byte is
to be read, the CS line should be driven high after the data comes out. The read
sequence can be continued since the byte address is automatically incremented and
data will continue to be shifted out. When the highest address is reached, the address
counter will roll over to the lowest address allowing the entire memory to be read in one
continuous read cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25P1024, two separate
instructions must be executed. First, the device must be write enabled via the WREN
instruction. Then a Write instruction may be executed. Also, the address of the memory
location(s) to be programmed must be outside the protected address field location
selected by the block write protection level. During an internal write cycle, all commands
will be ignored except the RDSR instruction.
A Write Instruction requires the following sequence. After the CS line is pulled low to
select the device, the Write op-code is transmitted via the SI line followed by the byte
address and the data (D7-D0) to be programmed (Refer to Table 9). Programming will
start after the CS pin is brought high. The low-to-high transition of the CS pin must occur
during the SCK low time immediately after clocking in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a Read Status
Register (RDSR) Instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”,
the write cycle has ended. Only the Read Status Register instruction is enabled during
the write programming cycle.
The AT25P1024 is capable of a 128-byte Page Write operation ONLY. Content of the
page in the array will not be guaranteed if less than 128 bytes of data is received (byte
operation is not supported). After each byte of data is received, the seven low order
address bits are internally incremented by one; the high order bits of the address will
remain constant. If more than 128 bytes of data are transmitted, the address counter will
roll over and the previously written data will be overwritten. The AT25P1024 is automatically returned to the write disable state at the completion of a write cycle.
NOTE: If the device is not Write enabled (WREN), the device will ignore the Write
instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication.
Table 10. Address Key
Address
AT25P1024
AN
A16 - A0
Don’t Care Bits
A23 - A17
9
1082I–SEEPR–7/06
Timing Diagrams (for SPI Mode 0 (0, 0))
Figure 3. Synchronous Data Timing
t CS
VIH
CS
VIL
t CSH
t CSS
VIH
t WH
SCK
t WL
VIL
tH
t SU
VIH
SI
VALID IN
VIL
tV
VOH
SO
HI-Z
t HO
t DIS
HI-Z
VOL
Figure 4. WREN Timing
Figure 5. WRDI Timing
10
AT25P1024
1082I–SEEPR–7/06
AT25P1024
Figure 6. RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
7
6
5
11
12
13
14
2
1
SCK
INSTRUCTION
SI
DATA OUT
HIGH IMPEDANCE
SO
4
3
0
MSB
Figure 7. WRSR Timing
Figure 8. READ Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 28 29 30 31 32 33 34 35 36 37 38
SCK
3-BYTE ADDRESS
SI
SO
INSTRUCTION
HIGH IMPEDANCE
23 22 21 ...
3
2
1
0
7
6
5
4
3
2
1
0
11
1082I–SEEPR–7/06
Figure 9. WRITE Timing
4
5
6
7
8
9
10 11 28 29 30 31 32 33 34
1055
3
1054
2
1053
1
1052
0
1051
CS
SCK
128th BYTE DATA-IN
1st BYTE DATA-IN
3-BYTE ADDRESS
SI
SO
INSTRUCTION
23 22 21
3
2
1
0
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
Figure 10. HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
SO
tLZ
12
AT25P1024
1082I–SEEPR–7/06
AT25P1024
Ordering Information(1)
Ordering Code
Package
Operation Range
AT25P1024C1-10CI-2.7
AT25P1024W1-10SI-2.7
8C1
20S2
Industrial
(-40°C to 85°C)
AT25P1024C1-10CU-2.7(2)
AT25P1024W1-10SU-2.7(2)
8C1
20S2
Lead-Free\Halogen-Free
Industrial Temperature
(-40°C to 85°C)
Notes:
1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics
tables.
2. “U” designates Green Package & RoHS Compliant.
Package Type
8C1
8-pad, 0.300" Wide, Leadless Array Package (LAP)
20S2
20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
Options
-2.7
Low-voltage (2.7V to 5.5V)
13
1082I–SEEPR–7/06
Packaging Information
8C1 – LAP
Marked Pin1 Indentifier
E
A
A1
D
Top View
Side View
Pin1 Corner
L1
0.10 mm
TYP
8
1
e
COMMON DIMENSIONS
(Unit of Measure = mm)
2
7
3
6
b
5
4
e1
L
Bottom View
Note:
SYMBOL
MIN
NOM
MAX
A
0.94
1.04
1.14
A1
0.30
0.34
0.38
b
0.36
0.41
0.46
D
7.90
8.00
8.10
E
4.90
5.00
5.10
e
1.27 BSC
e1
0.60 REF
NOTE
1
L
0.62
.0.67
0.72
1
L1
0.92
0.97
1.02
1
1. Metal Pad Dimensions.
2. All exposed metal area shall have the following finished platings.
Ni: 0.0005 to 0.015 mm
Au: 0.0005 to 0.001 mm
11/8/04
R
14
TITLE
1150 E.Cheyenne Mtn Blvd.
8CN1, 8-lead (8 x 5 x 1.04 mm Body), Lead Pitch 1.27 mm,
Colorado Springs, CO 80906 Leadless Array Package (LAP)
DRAWING NO.
8CN1
REV.
B
AT25P1024
1082I–SEEPR–7/06
AT25P1024
20S2 – JEDEC SOIC
C
1
L
E H
N
A1
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
e
SYMBOL
b
A
D
Side View
MIN
NOM
MAX
NOTE
A
0.0926
0.1043
A1
0.0040
0.0118
b
0.0130
0.0200
C
0.0091
0.0125
D
0.4961
0.5118
1
E
0.2914
0.2992
2
H
0.3940
0.4190
L
0.0160
0.050
e
4
3
0.050 BSC
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information.
2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006") per side.
3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010") per side.
4. "L" is the length of the terminal for soldering to a substrate.
5. The lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm
1/9/02
(0.024") per side.
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
20S2, 20-lead, 0.300" Wide Body, Plastic Gull
Wing Small Outline Package (SOIC)
DRAWING NO.
20S2
REV.
A
15
1082I–SEEPR–7/06
Revision History
16
Doc. Rev.
Comments
1082I
Added Note ‘Not Recommended for new design; please refer to AT25FS010
datasheet’ to first page.
AT25P1024
1082I–SEEPR–7/06
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
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Tel: (852) 2721-9778
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1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Atmel Operations
Memory
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
La Chantrerie
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Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
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Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
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Tel: (33) 4-76-58-30-00
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Zone Industrielle
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Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
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