Features • • • • • • • • • Low-voltage and Standard-voltage Operation, VCC = 2.7V to 5.5V Internally Organized 4096 x 8, 8192 x 8 Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 400 kHz Compatibility 32-byte Page Write Mode (Partial Page Writes Allowed) Self-timed Write Cycle (5 ms max) High Reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years – ESD Protection: >3,000V Description The AT24C32SC/64SC provides 32,768/65,536 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 4096/8192 words of 8 bits each. The devices are optimized for use in smart card applications where low-power and low-voltage operation may be essential. The devices are available in several standard ISO 7816 smart card modules (see Ordering Information, page 11). All devices are functionally equivalent to Atmel serial EEPROM products offered in standard IC packages (PDIP, SOIC, TSSOP), with the exception of the slave address and write protect functions, which are not required for smart card applications. Table 1. Pin Configurations Pad Name Description ISO Module Contact VCC Power Supply Voltage C1 GND Ground C5 SCL Serial Clock Input C3 SDA Serial Data Input/Output C7 NC No Connect Two-wire Serial EEPROM Smart Card Modules 32K (4096 x 8) 64K (8192 x 8) AT24C32SC AT24C64SC C2, C4, C6, C8 Figure 1. Card Module Contact VCC = C1 NC = C2 SCL = C3 NC = C4 C5 = GND C6 = NC C7 = SDA C8 = NC 1660B–SEEPR–04/04 1 Absolute Maximum Ratings* Operating Temperature......................................−55°C to +125°C Storage Temperature .........................................−65°C to +150°C Voltage on Any Pin with Respect to Ground ........................................ −1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Output Current........................................................ 5.0 mA Figure 2. Block Diagram Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or opencollector devices. Memory Organization AT24C32SC/64SC, 32K/64K SERIAL EEPROM: The 32K/64K is internally organized as 128/256 pages of 32 bytes each. Random word addressing requires a 12/13-bit data word address. 2 1660B–SEEPR–04/04 Pin Capacitance Table 2. Pin Capacitance (1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +2.7V Symbol Test Condition CI/O CIN Notes: Max Units Conditions Input/Output Capacitance (SDA) 8 pF VI/O = 0V Input Capacitance (SCL) 6 pF VIN = 0V 1. This parameter is characterized and is not 100% tested. Table 3. DC Characteristics (1) Symbol Parameter VCC Supply Voltage ICC1 Supply Current VCC = 5.0V Read at 400 kHz ICC2 Supply Current VCC = 5.0V Write at 400 kHz ISB Standby Current ILI Input Leakage Current VIN = VCC or GND 0.10 3.0 µA ILO Output Leakage Current VOUT = VCC or GND 0.05 3.0 µA VIL Input Low Level (2) −0.6 VCC x 0.3 V VIH Input High Level (2) VCC x 0.7 VCC + 0.5 V 0.4 V VOL Note: Test Condition Typ Max Units 5.5 V 0.4 1.0 mA 2.0 3.0 mA 2.0 µA 2.7 VCC = 2.7V VCC = 5.5V Output Low Level Min (2) VCC = 3.0V VIN = VCC or GND IOL = 2.1mA 6.0 1. Applicable over recommended operating range from TAC = 0°C to +70°C, V CC = +2.7V to +5.5V (unless otherwise noted) 2. VIL min and VIH max are reference only and are not tested. 3 1660B–SEEPR–04/04 Table 4. AC Characteristics AT24C32SC Min Symbol Parameter fSCL Clock Frequency, SCL tLOW Clock Pulse Width Low 1.3 1.3 µs tHIGH Clock Pulse Width High 0.6 0.6 µs tI Noise Suppression Time(1) tAA Clock Low to Data Out Valid 0.1 tBUF Time the bus must be free before a new transmission can start(1) 1.3 1.3 µs tHD.STA Start Hold Time 0.6 0.6 µs tSU.STA Start Set-up Time 0.6 0.6 µs tHD.DAT Data In Hold Time 0 0 µs tSU.DAT Data In Set-up Time Min 100 100 ns 400 50 (2) tR Max AT24C64SC Inputs Rise Time (2) 0.9 0.2 Max Units 400 kHz 100 ns 0.9 µs 0.3 0.3 µs 300 300 ns tF Inputs Fall Time tSU.STO Stop Setup Time 0.6 0.6 µs tDH Data Out Hold Time 50 200 ns tWR Write Cycle Time Endurance Notes: (2) 5 5.0V, 25°C, Page Mode 1M 5 1M ms Write Cycles 1. Applicable over recommended operating range from TA = 0°C to +70°C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) 2. This parameter is characterized and is not 100% tested. Device Operation CLOCK AND DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 5 on page 6). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command (see Figure 6 on page 6). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 6 on page 6). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word. STANDBY MODE: The AT24C32SC/64SC features a low-power standby mode that is enabled upon power-up and after the receipt of the stop bit and the completion of any internal operations. 4 1660B–SEEPR–04/04 MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: 1. Clock up to nine cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition as SDA is high. Timing Diagrams Bus Timing Figure 3. Bus Timing Note: Write Cycle Timing SCL: Serial Clock; SDA: Serial Data I/O Figure 4. Write Cycle Timing tWR(1) Note: SCL: Serial Clock; SDA: Serial Data I/O 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. 5 1660B–SEEPR–04/04 Data Validity Figure 5. Data Validity SDA SCL DATA STABLE DATA STABLE DATA CHANGE Start and Stop Definition Figure 6. Start and Stop Definition SDA SCL START STOP 6 1660B–SEEPR–04/04 Output Acknowledge Figure 7. Output Acknowledge SCL DATA IN DATA OUT START Device Addressing ACKNOWLEDGE The 32K/64K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 8 below). The device address word consists of a mandatory “1”, “0” sequence for the first four most significant bits as shown. This is common to all two-wire EEPROM devices. The next three bits of the device address word are unused. These three unused bits should be set to “0”. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high, and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the device will return to standby state. Figure 8. Device Address 1 MSB Write Operations 0 1 0 0 0 0 R/W LSB BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0” and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time, the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 9). 7 1660B–SEEPR–04/04 Figure 9. Byte Write PAGE WRITE: The 32K/64K EEPROM is capable of 32-byte page writes. A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 31 more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 10). Figure 10. Page Write Note: * = DON’T CARE bits † = DON’T CARE bits for the 32K The data word address lower five bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a “0”, allowing the read or write sequence to continue. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to “1”. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page, to the first byte of the first page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. 8 1660B–SEEPR–04/04 Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does generate a following stop condition (see Figure 11). Figure 11. Current Address Read S T A R T S T O P R E A D DEVICE ADDRESS SDA LINE M S B L R A S / C B W K N O DATA A C K RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” but does generate a following stop condition (refer to Figure 12). Figure 12. Random Read S T A R T DEVICE ADDRESS W R I T E S T A R T 1st, 2nd WORD ADDRESS n DEVICE ADDRESS S T O P R E A D SDA LINE M S B L R A S / C B W K DUMMY WRITE A C K A C K DATA n N O A C K SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a “0” but does generate a following stop condition (refer to Figure 13). 9 1660B–SEEPR–04/04 Figure 13. Sequential Read 10 1660B–SEEPR–04/04 AT24C16SC Ordering Information Ordering Code Package Voltage Range Operation Range AT24C32SC-09AT M2 – A Module 2.7V–5.5V Commercial (0°C–70°C) AT24C32SC-09BT M2 – B Module 2.7V–5.5V Commercial (0°C–70°C) AT24C32SC-10WI 7 mil Wafer 2.7V–5.5V Industrial (−40°C–85°C) Package Voltage Range Operation Range AT24C64SC-09AT M2 – A Module 2.7V–5.5V Commercial (0°C–70°C) AT24C64SC-09BT M2 – B Module 2.7V–5.5V Commercial (0°C–70°C) AT24C64SC-10WI 7 mil Wafer 2.7V–5.5V Industrial (−40°C–85°C) AT24C64SC Ordering Information Ordering Code Package Type(1) Description M2 – A Module M2 ISO 7816 Smart Card Module M2 – B Module M2 ISO 7816 Smart Card Module with Atmel Logo Notes: 1. Formal drawings may be obtained from an Atmel sales office. 11 1660B–SEEPR–04/04 Smart Card Modules Ordering Code: 09AT-00 Module Size: M2 Dimension*: 12.6 x 11.4 [mm] Glob Top: Square: 8.6 x 8.6 [mm] Thickness: 0.58 [mm] max Pitch: 14.25 [mm] Ordering Code: 09BT-00 Module Size: M2 Dimension*: 12.6 x 11.4 [mm] Glob Top: Square: 8.6 x 8.6 [mm] Thickness: 0.58 [mm] max Pitch: 14.25 [mm] *Note: The module dimensions listed refer to the dimensions of the exposed metal contact area. The actual dimensions of the module after excise or punching from the carrier tape are generally 0.4 mm greater in both directions (i.e., a punched M2 module will yield 13.0 x 11.8 mm). 12 1660B–SEEPR–04/04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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