ATA8402 - Complete

ATA8402
UHF ASK/FSK Industrial Transmitter
DATASHEET
Features
● Integrated PLL loop filter
● ESD protection (3kV HBM/150V MM)
● High output power (7.5dBm) with low supply current (9.0mA)
● Modulation scheme ASK/FSK
● FSK modulation is achieved by connecting an additional capacitor between the
XTAL load capacitor and the open drain output of the modulating microcontroller
● Easy to design-in due to excellent isolation of the PLL from the PA and power
supply
● Single Li-cell for power supply
● Supply voltage 2.0V to 4.0V in the temperature range of –40°C to +85°C
● Package TSSOP8L
● Single-ended antenna output with high efficient power amplifier
● CLK output for clocking the microcontroller
● One-chip solution with minimum external circuitry
Applications
● Industrial/aftermarket remote keyless entry systems
● Alarm, telemetering, and energy metering systems
● Remote control systems for consumer and industrial markets
● Access control systems
● Home automation
● Home entertainment
● Toys
4982E-INDCO-08/15
1.
Description
The ATA8402 is a PLL transmitter IC, which has been developed for the demands of RF low-cost transmission systems for
industrial applications at data rates up to 50kBaud ASK and 32kBaud FSK modulation scheme. The transmitting frequency
range is 429MHz to 439MHz. It can be used in both FSK and ASK systems.
Figure 1-1. System Block Diagram
UHF ASK/FSK
Remote control transmitter
UHF ASK/FSK
Remote control receiver
1 Li cell
Atmel
ATA8402
Keys
Encoder
ATARx9x
ATA3741/
ATA3745/
ATA5743/
ATA5744/
ATA8202
PLL
Antenna
XTO
2
ATA8402 [DATASHEET]
4982E–INDCO–08/15
Control
IF Amp
Antenna
VCO
Power
amp.
1 to 3
Demod
PLL
LNA
VCO
XTO
Microcontroller
2.
Pin Configuration
Figure 2-1. Pinning TSSOP8L
CLK
PA_ENABLE
ANT2
ANT1
Table 2-1.
Pin
ATA8402
1
8
2
7
3
6
4
5
ENABLE
GND
VS
XTAL
Pin Description
Symbol
Function
Configuration
VS
1
CLK
Clock output signal for
microconroller
The clock output frequency is set by
the crystal to fXTAL/4
100Ω
100Ω
PA_ENABLE
2
PA_ENABLE
CLK
UREF = 1.1V
50kΩ
Switches on power amplifier, which
is used for ASK modulation
20μA
ANT1
3
ANT2
Emitter of antenna output stage
4
ANT1
Open collector antenna output
ANT2
ATA8402 [DATASHEET]
4982E–INDCO–08/15
3
Table 2-1.
Pin
Pin Description (Continued)
Symbol
Function
Configuration
VS
1.5kΩ
5
XTAL
VS
1.2kΩ
Connection for crystal
XTAL
182μA
6
VS
7
GND
8
ENABLE
Supply voltage
See ESD protection circuitry (see Figure 4-5 on page 8)
Ground
See ESD protection circuitry (see Figure 4-5 on page 8)
ENABLE
Enable input
200kΩ
Figure 2-2. Block Diagram
Atmel
ATA8402
Power up/down
f
CLK
ENABLE
4
1
8
f
32
PA_ENABLE
GND
2
7
PDF
CP
ANT2
VS
3
6
LF
ANT1
4
PA
VCO
PLL
4
ATA8402 [DATASHEET]
4982E–INDCO–08/15
XTO
5
XTAL
3.
General Description
This fully integrated PLL transmitter allows particularly simple, low-cost RF miniature transmitters to be assembled. The
VCO is locked to 32 fXTAL, and therefore a 13.56MHz crystal is needed for a 433.92MHz transmitter. All other PLL and VCO
peripheral elements are integrated.
The XTO is a series resonance oscillator so that only one capacitor together with a crystal connected in series to GND are
needed as external elements.
The crystal oscillator together with the PLL typically needs < 1 ms until the PLL is locked and the CLK output is stable. There
is a wait time of ≥ 1 ms until the CLK is used for the microcontroller and the PA is switched on.
The power amplifier is an open-collector output delivering a current pulse, which is nearly independent from the load
impedance. The delivered output power is therefore controllable via the connected load impedance.
This output configuration enables a simple matching to any kind of antenna or to 50. A high power efficiency of
 = Pout/(IS,PA VS) of 36% for the power amplifier results when an optimized load impedance of ZLoad = (166 + j223) is used
at 3V supply voltage.
4.
Functional Description
If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode, consuming only a very small amount of current, so
that a lithium cell used as power supply can work for several years.
With ENABLE = H the XTO, PLL, and the CLK driver are switched on. If PA_ENABLE remains L, only the PLL and the XTO
are running, and the CLK signal is delivered to the microcontroller. The VCO locks to 32 times the XTO frequency.
With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver, and the power amplifier are on. The power amplifier can
be switched on and off with PA_ENABLE. This is used to perform the ASK modulation.
4.1
ASK Transmission
The ATA8402 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥1 ms, then the CLK signal can be taken to
clock the microcontroller and the output power can be modulated by means of the PA_ENABLE pin. After transmission,
PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The ATA8402 is switched back to
standby mode with ENABLE = L.
4.2
FSK Transmission
The ATA8402 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥1 ms, then the CLK signal can be taken to
clock the microcontroller, and the power amplifier is switched on with PA_ENABLE = H. The chip is then ready for FSK
modulation. The microcontroller starts to switch on and off the capacitor between the XTAL load capacitor and GND with an
open-drain output port, thus changing the reference frequency of the PLL. If the switch is closed, the output frequency is
lower than if the switch is open. After transmission, PA_ENABLE is switched to L, and the microcontroller switches back to
internal clocking. The ATA8402 is switched back to standby mode with ENABLE = L.
The accuracy of the frequency deviation with XTAL pulling method is about ±25% when the following tolerances are
considered.
Figure 4-1. Tolerances of Frequency Modulation
VS
CStray1
CStray2
LM
C4
XTAL
CM
RS
C0
Crystal equivalent circuit
C5
CSwitch
Using C4 = 9.2pF ±2%, C5 = 6.8pF ±5%, a switch port with CSwitch = 3pF ±10%, stray capacitances on each side of the crystal
of CStray1 = CStray2 = 1pF ±10%, a parallel capacitance of the crystal of C0 = 3.2pF ±10% and a crystal with CM = 13fF ±10%,
typically results in an FSK deviation of ±21kHz with worst case tolerances of ±16.3kHz to ±28.8kHz.
ATA8402 [DATASHEET]
4982E–INDCO–08/15
5
4.3
CLK Output
An output CLK signal is provided for a connected microcontroller. The delivered signal is CMOS compatible if the load
capacitance is lower than 10pF.
4.3.1
Clock Pulse Take-over
The clock of the crystal oscillator can be used for clocking the microcontroller. A special feature of Atmel®’s ATARx9x is that
it starts with an integrated RC-oscillator to switch on the ATA8402 with ENABLE = H, and after 1ms assumes the clock
signal of the transmission IC, so that the message can be sent with crystal accuracy.
4.3.2
Output Matching and Power Setting
The output power is set by the load impedance of the antenna. The maximum output power is achieved with a load
impedance of ZLoad,opt = (166 + j223). There must be a low resistive path to VS to deliver the DC current.
The delivered current pulse of the power amplifier is 9mA. The maximum output power is delivered to a resistive load of
465 if the 1.0pF output capacitance of the power amplifier is compensated by the load impedance.
An optimum load impedance of:
ZLoad = 465 || j/(2   1.0pF) = (166 + j223) thus results for the maximum output power of 7.5dBm.
The load impedance is defined as the impedance seen from the ATA8402’s ANT1, ANT2 into the matching network. Do not
confuse this large signal load impedance with a small signal input impedance delivered as input characteristic of RF
amplifiers and measured from the application into the IC instead of from the IC into the application for a power amplifier.
Less output power is achieved by lowering the real parallel part of 465 where the parallel imaginary part should be kept
constant.
Output power measurement can be done with the circuit shown in Figure 4-2 on page 6. Note that the component values
must be changed to compensate for individual board parasitics until the ATA8402 has the right load impedance
ZLoad,opt = (166 + j223). Also the damping of the cable used to measure the output power must be calibrated out.
Figure 4-2. Output Power Measurement
VS
C1
1nF
L1
C2
ANT1
ZLopt
ANT2
4.4
33nH
2.2pF
Z = 50Ω
Power
meter
Rin
50Ω
Application Circuit
A value of 68 nF/X7R is recommended for the supply-voltage blocking capacitor C3 (see Figure 4-3 on page 7 and Figure 44 on page 8). C1 and C2 are used to match the loop antenna to the power amplifier where C1 typically is 8.2pF/NP0 and C2 is
6pF/NP0 (10pF + 15pF in series). For C2, two capacitors in series should be used to achieve a better tolerance value and to
have the possibility of realizing the ZLoad,opt using standard valued capacitors.
C1, together with the pins of ATA8402 and the PCB board wires, forms a series resonance loop that suppresses the 1st
harmonic. Therefore, the position of C1 on the PCB is important. Normally the best suppression is achieved when C1 is
placed as close as possible to the pins ANT1 and ANT2.
The loop antenna should not exceed a width of 1.5mm, otherwise the Q-factor of the loop antenna is too high.
L1 ([50nH to 100nH) can be printed on PCB. C4 should be selected so that the XTO runs on the load resonance frequency of
the crystal. Normally, a 15pF load-capacitance crystal results in a value of 12pF.
6
ATA8402 [DATASHEET]
4982E–INDCO–08/15
Figure 4-3. ASK Application Circuit
S1
VDD
ATARx9x
BPXY
VS
1
S2
VSS
BPXY
20
BPXY
BPXY
OSC1
7
Atmel
ATA8402
Power up/down
CLK
ENABLE
f
4
1
8
f
32
GND
PA_ENABLE
2
7
PDF
C3
C2
CP
VS
ANT2
3
6
VS
Loop
Antenna
LF
C1
ANT1
XTAL
4
PA
VCO
PLL
L1
XTO
XTAL
5
C4
VS
ATA8402 [DATASHEET]
4982E–INDCO–08/15
7
Figure 4-4. FSK Application Circuit
S1
VDD
ATARx9x
BPXY
VS
1
S2
VSS
BPXY
20
BP42/T2O
BPXY
18
BPXY
OSC1
7
Atmel
ATA8402
Power up/down
CLK
ENABLE
f
4
1
8
f
32
PA_ENABLE
GND
2
7
PDF
C3
CP
C2
ANT2
VS
3
Loop
Antenna
6
VS
LF
C1
C5
ANT1
XTAL
4
PA
VCO
XTO
XTAL
5
PLL
L1
C4
VS
Figure 4-5. ESD Protection Circuit
VS
ANT1
CLK
GND
8
ATA8402 [DATASHEET]
4982E–INDCO–08/15
PA_ENABLE
ANT2
XTAL
ENABLE
5.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Minimum
Maximum
Unit
Supply voltage
VS
5
V
Power dissipation
Ptot
100
mW
Junction temperature
Tj
150
°C
Storage temperature
Tstg
–55
+85
°C
Ambient temperature
Tamb
–55
+85
Input voltage
VmaxPA_ENABLE
–0.3
Note:
1. If VS + 0.3 is higher than 3.7V, the maximum voltage will be reduced to 3.7V.
6.
(VS + 0.3)
V
Thermal Resistance
Parameters
Junction ambient
7.
°C
(1)
Symbol
Value
Unit
RthJA
170
K/W
Electrical Characteristics
VS = 2.0V to 4.0V, Tamb = 25°C unless otherwise specified.
Typical values are given at VS = 3.0 V and Tamb = 25°C. All parameters are referred to GND (pin 7).
Parameters
Test Conditions
Supply current
Power down
VENABLE < 0.25V, –40°C to 85°C
VPA-ENABLE < 0.25V, 25°C
(100% correlation tested)
Supply current
Symbol
Min.
Typ.
Max.
Unit
350
nA
nA
IS_Off
< 10
Power up, PA off, VS = 3V,
VENABLE > 1.7V, VPA-ENABLE < 0.25V
IS
3.7
4.8
mA
Supply current
Power up, VS = 3.0V,
VENABLE > 1.7V, VPA-ENABLE > 1.7V
IS_Transmit
9
11.6
mA
Output power
VS = 3.0V, Tamb = 25°C,
f = 433.92MHz, ZLoad = (166 + j233)
7.5
10
dBm
PRef
PRef
–1.5
–4.0
dB
dB
PRef
PRef
–2.0
–4.5
dB
dB
7.5
dBm
T
= 25°C,
Output power variation for the full amb
VS = 3.0V
temperature range
VS = 2.0V
Tamb = 25°C,
Output power variation for the full VS = 3.0V
temperature range
VS = 2.0V
POut = PRef + PRef
Achievable output-power range
Selectable by load impedance
PRef
POut_typ
fCLK = f0/128
Load capacitance at pin CLK = 10pF
Spurious emission
fO ±1  fCLK
fO ±4  fCLK
Other spurious are lower
Note:
1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V.
5.5
0
–55
–52
ATA8402 [DATASHEET]
4982E–INDCO–08/15
dBc
dBc
9
7.
Electrical Characteristics (Continued)
VS = 2.0V to 4.0V, Tamb = 25°C unless otherwise specified.
Typical values are given at VS = 3.0 V and Tamb = 25°C. All parameters are referred to GND (pin 7).
Parameters
Test Conditions
Oscillator frequency XTO
(= phase comparator frequency)
fXTO = f0/32
fXTAL = resonant frequency of the XTAL,
CM ≤ 10 fF, load capacitance selected
accordingly
Tamb = 25°C
Symbol
Min.
fXTO
PLL loop bandwidth
Typ.
Max.
Unit
fXTAL
ppm
250
kHz
Phase noise of phase comparator
Referred to fPC = fXT0,
25kHz distance to carrier
–116
–110
dBc/Hz
In-loop phase noise PLL
25kHz distance to carrier
–86
–80
dBc/Hz
Phase noise VCO
At 1MHz
At 36MHz
–94
–125
–90
–121
dBc/Hz
dBc/Hz
439
MHz
Frequency range of VCO
fVCO
429
Clock output frequency (CMOS
microcontroller compatible)
Voltage swing at pin CLK
f0/128
CLoad ≤ 10pF
Series resonance R of the crystal
V0h
V0l
VS  0.8
Rs
Capacitive load at pin XT0
MHz
VS  0.2
V
V
110

7
pF
FSK modulation frequency rate
Duty cycle of the modulation signal =
50%
0
32
kHz
ASK modulation frequency rate
Duty cycle of the modulation signal =
50%
0
50
kHz
Low level input voltage
High level input voltage
Input current high
0.25
ENABLE input
20
V
V
µA
0.25
VS(1)
5
V
V
µA
VIl
VIh
IIn
Low level input voltage
VIl
PA_ENABLE input
VIh
High level input voltage
IIn
Input current high
Note:
1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V.
10
ATA8402 [DATASHEET]
4982E–INDCO–08/15
1.7
1.7
Ordering Information
Extended Type Number
Package
MOQ
ATA8402C-6AQY-66
TSSOP8L
5000 pcs
Taped and reeled, Pb-free
Package Information
3±0.1
0.1±0.05
3±0.1
+0.06
0.31-0.07
0.65 nom.
+0.0
0.85±0.05
+0.05
Dimensions in mm
1-0.15
9.
Remarks
0.15-0.025
8.
3.8±0.3
4.9±0.1
3 x 0.65 = 1.95 nom.
8
5
technical drawings
according to DIN
specifications
1
4
03/15/04
TITLE
Package Drawing Contact:
[email protected]
Package: TSSOP 8L
GPC
DRAWING NO.
REV.
6.543-5083.01-4
2
ATA8402 [DATASHEET]
4982E–INDCO–08/15
11
10.
Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No.
History
4982E-INDCO-08/15
Section 8 “Ordering Information” on page 11 changed
4982D-INDCO-07/14
Put datasheet in the latest template
4982C-INDCO-08/12
Features on page 1 changed
4982B-INDCO-03/12
12
ATA8402 [DATASHEET]
4982E–INDCO–08/15
Features on page 1 changed
Section 8 “Ordering Information” on page 11 changed
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