AT97SC3205 Trusted Platform Module – SPI Interface SUMMARY DATASHEET Features Compliant to the Trusted Computing Group (TCG) Trusted Platform Module (TPM) Version 1.2 Specification Compliant with TCG PC Client-Specific TPM Interface Specification (TIS) Version 1.3 Single-chip, Turnkey Solution Hardware Asymmetric Crypto Engine Atmel® AVR® RISC Microprocessor Internal EEPROM Storage for RSA Keys Serial Peripheral Interface (SPI) Protocol Up to 45MHz* (*Typical PC Operating Range is 24MHz to 33MHz) Secure Hardware and Firmware Design and Chip Layout FIPS-140-2 Module Certified Including the High-quality Random Number Generator (RNG), HMAC, AES, SHA, and RSA Engines NV Storage Space for 2066 bytes of User Defined Data 3.3V Supply Voltage 28-lead Thin TSSOP and 32-pad QFN Package Offered in Both Commercial (0°C to 70°C) and Industrial (-40°C to +85°C) Temperature Ranges Description The Atmel AT97SC3205 is a fully integrated security module designed to be integrated into personal computers and other embedded systems. It implements version 1.2 of the Trusted Computing Group (TCG) specification for Trusted Platform Modules (TPM). This is a summary document. The complete document is available under NDA. For more information, please contact your local Atmel sales office. Atmel-8884AS-TPM-AT97SC3205-Datasheet-Summary_022014 1. Pin Configurations and Pinouts Table 1-1. Pin Configurations Pin Name Function VCC 3.3V Supply Voltage GND Ground GPIO Express-00 GPIO assigned to TPM_NV_INDEX_GPIO_00 PP/GPIO Hardware Physical Presence or GPIO pin. GPIO General Purpose Input/Output Pin MISO SPI Slave Data Output MOSI SPI Slave Data Input PIRQ# SPI Interrupt Requests SPI_CLK SPI Clock Input SPI_CS# SPI Chip Select SPI_RST# SPI Reset Pin TestI TestI Manufacturing Test Input (Disabled) TestBI TestBI Manufacturing Test Input (Disabled) XTamper Indicate External Tamper Event NC No Connect Figure 1-1. Pinouts 28-pin TSSOP 4.40mm x 9.70mm Body 0.65mm Pitch PP/GPIO 7 22 SPI_CS# TestI 8 21 SPI_CLK TestBI/GPIO/XTamper 9 20 PIRQ# VCC 10 GND 11 2 23 MOSI 19 VCC 18 GND NC 12 NC 13 17 GPIO3 NC 14 15 NC 16 SPI_RST# AT97SC3205 [SUMMARY DATASHEET] Atmel-8884AS-TPM-AT97SC3205-Datasheet-Summary_022014 NC NC NC 24 MISO GND 2 23 GND GPIO Express-00 3 22 VCC PP/GPIO 4 21 MOSI TestI 5 20 SPI_CS# TestBI/GPIO/XTamper 6 19 SPI_CLK NC 7 18 PIRQ# VCC 8 17 SPI_RST# 9 10 11 12 13 14 15 16 NC 6 1 NC GPIO Express-00 NC 24 VCC 32 31 30 29 28 27 26 25 VCC NC NC 5 GPIO1 25 GND NC 4 GPIO2 26 MISO GND NC 27 NC 3 GPIO3 2 VCC NC GPIO1 GND 28 NC NC 1 GND GPIO2 32-pin QFN 4.00mm x 4.00mm Body 0.90mm Pitch 2. Block Diagram ROM Program EEPROM Program AVR 8-bit RISC CPU GPIO Express-00 PP/GPIO GPIO SRAM EEPROM Data MOSI MISO SPI_CLK SPI RNG SPI_CS# CRYPTO Engine PIRQ# SPI_RST# Timer Physical Security Circuitry The TPM includes hardware Random Number Generator (RNG), including a FIPS certified Pseudo Random Number Generator that is used for key generation and TCG protocol functions. The RNG is also available to the system to generate random numbers that may be needed during normal operation. The chip uses a dynamic internal memory management scheme to store multiple RSA keys. Other than the standard TCG commands (TPM_FlushSpecific, TPM_Loadkey2), no system intervention is required to manage this internal key cache. The TPM is offered to OEM and ODM manufacturers as a turnkey solution, including the firmware integrated on the chip. In addition, Atmel provides the necessary device driver software for integration into certain operating systems, along with BIOS drivers. Atmel will also provide manufacturing support software for use by OEMs and ODMs during initialization and verification of the TPM during board assembly. Full documentation for TCG primitives can be found in the TCG TPM Main Specification, Parts 1 to 3, on the TCG web site located at https://www.trustedcomputinggroup.org. TPM features specific to PC client platforms are specified in the TCG PC Client Specific TPM Interface Specification, version 1.3, also available on the TCG web site. Implementation guidance for PC platforms is outlined in the TCG PC Client Specific Implementation Specification for Conventional Bios, version 1.2, also available on the TCG web site. AT97SC3205 [SUMMARY DATASHEET] Atmel-8884AS-TPM-AT97SC3205-Datasheet-Summary_022014 3 3. Pin Description = Table 3-1. Pin Descriptions Pin Description VCC Power Supply, 3.3V. Care should be taken to prevent excessive noise. Effective decoupling of the VCC inputs to the Atmel TPM is critical to assure consistently reliable operation over the lifetime of the system. The Atmel recommendation is for a decoupling bypass capacitor within the range of 2200pF to 4700pF, to be placed as close as possible, < 5mm, to each of the VCC pins, located between each VCC pin and the immediately adjacent GND pin. A 0.1μF decoupling bypass capacitor should be placed at the node in which these VCC traces join, which should be as close as possible, < 10mm, to the TPM. In all cases, this bypass capacitor should be closer than the next closest component. All capacitors should be of high quality, with dielectric ratings of X5R or X7R. A low-power state is automatically entered when the chip is idle. No further action is required by the system to enter low-power mode. GND System Ground. GPIO Express-00 General Purpose Input/Output. Internal pull-up resistor. This pin is mapped to NV Index TPM_NV_INDEX_GPIO_00. Default TPM configuration: GPIO Input. GPIO-Express-00 also serves as the XOR chain Output during I/O test mode. Since GPIO-Express-00 has an internal pull-up, it should be left floating if unused. PP/GPIO General Purpose Input/Output. Internal pull-down resistor. This pin is an indicator for hardware physical presence; active high. Default TPM configuration: GPIO input. Since PP/GPIO has an internal pull-down, it should be left floating if unused. GPIO General Purpose Input/Output. If unused, this pin can be tied to GND or VCC at the customers discretion. MISO Master In Slave Out. SPI Slave Data Output. This pin serves as the SPI Data output from the TPM. MOSI Master Out Slave In. SPI Slave Data Input. This pin serves as the SPI Data Input to the TPM. PIRQ# SPI Interrupt Pin, Active-low. This pin is used by the TPM to assert interrupts. If unused, this pin should be tied to ground directly or through a 4.7K resistor. SPI_CLK Clock used to drive the SPI bus. This pin should be asserted high for power savings when the TPM is not in use. SPI_CS# SPI_CS# Chip Select, Active-low. The TPM chip select. SPI_RST# SPI Reset Pin, Active-low. Pulsing this signal low resets the internal state of the TPM, and is equivalent to removal/restoration of power to the chip. The required minimum reset pulse width is 2μs. On power-up, it is critical that reset be kept active-low until VCC, and SPI_CLK stabilize. To be compliant with TCG requirements, this pin needs to be tied to system reset. TPM_Init is indicated by asserting this pin. TestI TestI Manufacturing Test Input. Disabled after manufacturing. Tie TestI to ground directly or through a 4.7k resistor. TestBI/GPIO/ XTamper TestBI Manufacturing Test Input. The Atmel TPM does not support legacy addressing via the optional BADD implementation of this pin.The TestBI pin also serves as the XTamper pin or an additional GPIO pin, active high. (See the application note, “Atmel Specific TPM Commands Reference Guide” for details on XTamper implementation). If unused, this pin should be tied to ground directly or through a 4.7K resistor. No Connect Pins (TSSOP). The AT97SC3205 TSSOP package has additional pins which are no connects and can be tied to GND, VCC, or left floating at the customers discretion: NC – TSSOP Pin 5 NC NC – TSSOP Pin 12 NC – TSSOP Pin 13 NC – TSSOP Pin 14 NC – TSSOP Pin 15 NC – TSSOP Pin 27 NC – TSSOP Pin 28 4 AT97SC3205 [SUMMARY DATASHEET] Atmel-8884AS-TPM-AT97SC3205-Datasheet-Summary_022014 Table 3-1. Pin Pin Descriptions (Continued) Description No Connect Pins (QFN). The AT97SC3205 QFN package has additional pins which are no connects and can be tied to GND, VCC, or left floating at the customers discretion: NC – QFN Pin 7 NC – QFN Pin 10 NC – QFN Pin 11 NC – QFN Pin 13 NC – QFN Pin 14 NC NC – QFN Pin 15 NC – QFN Pin 16 NC – QFN Pin 25 NC – QFN Pin 26 NC – QFN Pin 27 NC – QFN Pin 28 NC – QFN Pin 31 Note: 1. The substrate center pad for the 32-pin QFN is directly tied to GND internally; therefore, this pad can either be left floating or tied to GND. AT97SC3205 [SUMMARY DATASHEET] Atmel-8884AS-TPM-AT97SC3205-Datasheet-Summary_022014 5 4. Ordering Information Atmel Ordering Code AT97SC3205(1) Note: 1. Package Operating Range 28X1 (28-pin thin TSSOP) 32M3 (32-pin very thin QFN) Lead-free, RoHS Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Please see the AT97SC3205 datasheet addendum for the complete catalog number ordering code. Package Type 6 28X1 28-lead, 4.4mm body width, Plastic Thin Shrink Small Outline (thin TSSOP) 32M3 32-pad, 4.0 x 4.0 x 0.9mm body, 0.4mm lead pitch, Very Thin Quad Flat No-Lead (QFN) AT97SC3205 [SUMMARY DATASHEET] Atmel-8884AS-TPM-AT97SC3205-Datasheet-Summary_022014 5. Package Drawings 5.1 28X1 — 28-lead Thin TSSOP TOP VIEW DETAIL 'A' END VIEW C (12° REF) D B 1 14 S E E1 R1 H R C L (0°~8°) L d 0.20 C B A 28 15 e 2X N/2 TIPS A2 A 0.25 SEE DETAIL "A" A (1.00 REF) D C (12° REF) d 0.10 C 28X b A1 SEATING PLANE j n 0.10 m C B A SIDE VIEW COMMON DIMENSIONS (UNIT OF MEASURE=MM) SYMBOL Note: 1. Refer to JEDEC drawing MO-153,variation AE 2. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash,protrusions or gate burrs shall not exceed 0.15mm per end. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25mm per side. 3. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm total in excess of the "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. MIN NOM MAX NOTE A - - 1.10 A1 0.05 - 0.15 A2 0.85 0.90 0.95 b c 0.19 - 0.30 0.09 - 0.20 D 9.60 9.70 9.80 1 4.50 1 6.40BSC E E1 2 4.30 e 4.40 0.65 BSC L 0.45 0.60 0.75 R 0.09 - - R1 0.09 - - S 0.20 - - 7/8/2011 Package Drawing Contact: [email protected] TITLE GPC DRAWING NO. REV. 28X1, 28-lead, 4.4mm Body Width, Plastic Thin Shrink Small Outline Package (TSSOP) TFL 28X1 A AT97SC3205 [SUMMARY DATASHEET] Atmel-8884AS-TPM-AT97SC3205-Datasheet-Summary_022014 7 5.2 32M3 — 32-pad QFN D A B 32 1 2 PIN #1 ID DATUM A OR B E 2X d 0.10 C 2X d 0.10 C L TOP VIEW e/2 f 0.10 C C A 3. TERMINAL TIP d 0.05 C SEATING PLANE A3 A1 DETAIL "A" SIDE VIEW D2 (DATUM A) K D2/2 SEE DETAIL "A" 32X L E2/2 5. (NE-1) X e E2 (DATUM B) 2 1 PIN #1 ID COMMON DIMENSIONS (Unit of Measure = mm) K 32X b 32 e j (8D-1) X e 3. 0.07 m C A B 0.05 m C SEE DETAIL "A" SYMBOL MIN NOM MAX A 0.80 0.85 0.90 A1 0.00 0.02 0.05 A3 0.20 REF D BOTTOM VIEW NOTES : 1. DIMENSIONING AND TOLERANCING CONFORME TO ASME Y14.5M - 1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS, 0 IS IN DEGREES. 3. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE D2 NOTE 4.0 BSC 2.50 E 2.60 2.70 4.0 BSC E2 2.50 2.60 2.70 b 0.15 0.20 0.25 L 0.35 0.40 0.45 K 0.20 – - DIMENSION b SHOULD NOT BE MEASURED IN THAT RADIUS AREA. 4. MAX. PACKAGE WARPAGE IS 0.05 mm. e 0.40 BSC 5. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS. 6. THIS DRAWING CONFORMES TO JEDEC REGISTERED OUTLINE MO-220 05/15/13 Package Drawing Contact: [email protected] 8 TITLE 32M3, 32-pad 4.0 x 4.0 x 0.90mm Body, 0.40mm Lead Pitch, Very Thin Quad Flat No-Lead Package (VQFN) AT97SC3205 [SUMMARY DATASHEET] Atmel-8884AS-TPM-AT97SC3205-Datasheet-Summary_022014 GPC DRAWING NO. REV. ZAK 32M3 A 6. Revision History Doc. Rev. Date 8884AS 02/2014 Comments Initial summary document release FunctionZZ_Summary Notes AT97SC3205 [SUMMARY DATASHEET] Atmel-8884AS-TPM-AT97SC3205-Datasheet-Summary_022014 9 XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2014 Atmel Corporation. / Rev.: Atmel-8884AS-TPM-AT97SC3205-Datasheet-Summary_022014. Atmel®, Atmel logo and combinations thereof, AVR®, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 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