AT25128B and AT25256B SPI Serial EEPROM 128K (16,384 x 8), 256K (32,768 x 8) DATASHEET Features Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) ̶ Data Sheet Describes Mode 0 Operation Low-voltage and Standard-voltage Operation ̶ VCC = 1.8V to 5.5V 20MHz Clock Rate (5V) 64-byte Page Mode and Byte Write Operation Block Write Protection ̶ Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection Self-timed Write Cycle (5ms max) High Reliability ̶ ̶ Endurance: 1,000,000 Write Cycles Data Retention: 100 Years Green (Pb/Halogen-free/RoHS Compliant) Packaging Options Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers Description The Atmel® AT25128B/256B provides 131,072/262,144 bits of Serial Electrically Erasable Programmable Read-Only Memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25128B/256B is available in space saving JEDEC SOIC, TSSOP, UDFN, and VFBGA packages. The AT25128B/256B is enabled through the Chip Select pin (CS) and accessed via a 3-Wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate erase cycle is required before write. Block Write protection is enabled by programming the status register with one of four blocks of Write Protection. Separate Program Enable and Program Disable instructions are provided for additional data protection. Hardware Data Protection is provided via the WP pin to protect against inadvertent write attempts. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 1. Pin Configurations Table 1-1. Pin Configurations Pin Name Function CS Chip Select GND Ground HOLD Suspends Serial Input SCK Serial Data Clock SI Serial Data Input SO Serial Data Output VCC Power Supply WP Write Protect 8-lead TSSOP 8-lead SOIC CS 1 8 VCC SO 2 7 HOLD WP 3 6 SCK GND 4 5 SI CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI Top View Top View 8-ball VFBGA 8-pad UDFN VCC 8 1 CS VCC 8 1 CS HOLD 7 2 SO HOLD 7 2 SO SCK 6 3 WP SCK 6 3 WP SI 5 4 GND SI 5 4 GND Bottom View Note: 2. Drawings are not to scale. Absolute Maximum Ratings* Operating Temperature . . . . . . . . . . .-55C to +125C Storage Temperature . . . . . . . . . . . . .-65C to +150C Voltage on any pin with respect to ground . . . . . . . . . . . . . -1.0V to +7.0V Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V DC Output Current . . . . . . . . . . . . . . . . . . . . . . .5.0mA 2 Bottom View AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 *Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3. Block Diagram Figure 3-1. Block Diagram VCC Status Register Memory Array 16,384/32,768 x 8 Address Decoder Data Register Output Buffer Mode Decode Logic Clock Generator AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 3 4. Electrical Characteristics 4.1 Pin Capacitance (1) Table 4-1. Pin Capacitance Applicable over recommended operating range from TA = 25°C, f = 1MHz, VCC = +5V (unless otherwise noted). Symbol Test Conditions COUT CIN Note: 4.2 1. Max Units Conditions Output Capacitance (SO) 8 pF VOUT = 0V Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V This parameter is characterized and is not 100% tested. DC Characteristics Table 4-2. DC Characteristics Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +1.8V to +5.5V, (unless otherwise noted). Symbol Parameter VCC1 Supply Voltage VCC2 Max Units 1.8 5.5 V Supply Voltage 2.5 5.5 V VCC3 Supply Voltage 4.5 5.5 V ICC1 Supply Current VCC = 5V at 20MHz SO = Open, Read 9 10 mA ICC2 Supply Current VCC = 5V at 10MHz SO = Open, Read, Write 5 7 mA ICC3 Supply Current VCC = 5V at 1MHz SO = Open, Read, Write 2.2 3.5 mA ISB1 Standby Current VCC = 1.8V, CS = VCC 0.2 3 μA ISB2 Standby Current VCC = 2.5V, CS = VCC 0.5 3 μA ISB3 Standby Current VCC = 5.0V, CS = VCC 2 5 μA IIL Input Leakage VIN = 0V to VCC -3 3 μA IOL Output Leakage VIN = 0V to VCC TAC = 0°C to 70°C -3 3 μA VIL(1) Input Low-voltage -1 VCC x 0.3 V VIH(1) Input High-voltage VCC x 0.7 VCC + 0.5 V VOL1 Output Low-voltage 3.6V VCC 5.5V IOL = 3.00mA 0.4 V VOH1 Output High-voltage 3.6V VCC 5.5V IOH = -1.60mA VOL2 Output Low-voltage 1.8V VCC 3.6V IOL = 0.15mA VOH2 Output High-voltage 1.8V VCC 3.6V IOH = -100μA Note: 4 1. Test Condition Min VIL min and VIH max are reference only and are not tested. AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 Typ VCC – 0.8 V 0.2 VCC – 0.2 V V 4.3 AC Characteristics Table 4-3. AC Characteristics Applicable over recommended operating range from TAI = -40 to +85°C, VCC = As Specified, CL = 1 TTL Gate and 30pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units fSCK SCK Clock Frequency 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 0 0 0 20 10 5 MHz tRI Input Rise Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 2 2 2 μs tFI Input Fall Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 2 2 2 μs tWH SCK High Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 20 40 80 ns tWL SCK Low Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 20 40 80 ns tCS CS High Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 100 100 200 ns tCSS CS Setup Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 100 100 200 ns tCSH CS Hold Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 100 100 200 ns tSU Data In Setup Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 5 10 20 ns tH Data In Hold Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 5 10 20 ns tHD Hold Setup Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 5 10 20 ns tCD Hold Hold Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 5 10 20 ns tV Output Valid 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 0 0 0 tHO Output Hold Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 0 0 0 20 40 80 ns ns AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 5 Table 4-3. AC Characteristics (Continued) Applicable over recommended operating range from TAI = -40 to +85°C, VCC = As Specified, CL = 1 TTL Gate and 30pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units tLZ Hold to Output Low Z 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 0 0 0 25 50 100 ns tHZ Hold to Output High Z 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 25 50 100 ns tDIS Output Disable Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 25 50 100 ns tWC Write Cycle Time 4.5 – 5.5 2.5 – 5.5 1.8 – 5.5 5 5 5 ms Endurance(1) 3.3V, 25C, Page Mode Note: 5. 1. 1,000,000 Write Cycles This parameter is characterized and is not 100% tested. Serial Interface Description Master: The device that generates the serial clock. Slave: Because the Serial Clock pin (SCK) is always an input, the AT25128B/256B always operates as a slave. Transmitter/Receiver: The AT25128B/256B has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. Serial Opcode: After the device is selected with CS going low, the first byte will be received. This byte contains the opcode which defines the operations to be performed. Invalid Opcode: If an invalid opcode is received, no data will be shifted into the AT25128B/256B, and the serial output pin (SO) will remain in a high-impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. Chip Select: The AT25128B/256B is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the SO pin will remain in a high-impedance state. Hold: The HOLD pin is used in conjunction with the CS pin to select the AT25128B/256B. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high-impedance state. Write Protect: The Write Protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is one, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is zero. This will allow the user to install the AT25128B/256B in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to one. 6 AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 Figure 5-1. SPI Serial Interface Master: Microcontroller Data Out (MOSI) Data In (MISO) Serial Clock (SPI CK) SS0 SS1 SS2 SS3 Slave: AT25128B/256B SI SO SCK CS SI SO SCK CS SI SO SCK CS SI SO SCK CS AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 7 6. Functional Description The AT25128B/256B is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of the 6800 series of microcontrollers. The AT25128B/256B utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Figure 6-1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. Table 6-1. Instruction Set for the AT25010B/020B/040B Instruction Name Instruction Format Operation WREN 0000 X110 Set Write Enable Latch WRDI 0000 X100 Reset Write Enable Latch RDSR 0000 X101 Read Status Register WRSR 0000 X001 Write Status Register READ 0000 X011 Read Data from Memory Array WRITE 0000 X010 Write Data to Memory Array Write Enable (WREN): The device will power-up in the Write Disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. The WP pin must be held high during a WREN instruction. Write Disable (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. Read Status Register (RDSR): The Read Status Register instruction provides access to the status register. The Read/Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 6-2. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPEN X X X BP1 BP0 WEN RDY Table 6-3. Read Status Register Bit Definition Bit Definition Bit 0 (RDY) Bit 0 = 0 (RDY) indicates the device is ready. Bit 0 = 1 indicates the write cycle is in progress. Bit 1 (WEN) Bit 1 = 0 indicates the device is not write enabled. Bit 1 = 1 indicates the device is write enabled. Bit 2 (BP0) See Table 6-4. Bit 3 (BP1) See Table 6-4. Bits 4 to 6 are zeros when the device is not in an internal write cycle. Bit 7 (WPEN) See Table 6-5. Bits 0 to 7 are ones during an internal write cycle. 8 AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 Write Status Register (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25128B/256B is divided into four array segments. None, one-quarter (¼), one-half (½), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read-only. The block write protection levels and corresponding status register control bits are shown in Table 6-4. Bits BP1, BP0, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g., WREN, tWC, RDSR). Table 6-4. Block Write Protect Bits Status Register Bits Array Addresses Protected Level BP1 BP0 AT25128B AT25256B 0 0 0 None None 1 (¼) 0 1 3000 – 3FFF 6000 – 7FFF 2 (½) 1 0 2000 – 3FFF 4000 – 7FFF 3 (All) 1 1 0000 – 3FFF 0000 – 7FFF The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is one. The hardware write protection is disabled when either the WP pin is high or the WPEN bit is zero. When the device is hardware write protected, writes to the Status Register including the Block Protect bits, the WPEN bit, and the block protected sections in the memory array are disabled. Writes are only allowed to sections of the memory which are not block-protected. Note: When the WPEN bit is hardware write protected, it cannot be changed back to zero as long as the WP pin is held low. Table 6-5. WPEN Operation WPEN WP WEN Protected Blocks Unprotected Blocks Status Register 0 X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Protected Protected X High 1 Protected Writable Writable Read Sequence (READ): Reading the AT25128B/256B via the SO pin requires the following sequence. After the CS line is pulled low to select a device, the Read opcode is transmitted via the SI line followed by the byte address to be read (Table 6-6). Upon completion, any data on the SI line will be ignored. The data (D7 – D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The Read Sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll-over to the lowest address allowing the entire memory to be read in one continuous read cycle. AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 9 Write Sequence (WRITE): In order to program the AT25128B/256B, the Write Protect pin (WP) must be held high and two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then a Write (WRITE) instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A Write instruction requires the following sequence. After the CS line is pulled low to select the device, the Write opcode is transmitted via the SI line followed by the byte address and the data (D7 D0) to be programmed (see Table 6-6 for the address key). Programming will start after the CS pin is brought high. The low-to-high transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR) instruction. If Bit 0 is one, the write cycle is still in progress. If Bit 0 is zero, the write cycle has ended. Only the RDSR instruction is enabled during the write programming cycle. The AT25128B/256B is capable of an 64-byte Page Write operation. After each byte of data is received, the six low-order address bits are internally incremented by one; the high-order bits of the address will remain constant. If more than 64 bytes of data are transmitted, the address counter will roll-over, and the previously written data will be overwritten. The AT25128B/256B is automatically returned to the Write Disable state at the completion of a write cycle. Note: If the WP pin is brought low or if the device is not Write Enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to reinitiate the serial communication. Table 6-6. 10 Address Key Address AT25128B AT25256B AN A13 – A0 A14 – A0 Don’t Care Bits A15 – A14 A15 AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 7. Timing Diagrams — SPI Mode 0 (0,0) Figure 7-1. Synchronous Data Timing (for Mode 0) t CS VIH CS VIL t CSH tCSS VIH t WH SCK t WL VIL tH t SU VIH Valid In SI VIL tV VOH SO t HO t DIS HI-Z HI-Z VOL Figure 7-2. WREN Timing CS SCK SI WREN Opcode HI-Z SO Figure 7-3. WRDI Timing CS SCK SI SO WRDI Opcode HI-Z AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 11 Figure 7-4. RDSR Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK SI Instruction Data Out High-impedance SO 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 2 1 0 MSB Figure 7-5. WRSR Timing CS 0 1 2 3 4 5 6 7 SCK Data In SI 6 5 4 3 High-impedance SO Figure 7-6. 7 Instruction READ Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31 SCK Byte Address SI Instruction AN ... A0 Data Out SO High-impedance 7 MSB 12 AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 6 5 4 3 2 1 0 Figure 7-7. WRITE Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31 SCK Byte Address SI SO Figure 7-8. 15 14 13 ... 3 Instruction 2 Data In 1 0 7 6 5 4 3 2 1 0 High-impedance HOLD Timing CS t CD t CD SCK t HD HOLD t HD t HZ SO tLZ AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 13 8. Ordering Code Detail AT2 5 1 2 8 B - S S H L - B Atmel Designator Product Family 25 = Standard SPI Serial EPPROM Shipping Carrier Option B or Blank = Bulk (Tubes) T = Tape and Reel, Standard Quantity Option E = Tape and Reel, Expanded Quantity Option Operating Voltage L = 1.8V to 5.5V Device Density 128 = 128 kilobit 256 = 256 kilobit Device Revision Package Device Grade or Wafer/Die Thickness H = Green, NiPdAu Lead Finish, Industrial Temperature Range (-40°C to +85°C) U = Green, Matte Sn Lead Finish, Industrial Temperature Range (-40°C to +85°C) 11 = 11mil Wafer Thickness Package Option SS = X = MA = C = WWU WDT 14 AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 JEDEC SOIC TSSOP UDFN VFBGA = Wafer Unsawn = Die in Tape and Reel 9. Part Markings AT25128B and AT25256B: Package Marking Information 8-lead TSSOP 8-lead SOIC ATMLHYWW ###% @ AAAAAAAA ATHYWW ###% @ AAAAAAA 8-pad UDFN 8-ball VFBGA 2.0 x 3.0 mm Body 2.35 x 3.73 mm Body ### H%@ YXX Note 1: ###U @YMXX designates pin 1 Note 2: Package drawings are not to scale Catalog Number Truncation AT25128B Truncation Code ###: 5DB AT25256B Truncation Code ###: 5EB Date Codes Y = Year 4: 2014 5: 2015 6: 2016 7: 2017 Voltages 8: 2018 9: 2019 0: 2020 1: 2021 M = Month A: January B: February ... L: December WW = Work Week of Assembly 02: Week 2 04: Week 4 ... 52: Week 52 Country of Assembly Lot Number @ = Country of Assembly AAA...A = Atmel Wafer Lot Number Trace Code % = Minimum Voltage L: 1.8V min Grade/Lead Finish Material U: Industrial/Matte Tin/SnAgCu H: Industrial/NiPdAu Atmel Truncation XX = Trace Code (Atmel Lot Numbers Correspond to Code) Example: AA, AB.... YZ, ZZ AT: Atmel ATM: Atmel ATML: Atmel 3/11/14 TITLE Package Mark Contact: [email protected] 25128-256BSM, AT25128B and AT25256B Package Marking Information DRAWING NO. REV. 25128-256BSM A AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 15 10. Ordering Information Delivery Information Atmel Ordering Code Lead Finish Package AT25128B-SSHL-B Form Quantity Bulk (Tubes) 100 per Tube Tape and Reel 4,000 per Reel Bulk (Tubes) 100 per Tube Tape and Reel 5,000 per Reel Tape and Reel 5,000 per Reel Tape and Reel 15,000 per Reel Tape and Reel 5,000 per Reel Operation Range 8S1 AT25128B-SSHL-T AT25128B-XHL-B AT25128B-XHL-T NiPdAu (Lead-free/Halogen-free) 8X AT25128B-MAHL-T 8MA2 AT25128B-MAHL-E AT25128B-CUL-T SnAgCu (Lead-free/Halogen-free) AT25128B-WWU11L (1) N/A 8U2-1 Wafer AT25256B-SSHL-B Industrial Temperature (-40 to +85C) Note 1 Bulk (Tubes) 100 per Tube Tape and Reel 4,000 per Reel Bulk (Tubes) 100 per Tube Tape and Reel 5,000 per Reel Tape and Reel 5,000 per Reel Tape and Reel 15,000 per Reel Tape and Reel 5,000 per Reel 8S1 AT25256B-SSHL-T AT25256B-XHL-B AT25256B-XHL-T NiPdAu (Lead-free/Halogen-free) 8X AT25256B-MAHL-T 8MA2 AT25256B-MAHL-E AT25256B-CUL-T SnAgCu (Lead-free/Halogen-free) AT25256B-WWU11L (1) Note: 1. N/A 8U2-1 Wafer Industrial Temperature (-40 to +85C) Note 1 Contact Atmel Sales for Wafer sales. Package Type 16 8S1 8-lead, 0.15" wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8X 8-lead, 4.40mm body, Plastic Thin Shrink Small Outline Package (TSSOP) 8MA2 8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Plastic Ultra Thin Dual Flat No Lead (UDFN) 8U2-1 8-ball, 2.35mm x 3.73mm body, 0.75mm pitch, Very Thin, Fine-Pitch Ball Grid Array (VFBGA) AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 11. Packaging Information 11.1 8S1 — 8-lead JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. SYMBOL MIN A 1.35 NOM MAX – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.27 Ø 0° – 8° 6/22/11 Package Drawing Contact: [email protected] TITLE 8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) GPC SWB DRAWING NO. REV. 8S1 G AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 17 11.2 8X — 8-lead TSSOP C 1 Pin 1 indicator this corner E1 E L1 N L Top View End View A b A1 e D SYMBOL Side View Notes: COMMON DIMENSIONS (Unit of Measure = mm) A2 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07mm. 5. Dimension D and E1 to be determined at Datum Plane H. MIN NOM MAX A - - 1.20 A1 0.05 - 0.15 A2 0.80 1.00 1.05 D 2.90 3.00 3.10 2, 5 E NOTE 6.40 BSC E1 4.30 4.40 4.50 3, 5 b 0.19 0.25 0.30 4 e L 0.65 BSC 0.45 L1 C 0.60 0.75 1.00 REF 0.09 - 0.20 2/27/14 TITLE Package Drawing Contact: [email protected] 18 8X, 8-lead 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 GPC TNR DRAWING NO. 8X REV. E 11.3 8MA2 — 8-pad UDFN E 1 8 Pin 1 ID 2 7 3 6 4 5 D C TOP VIEW A2 SIDE VIEW A A1 E2 b (8x) 8 7 1 D2 6 3 5 4 e (6x) K L (8x) BOTTOM VIEW Notes: COMMON DIMENSIONS (Unit of Measure = mm) 2 Pin#1 ID 1. This drawing is for general information only. Refer to Drawing MO-229, for proper dimensions, tolerances, datums, etc. 2. The Pin #1 ID is a laser-marked feature on Top View. 3. Dimensions b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 4. The Pin #1 ID on the Bottom View is an orientation feature on the thermal pad. SYMBOL MIN NOM MAX A 0.50 0.55 0.60 A1 0.0 0.02 0.05 A2 - - 0.55 D 1.90 2.00 2.10 D2 1.40 1.50 1.60 E 2.90 3.00 3.10 E2 1.20 1.30 1.40 b 0.18 0.25 0.30 C NOTE 3 1.52 REF L 0.30 e 0.35 0.40 0.50 BSC K 0.20 - - 11/26/14 Package Drawing Contact: [email protected] TITLE 8MA2, 8-pad 2 x 3 x 0.6mm Body, Thermally Enhanced Plastic Ultra Thin Dual Flat No-Lead Package (UDFN) GPC DRAWING NO. REV. YNZ 8MA2 G AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 19 11.4 8U2-1 — 8-ball VFBGA f 0.10 C d 0.10 A1 BALL PAD CORNER D A (4X) d 0.08 C C A1 BALL PAD CORNER 2 1 Øb A j n0.15 m C A B j n0.08 m C B e E C D (e1) B A1 d A2 (d1) A TOP VIEW BOTTOM VIEW SIDE VIEW 8 SOLDER BALLS COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL Notes: 1. This drawing is for general 2. Dimension 'b' is measured at the maximum solder ball diameter. 3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu. A A1 A2 b D E e e1 d d1 MIN 0.81 0.15 0.40 0.25 NOM 0.91 0.20 0.45 0.30 2.35 BSC 3.73 BSC 0.75 BSC 0.74 REF 0.75 BSC 0.80 REF MAX NOTE 1.00 0.25 0.50 0.35 6/11/13 TITLE Package Drawing Contact: [email protected] 20 8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 GPC DRAWING NO. GWW 8U2-1 REV. G 12. Revision History Doc. Rev. Date 8698E 01/2015 8698D 07/2014 Comments Add the UDFN Expanded Quantity Option and ordering information. Update the 8MA2 package outline drawing. Update part markings, 8MA2 and 8U2-1 package drawings, package 8A2 to 8X, template, logos, and disclaimer page. No change to functional specification. Update 8A2 and 8S1 package drawings. 8698C 08/2011 Correct page 13, Device Density from 156K to 256K. Correct page 9, table headings. Correct cross references on pages 7, 8, and 9. 8698B 03/2010 8698A 12/2009 Update Catalog Numbering Scheme. Update Ordering Information and package types. Initial document release. AT25128B/256B [DATASHEET] Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015 21 XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2015 Atmel Corporation. / Rev.: Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015. Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems. Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade.